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docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

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New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM
sweep). Phase 0: no RTL changes, only measure the current baseline.

ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz,
a leftover from the STEP19 freeze, never updated to the project's real
64MHz target -- fixed (LPF only, zero RTL/datapath effect).

ERR-0031 (bigger one): the first two synthesis attempts targeted
nms_neural_multiprocessor_sdram_unified.v, which is NOT the real
board-level top -- it's an obsolete wrapper only exercised by one
testbench now. The real target is fpga_neural_v2_top.v (adds the real
PLL, reset_sync, spi_host_bridge, and a second arbitration level), which
is what actually goes through synthesis+P&R for hardware. Re-targeted
correctly, matched against constraints/v2_board_top.lpf (all 17 ports
real-ball-assigned).

An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m
without converging on a single seed; discarded rather than trusted.
N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is
fully understood -- re-attempt against the correct fpga_neural_v2_top
target with an agreed time budget.

Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4
8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than
DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL --
disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version
difference), adopted as the operative baseline for this session's
toolchain going forward. Full writeup in errors.log/timing.log/
experiments.log (EXP-0049).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
michele
2026-09-15 20:28:16 +00:00
co-authored by Claude Sonnet 5
parent 8b8ca239ca
commit 685a4d6cfe
21 changed files with 573188 additions and 1290227 deletions
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hardware/v2/logs/experiments.log
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@@ -2901,3 +2901,27 @@ decision: ACCEPT the single-SDRAM architecture as the STEP19 hardware
operation) is fully achieved, and the timing regression is reported
as a real, unresolved CRITICAL item for follow-up (see DEC-0034),
not hidden or worked around by reverting to two chips.
EXP-0049 -- Phase 0 baseline for the new N=8-timing/85F-retarget/
SDRAM-bank sweep brief (2026-09-15)
config: fpga_neural_v2_top (real board-level top), N_SLOTS=4, RTL
bit-identical to DEC-0042's frozen state (no RTL changes)
action: real Yosys synthesis + fresh 8-seed nextpnr-ecp5 P&R, real
physical pins (constraints/v2_board_top.lpf), real PLL-derived 64MHz
internal clock domain
result: 8/8 PASS at 64MHz. Fmax worst=81.20MHz, mean=91.05MHz (full
per-seed numbers and utilization in synthesis.log/timing.log).
Resources: LUT4 6905/43848 (15%), DFF 6527/43848 (14%), MULT18X18D
32/72 (44%), DP16KD 0/108 (0%).
decision: adopted as the operative Phase-0 BASELINE row (see
timing.log for the disclosed, unresolved discrepancy vs DEC-0042's
own historical numbers, and STEP19-era experiments.log precedent
showing N=4 Fmax as high as 81.84MHz on a related pre-fix config --
this range is not without precedent in this project's own history).
N_SLOTS=8 baseline deferred by explicit user request after the wrong
synthesis target (obsolete nms_neural_multiprocessor_sdram_unified.v
wrapper, see ERR-0031) caused a 2h42m non-converging P&R run;
N_SLOTS=8 to be re-attempted against fpga_neural_v2_top with an
agreed time budget.
next_action: Phase 1 (N=8 timing fix) blocked on N_SLOTS=8 baseline;
in the meantime this N_SLOTS=4 baseline is committed to branch v21.