docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq
New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM sweep). Phase 0: no RTL changes, only measure the current baseline. ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz, a leftover from the STEP19 freeze, never updated to the project's real 64MHz target -- fixed (LPF only, zero RTL/datapath effect). ERR-0031 (bigger one): the first two synthesis attempts targeted nms_neural_multiprocessor_sdram_unified.v, which is NOT the real board-level top -- it's an obsolete wrapper only exercised by one testbench now. The real target is fpga_neural_v2_top.v (adds the real PLL, reset_sync, spi_host_bridge, and a second arbitration level), which is what actually goes through synthesis+P&R for hardware. Re-targeted correctly, matched against constraints/v2_board_top.lpf (all 17 ports real-ball-assigned). An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m without converging on a single seed; discarded rather than trusted. N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is fully understood -- re-attempt against the correct fpga_neural_v2_top target with an agreed time budget. Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4 8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL -- disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version difference), adopted as the operative baseline for this session's toolchain going forward. Full writeup in errors.log/timing.log/ experiments.log (EXP-0049). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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Claude Sonnet 5
@@ -1463,3 +1463,94 @@ trace). N_SLOTS=4 remains 8/8 PASS at 64MHz but with reduced margin,
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disclosed above -- flagged, not hidden, per this project's own real-
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data-only reporting standard. File changed: hardware/v2/nms/rtl/
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sdram_unified_backend.v.
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ERR-0030 -- constraints/v2_unified.lpf's FREQUENCY PORT "clk" directive
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was stale at 80 MHz, silently mislabeling every real-pin-constrained
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nextpnr PASS/FAIL result against the wrong bar
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DATE: 2026-09-15
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CONTEXT: new brief to close N=8 timing, retarget to LFE5U-85F, and
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sweep 4/8/16 processors x 1/2 SDRAM banks. Phase 0 baseline: re-ran
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nms_neural_multiprocessor_sdram_unified (N_SLOTS=4/8) through the real
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existing flow. First attempt used `--lpf-allow-unconstrained` with NO
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`--lpf` file at all (no real pin locations) -- achieved Fmax came out
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implausibly high (N=4 worst-seed 86.86MHz, mean ~100MHz across 8
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seeds) versus the last real production baseline (DEC-0042: N=4
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worst-seed 64.55MHz). Re-ran the same N=4 netlist WITH the real
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`constraints/v2_unified.lpf` (real H5/B4 clk/rst balls, real SDRAM
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balls) -- achieved Fmax dropped to a much more plausible 70.03MHz
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(seed0), confirming free/unconstrained IO placement was the source of
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the gap, not an RTL difference.
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ROOT CAUSE (real, found while investigating): `v2_unified.lpf` line 35
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still reads `FREQUENCY PORT "clk" 80 MHZ` from its original STEP19
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freeze -- never updated when the project's achievable/target bar moved
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to 64MHz (DEC-0038 onward). Passing `--freq 64` on the nextpnr-ecp5
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command line does NOT override this: nextpnr uses the LPF's own
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explicit per-port FREQUENCY constraint for any port that has one, and
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`--freq` only supplies a default for ports left unconstrained. Real
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effect verified: with the LPF loaded, nextpnr-ecp5 reported "70.03 MHz
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(FAIL at 80.00 MHz)" even with `--freq 64` passed on the command line --
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the achieved-MHz number itself was real, but the PASS/FAIL label next
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to it was being judged against the wrong, stale 80MHz bar the whole
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time this LPF has been used for any 64MHz-era measurement.
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FIX: updated `constraints/v2_unified.lpf` line 35 to `FREQUENCY PORT
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"clk" 64 MHZ`, with a comment explaining why. This does not touch any
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physical pin/ball assignment (SDRAM/clk/rst LOCATE COMP lines are
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unchanged) and has zero effect on RTL/datapath semantics -- it only
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corrects which frequency nextpnr-ecp5 optimizes/labels against.
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OPEN QUESTION (disclosed, not resolved here): it is not established
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whether earlier 64MHz-labeled results in decisions.log (e.g. DEC-0042)
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were themselves generated WITH this same stale-80MHz LPF (in which
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case their own PASS/FAIL labels would have the same defect, though
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their raw achieved-MHz numbers would remain valid and comparable) or
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via a different invocation (e.g. no LPF, matching this session's first,
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discarded attempt). Re-verify against a fresh N=4 8-seed sweep with the
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corrected LPF before treating DEC-0042's specific pass-count (8/8) as
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still authoritative under real pin constraints.
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ERR-0031 -- Phase 0 baseline was being measured against the wrong
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top-level module (nms_neural_multiprocessor_sdram_unified.v, an
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obsolete testbench-only wrapper), giving falsely-optimistic Fmax
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DATE: 2026-09-15
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CONTEXT: same brief as ERR-0030. After fixing the stale 80MHz LPF
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constraint, re-ran the N=4 8-seed sweep against
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`nms_neural_multiprocessor_sdram_unified.v` + `constraints/
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v2_unified.lpf`: 8/8 PASS at 64MHz, worst-seed 84.91MHz, mean 92.65MHz
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-- still implausibly high, HIGHER than DEC-0042's own best-case seed
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(77.21MHz), not just its worst.
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ROOT CAUSE (found by re-reading decisions.log DEC-0038 entry, which
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explicitly documents this): `nms_neural_multiprocessor_sdram_unified.v`
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is NOT instantiated by the real board-level top. Per decisions.log's
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own prior finding (search "NOT instantiated by the real board-level
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top"), `fpga_neural_v2_top.v` instantiates `nms_dataflow_core_sdram`
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and `sdram_unified_backend` directly, bypassing this wrapper entirely.
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The wrapper is only still used by one testbench
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(`tb_nms_dstress_sdram_unified.v`) as a bit-exact regression oracle --
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it was never the real synthesis target. `constraints/v2_unified.lpf`
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itself says as much in its own superseding file's header
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(`v2_board_top.lpf`: "This supersedes ... v2_unified.lpf"), which this
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session missed on the first two attempts.
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The real board top adds an EHXPLLL PLL (16MHz osc -> 64MHz internal),
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a reset_sync POR synchronizer, a real spi_host_bridge (replacing the
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wrapper's raw 110-pin reg_* testbench bus), and a SECOND arbitration
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level (host SPI raw-memory port vs. compute AR stream) -- all real
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logic and real routing congestion the wrapper never has, which is
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exactly why the wrapper measured faster.
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FIX: re-target synthesis+P&R to `hardware/v2/nms/rtl/
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fpga_neural_v2_top.v` (chparam N_SLOTS) with `hardware/v2/constraints/
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v2_board_top.lpf` (all 17 real ports ball-assigned; PLL's own
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FREQUENCY_PIN_CLKI=16/FREQUENCY_PIN_CLKOP=64 attributes read
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automatically by nextpnr-ecp5 for the internal clock domain, no manual
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--freq needed). Sanity check, single seed: 72.23MHz achieved, PASS at
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64MHz -- squarely inside DEC-0042/ERR-0029's real historical range
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(60-77MHz), confirming this is now the right target.
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LESSON: ERR-0030's fix (to v2_unified.lpf) was not wrong on its own
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terms (the 80MHz value really was stale) but was applied to a file
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that should not be used for this brief's baseline going forward --
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`v2_unified.lpf` remains valid only for whoever still exercises the
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`nms_neural_multiprocessor_sdram_unified.v` testbench wrapper, not for
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any real hardware Fmax claim.
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STATUS: Phase 0 N=4 baseline being re-measured now against the correct
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target (fresh 8-seed sweep in progress). N=8 baseline deferred by user
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request until N=4 is fully understood.
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@@ -2901,3 +2901,27 @@ decision: ACCEPT the single-SDRAM architecture as the STEP19 hardware
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operation) is fully achieved, and the timing regression is reported
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as a real, unresolved CRITICAL item for follow-up (see DEC-0034),
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not hidden or worked around by reverting to two chips.
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EXP-0049 -- Phase 0 baseline for the new N=8-timing/85F-retarget/
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SDRAM-bank sweep brief (2026-09-15)
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config: fpga_neural_v2_top (real board-level top), N_SLOTS=4, RTL
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bit-identical to DEC-0042's frozen state (no RTL changes)
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action: real Yosys synthesis + fresh 8-seed nextpnr-ecp5 P&R, real
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physical pins (constraints/v2_board_top.lpf), real PLL-derived 64MHz
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internal clock domain
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result: 8/8 PASS at 64MHz. Fmax worst=81.20MHz, mean=91.05MHz (full
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per-seed numbers and utilization in synthesis.log/timing.log).
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Resources: LUT4 6905/43848 (15%), DFF 6527/43848 (14%), MULT18X18D
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32/72 (44%), DP16KD 0/108 (0%).
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decision: adopted as the operative Phase-0 BASELINE row (see
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timing.log for the disclosed, unresolved discrepancy vs DEC-0042's
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own historical numbers, and STEP19-era experiments.log precedent
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showing N=4 Fmax as high as 81.84MHz on a related pre-fix config --
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this range is not without precedent in this project's own history).
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N_SLOTS=8 baseline deferred by explicit user request after the wrong
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synthesis target (obsolete nms_neural_multiprocessor_sdram_unified.v
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wrapper, see ERR-0031) caused a 2h42m non-converging P&R run;
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N_SLOTS=8 to be re-attempted against fpga_neural_v2_top with an
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agreed time budget.
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next_action: Phase 1 (N=8 timing fix) blocked on N_SLOTS=8 baseline;
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in the meantime this N_SLOTS=4 baseline is committed to branch v21.
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@@ -122,3 +122,17 @@ N_SLOTS=4: LUT4=9158 CCU2C=698 TRELLIS_FF=7986 MULT18X18D=32 DP16KD=0
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CHECK: 0 problems on all three (same benign warnings as always).
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Resource cost is modest (activation_cache itself is small -- a
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16-tile x 64-bit store plus N_SLOTS-way pending/hit logic).
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[2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top,
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N_SLOTS=4), real synthesis via the corrected flow (see errors.log
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ERR-0030/ERR-0031)
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LUT4=6905 (15%) DFF=6527 (14%) MULT18X18D=32/72 (44%) DP16KD=0/108
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(0%) EHXPLLL=1/4 (25%) TRELLIS_IO=47/245 (19%)
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CHECK: 0 problems. File list: dependency_manager.v, neural_director.v,
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neural_processor.v, prefetch_engine.v, weight_prefetch_engine_wide.v,
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nms_activation_replicated.v, nms_activation_fill_ctrl_v3.v,
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nms_weight_packed.v, nms_memory_manager_stream_wide.v,
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nms_dataflow_core_sdram.v, slot_mem_arbiter.v, slot_mem_arbiter_wide.v,
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sdram_controller.v, sdram_unified_backend.v, ecp5_pll_sys_clk.v,
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reset_sync.v, spi_host_bridge.v, fpga_neural_v2_top.v.
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Log: hardware/v2/nms/synthesis/nms_multiproc_n4/yosys.log
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@@ -141,3 +141,51 @@ DEC-0015's own arbiter widening did. N_SLOTS=4 is no longer a passing
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80MHz design point with the cache active -- see decisions.log
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DEC-0016 for the full analysis and why N_SLOTS=2 (the recommended
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default, DEC-0014) is unaffected in its own recommendation.
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[2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top,
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N_SLOTS=4), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
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--lpf hardware/v2/constraints/v2_board_top.lpf (real ball-assigned
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pins; internal 64MHz clock domain derived from EHXPLLL's own
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FREQUENCY_PIN_CLKI=16/CLKOP=64 attributes, no --freq needed), fresh
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8-seed sweep
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Fmax (clock net off sdram_clk/EHXPLLL CLKOP, PASS bar 64MHz): seed0
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81.20, seed1 98.82, seed2 88.25, seed3 92.43, seed4 94.22, seed5 86.95,
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seed6 96.01, seed7 90.55 MHz. n=8, worst=81.20 MHz, mean=91.05 MHz,
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8/8 PASS at 64MHz.
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BASELINE row for the new N=8-timing/85F-retarget/SDRAM-bank-sweep
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brief (Phase 0). RTL is bit-identical to DEC-0042's own frozen N_SLOTS=4
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production state (no RTL changes since, only docs commits) -- this
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measurement is against the SAME dependency_manager.v pending_count fix
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DEC-0042 itself introduced.
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DISCLOSED, UNRESOLVED DISCREPANCY vs DEC-0042's own recorded N_SLOTS=4
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@ 64MHz numbers (worst-seed 64.55MHz, best-seed 77.21MHz, 8/8 PASS):
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this session's worst-seed (81.20MHz) exceeds DEC-0042's own best-seed.
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Both this session's ERR-0030 (stale 80MHz LPF frequency) and ERR-0031
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(wrong top-level target, the obsolete nms_neural_multiprocessor_
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sdram_unified.v wrapper) were real, found-and-fixed mistakes made
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earlier in this same session while trying to reproduce the baseline --
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but after correcting BOTH (real fpga_neural_v2_top.v target, real
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v2_board_top.lpf, verified 8/8 PASS at 64MHz, single-seed sanity check
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of 72.23MHz independently reproduced close to DEC-0042's range before
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this full 8-seed run), the full sweep still came out systematically
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higher than DEC-0042's historical numbers. No further RTL/config
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difference was found (same file list role, same default parameters:
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N_NODES=16, MAX_TILES=16, QUEUE_DEPTH=8, PREFETCH_DISTANCE=8). Leading
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hypothesis, NOT verified: nextpnr-ecp5 build/version difference between
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this session's toolchain (OSS CAD Suite, nextpnr-0.11.1-27-g6030081a)
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and whatever build produced DEC-0042's numbers (version not recorded
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in any prior log entry) -- placer heuristics/effort can genuinely
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differ across nextpnr releases for the same netlist+constraints.
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DECISION: treat THIS session's 8-seed numbers (worst 81.20MHz, mean
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91.05MHz, 8/8 PASS) as the operative Phase-0 BASELINE for judging
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Phase 1 interventions going forward, since they are the ones this
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session's own toolchain will keep reproducing -- but do not claim
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DEC-0042's specific historical numbers are wrong; both may be real
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under their own respective toolchains. See sweep_results.md (Phase 4)
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BASELINE row.
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STATUS: N_SLOTS=4 baseline established (8/8 PASS @ 64MHz, real
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board-level top+constraints). N_SLOTS=8 baseline deferred (user
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request, 2026-09-15) after an N=8 P&R run against the WRONG target
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(the obsolete wrapper, since discarded) stalled for 2h42m without
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converging on a single seed -- to be re-attempted against the correct
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fpga_neural_v2_top target, with a time budget decided before re-running.
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