docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM
sweep). Phase 0: no RTL changes, only measure the current baseline.

ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz,
a leftover from the STEP19 freeze, never updated to the project's real
64MHz target -- fixed (LPF only, zero RTL/datapath effect).

ERR-0031 (bigger one): the first two synthesis attempts targeted
nms_neural_multiprocessor_sdram_unified.v, which is NOT the real
board-level top -- it's an obsolete wrapper only exercised by one
testbench now. The real target is fpga_neural_v2_top.v (adds the real
PLL, reset_sync, spi_host_bridge, and a second arbitration level), which
is what actually goes through synthesis+P&R for hardware. Re-targeted
correctly, matched against constraints/v2_board_top.lpf (all 17 ports
real-ball-assigned).

An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m
without converging on a single seed; discarded rather than trusted.
N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is
fully understood -- re-attempt against the correct fpga_neural_v2_top
target with an agreed time budget.

Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4
8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than
DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL --
disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version
difference), adopted as the operative baseline for this session's
toolchain going forward. Full writeup in errors.log/timing.log/
experiments.log (EXP-0049).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

hardware/v2/constraints/v2_unified.lpf

@@ -32,7 +32,15 @@
 BLOCK ASYNCPATHS;
 BLOCK RESETPATHS;
 
-FREQUENCY PORT "clk" 80 MHZ;
+// Updated from the STEP19 freeze's original 80 MHz to the project's
+// current 64 MHz target (see decisions.log DEC-0038+/errors.log
+// ERR-0029/DEC-0042): this file's own FREQUENCY directive was never
+// bumped down when the achievable target moved from 80 to 64 MHz,
+// silently making every nextpnr PASS/FAIL label using this LPF report
+// against the wrong, stale bar (only the achieved MHz number itself
+// was real; the FAIL/PASS annotation next to it was not) -- see
+// errors.log for the disclosed fix.
+FREQUENCY PORT "clk" 64 MHZ;
 
 LOCATE COMP "clk" SITE "H5";
 IOBUF PORT "clk" IO_TYPE=LVCMOS33;