feat: extend neuron_memory to support N_NEURONS>1 (Phase 3)

neuron_memory.v only handled a single neuron. Added an N_NEURONS
parameter (default 1, fully backward compatible) and a memory-bound
neuron loop: X is read once (shared layer input), and for each
neuron in turn W and bias are re-read from PSRAM and fed to a
single, reused neuron_parallel instance -- no change to the
validated compute datapath (neuron_parallel/mac8/mac_unit).

Addressing follows layer.v's neuron-major convention: neuron n's
weights live at w_base + n*N_INPUTS bytes, its bias at
bias_addr + n. Output changed from a single `y` port to a packed
`y_bus` (DATA_WIDTH*N_NEURONS bits, neuron-major), matching
layer.v's y_bus.

- rtl/neuron_memory.v: N_NEURONS parameter, neuron_index/
  w_group_base/bias_group_addr tracking, y_reg[] array assembled
  into y_bus, STATE_WAIT_N now loops back to STATE_READ_W for the
  next neuron instead of finishing after one.
- sim/neuron_memory_tb.v: updated to the new y_bus port
  (N_NEURONS=1 explicit); all 5 existing tests still pass unchanged,
  confirming backward compatibility.
- sim/neuron_memory_multi_tb.v: new end-to-end test (full
  memory_interface + psram_controller + psram_model stack) with
  N_NEURONS=3, validating per-neuron addressing and a single done
  pulse at the end of the sequence (scale, larger value, ReLU).
- Full regression re-run: all existing testbenches still pass.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt

docs/FPGA-NeuralNetwork-Engine.md

@@ -639,6 +639,27 @@ Define:
 - memory addressing;
 - bandwidth requirements.
 
+- [x] `neuron_memory.v`: single-neuron memory integration (N_NEURONS=1)
+- [x] `neuron_memory.v`: multi-neuron memory integration (N_NEURONS>1)
+- [ ] Intermediate/multi-layer buffers (deferred to Phase 5)
+- [ ] Bandwidth analysis against PSRAM timing (deferred to Phase 7)
+
+**Multi-neuron design (2026-09-02):** `neuron_memory.v` now takes an
+`N_NEURONS` parameter and loops over neurons in memory: `X` is read
+once (shared input vector), and for each neuron in turn `W` and
+`bias` are re-read from PSRAM and fed to a single, reused
+`neuron_parallel` instance — memory-bound by design, one neuron
+computed at a time, no change to the validated compute datapath.
+Addressing follows the same neuron-major convention as `layer.v`:
+neuron `n`'s weights live at `w_base + n*N_INPUTS` bytes, its bias at
+`bias_addr + n`. Output is now `y_bus` (packed, `DATA_WIDTH*N_NEURONS`
+bits, neuron-major), replacing the old single-neuron `y` port.
+Validated end to end through the full memory stack
+(`memory_interface` + `psram_controller` + `psram_model`) in
+`sim/neuron_memory_multi_tb.v` (N_NEURONS=3: scale, larger value,
+ReLU). `sim/neuron_memory_tb.v` (N_NEURONS=1) still passes unchanged,
+confirming backward compatibility.
+
 ## Phase 4 — SPI Interface
 
 Implement: