perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
Implements optimization #2 from the final benchmark campaign's own recommendation, on top of DEC-0015's word-level burst rewrite: a new shared activation_cache.v module fetches a given activation (X) vector from PSRAM once instead of once per neuron sharing it - the exact redundant traffic pattern the dense-layer workloads in this project's benchmark suite exhibit. Each memory_manager's own prefetch_engine now fetches WEIGHTS only; the activation half is requested from the shared cache instead (single-tag, tile-granular, N_SLOTS request ports, its own real word-level PSRAM backend via a new dedicated arbiter port). dataflow_core.v/slot_mem_arbiter.v/neural_multiprocessor.v widened to N_SLOTS+1 ports to arbitrate the cache's traffic alongside each slot's weight traffic. Two real bugs found and fixed during implementation (ERR-0010): a target-bank/pending-bank race in memory_manager.v's activation-cache wiring (the same bug class ERR-0006 already fixed once for pf_target_bank - a later handoff's queued request can overwrite which bank an earlier, still-in-flight request's ack applies to), and a repeat of ERR-0009's N_SLOTS=1 zero-width replication bug in activation_cache.v itself. Real, measured results: the full final-benchmark campaign (24/24 workload/config combinations) re-verified bit-exact. D-Stress cycles fall a further 1.66-2.00x on top of DEC-0015 (~4x combined vs the original byte-level baseline). But the cache's real Fmax cost is much steeper than DEC-0015's own: N_SLOTS=2 (the recommended default, DEC-0014) drops from 133.58 to 87.72 MHz (-34%, margin over 80MHz shrinks from +67% to +9.7%), and N_SLOTS=4 drops to 65.01 MHz - now FAILING the 80MHz target it previously passed. Combined real wall-clock speedup vs the original baseline: N=1 3.86x, N=2 2.45x (both real net wins); N=4 is a real regression once its own now-failing Fmax is honestly used, though N=4 was never the recommended configuration. N_SLOTS=2 remains the recommended default (DEC-0014 unaffected) with a thinner but still real Fmax margin. Cache hit-detection pipelining is flagged as concrete follow-up work if N_SLOTS>2 is ever needed with the cache active - not attempted this round. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0016)/ experiments (EXP-0016)/errors (ERR-0010)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
@@ -34,19 +34,32 @@
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// component gluing the two together.
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//
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// Scope (see hardware/v2/logs/decisions.log DEC-0009):
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// - activation_buffer.v/weight_buffer.v/result_buffer.v (M3) are NOT
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// instantiated inside dataflow_core yet -- they belong on the OTHER
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// side of the Memory Backend Interface (§15's own diagram: Memory
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// Manager -> Memory Backend Interface -> PSRAM Controller), and
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// each memory_manager instance already owns its own prefetch double
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// buffer (M4) for the fast path. Wiring the M3 buffers in as a
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// shared on-chip cache in front of PSRAM is real future work, not
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// done here (no measured need for it yet, §22/§30).
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// - each slot's byte-level Memory Backend Interface port is exposed
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// SEPARATELY (N_SLOTS independent ports) rather than arbitrated
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// down to one shared PSRAM master -- real PSRAM integration
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// (including whatever arbitration N_SLOTS>1 requires) is explicitly
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// M8's job, not this one's.
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// - activation_buffer.v/weight_buffer.v/result_buffer.v (M3, BRAM-
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// backed FIFOs) are NOT instantiated here -- superseded by a
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// different, measurement-driven shared cache (activation_cache.v,
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// post-M10 DEC-0016, see below), not the original M3 modules
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// themselves.
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// - each slot's Memory Backend Interface port is exposed SEPARATELY
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// (N_SLOTS independent ports) rather than arbitrated down to one
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// shared PSRAM master -- real PSRAM integration (including whatever
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// arbitration N_SLOTS>1 requires) is done one level up, in
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// neural_multiprocessor.v (M8).
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//
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// Post-M10 (decisions.log DEC-0016): a single shared activation_cache
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// instance sits alongside the N_SLOTS memory_managers, serving the
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// ACTIVATION (X) half of each tile fetch -- in the realistic dense-
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// layer workloads this project benchmarks, many neurons share the
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// exact same X vector, and fetching it from PSRAM once instead of
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// once per memory_manager instance is real, measured, redundant-
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// traffic elimination (see hardware/v2/docs/benchmarks/
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// final-benchmark.md's own recommendation #2). Each memory_manager's
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// own prefetch_engine now fetches WEIGHTS only. The exposed
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// slot_mem_* arrays are sized N_SLOTS+1: indices [0, N_SLOTS) are the
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// per-slot memory_managers' own weight+write-back backend ports
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// (unchanged in spirit from before), index [N_SLOTS] is the shared
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// activation_cache's own backend port -- all N_SLOTS+1 arbitrated
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// together by neural_multiprocessor.v's slot_mem_arbiter.v (N_PORTS
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// widened to N_SLOTS+1 there to match).
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// ================================================================
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module dataflow_core #(
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@@ -73,19 +86,20 @@ module dataflow_core #(
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input wire [15:0] reg_n_tiles,
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input wire [ADDR_WIDTH-1:0] reg_result_addr,
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// ---- per-slot Memory Backend Interface (arrayed, one per slot --
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// see file header on why arbitration to one shared PSRAM port is
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// NOT done here). WORD-level (16-bit) post-M10 (decisions.log
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// DEC-0015) -- see memory_manager.v/prefetch_engine.v's own
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// headers for why. ----
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output wire [N_SLOTS-1:0] slot_mem_req,
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output wire [N_SLOTS-1:0] slot_mem_wr,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr, // WORD address
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output wire [16*N_SLOTS-1:0] slot_mem_wdata,
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output wire [N_SLOTS-1:0] slot_mem_lb_n,
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output wire [N_SLOTS-1:0] slot_mem_ub_n,
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input wire [16*N_SLOTS-1:0] slot_mem_rdata,
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input wire [N_SLOTS-1:0] slot_mem_ready
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// ---- Memory Backend Interface, arrayed N_SLOTS+1 wide (see file
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// header: indices [0,N_SLOTS) are the per-slot memory_managers'
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// own weight+write-back ports, index [N_SLOTS] is the shared
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// activation_cache's own port). WORD-level (16-bit) post-M10
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// (decisions.log DEC-0015) -- see memory_manager.v/
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// prefetch_engine.v's own headers for why. ----
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output wire [N_SLOTS:0] slot_mem_req,
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output wire [N_SLOTS:0] slot_mem_wr,
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output wire [ADDR_WIDTH*(N_SLOTS+1)-1:0] slot_mem_addr, // WORD address
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output wire [16*(N_SLOTS+1)-1:0] slot_mem_wdata,
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output wire [N_SLOTS:0] slot_mem_lb_n,
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output wire [N_SLOTS:0] slot_mem_ub_n,
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input wire [16*(N_SLOTS+1)-1:0] slot_mem_rdata,
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input wire [N_SLOTS:0] slot_mem_ready
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);
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localparam NODE_IDW = $clog2(N_NODES);
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@@ -153,6 +167,14 @@ module dataflow_core #(
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assign dm_producer_done_valid = dir_job_out_done;
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assign dm_producer_done_node_id = completed_node_id_16[NODE_IDW-1:0];
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// ---- shared activation_cache request bus (one port per slot,
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// collected here for the cache instance below) ----
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wire [N_SLOTS-1:0] xc_req;
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wire [ADDR_WIDTH*N_SLOTS-1:0] xc_x_base;
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wire [16*N_SLOTS-1:0] xc_tile_idx;
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wire [N_SLOTS-1:0] xc_ack;
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wire signed [DATA_WIDTH*P_IN*N_SLOTS-1:0] xc_tile_x;
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// ---- N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)) ----
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genvar g;
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generate
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@@ -177,6 +199,11 @@ module dataflow_core #(
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.operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready),
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.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
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.result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data),
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.xc_req(xc_req[g]),
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.xc_x_base(xc_x_base[g*ADDR_WIDTH +: ADDR_WIDTH]),
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.xc_tile_idx(xc_tile_idx[g*16 +: 16]),
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.xc_ack(xc_ack[g]),
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.xc_tile_x(xc_tile_x[g*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.mem_req(slot_mem_req[g]), .mem_wr(slot_mem_wr[g]),
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.mem_addr(slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
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.mem_wdata(slot_mem_wdata[g*16 +: 16]),
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@@ -215,4 +242,21 @@ module dataflow_core #(
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end
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endgenerate
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// ---- shared activation_cache (M10+, DEC-0016) -- serves the
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// ACTIVATION half of every slot's tile fetch, using arbiter port
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// index N_SLOTS (the last one) for its own PSRAM traffic on a
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// cache miss. ----
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activation_cache #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS)
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) u_activation_cache (
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.clk(clk), .rst(rst),
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.req(xc_req), .req_x_base(xc_x_base), .req_tile_idx(xc_tile_idx),
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.ack(xc_ack), .tile_x_out(xc_tile_x),
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.mem_req(slot_mem_req[N_SLOTS]), .mem_wr(slot_mem_wr[N_SLOTS]),
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.mem_addr(slot_mem_addr[N_SLOTS*ADDR_WIDTH +: ADDR_WIDTH]),
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.mem_wdata(slot_mem_wdata[N_SLOTS*16 +: 16]),
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.mem_lb_n(slot_mem_lb_n[N_SLOTS]), .mem_ub_n(slot_mem_ub_n[N_SLOTS]),
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.mem_rdata(slot_mem_rdata[N_SLOTS*16 +: 16]), .mem_ready(slot_mem_ready[N_SLOTS])
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);
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endmodule
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