perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)

Implements optimization #2 from the final benchmark campaign's own
recommendation, on top of DEC-0015's word-level burst rewrite: a new
shared activation_cache.v module fetches a given activation (X)
vector from PSRAM once instead of once per neuron sharing it - the
exact redundant traffic pattern the dense-layer workloads in this
project's benchmark suite exhibit.

Each memory_manager's own prefetch_engine now fetches WEIGHTS only;
the activation half is requested from the shared cache instead
(single-tag, tile-granular, N_SLOTS request ports, its own real
word-level PSRAM backend via a new dedicated arbiter port).
dataflow_core.v/slot_mem_arbiter.v/neural_multiprocessor.v widened to
N_SLOTS+1 ports to arbitrate the cache's traffic alongside each
slot's weight traffic.

Two real bugs found and fixed during implementation (ERR-0010): a
target-bank/pending-bank race in memory_manager.v's activation-cache
wiring (the same bug class ERR-0006 already fixed once for
pf_target_bank - a later handoff's queued request can overwrite which
bank an earlier, still-in-flight request's ack applies to), and a
repeat of ERR-0009's N_SLOTS=1 zero-width replication bug in
activation_cache.v itself.

Real, measured results: the full final-benchmark campaign (24/24
workload/config combinations) re-verified bit-exact. D-Stress cycles
fall a further 1.66-2.00x on top of DEC-0015 (~4x combined vs the
original byte-level baseline). But the cache's real Fmax cost is much
steeper than DEC-0015's own: N_SLOTS=2 (the recommended default,
DEC-0014) drops from 133.58 to 87.72 MHz (-34%, margin over 80MHz
shrinks from +67% to +9.7%), and N_SLOTS=4 drops to 65.01 MHz - now
FAILING the 80MHz target it previously passed. Combined real
wall-clock speedup vs the original baseline: N=1 3.86x, N=2 2.45x
(both real net wins); N=4 is a real regression once its own now-failing
Fmax is honestly used, though N=4 was never the recommended
configuration.

N_SLOTS=2 remains the recommended default (DEC-0014 unaffected) with
a thinner but still real Fmax margin. Cache hit-detection pipelining
is flagged as concrete follow-up work if N_SLOTS>2 is ever needed with
the cache active - not attempted this round.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0016)/
experiments (EXP-0016)/errors (ERR-0010)/development.log, ROADMAP.md
updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/ROADMAP.md

@@ -116,6 +116,28 @@ DEC-0014). Report completo (21 sezioni, THEORETICAL/SIMULATED/
 POST-P&R/DERIVED classificati): `hardware/v2/docs/benchmarks/
 final-benchmark.md`.
 
+### Ottimizzazioni post-campagna (su richiesta utente)
+
+Implementate entrambe le raccomandazioni #1/#2 del report:
+1. **Burst a livello di parola** (`prefetch_engine.v`/`memory_manager.v`
+   parlano direttamente il protocollo a 16 bit di `memory_interface.v`,
+   bypassando `int8_memory_access.v` -- ancora congelato, semplicemente
+   non piu' istanziato in questo percorso). Reale: -49/-56% cicli sui
+   job singoli, 2.24-2.37x speedup wall-clock reale sull'intera
+   campagna. `logs/decisions.log` DEC-0015.
+2. **Cache condivisa on-chip per il vettore di attivazione** (nuovo
+   `activation_cache.v`, evita che neuroni con lo stesso `x_base`
+   rileggano X da PSRAM). Reale: ulteriore -1.66/-2.00x cicli. MA costo
+   Fmax reale molto piu' ripido del previsto: N_SLOTS=4 ora FALLISCE il
+   target 80MHz (65.01 MHz, prima passava). N_SLOTS=2 (default
+   raccomandato) resta valido con margine piu' sottile (87.72 MHz).
+   Speedup wall-clock reale combinato (#1+#2) vs baseline originale:
+   N=1 3.86x, N=2 2.45x. `logs/decisions.log` DEC-0016.
+
+Trovati e risolti 3 bug RTL reali durante l'implementazione
+(`logs/errors.log` ERR-0009, ERR-0010). 24/24 combinazioni
+workload/config ancora bit-exact dopo entrambe le ottimizzazioni.
+
 ## Log
 
 Vedi `hardware/v2/logs/` (`development.log` per la cronologia di sessione,