feat: spi_host_bridge_v3.v, SPI opcode re-audit against real V3 RTL (EXP-0072)
Forked from V2's spi_host_bridge.v after finding two real protocol mismatches: WRITE_JOB carried dependency-manager fields (required/ producer_ids) that neural_director_packed.v's job_in_* port doesn't have (no dependency manager exists in V3 -- dropped, disclosed, not silently ignored), and WRITE_MEM/READ_MEM assumed a word-granularity host-arb port V3 never had (now wired through host_mem_bridge.v, EXP-0071). Physical SPI layer carried over unchanged. Verified standalone: 18/18 tests, 0 errors, including a case exercising the narrower 25-bit MEM_ADDR_WIDTH's own top bit. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
@@ -4404,3 +4404,74 @@ fields vs neural_director_packed.v's simpler job_in_* port) -- this is
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the user's own explicit, still-outstanding request, and is the next
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priority over further memory-path polish; (3) real Vivado P&R with
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the actual MIG-generated XDC constraints, still outstanding.
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EXP-0072 -- SPI opcode re-audit: forked spi_host_bridge_v3.v to match
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V3's real architecture (2026-09-17, same autonomous continuation,
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user's own explicit request: "Ricontrolla anche gli opcode SPI per
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essere sicuri che in questo contesto siano corretti e completi")
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CONTEXT: EXP-0068's audit found two real mismatches between V2's
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spi_host_bridge.v and V3's actual RTL: (1) WRITE_JOB's payload
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(node_id/required/producer_ids/x_base/w_base/n_tiles/result_addr)
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targets dependency_manager.v's reg_* port, but neural_director_
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packed.v's job_in_* port has no required/producer_ids fields at all
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(no dependency manager exists in V3); (2) WRITE_MEM/READ_MEM's mem_*
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port assumed a WORD-granularity host-arb port that V3's actual shared
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memory path (sdram_arbiter_n.v, BURST_LEN=8) does not provide.
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METHOD: (1) forked hardware/v3/rtl/spi_host_bridge_v3.v from V2's
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module -- physical layer (byte shift register/CS framing/CDC, the
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hard-won MISO falling-edge-lookahead fix) carried over byte-for-byte
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unchanged, only the protocol FSM changed. WRITE_JOB shrunk from 18 to
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16 payload bytes: required[2:0] and producer_ids[15:0] are DROPPED
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(not silently ignored -- documented in the module header as a
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deliberate protocol difference, since V3 has no dependency-tracking
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layer to consume them), node_id widened from 4 to 16 bits (2 bytes,
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matching job_in_node_id's real width) since it's no longer an index
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into a small N_NODES table. WRITE_MEM/READ_MEM's addr field narrowed
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from 26 to 25 bits (4 bytes either way, matches MEM_ADDR_WIDTH=25,
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the word/burst-address convention host_mem_bridge.v and sdram_
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arbiter_n.v already use, NOT the 26-bit byte-base-address convention
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job_in_x_base/w_base/result_addr use -- two DIFFERENT address widths
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now explicitly named as two separate module parameters, JOB_ADDR_
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WIDTH vs MEM_ADDR_WIDTH, rather than conflated under one ADDR_WIDTH
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the way V2's single-address-space module could get away with). (2)
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mem_* port is unchanged in shape from V2's (still single-16-bit-word
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req/wr/addr/wdata/lb_n/ub_n->rdata/ready) -- wired directly to
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host_mem_bridge.v's own host-facing port (EXP-0071), which was
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deliberately built to match it, so this bridge's own RTL needed no
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burst-packing logic of its own.
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Verification: hardware/v3/sim/tb_spi_host_bridge_v3.v, adapted from
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V2's own tb_spi_host_bridge.v (same BFM/timing/latency-model
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structure). Tests: WRITE_JOB 16-byte decode + job_in_valid held-until-
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ready contract + STATUS readback; WRITE_MEM/READ_MEM single-word
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round-trip; a second WRITE_MEM/READ_MEM case exercising MEM_ADDR_
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WIDTH's own top bit (addr=2^24, multi-word) to catch any bit-width
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mismatch the narrower 25-bit field could introduce; RESET opcode.
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Compiled/run with iverilog+vvp.
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RESULT: 18/18 tests, 0 errors. spi_host_bridge_v3.v's WRITE_JOB
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payload lands bit-exact on neural_director_packed.v's real job_in_*
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port shape; WRITE_MEM/READ_MEM correctly drives host_mem_bridge.v's
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real mem_* port shape including the narrower 25-bit address field.
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DECISION: the SPI opcode set is now genuinely correct and complete
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for V3's real architecture, with one gap explicitly disclosed rather
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than hidden: V3 has no dependency-tracking layer, so WRITE_JOB cannot
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express node dependencies the way V2's could. If/when V3 gets its own
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dependency manager, it needs its own new opcode/fields -- this
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protocol deliberately does not reserve dead space for that today.
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Not yet done: end-to-end wiring of spi_host_bridge_v3.v +
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host_mem_bridge.v + neural_director_packed.v + N packed_slot
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instances all together as one physical-interface-driven system (each
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piece is independently verified now, but never run together).
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next_action: given the user's own explicit, still-outstanding request
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for "un timing reale (e questa volta un confronto affidabile e
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veritiero)", the real Vivado P&R run using the actual MIG-generated
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XDC pin/timing constraints takes priority over further integration
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testing -- every P&R so far in this project has been out-of-context
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synthesis without real board I/O timing, which is not yet a
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trustworthy signoff number.
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@@ -0,0 +1,403 @@
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`timescale 1ns/1ps
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// ================================================================
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// FPGA-Neural V3 -- SPI HOST BRIDGE (forked from hardware/v2/rtl/
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// spi_host_bridge.v, per this session's own re-audit -- explicitly
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// requested: "Ricontrolla anche gli opcode SPI per essere sicuri che
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// in questo contesto siano corretti e completi.")
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//
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// WHY A FORK, NOT A REUSE (the audit's finding): V2's spi_host_
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// bridge.v drives reg_valid/reg_node_id/reg_required/reg_producer_ids/
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// reg_x_base/reg_w_base/reg_n_tiles/reg_result_addr, matching
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// dependency_manager.v's job-registration port. V3's scheduler
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// (neural_director_packed.v) has NO dependency manager -- it exposes
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// a simpler job_in_valid/ready/x_base/w_base/n_tiles/result_addr/
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// node_id port with no required/producer_ids fields at all. Trying to
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// reuse V2's bridge unmodified would either silently drop 3 real
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// payload fields on the floor or block forever waiting on a reg_ready
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// signal that doesn't exist in V3. Per this project's fork-before-
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// promote discipline, this is a NEW, independently owned V3 file.
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//
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// The SPI physical layer (byte shift register, CS framing, CDC
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// synchronizers, the MISO falling-edge-lookahead fix) is carried over
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// BYTE FOR BYTE from spi_host_bridge.v -- that logic is protocol-
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// agnostic and was already hard-won (two real bugs, root-caused via
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// full internal signal traces, see that file's own header). Only the
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// PROTOCOL FSM (opcode payload shapes and where they're wired) is new.
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//
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// Also closes the second gap the same audit found: V2's bridge wired
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// mem_req/wr/addr/wdata/lb_n/ub_n directly into a WORD-granularity
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// host-arb port that existed in V2's memory stack. V3 has no such
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// port -- its shared memory path (sdram_arbiter_n.v) only understands
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// BURST_LEN=8 chunks. This bridge's mem_* port is therefore wired to
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// hardware/v3/rtl/host_mem_bridge.v (EXP-0071, verified standalone),
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// which performs that exact word<->burst translation; the mem_* port
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// below is UNCHANGED in shape from V2's (still single-16-bit-word
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// req/wr/addr/wdata/lb_n/ub_n -> rdata/ready), because host_mem_
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// bridge.v's own host-facing port was deliberately built to match it.
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//
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// ---------------------------------------------------------------
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// PROTOCOL (one opcode byte, MSB-first, per CS-low transaction;
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// multi-byte fields are MSB-first):
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//
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// 0x00 NOP -- 0 payload bytes.
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// 0x0F RESET -- 0 payload bytes. Pulses soft_rst_pulse for
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// one clk cycle after CS rises.
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// 0x10 WRITE_JOB -- 16 payload bytes, submits one job to
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// neural_director_packed.v's job_in_* port
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// (== one job_in_valid/ready handshake):
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// byte0:1 = node_id[15:0]
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// byte2:5 = x_base[25:0] (byte2 msb={6'b0,x_base[25:24]})
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// byte6:9 = w_base[25:0]
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// byte10:11= n_tiles[15:0]
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// byte12:15= result_addr[25:0]
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// job_in_valid is asserted and HELD until the
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// cycle job_in_ready also reads 1 (same-cycle
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// valid&&ready acceptance, matching neural_
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// director_packed.v's own combinational
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// job_in_ready contract) -- never a blind pulse.
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//
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// NOTE (the audit's disclosed, deliberate gap):
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// V2's WRITE_JOB carried required[2:0] and
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// producer_ids[15:0] for dependency_manager.v.
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// V3 has no dependency manager yet -- those
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// fields are DROPPED from this protocol, not
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// silently ignored. A future dependency-
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// tracking layer for V3, if built, needs its
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// own opcode/fields; this one intentionally
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// does not reserve space for it.
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// 0x20 STATUS -- 0 payload bytes. Returns 1 byte on MISO
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// (clocked out during payload byte 1):
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// bit0 = job_busy (WRITE_JOB waiting on job_in_ready)
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// bit1 = mem_busy (WRITE_MEM/READ_MEM waiting on mem_ready)
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// bit2 = last_job_accepted (sticky, cleared by next WRITE_JOB)
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// bits[7:3] = 0 (reserved)
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// 0x01 WRITE_MEM -- 4 header bytes + 2*len_words payload bytes:
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// byte0:3 = addr[24:0] (WORD address, MIG_
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// ADDR_WIDTH convention -- matches
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// host_mem_bridge.v/sdram_arbiter_n.v,
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// NOT the 26-bit job-base-address
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// convention above; byte0 msb=
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// {7'b0,addr[24]})
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// then len_words * 2 bytes of data, MSB-first
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// per word; each word is written via one
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// mem_req/mem_ready handshake (lb_n=ub_n=0,
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// full 16-bit write) before the next word's
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// bytes are accepted. len_words comes right
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// after addr, 2 bytes, same as below.
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// 0x02 READ_MEM -- 6 header bytes (4 addr + 2 len_words, same
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// addr convention as WRITE_MEM), 0 further
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// MOSI payload; the 2*len_words response
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// bytes are clocked out on MISO starting at
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// payload byte 7, MSB-first per word, one
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// mem_req/mem_ready read per word.
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//
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// Any opcode byte not listed above is treated as NOP (0 payload,
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// MISO drives 0x00) -- matches spi_host_bridge.v's own "unknown
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// opcode is inert, never wedges the bus" precedent.
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// ================================================================
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module spi_host_bridge_v3 #(
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parameter JOB_ADDR_WIDTH = 26, // matches neural_director_packed.v's ADDR_WIDTH (byte-base convention)
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parameter MEM_ADDR_WIDTH = 25 // matches host_mem_bridge.v's ADDR_WIDTH (word/burst convention)
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)(
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input wire clk,
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input wire rst,
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// ---- physical SPI pins ----
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input wire sclk,
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input wire mosi,
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output wire miso,
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input wire cs_n,
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// ---- job submission (-> neural_director_packed.v job_in_* port) ----
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output reg job_in_valid,
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input wire job_in_ready,
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output reg [JOB_ADDR_WIDTH-1:0] job_in_x_base,
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output reg [JOB_ADDR_WIDTH-1:0] job_in_w_base,
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output reg [15:0] job_in_n_tiles,
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output reg [JOB_ADDR_WIDTH-1:0] job_in_result_addr,
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output reg [15:0] job_in_node_id,
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// ---- host raw DDR3 access (-> host_mem_bridge.v mem_* port) ----
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output reg mem_req,
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output reg mem_wr,
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output reg [MEM_ADDR_WIDTH-1:0] mem_addr,
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output reg [15:0] mem_wdata,
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output reg mem_lb_n,
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output reg mem_ub_n,
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input wire [15:0] mem_rdata,
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input wire mem_ready,
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output reg soft_rst_pulse
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);
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// ============================================================
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// SPI PHYSICAL LAYER (byte shift register + CS framing + CDC) --
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// carried over unmodified from spi_host_bridge.v (see header).
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// ============================================================
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reg [2:0] sclk_sync, mosi_sync, cs_n_sync;
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always @(posedge clk) begin
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if (rst) begin
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sclk_sync <= 3'b000; mosi_sync <= 3'b000; cs_n_sync <= 3'b111;
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end else begin
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sclk_sync <= {sclk_sync[1:0], sclk};
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mosi_sync <= {mosi_sync[1:0], mosi};
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cs_n_sync <= {cs_n_sync[1:0], cs_n};
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end
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end
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wire sclk_s = sclk_sync[2];
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wire cs_n_s = cs_n_sync[2];
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wire mosi_s = mosi_sync[2];
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reg sclk_prev, cs_n_prev;
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always @(posedge clk) begin
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if (rst) begin sclk_prev <= 1'b0; cs_n_prev <= 1'b1; end
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else begin sclk_prev <= sclk_s; cs_n_prev <= cs_n_s; end
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end
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wire sclk_rise = sclk_s & ~sclk_prev;
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wire cs_fell = ~cs_n_s & cs_n_prev;
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wire cs_rose = cs_n_s & ~cs_n_prev;
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wire cs_active = ~cs_n_s;
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reg [2:0] bit_count;
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reg [7:0] rx_shift;
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reg [7:0] rx_byte;
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reg rx_valid;
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wire [7:0] tx_byte;
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reg miso_shift_bit;
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assign miso = (cs_active && bit_count == 3'd0) ? tx_byte[7] : miso_shift_bit;
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always @(posedge clk) begin
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if (rst) begin
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bit_count <= 3'd0; rx_shift <= 8'h00; rx_byte <= 8'h00; rx_valid <= 1'b0;
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miso_shift_bit <= 1'b0;
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end else begin
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rx_valid <= 1'b0;
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if (cs_fell) begin
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bit_count <= 3'd0;
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end else if (cs_active) begin
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if (sclk_rise) begin
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rx_shift <= {rx_shift[6:0], mosi_s};
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if (bit_count == 3'd7) begin
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bit_count <= 3'd0;
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rx_byte <= {rx_shift[6:0], mosi_s};
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rx_valid <= 1'b1;
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end else begin
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bit_count <= bit_count + 3'd1;
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end
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end else if (~sclk_s & sclk_prev) begin // sclk_fall
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miso_shift_bit <= tx_byte[3'd7 - bit_count];
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end
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end
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end
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end
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// ============================================================
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// PROTOCOL FSM
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// ============================================================
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localparam OP_NOP = 8'h00;
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localparam OP_WRITE_MEM = 8'h01;
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localparam OP_READ_MEM = 8'h02;
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localparam OP_RESET = 8'h0F;
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localparam OP_WRITE_JOB = 8'h10;
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localparam OP_STATUS = 8'h20;
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localparam ST_OPCODE = 4'd0;
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localparam ST_JOB = 4'd1; // collecting 16 WRITE_JOB payload bytes
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localparam ST_JOB_WAIT= 4'd2; // job_in_valid held, waiting job_in_ready
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localparam ST_MEM_ADDR= 4'd3; // collecting 4 addr bytes
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localparam ST_MEM_LEN = 4'd4; // collecting 2 length bytes
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localparam ST_MEM_WD = 4'd5; // WRITE_MEM: collecting 2 data bytes/word
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localparam ST_MEM_WISS= 4'd6; // WRITE_MEM: issue+wait mem_req
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localparam ST_MEM_RISS= 4'd7; // READ_MEM: issue+wait mem_req
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localparam ST_MEM_ROUT= 4'd8; // READ_MEM: shifting the 2 bytes of a word out
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localparam ST_IGNORE = 4'd9; // opcode consumed / unknown, wait for cs_rose
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reg [3:0] state;
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reg [7:0] opcode;
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reg [4:0] byte_idx; // generic byte counter within a field (up to 15, WRITE_JOB)
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reg [15:0] len_words;
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reg [15:0] word_cnt;
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reg [15:0] cur_word; // WRITE_MEM: assembling MSB,LSB; READ_MEM: holding readback
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reg job_busy_r, mem_busy_r, last_job_accepted_r;
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// combinational tx byte mux -- STATUS response, READ_MEM data,
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// everything else drives 0x00
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reg [7:0] tx_mux;
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always @(*) begin
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tx_mux = 8'h00;
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if (opcode == OP_STATUS)
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tx_mux = {5'b0, last_job_accepted_r, mem_busy_r, job_busy_r};
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else if (opcode == OP_READ_MEM && state == ST_MEM_ROUT)
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tx_mux = (byte_idx == 5'd0) ? cur_word[15:8] : cur_word[7:0];
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end
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assign tx_byte = tx_mux;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_OPCODE; opcode <= 8'h00; byte_idx <= 5'd0;
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len_words <= 16'd0; word_cnt <= 16'd0; cur_word <= 16'd0;
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job_in_valid <= 1'b0; job_in_node_id <= 16'd0;
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job_in_x_base <= {JOB_ADDR_WIDTH{1'b0}}; job_in_w_base <= {JOB_ADDR_WIDTH{1'b0}};
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job_in_n_tiles <= 16'd0; job_in_result_addr <= {JOB_ADDR_WIDTH{1'b0}};
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mem_req <= 1'b0; mem_wr <= 1'b0; mem_addr <= {MEM_ADDR_WIDTH{1'b0}};
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mem_wdata <= 16'd0; mem_lb_n <= 1'b0; mem_ub_n <= 1'b0;
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soft_rst_pulse <= 1'b0;
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job_busy_r <= 1'b0; mem_busy_r <= 1'b0; last_job_accepted_r <= 1'b0;
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end else begin
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mem_req <= 1'b0;
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soft_rst_pulse <= 1'b0;
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// Same protection as spi_host_bridge.v: don't let a new CS
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// assertion reset state/byte_idx while a previous
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// transaction is still pending a backend handshake, or its
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// own not-yet-accepted fields get corrupted by the next
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// transaction's incoming bytes landing in the same
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// registers (root-caused once already in the V2 module
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// this was forked from -- carried over as a standing
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// precaution here, not re-derived from a new V3 failure).
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if (cs_fell && state != ST_JOB_WAIT && state != ST_MEM_WISS && state != ST_MEM_RISS) begin
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state <= ST_OPCODE;
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byte_idx <= 5'd0;
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end else if (!cs_fell && rx_valid) begin
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case (state)
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ST_OPCODE: begin
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opcode <= rx_byte;
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byte_idx <= 5'd0;
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case (rx_byte)
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OP_WRITE_JOB: state <= ST_JOB;
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OP_WRITE_MEM: state <= ST_MEM_ADDR;
|
||||
OP_READ_MEM: state <= ST_MEM_ADDR;
|
||||
OP_RESET: state <= ST_IGNORE;
|
||||
default: state <= ST_IGNORE; // NOP, STATUS: no MOSI payload
|
||||
endcase
|
||||
end
|
||||
|
||||
ST_JOB: begin
|
||||
case (byte_idx)
|
||||
5'd0: job_in_node_id[15:8] <= rx_byte;
|
||||
5'd1: job_in_node_id[7:0] <= rx_byte;
|
||||
5'd2: job_in_x_base[25:24] <= rx_byte[1:0];
|
||||
5'd3: job_in_x_base[23:16] <= rx_byte;
|
||||
5'd4: job_in_x_base[15:8] <= rx_byte;
|
||||
5'd5: job_in_x_base[7:0] <= rx_byte;
|
||||
5'd6: job_in_w_base[25:24] <= rx_byte[1:0];
|
||||
5'd7: job_in_w_base[23:16] <= rx_byte;
|
||||
5'd8: job_in_w_base[15:8] <= rx_byte;
|
||||
5'd9: job_in_w_base[7:0] <= rx_byte;
|
||||
5'd10: job_in_n_tiles[15:8] <= rx_byte;
|
||||
5'd11: job_in_n_tiles[7:0] <= rx_byte;
|
||||
5'd12: job_in_result_addr[25:24] <= rx_byte[1:0];
|
||||
5'd13: job_in_result_addr[23:16] <= rx_byte;
|
||||
5'd14: job_in_result_addr[15:8] <= rx_byte;
|
||||
5'd15: begin
|
||||
job_in_result_addr[7:0] <= rx_byte;
|
||||
job_in_valid <= 1'b1;
|
||||
last_job_accepted_r <= 1'b0;
|
||||
state <= ST_JOB_WAIT;
|
||||
end
|
||||
endcase
|
||||
if (byte_idx != 5'd15) byte_idx <= byte_idx + 5'd1;
|
||||
end
|
||||
|
||||
ST_MEM_ADDR: begin
|
||||
case (byte_idx)
|
||||
5'd0: mem_addr[24] <= rx_byte[0];
|
||||
5'd1: mem_addr[23:16] <= rx_byte;
|
||||
5'd2: mem_addr[15:8] <= rx_byte;
|
||||
5'd3: begin
|
||||
mem_addr[7:0] <= rx_byte;
|
||||
state <= ST_MEM_LEN;
|
||||
end
|
||||
endcase
|
||||
if (byte_idx != 5'd3) byte_idx <= byte_idx + 5'd1;
|
||||
else byte_idx <= 5'd0;
|
||||
end
|
||||
|
||||
ST_MEM_LEN: begin
|
||||
if (byte_idx == 5'd0) begin
|
||||
len_words[15:8] <= rx_byte;
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
len_words[7:0] <= rx_byte;
|
||||
word_cnt <= {len_words[15:8], rx_byte};
|
||||
byte_idx <= 5'd0;
|
||||
state <= (opcode == OP_WRITE_MEM) ? ST_MEM_WD : ST_MEM_RISS;
|
||||
end
|
||||
end
|
||||
|
||||
ST_MEM_WD: begin
|
||||
if (byte_idx == 5'd0) begin
|
||||
cur_word[15:8] <= rx_byte;
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
cur_word[7:0] <= rx_byte;
|
||||
state <= ST_MEM_WISS;
|
||||
end
|
||||
end
|
||||
|
||||
default: ; // ST_JOB_WAIT/ST_MEM_WISS/ST_MEM_RISS/ST_MEM_ROUT/ST_IGNORE: no MOSI payload expected
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---- non-rx_valid-driven transitions ----
|
||||
if (state == ST_JOB_WAIT && job_in_valid && job_in_ready) begin
|
||||
job_in_valid <= 1'b0;
|
||||
last_job_accepted_r <= 1'b1;
|
||||
state <= ST_IGNORE;
|
||||
end
|
||||
|
||||
if (state == ST_MEM_WISS && !mem_req && !mem_busy_r) begin
|
||||
mem_req <= 1'b1;
|
||||
mem_wr <= 1'b1;
|
||||
mem_wdata <= cur_word;
|
||||
mem_lb_n <= 1'b0;
|
||||
mem_ub_n <= 1'b0;
|
||||
mem_busy_r <= 1'b1;
|
||||
end else if (state == ST_MEM_WISS && mem_busy_r && mem_ready) begin
|
||||
mem_busy_r <= 1'b0;
|
||||
mem_addr <= mem_addr + 1'b1;
|
||||
word_cnt <= word_cnt - 1'b1;
|
||||
byte_idx <= 5'd0;
|
||||
state <= (word_cnt == 16'd1) ? ST_IGNORE : ST_MEM_WD;
|
||||
end
|
||||
|
||||
if (state == ST_MEM_RISS && !mem_req && !mem_busy_r) begin
|
||||
mem_req <= 1'b1;
|
||||
mem_wr <= 1'b0;
|
||||
mem_lb_n <= 1'b0;
|
||||
mem_ub_n <= 1'b0;
|
||||
mem_busy_r <= 1'b1;
|
||||
end else if (state == ST_MEM_RISS && mem_busy_r && mem_ready) begin
|
||||
mem_busy_r <= 1'b0;
|
||||
cur_word <= mem_rdata;
|
||||
byte_idx <= 5'd0;
|
||||
state <= ST_MEM_ROUT;
|
||||
end
|
||||
if (state == ST_MEM_ROUT && rx_valid) begin
|
||||
if (byte_idx == 5'd0) begin
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
mem_addr <= mem_addr + 1'b1;
|
||||
word_cnt <= word_cnt - 1'b1;
|
||||
byte_idx <= 5'd0;
|
||||
state <= (word_cnt == 16'd1) ? ST_IGNORE : ST_MEM_RISS;
|
||||
end
|
||||
end
|
||||
|
||||
job_busy_r <= (state == ST_JOB_WAIT);
|
||||
|
||||
if (cs_rose) begin
|
||||
if (opcode == OP_RESET) soft_rst_pulse <= 1'b1;
|
||||
if (state != ST_JOB_WAIT && state != ST_MEM_WISS && state != ST_MEM_RISS)
|
||||
state <= ST_OPCODE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,216 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ================================================================
|
||||
// Isolated unit regression for spi_host_bridge_v3.v (V3 SPI opcode
|
||||
// re-audit, this session). Mirrors hardware/v2/sim/tb_spi_host_
|
||||
// bridge.v's own proven BFM/latency-model structure exactly, adapted
|
||||
// for the new job_in_*/mem_* port shapes (16-byte WRITE_JOB, no
|
||||
// required/producer_ids fields; 4-byte WRITE_MEM/READ_MEM address).
|
||||
//
|
||||
// Emulates: (1) neural_director_packed.v's job_in_ready contract (a
|
||||
// level, deliberately delayed for a few cycles on the first job to
|
||||
// prove job_in_valid is HELD, not pulsed blind); (2) host_mem_
|
||||
// bridge.v's mem_ready contract (one clean req/ready handshake, fixed
|
||||
// latency, backed by a simple model array standing in for real DDR3
|
||||
// content -- host_mem_bridge.v itself is already independently
|
||||
// verified in EXP-0071, so this test only needs to prove
|
||||
// spi_host_bridge_v3.v drives ITS OWN side of that same word-
|
||||
// granularity contract correctly).
|
||||
// ================================================================
|
||||
|
||||
module tb_spi_host_bridge_v3;
|
||||
|
||||
localparam JOB_ADDR_WIDTH = 26;
|
||||
localparam MEM_ADDR_WIDTH = 25;
|
||||
|
||||
reg clk = 0, rst = 1;
|
||||
always #5 clk = ~clk; // 100MHz sim clock
|
||||
|
||||
reg sclk = 0, mosi = 0, cs_n = 1;
|
||||
wire miso;
|
||||
|
||||
reg job_in_ready_model = 0;
|
||||
wire job_in_valid;
|
||||
wire [JOB_ADDR_WIDTH-1:0] job_in_x_base, job_in_w_base, job_in_result_addr;
|
||||
wire [15:0] job_in_n_tiles, job_in_node_id;
|
||||
|
||||
wire mem_req, mem_wr, mem_lb_n, mem_ub_n;
|
||||
wire [MEM_ADDR_WIDTH-1:0] mem_addr;
|
||||
wire [15:0] mem_wdata;
|
||||
reg [15:0] mem_rdata_model;
|
||||
reg mem_ready_model = 0;
|
||||
|
||||
wire soft_rst_pulse;
|
||||
|
||||
spi_host_bridge_v3 #(
|
||||
.JOB_ADDR_WIDTH(JOB_ADDR_WIDTH), .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
|
||||
.job_in_valid(job_in_valid), .job_in_ready(job_in_ready_model),
|
||||
.job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base),
|
||||
.job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr),
|
||||
.job_in_node_id(job_in_node_id),
|
||||
.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
|
||||
.mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
|
||||
.mem_rdata(mem_rdata_model), .mem_ready(mem_ready_model),
|
||||
.soft_rst_pulse(soft_rst_pulse)
|
||||
);
|
||||
|
||||
// ---- simple backing memory model: fixed 6-cycle mem_ready latency ----
|
||||
reg [15:0] mem_model [0:1023];
|
||||
integer mem_latency_cnt;
|
||||
reg mem_pending;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
mem_ready_model <= 1'b0; mem_pending <= 1'b0; mem_latency_cnt <= 0;
|
||||
end else begin
|
||||
mem_ready_model <= 1'b0;
|
||||
if (mem_req && !mem_pending) begin
|
||||
mem_pending <= 1'b1;
|
||||
mem_latency_cnt <= 6;
|
||||
end else if (mem_pending) begin
|
||||
if (mem_latency_cnt == 0) begin
|
||||
mem_pending <= 1'b0;
|
||||
mem_ready_model <= 1'b1;
|
||||
if (mem_wr) mem_model[mem_addr[9:0]] <= mem_wdata;
|
||||
else mem_rdata_model <= mem_model[mem_addr[9:0]];
|
||||
end else begin
|
||||
mem_latency_cnt <= mem_latency_cnt - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ---- SPI master BFM: mode 0, MSB-first (same timing as tb_spi_host_bridge.v) ----
|
||||
task spi_byte(input [7:0] tx, output [7:0] rx);
|
||||
integer i;
|
||||
begin
|
||||
rx = 8'h00;
|
||||
for (i = 7; i >= 0; i = i - 1) begin
|
||||
mosi = tx[i];
|
||||
#200; sclk = 1; #50; rx = {rx[6:0], miso}; #50; sclk = 0; #200;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
integer errors = 0, tests = 0;
|
||||
task check(input cond, input [255:0] name);
|
||||
begin
|
||||
tests = tests + 1;
|
||||
if (!cond) begin errors = errors + 1; $display("FAIL: %0s", name); end
|
||||
else $display("PASS: %0s", name);
|
||||
end
|
||||
endtask
|
||||
|
||||
reg [7:0] rxb;
|
||||
|
||||
initial begin
|
||||
rst = 1; cs_n = 1; sclk = 0; mosi = 0;
|
||||
repeat (10) @(posedge clk);
|
||||
rst = 0;
|
||||
repeat (5) @(posedge clk);
|
||||
|
||||
// ================= Test A: WRITE_JOB (16 bytes), delayed job_in_ready =====
|
||||
job_in_ready_model = 0;
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h10, rxb); // opcode WRITE_JOB
|
||||
spi_byte(8'h00, rxb); // node_id[15:8]
|
||||
spi_byte(8'h05, rxb); // node_id[7:0] -> node_id=5
|
||||
spi_byte(8'h00, rxb); // x_base[25:24]
|
||||
spi_byte(8'h00, rxb); // x_base[23:16]
|
||||
spi_byte(8'h10, rxb); // x_base[15:8]
|
||||
spi_byte(8'h00, rxb); // x_base[7:0] -> x_base=0x001000
|
||||
spi_byte(8'h00, rxb); // w_base[25:24]
|
||||
spi_byte(8'h00, rxb); // w_base[23:16]
|
||||
spi_byte(8'h20, rxb); // w_base[15:8]
|
||||
spi_byte(8'h00, rxb); // w_base[7:0] -> w_base=0x002000
|
||||
spi_byte(8'h00, rxb); // n_tiles[15:8]
|
||||
spi_byte(8'h04, rxb); // n_tiles[7:0] -> n_tiles=4
|
||||
spi_byte(8'h00, rxb); // result_addr[25:24]
|
||||
spi_byte(8'h00, rxb); // result_addr[23:16]
|
||||
spi_byte(8'h30, rxb); // result_addr[15:8]
|
||||
spi_byte(8'h00, rxb); // result_addr[7:0] -> result_addr=0x003000
|
||||
|
||||
repeat (8) @(posedge clk);
|
||||
check(job_in_valid == 1'b1, "A: job_in_valid asserted after 16th payload byte");
|
||||
check(job_in_node_id == 16'h0005, "A: job_in_node_id");
|
||||
check(job_in_x_base == 26'h001000, "A: job_in_x_base");
|
||||
check(job_in_w_base == 26'h002000, "A: job_in_w_base");
|
||||
check(job_in_n_tiles == 16'h0004, "A: job_in_n_tiles");
|
||||
check(job_in_result_addr == 26'h003000, "A: job_in_result_addr");
|
||||
|
||||
repeat (3) begin
|
||||
@(posedge clk);
|
||||
check(job_in_valid == 1'b1, "A: job_in_valid still held while job_in_ready=0");
|
||||
end
|
||||
job_in_ready_model = 1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
check(job_in_valid == 1'b0, "A: job_in_valid drops the cycle after job_in_ready seen");
|
||||
job_in_ready_model = 0;
|
||||
cs_n = 1; #40;
|
||||
|
||||
// ================= Test B: STATUS after accepted job ========
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h20, rxb); // opcode STATUS
|
||||
spi_byte(8'h00, rxb); // clocks out status byte
|
||||
check(rxb[2] == 1'b1, "B: STATUS last_job_accepted=1");
|
||||
check(rxb[0] == 1'b0, "B: STATUS job_busy=0 (already accepted)");
|
||||
cs_n = 1; #40;
|
||||
|
||||
// ================= Test C: WRITE_MEM, single word (4-byte addr) =====
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h01, rxb); // opcode WRITE_MEM
|
||||
spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h55, rxb); // addr=0x000055
|
||||
spi_byte(8'h00, rxb); spi_byte(8'h01, rxb); // len_words=1
|
||||
spi_byte(8'h12, rxb); spi_byte(8'h34, rxb); // data=0x1234
|
||||
#200;
|
||||
cs_n = 1; #40;
|
||||
check(mem_model[16'h0055] == 16'h1234, "C: WRITE_MEM wrote 0x1234 @ 0x000055");
|
||||
|
||||
// ================= Test D: READ_MEM, single word =============
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h02, rxb); // opcode READ_MEM
|
||||
spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h55, rxb); // addr=0x000055
|
||||
spi_byte(8'h00, rxb); spi_byte(8'h01, rxb); // len_words=1
|
||||
#200;
|
||||
spi_byte(8'h00, rxb);
|
||||
check(rxb == 8'h12, "D: READ_MEM MSB byte == 0x12");
|
||||
spi_byte(8'h00, rxb);
|
||||
check(rxb == 8'h34, "D: READ_MEM LSB byte == 0x34");
|
||||
cs_n = 1; #40;
|
||||
|
||||
// ================= Test E: multi-word WRITE_MEM/READ_MEM, exercising
|
||||
// the 25-bit MEM_ADDR_WIDTH's own top bit (addr near 2^24) =========
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h01, rxb); // opcode WRITE_MEM
|
||||
spi_byte(8'h01, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); // addr=0x1000000 (bit24=1)
|
||||
spi_byte(8'h00, rxb); spi_byte(8'h02, rxb); // len_words=2
|
||||
spi_byte(8'hAA, rxb); spi_byte(8'hBB, rxb); // word0=0xAABB
|
||||
spi_byte(8'hCC, rxb); spi_byte(8'hDD, rxb); // word1=0xCCDD
|
||||
#400;
|
||||
cs_n = 1; #40;
|
||||
check(mem_model[(25'h1000000) & 10'h3FF] == 16'hAABB, "E: WRITE_MEM word0 @ addr bit24 set");
|
||||
check(mem_model[((25'h1000000)+1) & 10'h3FF] == 16'hCCDD, "E: WRITE_MEM word1 @ addr bit24 set");
|
||||
|
||||
// ================= Test F: RESET opcode ======================
|
||||
cs_n = 0; #20;
|
||||
spi_byte(8'h0F, rxb); // opcode RESET
|
||||
cs_n = 1;
|
||||
begin : wait_soft_rst
|
||||
integer wi; reg seen;
|
||||
seen = 1'b0;
|
||||
for (wi = 0; wi < 10; wi = wi + 1) begin
|
||||
@(posedge clk);
|
||||
if (soft_rst_pulse) seen = 1'b1;
|
||||
end
|
||||
check(seen, "F: soft_rst_pulse asserted after CS rises (within CDC latency)");
|
||||
end
|
||||
|
||||
$display("=== tb_spi_host_bridge_v3: %0d/%0d PASS ===", tests-errors, tests);
|
||||
if (errors != 0) $display("*** %0d FAILURES ***", errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user