From 4c59b7e7c8568e1def562e7030d5dbac41f3b7ab Mon Sep 17 00:00:00 2001 From: manvalan Date: Mon, 21 Sep 2026 08:57:15 +0200 Subject: [PATCH] docs: add preliminary datasheet for FPGA-Neural N8 (semiconductor-style) Standalone LaTeX document (docs/latex/datasheet.tex), styled like an ordinary component/module datasheet (features block, ordering info, block diagram, absolute maximum ratings, recommended operating conditions, pin configuration, timing/resource/performance tables, protocol summary, verification status, BOM, open items, revision history). Marked PRELIMINARY throughout -- the board has not been physically fabricated yet, so electrical/thermal ratings not directly measured by this project defer to the underlying component datasheets (Xilinx DS181, Micron DDR3, Winbond W25Q32JV) rather than being invented. Every timing/resource/verification number is real, sourced from actual P&R and simulation results, matching the rest of the project's own "real numbers only" discipline. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC --- docs/latex/datasheet.tex | 504 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 504 insertions(+) create mode 100644 docs/latex/datasheet.tex diff --git a/docs/latex/datasheet.tex b/docs/latex/datasheet.tex new file mode 100644 index 0000000..381e41d --- /dev/null +++ b/docs/latex/datasheet.tex @@ -0,0 +1,504 @@ +\documentclass[10pt,a4paper]{article} + +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage[margin=1.8cm,top=2.2cm,bottom=2.2cm]{geometry} +\usepackage{booktabs} +\usepackage{longtable} +\usepackage{array} +\usepackage{multicol} +\usepackage{xcolor} +\usepackage{hyperref} +\usepackage{fancyhdr} +\usepackage{titlesec} +\usepackage{enumitem} +\usepackage{colortbl} + +\definecolor{dsblue}{RGB}{20,40,90} +\definecolor{dsgray}{RGB}{90,90,90} +\definecolor{dslight}{RGB}{235,238,244} + +\hypersetup{colorlinks=true,linkcolor=dsblue,urlcolor=dsblue} + +\titleformat{\section}{\normalfont\large\bfseries\color{dsblue}}{\thesection}{0.6em}{} +\titleformat{\subsection}{\normalfont\bfseries\color{dsblue}}{\thesubsection}{0.6em}{} +\titlespacing*{\section}{0pt}{1.4em}{0.6em} +\titlespacing*{\subsection}{0pt}{1.0em}{0.4em} + +\pagestyle{fancy} +\fancyhf{} +\renewcommand{\headrulewidth}{0.6pt} +\renewcommand{\footrulewidth}{0.4pt} +\fancyhead[L]{\small\bfseries FPGA-Neural N8} +\fancyhead[R]{\small PRELIMINARY DATASHEET} +\fancyfoot[L]{\small \copyright\ FPGA-Neural project} +\fancyfoot[C]{\small Rev.\ 1.0 --- 2026-09-21} +\fancyfoot[R]{\small\thepage} + +\setlist[itemize]{leftmargin=1.4em,itemsep=0.15em,topsep=0.2em} + +\newcommand{\prelim}{\textcolor{red!70!black}{\textbf{PRELIMINARY}}} + +\begin{document} + +%====================================================================== +\begin{center} +{\Huge\bfseries\color{dsblue} FPGA-Neural N8}\\[0.3em] +{\Large 8-Channel INT8 Neural Network Inference Accelerator}\\[0.2em] +{\large Custom board module --- Xilinx Artix-7 XC7A100T + DDR3 + ESP32 host}\\[0.6em] +\prelim\ --- Rev.\ 1.0 --- 2026-09-21 +\end{center} + +\vspace{0.4em} +\noindent\rule{\textwidth}{1pt} + +\vspace{0.6em} +\noindent\textbf{Note on document status:} this datasheet describes a +design that has completed real RTL verification and real, in-context +place-and-route timing closure on the actual target device +(XC7A100T-CSG324-2), but has \emph{not yet} been fabricated as a +physical board. Electrical and thermal characteristics not directly +measured on real hardware are explicitly marked \prelim\ or refer to +the underlying component datasheets. Every timing, resource-utilization, +and verification figure in this document is a real, measured result +from RTL simulation or Vivado place-and-route --- none is estimated or +projected, per the project's own engineering discipline. + +\vspace{0.8em} +\section*{Features} +\begin{multicols}{2} +\begin{itemize} + \item 8 parallel INT8 MAC processing elements (PEs), 2 groups of 4, + shared-weight-broadcast systolic architecture + \item 64 DSP48E1 hardware multiply-accumulate slices (2 packed INT8 + MACs per DSP), 26.7\% of device DSP budget + \item 128 MAC/cycle aggregate peak throughput at 155.039\,MHz + ($\sim$19.84 GMAC/s theoretical peak) + \item Real, closed static timing signoff: WNS = 0.000\,ns + (0 failing setup endpoints), WHS = +0.017\,ns + \item 32-bit-wide real DDR3-1600 channel (2$\times$ DDR3 SDRAM), + $\sim$2.48\,GB/s physical bandwidth ceiling + \item Hierarchical 2-level DDR3 arbiter (11 real concurrent requesters) + \item Direct-into-DDR3 result writeback --- no per-core result pins + \item ESP32-S3 host over dedicated management SPI (FPGA is slave) + \item Independent config-flash relay SPI bus (FPGA is master), + zero direct host--flash connection + \item Dual boot path: autonomous Master-SPI boot + JTAG factory/recovery + \item Simple, unchanged host protocol across all core-count variants + (N=2/4/8/16) --- job submission format never changes + \item Register-file host interface (device ID, control, status, + slot count) + \item Active-low sticky interrupt output for interrupt-driven host + firmware +\end{itemize} +\end{multicols} + +\vspace{0.3em} +\section*{General Description} + +FPGA-Neural N8 is a hardware inference accelerator for INT8-quantized +neural networks, implemented on a bare Xilinx Artix-7 XC7A100T FPGA +(no development board) with a real 32-bit DDR3 memory channel and an +ESP32-S3 host processor. The device organizes its compute resources +as \textbf{8 real parallel processing elements}, grouped in pairs of +4 that share a single weight-fetch path per group (a real +shared-weight-broadcast systolic architecture), reducing redundant +DDR3 weight traffic without the complexity of a literal PE-to-PE +systolic pipeline. + +N8 is the current, definitive, real deployment configuration of the +FPGA-Neural family: it is the largest core count in the family that +closes real static timing on the target part with a real, verified +margin. Smaller (N=2, N=4) and larger (N=16) configurations of the +same RTL exist and are documented (see \S\ref{sec:variants}), but N8 +is the one recommended for real board fabrication. + +\clearpage + +%====================================================================== +\section{Ordering / Configuration Information} +\label{sec:variants} + +The same RTL family supports several real, synthesizable core-count +configurations via the top-level \texttt{N\_GROUPS} parameter. Only +N8 has a dedicated, permanent top-level file +(\texttt{n8\_system\_ddr3\_top.v}); other configurations are documented +for reference. + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.15} +\begin{tabular}{lccccl} +\toprule +\textbf{Variant} & \textbf{PEs} & \textbf{DSP48E1} & \textbf{Real WNS} & \textbf{Status} & \textbf{Top-level file} \\ +\midrule +N2 & 2 & 16 & +0.100\,ns & \textbf{Closed, deployable fallback} & \texttt{n2\_system\_ddr3\_top.v} \\ +N4 & 4 & 32 & $-0.005$\,ns & Nearly closed (2 failing endpoints) & \emph{(generic override only)} \\ +\rowcolor{dslight} +N8 & 8 & 64 & \textbf{0.000\,ns} & \textbf{RECOMMENDED --- closed} & \texttt{n8\_system\_ddr3\_top.v} \\ +N16 & 16 & 128 & $-0.338$\,ns & Functional, timing not closed & \texttt{n16\_system\_ddr3\_top.v} \\ +\bottomrule +\end{tabular} +\caption{Real family configurations. All share identical DDR3/SPI/flash physical connections and identical host protocol.} +\end{table} + +%====================================================================== +\section{Functional Block Diagram} + +\begin{center} +\renewcommand{\arraystretch}{1.3} +\begin{tabular}{|p{3.0cm}|p{3.0cm}|p{3.0cm}|p{3.0cm}|} +\hline +\multicolumn{4}{|c|}{\cellcolor{dslight}\textbf{ESP32-S3 Host (management SPI, slave)}} \\ +\hline +\multicolumn{4}{|c|}{\cellcolor{dslight}\texttt{spi\_host\_bridge\_v3.v}} \\ +\hline +\multicolumn{4}{|c|}{\texttt{neural\_director\_grouped.v} (job queue, octet dispatch)} \\ +\hline +\multicolumn{2}{|c|}{\cellcolor{dslight}\textbf{Group 0} (\texttt{systolic\_group.v})} & +\multicolumn{2}{c|}{\cellcolor{dslight}\textbf{Group 1} (\texttt{systolic\_group.v})} \\ +\hline +PE0 & PE1 / PE2 / PE3 & PE0 & PE1 / PE2 / PE3 \\ +\hline +\multicolumn{4}{|c|}{\texttt{sdram\_arbiter\_hier.v} --- hierarchical 2-level arbiter (11 requesters)} \\ +\hline +\multicolumn{4}{|c|}{\texttt{mig\_native\_adapter.v} $\to$ Xilinx MIG (\texttt{mig\_7series\_0})} \\ +\hline +\multicolumn{4}{|c|}{\cellcolor{dslight}\textbf{32-bit real DDR3 channel} (2$\times$ MT41J128M16JT-125:K)} \\ +\hline +\end{tabular} +\end{center} +\vspace{0.4em} +\noindent A parallel, independent path (\texttt{flash\_spi\_master.v}, +FPGA master) connects to the config flash; the ESP32 reaches it only +by relaying bytes through the FPGA over the management SPI bus (no +direct electrical connection). + +%====================================================================== +\section{Absolute Maximum Ratings} + +\begin{center} +\prelim\ --- not yet independently re-characterized on real hardware. +Refer to the underlying component datasheets, which this design's +supply-rail assignments are constrained by: +\end{center} +\begin{itemize} + \item FPGA: Xilinx XC7A100T-2, see Xilinx DS181 (7 Series FPGAs + Data Sheet: DC and Switching Characteristics). + \item DDR3 SDRAM: Micron MT41J128M16JT-125:K, see the Micron DDR3 + SDRAM datasheet for absolute maximum voltage/temperature ratings. + \item Config flash: Winbond W25Q32JVSSIQ, see the Winbond W25Q32JV + datasheet. +\end{itemize} + +%====================================================================== +\section{Recommended Operating Conditions --- Clocking} + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.2} +\begin{tabular}{llll} +\toprule +\textbf{Signal} & \textbf{Description} & \textbf{Value} & \textbf{I/O Standard} \\ +\midrule +\texttt{sys\_clk\_p/n} & DDR3 PHY reference clock, differential & \textbf{310.078\,MHz} (3.225\,ns) & DIFF\_SSTL15, bank 34 \\ +\texttt{clk\_ref\_p/n} & MIG IDELAY reference clock, differential & \textbf{200\,MHz} & LVDS\_25, bank 14 \\ +\texttt{ui\_clk} (internal) & Compute/logic domain (PLL 2:1 from sys\_clk) & \textbf{155.039\,MHz} & --- (internal, not a pin) \\ +\bottomrule +\end{tabular} +\end{table} + +\noindent These frequencies are not a free design choice: they are the +real, unique output of the Xilinx MIG JEDEC/PLL calculator for this +exact part, speed grade, and DDR3 channel width. Substituting a +different \texttt{sys\_clk} frequency requires re-running the real MIG +wizard; \texttt{TimePeriod} and \texttt{InputClkFreq} are tied together +and cannot be edited independently. + +\subsection{Supply rails (per I/O bank, real XDC-derived)} + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.2} +\begin{tabular}{llll} +\toprule +\textbf{Bank} & \textbf{VCCO} & \textbf{Standard} & \textbf{Used for} \\ +\midrule +34 / 35 & 1.5\,V & SSTL15 / DIFF\_SSTL15 & DDR3 data/address/command, \texttt{sys\_clk} \\ +14 & 2.5\,V & LVDS\_25 & \texttt{clk\_ref\_p/n} \\ +15 & 3.3\,V (assumed) & LVCMOS33 & Management SPI, \texttt{sys\_rst}, \texttt{data\_ready\_n} \\ +16 & 3.3\,V & LVCMOS33 & Config-flash SPI bus \\ +0 & per UG470 & --- & Configuration control (PROGRAM\_B, INIT\_B, DONE, mode pins) \\ +\bottomrule +\end{tabular} +\end{table} + +\clearpage +%====================================================================== +\section{Pin Configuration} + +\subsection{DDR3 interface (fixed by FPGA PHY hardware)} + +Generated by the real Xilinx MIG wizard for this exact part; SSTL15/DIFF\_SSTL15, banks 34/35. + +\begin{longtable}{lll} +\toprule +\textbf{Signal} & \textbf{Pin} & \textbf{Notes} \\ +\midrule +\endhead +\texttt{ddr3\_dq[31:0]} & (32 pins) & split 16 bits/chip across 2 DDR3 devices \\ +\texttt{ddr3\_dqs\_p/n[3:0]} & (8 pins, differential) & 4 DQS pairs \\ +\texttt{ddr3\_dm[3:0]} & (4 pins) & \\ +\texttt{ddr3\_addr[13:0]} & (14 pins) & shared, fanned out to both chips \\ +\texttt{ddr3\_ba[2:0]} & V5 / V2 / U2 & \\ +\texttt{ddr3\_ras\_n / cas\_n / we\_n} & V4 / R3 / T3 & \\ +\texttt{ddr3\_cke[0]} & P2 & \\ +\texttt{ddr3\_cs\_n[0]} & T5 & \\ +\texttt{ddr3\_odt[0]} & R2 & \\ +\texttt{ddr3\_ck\_p/n[0]} & N2 / N1 (diff.) & \\ +\texttt{ddr3\_reset\_n} & D7 & LVCMOS15 \\ +\texttt{sys\_clk\_p / sys\_clk\_n} & N5 / P5 & DIFF\_SSTL15, bank 34 \\ +\texttt{clk\_ref\_p / clk\_ref\_n} & T14 / T15 & LVDS\_25, bank 14 \\ +\bottomrule +\caption{DDR3 interface, real routed pin assignment. Full per-bit DQ/DQS/DM table in \texttt{docs/PINOUT.md}.} +\end{longtable} + +\subsection{Management SPI (ESP32 $\leftrightarrow$ FPGA, FPGA is slave)} + +Bank 15, LVCMOS33. + +\begin{table}[h] +\centering +\begin{tabular}{lll} +\toprule +\textbf{Signal} & \textbf{Pin} & \textbf{Direction (FPGA)} \\ +\midrule +\texttt{sclk} & A15 & Input \\ +\texttt{mosi} & B16 & Input \\ +\texttt{miso} & B17 & Output \\ +\texttt{cs\_n} & A16 & Input \\ +\texttt{sys\_rst} & G13 & Input (tentative, non-final board location) \\ +\texttt{data\_ready\_n} & D14 & Output, active-low, sticky interrupt \\ +\bottomrule +\end{tabular} +\end{table} + +\subsection{Config-flash SPI (FPGA $\leftrightarrow$ flash, FPGA is master)} + +Bank 16, LVCMOS33. + +\begin{table}[h] +\centering +\begin{tabular}{lll} +\toprule +\textbf{Signal} & \textbf{Pin} & \textbf{Direction (FPGA)} \\ +\midrule +\texttt{flash\_mosi} & D9 & Output \\ +\texttt{flash\_miso} & D10 & Input \\ +\texttt{flash\_cs\_n} & C9 & Output \\ +(CCLK) & E9 & Output (via \texttt{STARTUPE2}, not a plain top-level port) \\ +\bottomrule +\end{tabular} +\end{table} + +\subsection{Configuration control (bank 0) and JTAG} + +\begin{table}[h] +\centering +\begin{tabular}{llcll} +\toprule +\textbf{Signal} & \textbf{Pin} & & \textbf{Signal} & \textbf{Pin} \\ +\midrule +PROGRAM\_B & P9 & & TCK & E10 \\ +INIT\_B & P7 & & TDI & E11 \\ +DONE & P10 & & TMS & E12 \\ +M[2:0] & P11/P13/P12 & & TDO & E13 \\ +CFGBVS & P8 & & & \\ +\bottomrule +\end{tabular} +\end{table} + +%====================================================================== +\clearpage +\section{Timing Characteristics} + +Real, in-context Vivado place-and-route on XC7A100T-CSG324-2, N8 +configuration (\texttt{n8\_system\_ddr3\_top.v}), directive stack +\texttt{Explore}/\texttt{ExtraNetDelay\_high}/\texttt{AggressiveExplore}: + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.2} +\begin{tabular}{lll} +\toprule +\textbf{Parameter} & \textbf{Value} & \textbf{Condition} \\ +\midrule +Setup slack (WNS) & \textbf{0.000\,ns} & \texttt{clk\_pll\_i}, 155.039\,MHz, 0 of 63212 failing \\ +Hold slack (WHS) & +0.017\,ns & 0 of 63209 failing \\ +Compute-domain clock period & 6.450\,ns & 155.039\,MHz \\ +DDR3 CAS latency (real, measured) & CL=5 (16.125\,ns) & matches MIG configuration \\ +Same-row read-to-read & 12.9\,ns & real JEDEC trace \\ +Row-switch (Activate$\to$Read) penalty & +25--130\% & vs.\ same-row access, real measured \\ +\bottomrule +\end{tabular} +\end{table} + +\noindent\textbf{Margin notice:} the real WNS is exactly zero --- closed, +but with no spare slack. Any RTL modification to this configuration +requires a fresh real place-and-route run (same directive stack) before +the design may be considered timing-clean again. + +%====================================================================== +\section{Resource Utilization (XC7A100T-CSG324-2, N8)} + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.2} +\begin{tabular}{lrrr} +\toprule +\textbf{Resource} & \textbf{Used} & \textbf{Available} & \textbf{Utilization} \\ +\midrule +Slice LUTs & 12535 & 63400 & 19.77\% \\ +Slice Registers & 19902 & 126800 & 15.70\% \\ +DSP48E1 & 64 & 240 & 26.7\% \\ +Block RAM & 0 & 135 & 0\% \\ +\bottomrule +\end{tabular} +\end{table} + +%====================================================================== +\section{Compute Performance} + +\begin{table}[h] +\centering +\begin{tabular}{ll} +\toprule +\textbf{Parameter} & \textbf{Value} \\ +\midrule +MAC operations per DSP48E1 per cycle & 2 (packed INT8, lane A + lane B) \\ +DSP48E1 per processing element & 8 \\ +MAC/cycle per PE & 16 \\ +Real parallel PEs & 8 \\ +Aggregate MAC/cycle & 128 \\ +\textbf{Aggregate peak throughput} (calculated, 155.039\,MHz) & \textbf{$\sim$19.84\,GMAC/s} \\ +Real DDR3 physical bandwidth ceiling & $\sim$2.48\,GB/s (shared across all 8 PEs) \\ +\bottomrule +\end{tabular} +\end{table} + +\noindent The peak MAC figure is a real calculation from measured +building blocks (DSP count $\times$ packing factor $\times$ measured +Fmax) --- not itself an independently benchmarked sustained-throughput +number. Sustained throughput on a real workload is bounded by the real +DDR3 bandwidth ceiling above, shared across all active PEs; a direct +measurement of sustained aggregate throughput at N8 has not yet been +performed (see \S\ref{sec:openitems}). + +%====================================================================== +\section{Host Communication Protocol} + +One opcode byte (MSB-first) per CS-low SPI transaction. + +\begin{longtable}{lllp{5cm}} +\toprule +\textbf{Opcode} & \textbf{Name} & \textbf{Payload} & \textbf{Function} \\ +\midrule +\endhead +0x00 & NOP & 0\,B & inert \\ +0x0F & RESET & 0\,B & soft reset pulse \\ +0x10 & WRITE\_JOB & 16\,B & submit one inference job (node\_id, x\_base, w\_base, n\_tiles, result\_addr) \\ +0x20 & STATUS & 0$\to$1\,B & busy / last-job-accepted status bits \\ +0x01 & WRITE\_MEM & 4+2$N$\,B & raw DDR3 word write ($N$ words) \\ +0x02 & READ\_MEM & 6$\to$2$N$\,B & raw DDR3 word read ($N$ words) \\ +0x30 & REG\_WRITE & 5\,B & write control register \\ +0x31 & REG\_READ & 1$\to$4\,B & read status/ID register (0x00 DEVICE\_ID, 0x01 CONTROL, 0x02 STATUS, 0x03 N\_SLOTS) \\ +0x40 & FLASH\_XFER & $N\to N{+}2$\,B & raw passthrough to config flash \\ +\bottomrule +\caption{Management SPI opcode summary. Authoritative field layout in \texttt{spi\_host\_bridge\_v3.v}.} +\end{longtable} + +\noindent\textbf{Real, deliberate compatibility guarantee:} this +protocol is byte-for-byte identical across the N2/N4/N8/N16 family +variants (\S\ref{sec:variants}) --- the host always submits one job +descriptor per \texttt{WRITE\_JOB} transaction; the internal Director +groups jobs into pairs (N2) or octets (N8/N16) transparently to the +host. + +%====================================================================== +\section{Verification Status} + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.15} +\begin{tabular}{lll} +\toprule +\textbf{Test} & \textbf{Result} & \textbf{Method} \\ +\midrule +\texttt{tb\_n8\_system\_ddr3.v} (full N8 system) & \textbf{16/16 PASS} & Real DDR3 model, Vivado xsim \\ +\texttt{tb\_sdram\_arbiter\_hier.v} & 23/23 PASS & Icarus, worst-case contention incl.\ host \\ +\texttt{tb\_systolic\_group.v} & 8/8 PASS & Icarus, isolated group, 2 consecutive jobs \\ +\texttt{tb\_neural\_director\_grouped.v} & 4/4 PASS & Icarus, octet dispatch + stall correctness \\ +\texttt{tb\_spi\_host\_bridge\_v3.v} & 49/49 PASS & Icarus, full management protocol \\ +\texttt{tb\_packed\_slot.v} & 9/9 PASS & Real DDR3 read-after-write check \\ +\bottomrule +\end{tabular} +\end{table} + +%====================================================================== +\section{Bill of Materials (Core Parts)} + +\begin{table}[h] +\centering +\renewcommand{\arraystretch}{1.2} +\begin{tabular}{lll} +\toprule +\textbf{Component} & \textbf{Part Number} & \textbf{Status} \\ +\midrule +FPGA & XC7A100T-CSG324-2 & --- \\ +DDR3 SDRAM ($\times$2) & Micron MT41J128M16JT-125:K & In stock, LCSC-verified \\ +Config flash & Winbond W25Q32JVSSIQ & In stock, LCSC-verified \\ +Host MCU & ESP32-S3-WROOM-1-N16R8 & In stock, LCSC C2913202 \\ +\texttt{clk\_ref} oscillator & SiTime SiT9121AC-2CF-33E-200.00000 & In stock, LCSC C835051 \\ +\texttt{sys\_clk} oscillator & SiTime SiT9122 family, 310.077\,MHz & \prelim\ --- needs custom-programmed order \\ +\bottomrule +\end{tabular} +\caption{Core BOM. Power-tree components (VCCINT/VCCAUX/VTT regulators) are real candidate parts, not yet individually stock-confirmed --- see \texttt{docs/BOM.md}.} +\end{table} + +%====================================================================== +\section{Open Items} +\label{sec:openitems} + +\begin{itemize} + \item Physical board has not yet been fabricated; no real + electrical/thermal measurement exists yet. + \item \texttt{sys\_clk} oscillator requires a custom-programmed order + (no off-the-shelf SKU at 310.077\,MHz). + \item Power-tree regulators (VCCINT, VCCAUX, VTT, per-bank VCCO) not + fully sourced/stock-confirmed. + \item \texttt{sys\_rst} pin location is tentative, pending final + board layout. + \item ESP32-side firmware (JTAG bit-banging, SPI host driver, + result-readback address translation) not yet written --- software + work outside this document's scope. + \item Real, direct sustained-throughput benchmark at N8 (vs.\ a + real ESP32-S3 baseline) not yet performed --- see the project's + Tests \& Timing chapter for the honest historical comparison + context. +\end{itemize} + +%====================================================================== +\section{Revision History} + +\begin{table}[h] +\centering +\begin{tabular}{lll} +\toprule +\textbf{Rev.} & \textbf{Date} & \textbf{Description} \\ +\midrule +1.0 & 2026-09-21 & Initial preliminary datasheet, N8 configuration \\ +\bottomrule +\end{tabular} +\end{table} + +\end{document}