From 4b5cd4e5588e6681583ab57db3b179b897f46c7a Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Wed, 2 Sep 2026 14:16:34 +0200 Subject: [PATCH] fix: rewrite layer_tb and neuron_parallel_tb for current INT8 architecture Both testbenches instantiated their DUTs with a FRAC_BITS parameter and Q8.8 fixed-point 16-bit values, which no longer exist in rtl/neuron_parallel.v (now plain INT8, DATA_WIDTH=8, hardcoded +127 saturation, ReLU-only clamp). This made both tests fail elaboration ("parameter FRAC_BITS not found"). Rewrote both benches with integer INT8 stimuli and expectations matching the current core (no RTL changes): neuron_parallel_tb covers a mixed vector, ReLU, positive saturation, and mixed values with a boundary negative bias; layer_tb covers 8 neurons exercising scale, ReLU, saturation, bias-only, and a sparse weight pattern across groups. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt --- WORKLOG.md | 25 + sim/layer.vcd | 6572 ++++++++++++------------- sim/layer_sim | 9741 ++++++++++++++++++++++++-------------- sim/layer_tb.v | 115 +- sim/neuron_parallel.vcd | 1707 +++---- sim/neuron_parallel_tb.v | 89 +- sim/neuron_sim | 7712 +++++++++++++++++++++++++++--- 7 files changed, 17623 insertions(+), 8338 deletions(-) diff --git a/WORKLOG.md b/WORKLOG.md index 87c01ab..c9a2b39 100644 --- a/WORKLOG.md +++ b/WORKLOG.md @@ -22,3 +22,28 @@ - neuron_parallel_tb: FALLISCE in elaborazione — stesso errore, `parameter FRAC_BITS not found in tb.dut`, riferito a rtl/neuron_parallel.v. - NOTA: questi due fallimenti sono preesistenti e non toccano i file modificati in questa sessione (sim/neuron_memory_tb.v). Non risolti in questa sessione perché fuori scope dichiarato (debug neuron_memory); da segnalare all'utente. - 2026-09-02T00:20 — [FASE 3] — CONCLUSIONE: il bug indirizzamento byte/word nei task preload_vector/preload_weights di sim/neuron_memory_tb.v era l'unico difetto riscontrato nel percorso neuron_memory; risulta già corretto nel working tree e validato con successo da tutti e 5 i test (incl. il nuovo test PATTERN aggiunto). Nessun bug residuo individuato in rtl/neuron_memory.v o rtl/int8_memory_access.v per il caso N_NEURONS=1. Procedo al commit del fix sul branch `fix/neuron-memory-debug`. +- 2026-09-02T00:21 — [FASE 4] — Committato (896f56c) il fix di sim/neuron_memory_tb.v + artefatti sim/neuron_memory_sim, sim/neuron_memory.vcd + WORKLOG.md sul branch fix/neuron-memory-debug. Ripristinati con `git checkout --` i .vcd di altri testbench (int8_memory_access, int8_psram_integration, memory_interface, parametric, psram_controller) rigenerati per errore durante la regressione, per non introdurre diff non pertinenti. +- 2026-09-02T00:25 — [FASE 5] — Contesto hardware fornito dall'utente durante la sessione (per riferimento futuro, non ancora usato in RTL/sim): FPGA target = Lattice ECP5 LFE5U-45F-8BG381C; PSRAM = ISSI IS66WVE4M16EBLL-70BLI; il controller esterno pilota il sistema FPGA+RAM via SPI, e accede alla RAM solo tramite la FPGA (mai in accesso diretto). +- 2026-09-02T00:26 — [FASE 6] — Richiesta utente: "sistema i due test e così chiudiamo" — riferito a sim/layer_tb.v e sim/neuron_parallel_tb.v, che fallivano in elaborazione con `parameter FRAC_BITS not found in tb.dut`. +- 2026-09-02T00:27 — [FASE 6] — Letto rtl/neuron_parallel.v per intero: DATA_WIDTH default 8, nessun parametro FRAC_BITS, ReLU (final_acc<=0 -> y=0) e saturazione positiva HARDCODED a `8'sd127` indipendentemente da DATA_WIDTH (nessuna saturazione negativa esplicita, solo ReLU). Confermato che il modulo non supporta più (e non ha mai realmente supportato in questa versione) il formato fixed-point Q8.8 a 16 bit assunto dai due testbench. +- 2026-09-02T00:28 — [FASE 6] — Letto rtl/layer.v per intero: parametrico, instanzia N_NEURONS x neuron_parallel con layout pesi neuron-major; nessun riferimento a FRAC_BITS. +- 2026-09-02T00:29 — [FASE 6] — Letto per intero sim/neuron_parallel_tb.v e sim/layer_tb.v (versioni obsolete, DATA_WIDTH=16, FRAC_BITS=8, valori Q8.8 via funzione q8_8(), saturazione attesa a ±32767): confermato che sono residui di una precedente architettura fixed-point a 16 bit, incompatibile con neuron_parallel.v attuale (core validato, da NON modificare). +- 2026-09-02T00:30 — [FASE 6] — Letto sim/parametric_tb.v (test già passante) come riferimento di stile/parametri corretti per l'architettura INT8 attuale (DATA_WIDTH=8, valori interi, saturazione a 127). +- 2026-09-02T00:35 — [FASE 6] — Riscritto interamente sim/neuron_parallel_tb.v: rimosso FRAC_BITS e funzione q8_8; parametri allineati ai default di rtl/neuron_parallel.v (DATA_WIDTH=8, N_INPUTS=32, PARALLEL=8, ACC_WIDTH=32); 4 test ridisegnati con valori interi INT8 mantenendo lo stesso intento dei test originali: + - TEST 1 DIVERSE VECTOR: x0=3,w0=2 / x1=4,w1=-1 / x2=2,w2=1 / bias=1 -> atteso 5. + - TEST 2 RELU: tutti i prodotti negativi (x=1,w=-1 su 32 input) -> atteso 0. + - TEST 3 POSITIVE SATURATION: x=100,w=2 su 32 input -> somma 6400, satura a 127. + - TEST 4 MIXED + NEGATIVE BIAS: 16 input pari (x=2,w=1) + 16 dispari (x=-1,w=1), bias=-16 -> somma esattamente 0 -> ReLU -> atteso 0. +- 2026-09-02T00:40 — [FASE 6] — Riscritto interamente sim/layer_tb.v: rimosso FRAC_BITS; parametri DATA_WIDTH=8, N_INPUTS=32, N_NEURONS=8, PARALLEL=8, ACC_WIDTH=32; input vettore tutti =1; 8 neuroni con scenari distinti (pattern ispirato a parametric_tb.v): + - N0 w=1,bias=0 -> 32 + - N1 w=3,bias=0 -> 96 + - N2 w=-1 -> ReLU -> 0 + - N3 w=8 -> somma 256 -> satura 127 + - N4 w=0,bias=+5 -> 5 + - N5 w=0,bias=-5 -> ReLU -> 0 + - N6 w=1,bias=-10 -> 32-10=22 + - N7 primi 16 pesi=1 resto 0, bias=+5 -> 16+5=21 (verifica pattern di pesi sparso su più gruppi, PARALLEL=8 -> GROUPS=4) +- 2026-09-02T00:42 — [FASE 6] — Compilato ed eseguito `sim/neuron_parallel_tb.v`: `iverilog -g2012 -o rtl/*.v sim/neuron_parallel_tb.v` + `vvp`. Risultato: TUTTI I 4 TEST PASSANO (TEST1=5, TEST2=0, TEST3=127, TEST4=0). +- 2026-09-02T00:43 — [FASE 6] — Compilato ed eseguito `sim/layer_tb.v`: `iverilog -g2012 -o rtl/*.v sim/layer_tb.v` + `vvp`. Risultato: TUTTI GLI 8 NEURONI PASSANO (32,96,0,127,5,0,22,21), busy=0, done=1 a fine test. +- 2026-09-02T00:44 — [FASE 6] — Rigenerati gli artefatti tracciati in git `sim/neuron_sim` (da neuron_parallel_tb.v) e `sim/layer_sim` (da layer_tb.v) con i relativi `.vcd`, per coerenza con la convenzione del repo di committare i binari di simulazione insieme alle sorgenti. +- 2026-09-02T00:45 — [FASE 7] — Nessuna modifica a rtl/ in questa fase: root cause dei due fallimenti era esclusivamente nei testbench (riferimento a un parametro FRAC_BITS rimosso da tempo dall'RTL), non nel core di calcolo. Sessione di debug neuron_memory + fix dei due test residui considerata chiusa. diff --git a/sim/layer.vcd b/sim/layer.vcd index 5eb741e..0b1776a 100644 --- a/sim/layer.vcd +++ b/sim/layer.vcd @@ -1,1175 +1,1666 @@ $date - Wed Sep 2 09:14:02 2026 + Wed Sep 2 14:15:53 2026 $end $version Icarus Verilog $end $timescale - 1s + 1ps $end $scope module tb $end -$var wire 128 ! y_bus [127:0] $end +$var wire 64 ! y_bus [63:0] $end $var wire 1 " done $end $var wire 1 # busy $end $var parameter 32 $ ACC_WIDTH $end $var parameter 32 % DATA_WIDTH $end -$var parameter 32 & FRAC_BITS $end -$var parameter 32 ' N_INPUTS $end -$var parameter 32 ( N_NEURONS $end -$var parameter 32 ) PARALLEL $end -$var reg 128 * bias_bus [127:0] $end -$var reg 1 + clk $end -$var reg 1 , rst $end -$var reg 1 - start $end -$var reg 8192 . weights_bus [8191:0] $end -$var reg 1024 / x_bus [1023:0] $end -$var integer 32 0 errors [31:0] $end -$var integer 32 1 i [31:0] $end -$scope function q8_8 $end -$var real 1 2 value $end -$upscope $end +$var parameter 32 & N_INPUTS $end +$var parameter 32 ' N_NEURONS $end +$var parameter 32 ( PARALLEL $end +$var reg 64 ) bias_bus [63:0] $end +$var reg 1 * clk $end +$var reg 1 + rst $end +$var reg 1 , start $end +$var reg 2048 - weights_bus [2047:0] $end +$var reg 256 . x_bus [255:0] $end +$var integer 32 / errors [31:0] $end +$var integer 32 0 i [31:0] $end $scope module dut $end -$var wire 128 3 bias_bus [127:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 8192 4 weights_bus [8191:0] $end -$var wire 1024 5 x_bus [1023:0] $end -$var wire 128 6 y_bus [127:0] $end -$var wire 8 7 neuron_done [7:0] $end -$var wire 8 8 neuron_busy [7:0] $end +$var wire 64 1 bias_bus [63:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 2048 2 weights_bus [2047:0] $end +$var wire 256 3 x_bus [255:0] $end +$var wire 64 4 y_bus [63:0] $end +$var wire 8 5 neuron_done [7:0] $end +$var wire 8 6 neuron_busy [7:0] $end $var wire 1 " done $end $var wire 1 # busy $end -$var parameter 32 9 ACC_WIDTH $end -$var parameter 32 : DATA_WIDTH $end -$var parameter 32 ; FRAC_BITS $end -$var parameter 32 < N_INPUTS $end -$var parameter 32 = N_NEURONS $end -$var parameter 32 > PARALLEL $end +$var parameter 32 7 ACC_WIDTH $end +$var parameter 32 8 DATA_WIDTH $end +$var parameter 32 9 N_INPUTS $end +$var parameter 32 : N_NEURONS $end +$var parameter 32 ; PARALLEL $end $scope begin GEN_NEURON[0] $end -$var parameter 2 ? n $end +$var parameter 2 < n $end $scope module u_neuron $end -$var wire 16 @ bias [15:0] $end -$var wire 16 A bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 B w_bus [1023:0] $end -$var wire 1024 C x_bus [1023:0] $end -$var wire 128 D x_group [127:0] $end -$var wire 128 E w_group [127:0] $end -$var wire 40 F final_value [39:0] $end -$var wire 40 G final_acc [39:0] $end -$var wire 40 H bias_ext [39:0] $end -$var wire 40 I acc_next [39:0] $end -$var parameter 32 J ACC_WIDTH $end -$var parameter 32 K DATA_WIDTH $end -$var parameter 32 L FRAC_BITS $end -$var parameter 32 M GROUPS $end -$var parameter 32 N GROUP_INDEX_WIDTH $end -$var parameter 32 O N_INPUTS $end -$var parameter 32 P PARALLEL $end -$var reg 40 Q acc [39:0] $end -$var reg 1 R busy $end -$var reg 1 S done $end -$var reg 3 T group_index [2:0] $end -$var reg 16 U y [15:0] $end +$var wire 8 = bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 > w_bus [255:0] $end +$var wire 256 ? x_bus [255:0] $end +$var wire 64 @ x_group [63:0] $end +$var wire 64 A w_group [63:0] $end +$var wire 32 B final_acc [31:0] $end +$var wire 32 C bias_ext [31:0] $end +$var wire 32 D acc_next [31:0] $end +$var parameter 32 E ACC_WIDTH $end +$var parameter 32 F DATA_WIDTH $end +$var parameter 32 G GROUPS $end +$var parameter 32 H GROUP_INDEX_WIDTH $end +$var parameter 32 I N_INPUTS $end +$var parameter 32 J PARALLEL $end +$var reg 32 K acc [31:0] $end +$var reg 1 L busy $end +$var reg 1 M done $end +$var reg 2 N group_index [1:0] $end +$var reg 8 O y [7:0] $end $scope module u_mac8 $end -$var wire 40 V acc_in [39:0] $end -$var wire 128 W w_bus [127:0] $end -$var wire 128 X x_bus [127:0] $end -$var wire 40 Y sum [39:0] $end -$var wire 40 Z s5 [39:0] $end -$var wire 40 [ s4 [39:0] $end -$var wire 40 \ s3 [39:0] $end -$var wire 40 ] s2 [39:0] $end -$var wire 40 ^ s1 [39:0] $end -$var wire 40 _ s0 [39:0] $end -$var wire 40 ` m7 [39:0] $end -$var wire 40 a m6 [39:0] $end -$var wire 40 b m5 [39:0] $end -$var wire 40 c m4 [39:0] $end -$var wire 40 d m3 [39:0] $end -$var wire 40 e m2 [39:0] $end -$var wire 40 f m1 [39:0] $end -$var wire 40 g m0 [39:0] $end -$var wire 40 h acc_out [39:0] $end +$var wire 32 P acc_in [31:0] $end +$var wire 64 Q w_bus [63:0] $end +$var wire 64 R x_bus [63:0] $end +$var wire 32 S acc_out [31:0] $end +$var parameter 32 T ACC_WIDTH $end +$var parameter 32 U DATA_WIDTH $end +$var parameter 32 V PARALLEL $end +$var parameter 32 W TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 X i $end +$scope module u_mac $end +$var wire 32 Y acc_in [31:0] $end +$var wire 8 Z w [7:0] $end +$var wire 8 [ x [7:0] $end +$var wire 32 \ product_ext [31:0] $end +$var wire 16 ] product [15:0] $end +$var wire 32 ^ acc_out [31:0] $end +$var parameter 32 _ ACC_WIDTH $end +$var parameter 32 ` DATA_WIDTH $end +$var parameter 64 a PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[1] $end +$var parameter 2 b i $end +$scope module u_mac $end +$var wire 32 c acc_in [31:0] $end +$var wire 8 d w [7:0] $end +$var wire 8 e x [7:0] $end +$var wire 32 f product_ext [31:0] $end +$var wire 16 g product [15:0] $end +$var wire 32 h acc_out [31:0] $end $var parameter 32 i ACC_WIDTH $end $var parameter 32 j DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 k acc_in [39:0] $end -$var wire 16 l w [15:0] $end -$var wire 16 m x [15:0] $end -$var wire 40 n product_ext [39:0] $end -$var wire 32 o product [31:0] $end -$var wire 40 p acc_out [39:0] $end -$var parameter 32 q ACC_WIDTH $end -$var parameter 32 r DATA_WIDTH $end -$var parameter 64 s PROD_WIDTH $end +$var parameter 64 k PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 t acc_in [39:0] $end -$var wire 16 u w [15:0] $end -$var wire 16 v x [15:0] $end -$var wire 40 w product_ext [39:0] $end -$var wire 32 x product [31:0] $end -$var wire 40 y acc_out [39:0] $end -$var parameter 32 z ACC_WIDTH $end -$var parameter 32 { DATA_WIDTH $end -$var parameter 64 | PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 } acc_in [39:0] $end -$var wire 16 ~ w [15:0] $end -$var wire 16 !" x [15:0] $end -$var wire 40 "" product_ext [39:0] $end -$var wire 32 #" product [31:0] $end -$var wire 40 $" acc_out [39:0] $end -$var parameter 32 %" ACC_WIDTH $end -$var parameter 32 &" DATA_WIDTH $end -$var parameter 64 '" PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 l i $end +$scope module u_mac $end +$var wire 32 m acc_in [31:0] $end +$var wire 8 n w [7:0] $end +$var wire 8 o x [7:0] $end +$var wire 32 p product_ext [31:0] $end +$var wire 16 q product [15:0] $end +$var wire 32 r acc_out [31:0] $end +$var parameter 32 s ACC_WIDTH $end +$var parameter 32 t DATA_WIDTH $end +$var parameter 64 u PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 (" acc_in [39:0] $end -$var wire 16 )" w [15:0] $end -$var wire 16 *" x [15:0] $end -$var wire 40 +" product_ext [39:0] $end -$var wire 32 ," product [31:0] $end -$var wire 40 -" acc_out [39:0] $end -$var parameter 32 ." ACC_WIDTH $end -$var parameter 32 /" DATA_WIDTH $end -$var parameter 64 0" PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 1" acc_in [39:0] $end -$var wire 16 2" w [15:0] $end -$var wire 16 3" x [15:0] $end -$var wire 40 4" product_ext [39:0] $end -$var wire 32 5" product [31:0] $end -$var wire 40 6" acc_out [39:0] $end -$var parameter 32 7" ACC_WIDTH $end -$var parameter 32 8" DATA_WIDTH $end -$var parameter 64 9" PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 v i $end +$scope module u_mac $end +$var wire 32 w acc_in [31:0] $end +$var wire 8 x w [7:0] $end +$var wire 8 y x [7:0] $end +$var wire 32 z product_ext [31:0] $end +$var wire 16 { product [15:0] $end +$var wire 32 | acc_out [31:0] $end +$var parameter 32 } ACC_WIDTH $end +$var parameter 32 ~ DATA_WIDTH $end +$var parameter 64 !" PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 :" acc_in [39:0] $end -$var wire 16 ;" w [15:0] $end -$var wire 16 <" x [15:0] $end -$var wire 40 =" product_ext [39:0] $end -$var wire 32 >" product [31:0] $end -$var wire 40 ?" acc_out [39:0] $end -$var parameter 32 @" ACC_WIDTH $end -$var parameter 32 A" DATA_WIDTH $end -$var parameter 64 B" PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 C" acc_in [39:0] $end -$var wire 16 D" w [15:0] $end -$var wire 16 E" x [15:0] $end -$var wire 40 F" product_ext [39:0] $end -$var wire 32 G" product [31:0] $end -$var wire 40 H" acc_out [39:0] $end -$var parameter 32 I" ACC_WIDTH $end -$var parameter 32 J" DATA_WIDTH $end -$var parameter 64 K" PROD_WIDTH $end +$scope begin GEN_MAC[4] $end +$var parameter 4 "" i $end +$scope module u_mac $end +$var wire 32 #" acc_in [31:0] $end +$var wire 8 $" w [7:0] $end +$var wire 8 %" x [7:0] $end +$var wire 32 &" product_ext [31:0] $end +$var wire 16 '" product [15:0] $end +$var wire 32 (" acc_out [31:0] $end +$var parameter 32 )" ACC_WIDTH $end +$var parameter 32 *" DATA_WIDTH $end +$var parameter 64 +" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 ," i $end +$scope module u_mac $end +$var wire 32 -" acc_in [31:0] $end +$var wire 8 ." w [7:0] $end +$var wire 8 /" x [7:0] $end +$var wire 32 0" product_ext [31:0] $end +$var wire 16 1" product [15:0] $end +$var wire 32 2" acc_out [31:0] $end +$var parameter 32 3" ACC_WIDTH $end +$var parameter 32 4" DATA_WIDTH $end +$var parameter 64 5" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 6" i $end +$scope module u_mac $end +$var wire 32 7" acc_in [31:0] $end +$var wire 8 8" w [7:0] $end +$var wire 8 9" x [7:0] $end +$var wire 32 :" product_ext [31:0] $end +$var wire 16 ;" product [15:0] $end +$var wire 32 <" acc_out [31:0] $end +$var parameter 32 =" ACC_WIDTH $end +$var parameter 32 >" DATA_WIDTH $end +$var parameter 64 ?" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 @" i $end +$scope module u_mac $end +$var wire 32 A" acc_in [31:0] $end +$var wire 8 B" w [7:0] $end +$var wire 8 C" x [7:0] $end +$var wire 32 D" product_ext [31:0] $end +$var wire 16 E" product [15:0] $end +$var wire 32 F" acc_out [31:0] $end +$var parameter 32 G" ACC_WIDTH $end +$var parameter 32 H" DATA_WIDTH $end +$var parameter 64 I" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 J" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 K" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 L" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 M" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 N" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 O" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 P" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 Q" i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 R" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 S" node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 T" node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 U" node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 V" node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 W" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 X" node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 Y" node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 Z" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 [" node $end $upscope $end -$scope module mac7 $end -$var wire 40 L" acc_in [39:0] $end -$var wire 16 M" w [15:0] $end -$var wire 16 N" x [15:0] $end -$var wire 40 O" product_ext [39:0] $end -$var wire 32 P" product [31:0] $end -$var wire 40 Q" acc_out [39:0] $end -$var parameter 32 R" ACC_WIDTH $end -$var parameter 32 S" DATA_WIDTH $end -$var parameter 64 T" PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[1] $end -$var parameter 2 U" n $end +$var parameter 2 \" n $end $scope module u_neuron $end -$var wire 16 V" bias [15:0] $end -$var wire 16 W" bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 X" w_bus [1023:0] $end -$var wire 1024 Y" x_bus [1023:0] $end -$var wire 128 Z" x_group [127:0] $end -$var wire 128 [" w_group [127:0] $end -$var wire 40 \" final_value [39:0] $end -$var wire 40 ]" final_acc [39:0] $end -$var wire 40 ^" bias_ext [39:0] $end -$var wire 40 _" acc_next [39:0] $end -$var parameter 32 `" ACC_WIDTH $end -$var parameter 32 a" DATA_WIDTH $end -$var parameter 32 b" FRAC_BITS $end -$var parameter 32 c" GROUPS $end -$var parameter 32 d" GROUP_INDEX_WIDTH $end -$var parameter 32 e" N_INPUTS $end -$var parameter 32 f" PARALLEL $end -$var reg 40 g" acc [39:0] $end -$var reg 1 h" busy $end -$var reg 1 i" done $end -$var reg 3 j" group_index [2:0] $end -$var reg 16 k" y [15:0] $end +$var wire 8 ]" bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 ^" w_bus [255:0] $end +$var wire 256 _" x_bus [255:0] $end +$var wire 64 `" x_group [63:0] $end +$var wire 64 a" w_group [63:0] $end +$var wire 32 b" final_acc [31:0] $end +$var wire 32 c" bias_ext [31:0] $end +$var wire 32 d" acc_next [31:0] $end +$var parameter 32 e" ACC_WIDTH $end +$var parameter 32 f" DATA_WIDTH $end +$var parameter 32 g" GROUPS $end +$var parameter 32 h" GROUP_INDEX_WIDTH $end +$var parameter 32 i" N_INPUTS $end +$var parameter 32 j" PARALLEL $end +$var reg 32 k" acc [31:0] $end +$var reg 1 l" busy $end +$var reg 1 m" done $end +$var reg 2 n" group_index [1:0] $end +$var reg 8 o" y [7:0] $end $scope module u_mac8 $end -$var wire 40 l" acc_in [39:0] $end -$var wire 128 m" w_bus [127:0] $end -$var wire 128 n" x_bus [127:0] $end -$var wire 40 o" sum [39:0] $end -$var wire 40 p" s5 [39:0] $end -$var wire 40 q" s4 [39:0] $end -$var wire 40 r" s3 [39:0] $end -$var wire 40 s" s2 [39:0] $end -$var wire 40 t" s1 [39:0] $end -$var wire 40 u" s0 [39:0] $end -$var wire 40 v" m7 [39:0] $end -$var wire 40 w" m6 [39:0] $end -$var wire 40 x" m5 [39:0] $end -$var wire 40 y" m4 [39:0] $end -$var wire 40 z" m3 [39:0] $end -$var wire 40 {" m2 [39:0] $end -$var wire 40 |" m1 [39:0] $end -$var wire 40 }" m0 [39:0] $end -$var wire 40 ~" acc_out [39:0] $end +$var wire 32 p" acc_in [31:0] $end +$var wire 64 q" w_bus [63:0] $end +$var wire 64 r" x_bus [63:0] $end +$var wire 32 s" acc_out [31:0] $end +$var parameter 32 t" ACC_WIDTH $end +$var parameter 32 u" DATA_WIDTH $end +$var parameter 32 v" PARALLEL $end +$var parameter 32 w" TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 x" i $end +$scope module u_mac $end +$var wire 32 y" acc_in [31:0] $end +$var wire 8 z" w [7:0] $end +$var wire 8 {" x [7:0] $end +$var wire 32 |" product_ext [31:0] $end +$var wire 16 }" product [15:0] $end +$var wire 32 ~" acc_out [31:0] $end $var parameter 32 !# ACC_WIDTH $end $var parameter 32 "# DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 ## acc_in [39:0] $end -$var wire 16 $# w [15:0] $end -$var wire 16 %# x [15:0] $end -$var wire 40 &# product_ext [39:0] $end -$var wire 32 '# product [31:0] $end -$var wire 40 (# acc_out [39:0] $end -$var parameter 32 )# ACC_WIDTH $end -$var parameter 32 *# DATA_WIDTH $end -$var parameter 64 +# PROD_WIDTH $end +$var parameter 64 ## PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 ,# acc_in [39:0] $end -$var wire 16 -# w [15:0] $end -$var wire 16 .# x [15:0] $end -$var wire 40 /# product_ext [39:0] $end -$var wire 32 0# product [31:0] $end -$var wire 40 1# acc_out [39:0] $end -$var parameter 32 2# ACC_WIDTH $end -$var parameter 32 3# DATA_WIDTH $end -$var parameter 64 4# PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 5# acc_in [39:0] $end -$var wire 16 6# w [15:0] $end -$var wire 16 7# x [15:0] $end -$var wire 40 8# product_ext [39:0] $end -$var wire 32 9# product [31:0] $end -$var wire 40 :# acc_out [39:0] $end -$var parameter 32 ;# ACC_WIDTH $end -$var parameter 32 <# DATA_WIDTH $end -$var parameter 64 =# PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 $# i $end +$scope module u_mac $end +$var wire 32 %# acc_in [31:0] $end +$var wire 8 &# w [7:0] $end +$var wire 8 '# x [7:0] $end +$var wire 32 (# product_ext [31:0] $end +$var wire 16 )# product [15:0] $end +$var wire 32 *# acc_out [31:0] $end +$var parameter 32 +# ACC_WIDTH $end +$var parameter 32 ,# DATA_WIDTH $end +$var parameter 64 -# PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 ># acc_in [39:0] $end -$var wire 16 ?# w [15:0] $end -$var wire 16 @# x [15:0] $end -$var wire 40 A# product_ext [39:0] $end -$var wire 32 B# product [31:0] $end -$var wire 40 C# acc_out [39:0] $end -$var parameter 32 D# ACC_WIDTH $end -$var parameter 32 E# DATA_WIDTH $end -$var parameter 64 F# PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 G# acc_in [39:0] $end -$var wire 16 H# w [15:0] $end -$var wire 16 I# x [15:0] $end -$var wire 40 J# product_ext [39:0] $end -$var wire 32 K# product [31:0] $end -$var wire 40 L# acc_out [39:0] $end -$var parameter 32 M# ACC_WIDTH $end -$var parameter 32 N# DATA_WIDTH $end -$var parameter 64 O# PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 .# i $end +$scope module u_mac $end +$var wire 32 /# acc_in [31:0] $end +$var wire 8 0# w [7:0] $end +$var wire 8 1# x [7:0] $end +$var wire 32 2# product_ext [31:0] $end +$var wire 16 3# product [15:0] $end +$var wire 32 4# acc_out [31:0] $end +$var parameter 32 5# ACC_WIDTH $end +$var parameter 32 6# DATA_WIDTH $end +$var parameter 64 7# PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 P# acc_in [39:0] $end -$var wire 16 Q# w [15:0] $end -$var wire 16 R# x [15:0] $end -$var wire 40 S# product_ext [39:0] $end -$var wire 32 T# product [31:0] $end -$var wire 40 U# acc_out [39:0] $end -$var parameter 32 V# ACC_WIDTH $end -$var parameter 32 W# DATA_WIDTH $end -$var parameter 64 X# PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 Y# acc_in [39:0] $end -$var wire 16 Z# w [15:0] $end -$var wire 16 [# x [15:0] $end -$var wire 40 \# product_ext [39:0] $end -$var wire 32 ]# product [31:0] $end -$var wire 40 ^# acc_out [39:0] $end -$var parameter 32 _# ACC_WIDTH $end -$var parameter 32 `# DATA_WIDTH $end -$var parameter 64 a# PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 8# i $end +$scope module u_mac $end +$var wire 32 9# acc_in [31:0] $end +$var wire 8 :# w [7:0] $end +$var wire 8 ;# x [7:0] $end +$var wire 32 <# product_ext [31:0] $end +$var wire 16 =# product [15:0] $end +$var wire 32 ># acc_out [31:0] $end +$var parameter 32 ?# ACC_WIDTH $end +$var parameter 32 @# DATA_WIDTH $end +$var parameter 64 A# PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 B# i $end +$scope module u_mac $end +$var wire 32 C# acc_in [31:0] $end +$var wire 8 D# w [7:0] $end +$var wire 8 E# x [7:0] $end +$var wire 32 F# product_ext [31:0] $end +$var wire 16 G# product [15:0] $end +$var wire 32 H# acc_out [31:0] $end +$var parameter 32 I# ACC_WIDTH $end +$var parameter 32 J# DATA_WIDTH $end +$var parameter 64 K# PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 L# i $end +$scope module u_mac $end +$var wire 32 M# acc_in [31:0] $end +$var wire 8 N# w [7:0] $end +$var wire 8 O# x [7:0] $end +$var wire 32 P# product_ext [31:0] $end +$var wire 16 Q# product [15:0] $end +$var wire 32 R# acc_out [31:0] $end +$var parameter 32 S# ACC_WIDTH $end +$var parameter 32 T# DATA_WIDTH $end +$var parameter 64 U# PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 V# i $end +$scope module u_mac $end +$var wire 32 W# acc_in [31:0] $end +$var wire 8 X# w [7:0] $end +$var wire 8 Y# x [7:0] $end +$var wire 32 Z# product_ext [31:0] $end +$var wire 16 [# product [15:0] $end +$var wire 32 \# acc_out [31:0] $end +$var parameter 32 ]# ACC_WIDTH $end +$var parameter 32 ^# DATA_WIDTH $end +$var parameter 64 _# PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 `# i $end +$scope module u_mac $end +$var wire 32 a# acc_in [31:0] $end +$var wire 8 b# w [7:0] $end +$var wire 8 c# x [7:0] $end +$var wire 32 d# product_ext [31:0] $end +$var wire 16 e# product [15:0] $end +$var wire 32 f# acc_out [31:0] $end +$var parameter 32 g# ACC_WIDTH $end +$var parameter 32 h# DATA_WIDTH $end +$var parameter 64 i# PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 j# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 k# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 l# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 m# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 n# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 o# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 p# i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 q# i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 r# level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 s# node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 t# node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 u# node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 v# node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 w# level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 x# node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 y# node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 z# level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 {# node $end $upscope $end -$scope module mac7 $end -$var wire 40 b# acc_in [39:0] $end -$var wire 16 c# w [15:0] $end -$var wire 16 d# x [15:0] $end -$var wire 40 e# product_ext [39:0] $end -$var wire 32 f# product [31:0] $end -$var wire 40 g# acc_out [39:0] $end -$var parameter 32 h# ACC_WIDTH $end -$var parameter 32 i# DATA_WIDTH $end -$var parameter 64 j# PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[2] $end -$var parameter 3 k# n $end +$var parameter 3 |# n $end $scope module u_neuron $end -$var wire 16 l# bias [15:0] $end -$var wire 16 m# bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 n# w_bus [1023:0] $end -$var wire 1024 o# x_bus [1023:0] $end -$var wire 128 p# x_group [127:0] $end -$var wire 128 q# w_group [127:0] $end -$var wire 40 r# final_value [39:0] $end -$var wire 40 s# final_acc [39:0] $end -$var wire 40 t# bias_ext [39:0] $end -$var wire 40 u# acc_next [39:0] $end -$var parameter 32 v# ACC_WIDTH $end -$var parameter 32 w# DATA_WIDTH $end -$var parameter 32 x# FRAC_BITS $end -$var parameter 32 y# GROUPS $end -$var parameter 32 z# GROUP_INDEX_WIDTH $end -$var parameter 32 {# N_INPUTS $end -$var parameter 32 |# PARALLEL $end -$var reg 40 }# acc [39:0] $end -$var reg 1 ~# busy $end -$var reg 1 !$ done $end -$var reg 3 "$ group_index [2:0] $end -$var reg 16 #$ y [15:0] $end +$var wire 8 }# bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 ~# w_bus [255:0] $end +$var wire 256 !$ x_bus [255:0] $end +$var wire 64 "$ x_group [63:0] $end +$var wire 64 #$ w_group [63:0] $end +$var wire 32 $$ final_acc [31:0] $end +$var wire 32 %$ bias_ext [31:0] $end +$var wire 32 &$ acc_next [31:0] $end +$var parameter 32 '$ ACC_WIDTH $end +$var parameter 32 ($ DATA_WIDTH $end +$var parameter 32 )$ GROUPS $end +$var parameter 32 *$ GROUP_INDEX_WIDTH $end +$var parameter 32 +$ N_INPUTS $end +$var parameter 32 ,$ PARALLEL $end +$var reg 32 -$ acc [31:0] $end +$var reg 1 .$ busy $end +$var reg 1 /$ done $end +$var reg 2 0$ group_index [1:0] $end +$var reg 8 1$ y [7:0] $end $scope module u_mac8 $end -$var wire 40 $$ acc_in [39:0] $end -$var wire 128 %$ w_bus [127:0] $end -$var wire 128 &$ x_bus [127:0] $end -$var wire 40 '$ sum [39:0] $end -$var wire 40 ($ s5 [39:0] $end -$var wire 40 )$ s4 [39:0] $end -$var wire 40 *$ s3 [39:0] $end -$var wire 40 +$ s2 [39:0] $end -$var wire 40 ,$ s1 [39:0] $end -$var wire 40 -$ s0 [39:0] $end -$var wire 40 .$ m7 [39:0] $end -$var wire 40 /$ m6 [39:0] $end -$var wire 40 0$ m5 [39:0] $end -$var wire 40 1$ m4 [39:0] $end -$var wire 40 2$ m3 [39:0] $end -$var wire 40 3$ m2 [39:0] $end -$var wire 40 4$ m1 [39:0] $end -$var wire 40 5$ m0 [39:0] $end -$var wire 40 6$ acc_out [39:0] $end -$var parameter 32 7$ ACC_WIDTH $end -$var parameter 32 8$ DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 9$ acc_in [39:0] $end -$var wire 16 :$ w [15:0] $end -$var wire 16 ;$ x [15:0] $end -$var wire 40 <$ product_ext [39:0] $end -$var wire 32 =$ product [31:0] $end -$var wire 40 >$ acc_out [39:0] $end -$var parameter 32 ?$ ACC_WIDTH $end -$var parameter 32 @$ DATA_WIDTH $end -$var parameter 64 A$ PROD_WIDTH $end +$var wire 32 2$ acc_in [31:0] $end +$var wire 64 3$ w_bus [63:0] $end +$var wire 64 4$ x_bus [63:0] $end +$var wire 32 5$ acc_out [31:0] $end +$var parameter 32 6$ ACC_WIDTH $end +$var parameter 32 7$ DATA_WIDTH $end +$var parameter 32 8$ PARALLEL $end +$var parameter 32 9$ TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 :$ i $end +$scope module u_mac $end +$var wire 32 ;$ acc_in [31:0] $end +$var wire 8 <$ w [7:0] $end +$var wire 8 =$ x [7:0] $end +$var wire 32 >$ product_ext [31:0] $end +$var wire 16 ?$ product [15:0] $end +$var wire 32 @$ acc_out [31:0] $end +$var parameter 32 A$ ACC_WIDTH $end +$var parameter 32 B$ DATA_WIDTH $end +$var parameter 64 C$ PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 B$ acc_in [39:0] $end -$var wire 16 C$ w [15:0] $end -$var wire 16 D$ x [15:0] $end -$var wire 40 E$ product_ext [39:0] $end -$var wire 32 F$ product [31:0] $end -$var wire 40 G$ acc_out [39:0] $end -$var parameter 32 H$ ACC_WIDTH $end -$var parameter 32 I$ DATA_WIDTH $end -$var parameter 64 J$ PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 K$ acc_in [39:0] $end -$var wire 16 L$ w [15:0] $end -$var wire 16 M$ x [15:0] $end -$var wire 40 N$ product_ext [39:0] $end -$var wire 32 O$ product [31:0] $end -$var wire 40 P$ acc_out [39:0] $end -$var parameter 32 Q$ ACC_WIDTH $end -$var parameter 32 R$ DATA_WIDTH $end -$var parameter 64 S$ PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 D$ i $end +$scope module u_mac $end +$var wire 32 E$ acc_in [31:0] $end +$var wire 8 F$ w [7:0] $end +$var wire 8 G$ x [7:0] $end +$var wire 32 H$ product_ext [31:0] $end +$var wire 16 I$ product [15:0] $end +$var wire 32 J$ acc_out [31:0] $end +$var parameter 32 K$ ACC_WIDTH $end +$var parameter 32 L$ DATA_WIDTH $end +$var parameter 64 M$ PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 T$ acc_in [39:0] $end -$var wire 16 U$ w [15:0] $end -$var wire 16 V$ x [15:0] $end -$var wire 40 W$ product_ext [39:0] $end -$var wire 32 X$ product [31:0] $end -$var wire 40 Y$ acc_out [39:0] $end -$var parameter 32 Z$ ACC_WIDTH $end -$var parameter 32 [$ DATA_WIDTH $end -$var parameter 64 \$ PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 ]$ acc_in [39:0] $end -$var wire 16 ^$ w [15:0] $end -$var wire 16 _$ x [15:0] $end -$var wire 40 `$ product_ext [39:0] $end -$var wire 32 a$ product [31:0] $end -$var wire 40 b$ acc_out [39:0] $end -$var parameter 32 c$ ACC_WIDTH $end -$var parameter 32 d$ DATA_WIDTH $end -$var parameter 64 e$ PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 N$ i $end +$scope module u_mac $end +$var wire 32 O$ acc_in [31:0] $end +$var wire 8 P$ w [7:0] $end +$var wire 8 Q$ x [7:0] $end +$var wire 32 R$ product_ext [31:0] $end +$var wire 16 S$ product [15:0] $end +$var wire 32 T$ acc_out [31:0] $end +$var parameter 32 U$ ACC_WIDTH $end +$var parameter 32 V$ DATA_WIDTH $end +$var parameter 64 W$ PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 f$ acc_in [39:0] $end -$var wire 16 g$ w [15:0] $end -$var wire 16 h$ x [15:0] $end -$var wire 40 i$ product_ext [39:0] $end -$var wire 32 j$ product [31:0] $end -$var wire 40 k$ acc_out [39:0] $end -$var parameter 32 l$ ACC_WIDTH $end -$var parameter 32 m$ DATA_WIDTH $end -$var parameter 64 n$ PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 o$ acc_in [39:0] $end -$var wire 16 p$ w [15:0] $end -$var wire 16 q$ x [15:0] $end -$var wire 40 r$ product_ext [39:0] $end -$var wire 32 s$ product [31:0] $end -$var wire 40 t$ acc_out [39:0] $end -$var parameter 32 u$ ACC_WIDTH $end -$var parameter 32 v$ DATA_WIDTH $end -$var parameter 64 w$ PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 X$ i $end +$scope module u_mac $end +$var wire 32 Y$ acc_in [31:0] $end +$var wire 8 Z$ w [7:0] $end +$var wire 8 [$ x [7:0] $end +$var wire 32 \$ product_ext [31:0] $end +$var wire 16 ]$ product [15:0] $end +$var wire 32 ^$ acc_out [31:0] $end +$var parameter 32 _$ ACC_WIDTH $end +$var parameter 32 `$ DATA_WIDTH $end +$var parameter 64 a$ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 b$ i $end +$scope module u_mac $end +$var wire 32 c$ acc_in [31:0] $end +$var wire 8 d$ w [7:0] $end +$var wire 8 e$ x [7:0] $end +$var wire 32 f$ product_ext [31:0] $end +$var wire 16 g$ product [15:0] $end +$var wire 32 h$ acc_out [31:0] $end +$var parameter 32 i$ ACC_WIDTH $end +$var parameter 32 j$ DATA_WIDTH $end +$var parameter 64 k$ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 l$ i $end +$scope module u_mac $end +$var wire 32 m$ acc_in [31:0] $end +$var wire 8 n$ w [7:0] $end +$var wire 8 o$ x [7:0] $end +$var wire 32 p$ product_ext [31:0] $end +$var wire 16 q$ product [15:0] $end +$var wire 32 r$ acc_out [31:0] $end +$var parameter 32 s$ ACC_WIDTH $end +$var parameter 32 t$ DATA_WIDTH $end +$var parameter 64 u$ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 v$ i $end +$scope module u_mac $end +$var wire 32 w$ acc_in [31:0] $end +$var wire 8 x$ w [7:0] $end +$var wire 8 y$ x [7:0] $end +$var wire 32 z$ product_ext [31:0] $end +$var wire 16 {$ product [15:0] $end +$var wire 32 |$ acc_out [31:0] $end +$var parameter 32 }$ ACC_WIDTH $end +$var parameter 32 ~$ DATA_WIDTH $end +$var parameter 64 !% PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 "% i $end +$scope module u_mac $end +$var wire 32 #% acc_in [31:0] $end +$var wire 8 $% w [7:0] $end +$var wire 8 %% x [7:0] $end +$var wire 32 &% product_ext [31:0] $end +$var wire 16 '% product [15:0] $end +$var wire 32 (% acc_out [31:0] $end +$var parameter 32 )% ACC_WIDTH $end +$var parameter 32 *% DATA_WIDTH $end +$var parameter 64 +% PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 ,% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 -% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 .% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 /% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 0% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 1% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 2% i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 3% i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 4% level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 5% node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 6% node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 7% node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 8% node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 9% level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 :% node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 ;% node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 <% level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 =% node $end $upscope $end -$scope module mac7 $end -$var wire 40 x$ acc_in [39:0] $end -$var wire 16 y$ w [15:0] $end -$var wire 16 z$ x [15:0] $end -$var wire 40 {$ product_ext [39:0] $end -$var wire 32 |$ product [31:0] $end -$var wire 40 }$ acc_out [39:0] $end -$var parameter 32 ~$ ACC_WIDTH $end -$var parameter 32 !% DATA_WIDTH $end -$var parameter 64 "% PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[3] $end -$var parameter 3 #% n $end +$var parameter 3 >% n $end $scope module u_neuron $end -$var wire 16 $% bias [15:0] $end -$var wire 16 %% bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 &% w_bus [1023:0] $end -$var wire 1024 '% x_bus [1023:0] $end -$var wire 128 (% x_group [127:0] $end -$var wire 128 )% w_group [127:0] $end -$var wire 40 *% final_value [39:0] $end -$var wire 40 +% final_acc [39:0] $end -$var wire 40 ,% bias_ext [39:0] $end -$var wire 40 -% acc_next [39:0] $end -$var parameter 32 .% ACC_WIDTH $end -$var parameter 32 /% DATA_WIDTH $end -$var parameter 32 0% FRAC_BITS $end -$var parameter 32 1% GROUPS $end -$var parameter 32 2% GROUP_INDEX_WIDTH $end -$var parameter 32 3% N_INPUTS $end -$var parameter 32 4% PARALLEL $end -$var reg 40 5% acc [39:0] $end -$var reg 1 6% busy $end -$var reg 1 7% done $end -$var reg 3 8% group_index [2:0] $end -$var reg 16 9% y [15:0] $end +$var wire 8 ?% bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 @% w_bus [255:0] $end +$var wire 256 A% x_bus [255:0] $end +$var wire 64 B% x_group [63:0] $end +$var wire 64 C% w_group [63:0] $end +$var wire 32 D% final_acc [31:0] $end +$var wire 32 E% bias_ext [31:0] $end +$var wire 32 F% acc_next [31:0] $end +$var parameter 32 G% ACC_WIDTH $end +$var parameter 32 H% DATA_WIDTH $end +$var parameter 32 I% GROUPS $end +$var parameter 32 J% GROUP_INDEX_WIDTH $end +$var parameter 32 K% N_INPUTS $end +$var parameter 32 L% PARALLEL $end +$var reg 32 M% acc [31:0] $end +$var reg 1 N% busy $end +$var reg 1 O% done $end +$var reg 2 P% group_index [1:0] $end +$var reg 8 Q% y [7:0] $end $scope module u_mac8 $end -$var wire 40 :% acc_in [39:0] $end -$var wire 128 ;% w_bus [127:0] $end -$var wire 128 <% x_bus [127:0] $end -$var wire 40 =% sum [39:0] $end -$var wire 40 >% s5 [39:0] $end -$var wire 40 ?% s4 [39:0] $end -$var wire 40 @% s3 [39:0] $end -$var wire 40 A% s2 [39:0] $end -$var wire 40 B% s1 [39:0] $end -$var wire 40 C% s0 [39:0] $end -$var wire 40 D% m7 [39:0] $end -$var wire 40 E% m6 [39:0] $end -$var wire 40 F% m5 [39:0] $end -$var wire 40 G% m4 [39:0] $end -$var wire 40 H% m3 [39:0] $end -$var wire 40 I% m2 [39:0] $end -$var wire 40 J% m1 [39:0] $end -$var wire 40 K% m0 [39:0] $end -$var wire 40 L% acc_out [39:0] $end -$var parameter 32 M% ACC_WIDTH $end -$var parameter 32 N% DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 O% acc_in [39:0] $end -$var wire 16 P% w [15:0] $end -$var wire 16 Q% x [15:0] $end -$var wire 40 R% product_ext [39:0] $end -$var wire 32 S% product [31:0] $end -$var wire 40 T% acc_out [39:0] $end -$var parameter 32 U% ACC_WIDTH $end -$var parameter 32 V% DATA_WIDTH $end -$var parameter 64 W% PROD_WIDTH $end +$var wire 32 R% acc_in [31:0] $end +$var wire 64 S% w_bus [63:0] $end +$var wire 64 T% x_bus [63:0] $end +$var wire 32 U% acc_out [31:0] $end +$var parameter 32 V% ACC_WIDTH $end +$var parameter 32 W% DATA_WIDTH $end +$var parameter 32 X% PARALLEL $end +$var parameter 32 Y% TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 Z% i $end +$scope module u_mac $end +$var wire 32 [% acc_in [31:0] $end +$var wire 8 \% w [7:0] $end +$var wire 8 ]% x [7:0] $end +$var wire 32 ^% product_ext [31:0] $end +$var wire 16 _% product [15:0] $end +$var wire 32 `% acc_out [31:0] $end +$var parameter 32 a% ACC_WIDTH $end +$var parameter 32 b% DATA_WIDTH $end +$var parameter 64 c% PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 X% acc_in [39:0] $end -$var wire 16 Y% w [15:0] $end -$var wire 16 Z% x [15:0] $end -$var wire 40 [% product_ext [39:0] $end -$var wire 32 \% product [31:0] $end -$var wire 40 ]% acc_out [39:0] $end -$var parameter 32 ^% ACC_WIDTH $end -$var parameter 32 _% DATA_WIDTH $end -$var parameter 64 `% PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 a% acc_in [39:0] $end -$var wire 16 b% w [15:0] $end -$var wire 16 c% x [15:0] $end -$var wire 40 d% product_ext [39:0] $end -$var wire 32 e% product [31:0] $end -$var wire 40 f% acc_out [39:0] $end -$var parameter 32 g% ACC_WIDTH $end -$var parameter 32 h% DATA_WIDTH $end -$var parameter 64 i% PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 d% i $end +$scope module u_mac $end +$var wire 32 e% acc_in [31:0] $end +$var wire 8 f% w [7:0] $end +$var wire 8 g% x [7:0] $end +$var wire 32 h% product_ext [31:0] $end +$var wire 16 i% product [15:0] $end +$var wire 32 j% acc_out [31:0] $end +$var parameter 32 k% ACC_WIDTH $end +$var parameter 32 l% DATA_WIDTH $end +$var parameter 64 m% PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 j% acc_in [39:0] $end -$var wire 16 k% w [15:0] $end -$var wire 16 l% x [15:0] $end -$var wire 40 m% product_ext [39:0] $end -$var wire 32 n% product [31:0] $end -$var wire 40 o% acc_out [39:0] $end -$var parameter 32 p% ACC_WIDTH $end -$var parameter 32 q% DATA_WIDTH $end -$var parameter 64 r% PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 s% acc_in [39:0] $end -$var wire 16 t% w [15:0] $end -$var wire 16 u% x [15:0] $end -$var wire 40 v% product_ext [39:0] $end -$var wire 32 w% product [31:0] $end -$var wire 40 x% acc_out [39:0] $end -$var parameter 32 y% ACC_WIDTH $end -$var parameter 32 z% DATA_WIDTH $end -$var parameter 64 {% PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 n% i $end +$scope module u_mac $end +$var wire 32 o% acc_in [31:0] $end +$var wire 8 p% w [7:0] $end +$var wire 8 q% x [7:0] $end +$var wire 32 r% product_ext [31:0] $end +$var wire 16 s% product [15:0] $end +$var wire 32 t% acc_out [31:0] $end +$var parameter 32 u% ACC_WIDTH $end +$var parameter 32 v% DATA_WIDTH $end +$var parameter 64 w% PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 |% acc_in [39:0] $end -$var wire 16 }% w [15:0] $end -$var wire 16 ~% x [15:0] $end -$var wire 40 !& product_ext [39:0] $end -$var wire 32 "& product [31:0] $end -$var wire 40 #& acc_out [39:0] $end -$var parameter 32 $& ACC_WIDTH $end -$var parameter 32 %& DATA_WIDTH $end -$var parameter 64 && PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 '& acc_in [39:0] $end -$var wire 16 (& w [15:0] $end -$var wire 16 )& x [15:0] $end -$var wire 40 *& product_ext [39:0] $end -$var wire 32 +& product [31:0] $end -$var wire 40 ,& acc_out [39:0] $end -$var parameter 32 -& ACC_WIDTH $end -$var parameter 32 .& DATA_WIDTH $end -$var parameter 64 /& PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 x% i $end +$scope module u_mac $end +$var wire 32 y% acc_in [31:0] $end +$var wire 8 z% w [7:0] $end +$var wire 8 {% x [7:0] $end +$var wire 32 |% product_ext [31:0] $end +$var wire 16 }% product [15:0] $end +$var wire 32 ~% acc_out [31:0] $end +$var parameter 32 !& ACC_WIDTH $end +$var parameter 32 "& DATA_WIDTH $end +$var parameter 64 #& PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 $& i $end +$scope module u_mac $end +$var wire 32 %& acc_in [31:0] $end +$var wire 8 && w [7:0] $end +$var wire 8 '& x [7:0] $end +$var wire 32 (& product_ext [31:0] $end +$var wire 16 )& product [15:0] $end +$var wire 32 *& acc_out [31:0] $end +$var parameter 32 +& ACC_WIDTH $end +$var parameter 32 ,& DATA_WIDTH $end +$var parameter 64 -& PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 .& i $end +$scope module u_mac $end +$var wire 32 /& acc_in [31:0] $end +$var wire 8 0& w [7:0] $end +$var wire 8 1& x [7:0] $end +$var wire 32 2& product_ext [31:0] $end +$var wire 16 3& product [15:0] $end +$var wire 32 4& acc_out [31:0] $end +$var parameter 32 5& ACC_WIDTH $end +$var parameter 32 6& DATA_WIDTH $end +$var parameter 64 7& PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 8& i $end +$scope module u_mac $end +$var wire 32 9& acc_in [31:0] $end +$var wire 8 :& w [7:0] $end +$var wire 8 ;& x [7:0] $end +$var wire 32 <& product_ext [31:0] $end +$var wire 16 =& product [15:0] $end +$var wire 32 >& acc_out [31:0] $end +$var parameter 32 ?& ACC_WIDTH $end +$var parameter 32 @& DATA_WIDTH $end +$var parameter 64 A& PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 B& i $end +$scope module u_mac $end +$var wire 32 C& acc_in [31:0] $end +$var wire 8 D& w [7:0] $end +$var wire 8 E& x [7:0] $end +$var wire 32 F& product_ext [31:0] $end +$var wire 16 G& product [15:0] $end +$var wire 32 H& acc_out [31:0] $end +$var parameter 32 I& ACC_WIDTH $end +$var parameter 32 J& DATA_WIDTH $end +$var parameter 64 K& PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 L& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 M& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 N& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 O& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 P& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 Q& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 R& i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 S& i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 T& level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 U& node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 V& node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 W& node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 X& node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 Y& level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 Z& node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 [& node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 \& level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 ]& node $end $upscope $end -$scope module mac7 $end -$var wire 40 0& acc_in [39:0] $end -$var wire 16 1& w [15:0] $end -$var wire 16 2& x [15:0] $end -$var wire 40 3& product_ext [39:0] $end -$var wire 32 4& product [31:0] $end -$var wire 40 5& acc_out [39:0] $end -$var parameter 32 6& ACC_WIDTH $end -$var parameter 32 7& DATA_WIDTH $end -$var parameter 64 8& PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[4] $end -$var parameter 4 9& n $end +$var parameter 4 ^& n $end $scope module u_neuron $end -$var wire 16 :& bias [15:0] $end -$var wire 16 ;& bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 <& w_bus [1023:0] $end -$var wire 1024 =& x_bus [1023:0] $end -$var wire 128 >& x_group [127:0] $end -$var wire 128 ?& w_group [127:0] $end -$var wire 40 @& final_value [39:0] $end -$var wire 40 A& final_acc [39:0] $end -$var wire 40 B& bias_ext [39:0] $end -$var wire 40 C& acc_next [39:0] $end -$var parameter 32 D& ACC_WIDTH $end -$var parameter 32 E& DATA_WIDTH $end -$var parameter 32 F& FRAC_BITS $end -$var parameter 32 G& GROUPS $end -$var parameter 32 H& GROUP_INDEX_WIDTH $end -$var parameter 32 I& N_INPUTS $end -$var parameter 32 J& PARALLEL $end -$var reg 40 K& acc [39:0] $end -$var reg 1 L& busy $end -$var reg 1 M& done $end -$var reg 3 N& group_index [2:0] $end -$var reg 16 O& y [15:0] $end +$var wire 8 _& bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 `& w_bus [255:0] $end +$var wire 256 a& x_bus [255:0] $end +$var wire 64 b& x_group [63:0] $end +$var wire 64 c& w_group [63:0] $end +$var wire 32 d& final_acc [31:0] $end +$var wire 32 e& bias_ext [31:0] $end +$var wire 32 f& acc_next [31:0] $end +$var parameter 32 g& ACC_WIDTH $end +$var parameter 32 h& DATA_WIDTH $end +$var parameter 32 i& GROUPS $end +$var parameter 32 j& GROUP_INDEX_WIDTH $end +$var parameter 32 k& N_INPUTS $end +$var parameter 32 l& PARALLEL $end +$var reg 32 m& acc [31:0] $end +$var reg 1 n& busy $end +$var reg 1 o& done $end +$var reg 2 p& group_index [1:0] $end +$var reg 8 q& y [7:0] $end $scope module u_mac8 $end -$var wire 40 P& acc_in [39:0] $end -$var wire 128 Q& w_bus [127:0] $end -$var wire 128 R& x_bus [127:0] $end -$var wire 40 S& sum [39:0] $end -$var wire 40 T& s5 [39:0] $end -$var wire 40 U& s4 [39:0] $end -$var wire 40 V& s3 [39:0] $end -$var wire 40 W& s2 [39:0] $end -$var wire 40 X& s1 [39:0] $end -$var wire 40 Y& s0 [39:0] $end -$var wire 40 Z& m7 [39:0] $end -$var wire 40 [& m6 [39:0] $end -$var wire 40 \& m5 [39:0] $end -$var wire 40 ]& m4 [39:0] $end -$var wire 40 ^& m3 [39:0] $end -$var wire 40 _& m2 [39:0] $end -$var wire 40 `& m1 [39:0] $end -$var wire 40 a& m0 [39:0] $end -$var wire 40 b& acc_out [39:0] $end -$var parameter 32 c& ACC_WIDTH $end -$var parameter 32 d& DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 e& acc_in [39:0] $end -$var wire 16 f& w [15:0] $end -$var wire 16 g& x [15:0] $end -$var wire 40 h& product_ext [39:0] $end -$var wire 32 i& product [31:0] $end -$var wire 40 j& acc_out [39:0] $end -$var parameter 32 k& ACC_WIDTH $end -$var parameter 32 l& DATA_WIDTH $end -$var parameter 64 m& PROD_WIDTH $end +$var wire 32 r& acc_in [31:0] $end +$var wire 64 s& w_bus [63:0] $end +$var wire 64 t& x_bus [63:0] $end +$var wire 32 u& acc_out [31:0] $end +$var parameter 32 v& ACC_WIDTH $end +$var parameter 32 w& DATA_WIDTH $end +$var parameter 32 x& PARALLEL $end +$var parameter 32 y& TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 z& i $end +$scope module u_mac $end +$var wire 32 {& acc_in [31:0] $end +$var wire 8 |& w [7:0] $end +$var wire 8 }& x [7:0] $end +$var wire 32 ~& product_ext [31:0] $end +$var wire 16 !' product [15:0] $end +$var wire 32 "' acc_out [31:0] $end +$var parameter 32 #' ACC_WIDTH $end +$var parameter 32 $' DATA_WIDTH $end +$var parameter 64 %' PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 n& acc_in [39:0] $end -$var wire 16 o& w [15:0] $end -$var wire 16 p& x [15:0] $end -$var wire 40 q& product_ext [39:0] $end -$var wire 32 r& product [31:0] $end -$var wire 40 s& acc_out [39:0] $end -$var parameter 32 t& ACC_WIDTH $end -$var parameter 32 u& DATA_WIDTH $end -$var parameter 64 v& PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 w& acc_in [39:0] $end -$var wire 16 x& w [15:0] $end -$var wire 16 y& x [15:0] $end -$var wire 40 z& product_ext [39:0] $end -$var wire 32 {& product [31:0] $end -$var wire 40 |& acc_out [39:0] $end -$var parameter 32 }& ACC_WIDTH $end -$var parameter 32 ~& DATA_WIDTH $end -$var parameter 64 !' PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 &' i $end +$scope module u_mac $end +$var wire 32 '' acc_in [31:0] $end +$var wire 8 (' w [7:0] $end +$var wire 8 )' x [7:0] $end +$var wire 32 *' product_ext [31:0] $end +$var wire 16 +' product [15:0] $end +$var wire 32 ,' acc_out [31:0] $end +$var parameter 32 -' ACC_WIDTH $end +$var parameter 32 .' DATA_WIDTH $end +$var parameter 64 /' PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 "' acc_in [39:0] $end -$var wire 16 #' w [15:0] $end -$var wire 16 $' x [15:0] $end -$var wire 40 %' product_ext [39:0] $end -$var wire 32 &' product [31:0] $end -$var wire 40 '' acc_out [39:0] $end -$var parameter 32 (' ACC_WIDTH $end -$var parameter 32 )' DATA_WIDTH $end -$var parameter 64 *' PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 +' acc_in [39:0] $end -$var wire 16 ,' w [15:0] $end -$var wire 16 -' x [15:0] $end -$var wire 40 .' product_ext [39:0] $end -$var wire 32 /' product [31:0] $end -$var wire 40 0' acc_out [39:0] $end -$var parameter 32 1' ACC_WIDTH $end -$var parameter 32 2' DATA_WIDTH $end -$var parameter 64 3' PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 0' i $end +$scope module u_mac $end +$var wire 32 1' acc_in [31:0] $end +$var wire 8 2' w [7:0] $end +$var wire 8 3' x [7:0] $end +$var wire 32 4' product_ext [31:0] $end +$var wire 16 5' product [15:0] $end +$var wire 32 6' acc_out [31:0] $end +$var parameter 32 7' ACC_WIDTH $end +$var parameter 32 8' DATA_WIDTH $end +$var parameter 64 9' PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 4' acc_in [39:0] $end -$var wire 16 5' w [15:0] $end -$var wire 16 6' x [15:0] $end -$var wire 40 7' product_ext [39:0] $end -$var wire 32 8' product [31:0] $end -$var wire 40 9' acc_out [39:0] $end -$var parameter 32 :' ACC_WIDTH $end -$var parameter 32 ;' DATA_WIDTH $end -$var parameter 64 <' PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 =' acc_in [39:0] $end -$var wire 16 >' w [15:0] $end -$var wire 16 ?' x [15:0] $end -$var wire 40 @' product_ext [39:0] $end -$var wire 32 A' product [31:0] $end -$var wire 40 B' acc_out [39:0] $end -$var parameter 32 C' ACC_WIDTH $end -$var parameter 32 D' DATA_WIDTH $end -$var parameter 64 E' PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 :' i $end +$scope module u_mac $end +$var wire 32 ;' acc_in [31:0] $end +$var wire 8 <' w [7:0] $end +$var wire 8 =' x [7:0] $end +$var wire 32 >' product_ext [31:0] $end +$var wire 16 ?' product [15:0] $end +$var wire 32 @' acc_out [31:0] $end +$var parameter 32 A' ACC_WIDTH $end +$var parameter 32 B' DATA_WIDTH $end +$var parameter 64 C' PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 D' i $end +$scope module u_mac $end +$var wire 32 E' acc_in [31:0] $end +$var wire 8 F' w [7:0] $end +$var wire 8 G' x [7:0] $end +$var wire 32 H' product_ext [31:0] $end +$var wire 16 I' product [15:0] $end +$var wire 32 J' acc_out [31:0] $end +$var parameter 32 K' ACC_WIDTH $end +$var parameter 32 L' DATA_WIDTH $end +$var parameter 64 M' PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 N' i $end +$scope module u_mac $end +$var wire 32 O' acc_in [31:0] $end +$var wire 8 P' w [7:0] $end +$var wire 8 Q' x [7:0] $end +$var wire 32 R' product_ext [31:0] $end +$var wire 16 S' product [15:0] $end +$var wire 32 T' acc_out [31:0] $end +$var parameter 32 U' ACC_WIDTH $end +$var parameter 32 V' DATA_WIDTH $end +$var parameter 64 W' PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 X' i $end +$scope module u_mac $end +$var wire 32 Y' acc_in [31:0] $end +$var wire 8 Z' w [7:0] $end +$var wire 8 [' x [7:0] $end +$var wire 32 \' product_ext [31:0] $end +$var wire 16 ]' product [15:0] $end +$var wire 32 ^' acc_out [31:0] $end +$var parameter 32 _' ACC_WIDTH $end +$var parameter 32 `' DATA_WIDTH $end +$var parameter 64 a' PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 b' i $end +$scope module u_mac $end +$var wire 32 c' acc_in [31:0] $end +$var wire 8 d' w [7:0] $end +$var wire 8 e' x [7:0] $end +$var wire 32 f' product_ext [31:0] $end +$var wire 16 g' product [15:0] $end +$var wire 32 h' acc_out [31:0] $end +$var parameter 32 i' ACC_WIDTH $end +$var parameter 32 j' DATA_WIDTH $end +$var parameter 64 k' PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 l' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 m' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 n' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 o' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 p' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 q' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 r' i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 s' i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 t' level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 u' node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 v' node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 w' node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 x' node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 y' level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 z' node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 {' node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 |' level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 }' node $end $upscope $end -$scope module mac7 $end -$var wire 40 F' acc_in [39:0] $end -$var wire 16 G' w [15:0] $end -$var wire 16 H' x [15:0] $end -$var wire 40 I' product_ext [39:0] $end -$var wire 32 J' product [31:0] $end -$var wire 40 K' acc_out [39:0] $end -$var parameter 32 L' ACC_WIDTH $end -$var parameter 32 M' DATA_WIDTH $end -$var parameter 64 N' PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[5] $end -$var parameter 4 O' n $end +$var parameter 4 ~' n $end $scope module u_neuron $end -$var wire 16 P' bias [15:0] $end -$var wire 16 Q' bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 R' w_bus [1023:0] $end -$var wire 1024 S' x_bus [1023:0] $end -$var wire 128 T' x_group [127:0] $end -$var wire 128 U' w_group [127:0] $end -$var wire 40 V' final_value [39:0] $end -$var wire 40 W' final_acc [39:0] $end -$var wire 40 X' bias_ext [39:0] $end -$var wire 40 Y' acc_next [39:0] $end -$var parameter 32 Z' ACC_WIDTH $end -$var parameter 32 [' DATA_WIDTH $end -$var parameter 32 \' FRAC_BITS $end -$var parameter 32 ]' GROUPS $end -$var parameter 32 ^' GROUP_INDEX_WIDTH $end -$var parameter 32 _' N_INPUTS $end -$var parameter 32 `' PARALLEL $end -$var reg 40 a' acc [39:0] $end -$var reg 1 b' busy $end -$var reg 1 c' done $end -$var reg 3 d' group_index [2:0] $end -$var reg 16 e' y [15:0] $end +$var wire 8 !( bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 "( w_bus [255:0] $end +$var wire 256 #( x_bus [255:0] $end +$var wire 64 $( x_group [63:0] $end +$var wire 64 %( w_group [63:0] $end +$var wire 32 &( final_acc [31:0] $end +$var wire 32 '( bias_ext [31:0] $end +$var wire 32 (( acc_next [31:0] $end +$var parameter 32 )( ACC_WIDTH $end +$var parameter 32 *( DATA_WIDTH $end +$var parameter 32 +( GROUPS $end +$var parameter 32 ,( GROUP_INDEX_WIDTH $end +$var parameter 32 -( N_INPUTS $end +$var parameter 32 .( PARALLEL $end +$var reg 32 /( acc [31:0] $end +$var reg 1 0( busy $end +$var reg 1 1( done $end +$var reg 2 2( group_index [1:0] $end +$var reg 8 3( y [7:0] $end $scope module u_mac8 $end -$var wire 40 f' acc_in [39:0] $end -$var wire 128 g' w_bus [127:0] $end -$var wire 128 h' x_bus [127:0] $end -$var wire 40 i' sum [39:0] $end -$var wire 40 j' s5 [39:0] $end -$var wire 40 k' s4 [39:0] $end -$var wire 40 l' s3 [39:0] $end -$var wire 40 m' s2 [39:0] $end -$var wire 40 n' s1 [39:0] $end -$var wire 40 o' s0 [39:0] $end -$var wire 40 p' m7 [39:0] $end -$var wire 40 q' m6 [39:0] $end -$var wire 40 r' m5 [39:0] $end -$var wire 40 s' m4 [39:0] $end -$var wire 40 t' m3 [39:0] $end -$var wire 40 u' m2 [39:0] $end -$var wire 40 v' m1 [39:0] $end -$var wire 40 w' m0 [39:0] $end -$var wire 40 x' acc_out [39:0] $end -$var parameter 32 y' ACC_WIDTH $end -$var parameter 32 z' DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 {' acc_in [39:0] $end -$var wire 16 |' w [15:0] $end -$var wire 16 }' x [15:0] $end -$var wire 40 ~' product_ext [39:0] $end -$var wire 32 !( product [31:0] $end -$var wire 40 "( acc_out [39:0] $end -$var parameter 32 #( ACC_WIDTH $end -$var parameter 32 $( DATA_WIDTH $end -$var parameter 64 %( PROD_WIDTH $end +$var wire 32 4( acc_in [31:0] $end +$var wire 64 5( w_bus [63:0] $end +$var wire 64 6( x_bus [63:0] $end +$var wire 32 7( acc_out [31:0] $end +$var parameter 32 8( ACC_WIDTH $end +$var parameter 32 9( DATA_WIDTH $end +$var parameter 32 :( PARALLEL $end +$var parameter 32 ;( TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 <( i $end +$scope module u_mac $end +$var wire 32 =( acc_in [31:0] $end +$var wire 8 >( w [7:0] $end +$var wire 8 ?( x [7:0] $end +$var wire 32 @( product_ext [31:0] $end +$var wire 16 A( product [15:0] $end +$var wire 32 B( acc_out [31:0] $end +$var parameter 32 C( ACC_WIDTH $end +$var parameter 32 D( DATA_WIDTH $end +$var parameter 64 E( PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 &( acc_in [39:0] $end -$var wire 16 '( w [15:0] $end -$var wire 16 (( x [15:0] $end -$var wire 40 )( product_ext [39:0] $end -$var wire 32 *( product [31:0] $end -$var wire 40 +( acc_out [39:0] $end -$var parameter 32 ,( ACC_WIDTH $end -$var parameter 32 -( DATA_WIDTH $end -$var parameter 64 .( PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 /( acc_in [39:0] $end -$var wire 16 0( w [15:0] $end -$var wire 16 1( x [15:0] $end -$var wire 40 2( product_ext [39:0] $end -$var wire 32 3( product [31:0] $end -$var wire 40 4( acc_out [39:0] $end -$var parameter 32 5( ACC_WIDTH $end -$var parameter 32 6( DATA_WIDTH $end -$var parameter 64 7( PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 F( i $end +$scope module u_mac $end +$var wire 32 G( acc_in [31:0] $end +$var wire 8 H( w [7:0] $end +$var wire 8 I( x [7:0] $end +$var wire 32 J( product_ext [31:0] $end +$var wire 16 K( product [15:0] $end +$var wire 32 L( acc_out [31:0] $end +$var parameter 32 M( ACC_WIDTH $end +$var parameter 32 N( DATA_WIDTH $end +$var parameter 64 O( PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 8( acc_in [39:0] $end -$var wire 16 9( w [15:0] $end -$var wire 16 :( x [15:0] $end -$var wire 40 ;( product_ext [39:0] $end -$var wire 32 <( product [31:0] $end -$var wire 40 =( acc_out [39:0] $end -$var parameter 32 >( ACC_WIDTH $end -$var parameter 32 ?( DATA_WIDTH $end -$var parameter 64 @( PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 A( acc_in [39:0] $end -$var wire 16 B( w [15:0] $end -$var wire 16 C( x [15:0] $end -$var wire 40 D( product_ext [39:0] $end -$var wire 32 E( product [31:0] $end -$var wire 40 F( acc_out [39:0] $end -$var parameter 32 G( ACC_WIDTH $end -$var parameter 32 H( DATA_WIDTH $end -$var parameter 64 I( PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 P( i $end +$scope module u_mac $end +$var wire 32 Q( acc_in [31:0] $end +$var wire 8 R( w [7:0] $end +$var wire 8 S( x [7:0] $end +$var wire 32 T( product_ext [31:0] $end +$var wire 16 U( product [15:0] $end +$var wire 32 V( acc_out [31:0] $end +$var parameter 32 W( ACC_WIDTH $end +$var parameter 32 X( DATA_WIDTH $end +$var parameter 64 Y( PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 J( acc_in [39:0] $end -$var wire 16 K( w [15:0] $end -$var wire 16 L( x [15:0] $end -$var wire 40 M( product_ext [39:0] $end -$var wire 32 N( product [31:0] $end -$var wire 40 O( acc_out [39:0] $end -$var parameter 32 P( ACC_WIDTH $end -$var parameter 32 Q( DATA_WIDTH $end -$var parameter 64 R( PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 S( acc_in [39:0] $end -$var wire 16 T( w [15:0] $end -$var wire 16 U( x [15:0] $end -$var wire 40 V( product_ext [39:0] $end -$var wire 32 W( product [31:0] $end -$var wire 40 X( acc_out [39:0] $end -$var parameter 32 Y( ACC_WIDTH $end -$var parameter 32 Z( DATA_WIDTH $end -$var parameter 64 [( PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 Z( i $end +$scope module u_mac $end +$var wire 32 [( acc_in [31:0] $end +$var wire 8 \( w [7:0] $end +$var wire 8 ]( x [7:0] $end +$var wire 32 ^( product_ext [31:0] $end +$var wire 16 _( product [15:0] $end +$var wire 32 `( acc_out [31:0] $end +$var parameter 32 a( ACC_WIDTH $end +$var parameter 32 b( DATA_WIDTH $end +$var parameter 64 c( PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 d( i $end +$scope module u_mac $end +$var wire 32 e( acc_in [31:0] $end +$var wire 8 f( w [7:0] $end +$var wire 8 g( x [7:0] $end +$var wire 32 h( product_ext [31:0] $end +$var wire 16 i( product [15:0] $end +$var wire 32 j( acc_out [31:0] $end +$var parameter 32 k( ACC_WIDTH $end +$var parameter 32 l( DATA_WIDTH $end +$var parameter 64 m( PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 n( i $end +$scope module u_mac $end +$var wire 32 o( acc_in [31:0] $end +$var wire 8 p( w [7:0] $end +$var wire 8 q( x [7:0] $end +$var wire 32 r( product_ext [31:0] $end +$var wire 16 s( product [15:0] $end +$var wire 32 t( acc_out [31:0] $end +$var parameter 32 u( ACC_WIDTH $end +$var parameter 32 v( DATA_WIDTH $end +$var parameter 64 w( PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 x( i $end +$scope module u_mac $end +$var wire 32 y( acc_in [31:0] $end +$var wire 8 z( w [7:0] $end +$var wire 8 {( x [7:0] $end +$var wire 32 |( product_ext [31:0] $end +$var wire 16 }( product [15:0] $end +$var wire 32 ~( acc_out [31:0] $end +$var parameter 32 !) ACC_WIDTH $end +$var parameter 32 ") DATA_WIDTH $end +$var parameter 64 #) PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 $) i $end +$scope module u_mac $end +$var wire 32 %) acc_in [31:0] $end +$var wire 8 &) w [7:0] $end +$var wire 8 ') x [7:0] $end +$var wire 32 () product_ext [31:0] $end +$var wire 16 )) product [15:0] $end +$var wire 32 *) acc_out [31:0] $end +$var parameter 32 +) ACC_WIDTH $end +$var parameter 32 ,) DATA_WIDTH $end +$var parameter 64 -) PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 .) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 /) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 0) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 1) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 2) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 3) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 4) i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 5) i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 6) level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 7) node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 8) node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 9) node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 :) node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 ;) level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 <) node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 =) node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 >) level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 ?) node $end $upscope $end -$scope module mac7 $end -$var wire 40 \( acc_in [39:0] $end -$var wire 16 ]( w [15:0] $end -$var wire 16 ^( x [15:0] $end -$var wire 40 _( product_ext [39:0] $end -$var wire 32 `( product [31:0] $end -$var wire 40 a( acc_out [39:0] $end -$var parameter 32 b( ACC_WIDTH $end -$var parameter 32 c( DATA_WIDTH $end -$var parameter 64 d( PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[6] $end -$var parameter 4 e( n $end +$var parameter 4 @) n $end $scope module u_neuron $end -$var wire 16 f( bias [15:0] $end -$var wire 16 g( bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 h( w_bus [1023:0] $end -$var wire 1024 i( x_bus [1023:0] $end -$var wire 128 j( x_group [127:0] $end -$var wire 128 k( w_group [127:0] $end -$var wire 40 l( final_value [39:0] $end -$var wire 40 m( final_acc [39:0] $end -$var wire 40 n( bias_ext [39:0] $end -$var wire 40 o( acc_next [39:0] $end -$var parameter 32 p( ACC_WIDTH $end -$var parameter 32 q( DATA_WIDTH $end -$var parameter 32 r( FRAC_BITS $end -$var parameter 32 s( GROUPS $end -$var parameter 32 t( GROUP_INDEX_WIDTH $end -$var parameter 32 u( N_INPUTS $end -$var parameter 32 v( PARALLEL $end -$var reg 40 w( acc [39:0] $end -$var reg 1 x( busy $end -$var reg 1 y( done $end -$var reg 3 z( group_index [2:0] $end -$var reg 16 {( y [15:0] $end +$var wire 8 A) bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 B) w_bus [255:0] $end +$var wire 256 C) x_bus [255:0] $end +$var wire 64 D) x_group [63:0] $end +$var wire 64 E) w_group [63:0] $end +$var wire 32 F) final_acc [31:0] $end +$var wire 32 G) bias_ext [31:0] $end +$var wire 32 H) acc_next [31:0] $end +$var parameter 32 I) ACC_WIDTH $end +$var parameter 32 J) DATA_WIDTH $end +$var parameter 32 K) GROUPS $end +$var parameter 32 L) GROUP_INDEX_WIDTH $end +$var parameter 32 M) N_INPUTS $end +$var parameter 32 N) PARALLEL $end +$var reg 32 O) acc [31:0] $end +$var reg 1 P) busy $end +$var reg 1 Q) done $end +$var reg 2 R) group_index [1:0] $end +$var reg 8 S) y [7:0] $end $scope module u_mac8 $end -$var wire 40 |( acc_in [39:0] $end -$var wire 128 }( w_bus [127:0] $end -$var wire 128 ~( x_bus [127:0] $end -$var wire 40 !) sum [39:0] $end -$var wire 40 ") s5 [39:0] $end -$var wire 40 #) s4 [39:0] $end -$var wire 40 $) s3 [39:0] $end -$var wire 40 %) s2 [39:0] $end -$var wire 40 &) s1 [39:0] $end -$var wire 40 ') s0 [39:0] $end -$var wire 40 () m7 [39:0] $end -$var wire 40 )) m6 [39:0] $end -$var wire 40 *) m5 [39:0] $end -$var wire 40 +) m4 [39:0] $end -$var wire 40 ,) m3 [39:0] $end -$var wire 40 -) m2 [39:0] $end -$var wire 40 .) m1 [39:0] $end -$var wire 40 /) m0 [39:0] $end -$var wire 40 0) acc_out [39:0] $end -$var parameter 32 1) ACC_WIDTH $end -$var parameter 32 2) DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 3) acc_in [39:0] $end -$var wire 16 4) w [15:0] $end -$var wire 16 5) x [15:0] $end -$var wire 40 6) product_ext [39:0] $end -$var wire 32 7) product [31:0] $end -$var wire 40 8) acc_out [39:0] $end -$var parameter 32 9) ACC_WIDTH $end -$var parameter 32 :) DATA_WIDTH $end -$var parameter 64 ;) PROD_WIDTH $end +$var wire 32 T) acc_in [31:0] $end +$var wire 64 U) w_bus [63:0] $end +$var wire 64 V) x_bus [63:0] $end +$var wire 32 W) acc_out [31:0] $end +$var parameter 32 X) ACC_WIDTH $end +$var parameter 32 Y) DATA_WIDTH $end +$var parameter 32 Z) PARALLEL $end +$var parameter 32 [) TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 \) i $end +$scope module u_mac $end +$var wire 32 ]) acc_in [31:0] $end +$var wire 8 ^) w [7:0] $end +$var wire 8 _) x [7:0] $end +$var wire 32 `) product_ext [31:0] $end +$var wire 16 a) product [15:0] $end +$var wire 32 b) acc_out [31:0] $end +$var parameter 32 c) ACC_WIDTH $end +$var parameter 32 d) DATA_WIDTH $end +$var parameter 64 e) PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 <) acc_in [39:0] $end -$var wire 16 =) w [15:0] $end -$var wire 16 >) x [15:0] $end -$var wire 40 ?) product_ext [39:0] $end -$var wire 32 @) product [31:0] $end -$var wire 40 A) acc_out [39:0] $end -$var parameter 32 B) ACC_WIDTH $end -$var parameter 32 C) DATA_WIDTH $end -$var parameter 64 D) PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 E) acc_in [39:0] $end -$var wire 16 F) w [15:0] $end -$var wire 16 G) x [15:0] $end -$var wire 40 H) product_ext [39:0] $end -$var wire 32 I) product [31:0] $end -$var wire 40 J) acc_out [39:0] $end -$var parameter 32 K) ACC_WIDTH $end -$var parameter 32 L) DATA_WIDTH $end -$var parameter 64 M) PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 f) i $end +$scope module u_mac $end +$var wire 32 g) acc_in [31:0] $end +$var wire 8 h) w [7:0] $end +$var wire 8 i) x [7:0] $end +$var wire 32 j) product_ext [31:0] $end +$var wire 16 k) product [15:0] $end +$var wire 32 l) acc_out [31:0] $end +$var parameter 32 m) ACC_WIDTH $end +$var parameter 32 n) DATA_WIDTH $end +$var parameter 64 o) PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 N) acc_in [39:0] $end -$var wire 16 O) w [15:0] $end -$var wire 16 P) x [15:0] $end -$var wire 40 Q) product_ext [39:0] $end -$var wire 32 R) product [31:0] $end -$var wire 40 S) acc_out [39:0] $end -$var parameter 32 T) ACC_WIDTH $end -$var parameter 32 U) DATA_WIDTH $end -$var parameter 64 V) PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 W) acc_in [39:0] $end -$var wire 16 X) w [15:0] $end -$var wire 16 Y) x [15:0] $end -$var wire 40 Z) product_ext [39:0] $end -$var wire 32 [) product [31:0] $end -$var wire 40 \) acc_out [39:0] $end -$var parameter 32 ]) ACC_WIDTH $end -$var parameter 32 ^) DATA_WIDTH $end -$var parameter 64 _) PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 p) i $end +$scope module u_mac $end +$var wire 32 q) acc_in [31:0] $end +$var wire 8 r) w [7:0] $end +$var wire 8 s) x [7:0] $end +$var wire 32 t) product_ext [31:0] $end +$var wire 16 u) product [15:0] $end +$var wire 32 v) acc_out [31:0] $end +$var parameter 32 w) ACC_WIDTH $end +$var parameter 32 x) DATA_WIDTH $end +$var parameter 64 y) PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 `) acc_in [39:0] $end -$var wire 16 a) w [15:0] $end -$var wire 16 b) x [15:0] $end -$var wire 40 c) product_ext [39:0] $end -$var wire 32 d) product [31:0] $end -$var wire 40 e) acc_out [39:0] $end -$var parameter 32 f) ACC_WIDTH $end -$var parameter 32 g) DATA_WIDTH $end -$var parameter 64 h) PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 i) acc_in [39:0] $end -$var wire 16 j) w [15:0] $end -$var wire 16 k) x [15:0] $end -$var wire 40 l) product_ext [39:0] $end -$var wire 32 m) product [31:0] $end -$var wire 40 n) acc_out [39:0] $end -$var parameter 32 o) ACC_WIDTH $end -$var parameter 32 p) DATA_WIDTH $end -$var parameter 64 q) PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 z) i $end +$scope module u_mac $end +$var wire 32 {) acc_in [31:0] $end +$var wire 8 |) w [7:0] $end +$var wire 8 }) x [7:0] $end +$var wire 32 ~) product_ext [31:0] $end +$var wire 16 !* product [15:0] $end +$var wire 32 "* acc_out [31:0] $end +$var parameter 32 #* ACC_WIDTH $end +$var parameter 32 $* DATA_WIDTH $end +$var parameter 64 %* PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 &* i $end +$scope module u_mac $end +$var wire 32 '* acc_in [31:0] $end +$var wire 8 (* w [7:0] $end +$var wire 8 )* x [7:0] $end +$var wire 32 ** product_ext [31:0] $end +$var wire 16 +* product [15:0] $end +$var wire 32 ,* acc_out [31:0] $end +$var parameter 32 -* ACC_WIDTH $end +$var parameter 32 .* DATA_WIDTH $end +$var parameter 64 /* PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 0* i $end +$scope module u_mac $end +$var wire 32 1* acc_in [31:0] $end +$var wire 8 2* w [7:0] $end +$var wire 8 3* x [7:0] $end +$var wire 32 4* product_ext [31:0] $end +$var wire 16 5* product [15:0] $end +$var wire 32 6* acc_out [31:0] $end +$var parameter 32 7* ACC_WIDTH $end +$var parameter 32 8* DATA_WIDTH $end +$var parameter 64 9* PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 :* i $end +$scope module u_mac $end +$var wire 32 ;* acc_in [31:0] $end +$var wire 8 <* w [7:0] $end +$var wire 8 =* x [7:0] $end +$var wire 32 >* product_ext [31:0] $end +$var wire 16 ?* product [15:0] $end +$var wire 32 @* acc_out [31:0] $end +$var parameter 32 A* ACC_WIDTH $end +$var parameter 32 B* DATA_WIDTH $end +$var parameter 64 C* PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 D* i $end +$scope module u_mac $end +$var wire 32 E* acc_in [31:0] $end +$var wire 8 F* w [7:0] $end +$var wire 8 G* x [7:0] $end +$var wire 32 H* product_ext [31:0] $end +$var wire 16 I* product [15:0] $end +$var wire 32 J* acc_out [31:0] $end +$var parameter 32 K* ACC_WIDTH $end +$var parameter 32 L* DATA_WIDTH $end +$var parameter 64 M* PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 N* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 O* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 P* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 Q* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 R* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 S* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 T* i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 U* i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 V* level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 W* node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 X* node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 Y* node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 Z* node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 [* level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 \* node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 ]* node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 ^* level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 _* node $end $upscope $end -$scope module mac7 $end -$var wire 40 r) acc_in [39:0] $end -$var wire 16 s) w [15:0] $end -$var wire 16 t) x [15:0] $end -$var wire 40 u) product_ext [39:0] $end -$var wire 32 v) product [31:0] $end -$var wire 40 w) acc_out [39:0] $end -$var parameter 32 x) ACC_WIDTH $end -$var parameter 32 y) DATA_WIDTH $end -$var parameter 64 z) PROD_WIDTH $end $upscope $end $upscope $end $upscope $end $upscope $end $scope begin GEN_NEURON[7] $end -$var parameter 4 {) n $end +$var parameter 4 `* n $end $scope module u_neuron $end -$var wire 16 |) bias [15:0] $end -$var wire 16 }) bias_ext_small [15:0] $end -$var wire 1 + clk $end -$var wire 1 , rst $end -$var wire 1 - start $end -$var wire 1024 ~) w_bus [1023:0] $end -$var wire 1024 !* x_bus [1023:0] $end -$var wire 128 "* x_group [127:0] $end -$var wire 128 #* w_group [127:0] $end -$var wire 40 $* final_value [39:0] $end -$var wire 40 %* final_acc [39:0] $end -$var wire 40 &* bias_ext [39:0] $end -$var wire 40 '* acc_next [39:0] $end -$var parameter 32 (* ACC_WIDTH $end -$var parameter 32 )* DATA_WIDTH $end -$var parameter 32 ** FRAC_BITS $end -$var parameter 32 +* GROUPS $end -$var parameter 32 ,* GROUP_INDEX_WIDTH $end -$var parameter 32 -* N_INPUTS $end -$var parameter 32 .* PARALLEL $end -$var reg 40 /* acc [39:0] $end -$var reg 1 0* busy $end -$var reg 1 1* done $end -$var reg 3 2* group_index [2:0] $end -$var reg 16 3* y [15:0] $end +$var wire 8 a* bias [7:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 256 b* w_bus [255:0] $end +$var wire 256 c* x_bus [255:0] $end +$var wire 64 d* x_group [63:0] $end +$var wire 64 e* w_group [63:0] $end +$var wire 32 f* final_acc [31:0] $end +$var wire 32 g* bias_ext [31:0] $end +$var wire 32 h* acc_next [31:0] $end +$var parameter 32 i* ACC_WIDTH $end +$var parameter 32 j* DATA_WIDTH $end +$var parameter 32 k* GROUPS $end +$var parameter 32 l* GROUP_INDEX_WIDTH $end +$var parameter 32 m* N_INPUTS $end +$var parameter 32 n* PARALLEL $end +$var reg 32 o* acc [31:0] $end +$var reg 1 p* busy $end +$var reg 1 q* done $end +$var reg 2 r* group_index [1:0] $end +$var reg 8 s* y [7:0] $end $scope module u_mac8 $end -$var wire 40 4* acc_in [39:0] $end -$var wire 128 5* w_bus [127:0] $end -$var wire 128 6* x_bus [127:0] $end -$var wire 40 7* sum [39:0] $end -$var wire 40 8* s5 [39:0] $end -$var wire 40 9* s4 [39:0] $end -$var wire 40 :* s3 [39:0] $end -$var wire 40 ;* s2 [39:0] $end -$var wire 40 <* s1 [39:0] $end -$var wire 40 =* s0 [39:0] $end -$var wire 40 >* m7 [39:0] $end -$var wire 40 ?* m6 [39:0] $end -$var wire 40 @* m5 [39:0] $end -$var wire 40 A* m4 [39:0] $end -$var wire 40 B* m3 [39:0] $end -$var wire 40 C* m2 [39:0] $end -$var wire 40 D* m1 [39:0] $end -$var wire 40 E* m0 [39:0] $end -$var wire 40 F* acc_out [39:0] $end -$var parameter 32 G* ACC_WIDTH $end -$var parameter 32 H* DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 I* acc_in [39:0] $end -$var wire 16 J* w [15:0] $end -$var wire 16 K* x [15:0] $end -$var wire 40 L* product_ext [39:0] $end -$var wire 32 M* product [31:0] $end -$var wire 40 N* acc_out [39:0] $end -$var parameter 32 O* ACC_WIDTH $end -$var parameter 32 P* DATA_WIDTH $end -$var parameter 64 Q* PROD_WIDTH $end +$var wire 32 t* acc_in [31:0] $end +$var wire 64 u* w_bus [63:0] $end +$var wire 64 v* x_bus [63:0] $end +$var wire 32 w* acc_out [31:0] $end +$var parameter 32 x* ACC_WIDTH $end +$var parameter 32 y* DATA_WIDTH $end +$var parameter 32 z* PARALLEL $end +$var parameter 32 {* TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 |* i $end +$scope module u_mac $end +$var wire 32 }* acc_in [31:0] $end +$var wire 8 ~* w [7:0] $end +$var wire 8 !+ x [7:0] $end +$var wire 32 "+ product_ext [31:0] $end +$var wire 16 #+ product [15:0] $end +$var wire 32 $+ acc_out [31:0] $end +$var parameter 32 %+ ACC_WIDTH $end +$var parameter 32 &+ DATA_WIDTH $end +$var parameter 64 '+ PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 R* acc_in [39:0] $end -$var wire 16 S* w [15:0] $end -$var wire 16 T* x [15:0] $end -$var wire 40 U* product_ext [39:0] $end -$var wire 32 V* product [31:0] $end -$var wire 40 W* acc_out [39:0] $end -$var parameter 32 X* ACC_WIDTH $end -$var parameter 32 Y* DATA_WIDTH $end -$var parameter 64 Z* PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 [* acc_in [39:0] $end -$var wire 16 \* w [15:0] $end -$var wire 16 ]* x [15:0] $end -$var wire 40 ^* product_ext [39:0] $end -$var wire 32 _* product [31:0] $end -$var wire 40 `* acc_out [39:0] $end -$var parameter 32 a* ACC_WIDTH $end -$var parameter 32 b* DATA_WIDTH $end -$var parameter 64 c* PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 (+ i $end +$scope module u_mac $end +$var wire 32 )+ acc_in [31:0] $end +$var wire 8 *+ w [7:0] $end +$var wire 8 ++ x [7:0] $end +$var wire 32 ,+ product_ext [31:0] $end +$var wire 16 -+ product [15:0] $end +$var wire 32 .+ acc_out [31:0] $end +$var parameter 32 /+ ACC_WIDTH $end +$var parameter 32 0+ DATA_WIDTH $end +$var parameter 64 1+ PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 d* acc_in [39:0] $end -$var wire 16 e* w [15:0] $end -$var wire 16 f* x [15:0] $end -$var wire 40 g* product_ext [39:0] $end -$var wire 32 h* product [31:0] $end -$var wire 40 i* acc_out [39:0] $end -$var parameter 32 j* ACC_WIDTH $end -$var parameter 32 k* DATA_WIDTH $end -$var parameter 64 l* PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 m* acc_in [39:0] $end -$var wire 16 n* w [15:0] $end -$var wire 16 o* x [15:0] $end -$var wire 40 p* product_ext [39:0] $end -$var wire 32 q* product [31:0] $end -$var wire 40 r* acc_out [39:0] $end -$var parameter 32 s* ACC_WIDTH $end -$var parameter 32 t* DATA_WIDTH $end -$var parameter 64 u* PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 2+ i $end +$scope module u_mac $end +$var wire 32 3+ acc_in [31:0] $end +$var wire 8 4+ w [7:0] $end +$var wire 8 5+ x [7:0] $end +$var wire 32 6+ product_ext [31:0] $end +$var wire 16 7+ product [15:0] $end +$var wire 32 8+ acc_out [31:0] $end +$var parameter 32 9+ ACC_WIDTH $end +$var parameter 32 :+ DATA_WIDTH $end +$var parameter 64 ;+ PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 v* acc_in [39:0] $end -$var wire 16 w* w [15:0] $end -$var wire 16 x* x [15:0] $end -$var wire 40 y* product_ext [39:0] $end -$var wire 32 z* product [31:0] $end -$var wire 40 {* acc_out [39:0] $end -$var parameter 32 |* ACC_WIDTH $end -$var parameter 32 }* DATA_WIDTH $end -$var parameter 64 ~* PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 !+ acc_in [39:0] $end -$var wire 16 "+ w [15:0] $end -$var wire 16 #+ x [15:0] $end -$var wire 40 $+ product_ext [39:0] $end -$var wire 32 %+ product [31:0] $end -$var wire 40 &+ acc_out [39:0] $end -$var parameter 32 '+ ACC_WIDTH $end -$var parameter 32 (+ DATA_WIDTH $end -$var parameter 64 )+ PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 <+ i $end +$scope module u_mac $end +$var wire 32 =+ acc_in [31:0] $end +$var wire 8 >+ w [7:0] $end +$var wire 8 ?+ x [7:0] $end +$var wire 32 @+ product_ext [31:0] $end +$var wire 16 A+ product [15:0] $end +$var wire 32 B+ acc_out [31:0] $end +$var parameter 32 C+ ACC_WIDTH $end +$var parameter 32 D+ DATA_WIDTH $end +$var parameter 64 E+ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 F+ i $end +$scope module u_mac $end +$var wire 32 G+ acc_in [31:0] $end +$var wire 8 H+ w [7:0] $end +$var wire 8 I+ x [7:0] $end +$var wire 32 J+ product_ext [31:0] $end +$var wire 16 K+ product [15:0] $end +$var wire 32 L+ acc_out [31:0] $end +$var parameter 32 M+ ACC_WIDTH $end +$var parameter 32 N+ DATA_WIDTH $end +$var parameter 64 O+ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 P+ i $end +$scope module u_mac $end +$var wire 32 Q+ acc_in [31:0] $end +$var wire 8 R+ w [7:0] $end +$var wire 8 S+ x [7:0] $end +$var wire 32 T+ product_ext [31:0] $end +$var wire 16 U+ product [15:0] $end +$var wire 32 V+ acc_out [31:0] $end +$var parameter 32 W+ ACC_WIDTH $end +$var parameter 32 X+ DATA_WIDTH $end +$var parameter 64 Y+ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 Z+ i $end +$scope module u_mac $end +$var wire 32 [+ acc_in [31:0] $end +$var wire 8 \+ w [7:0] $end +$var wire 8 ]+ x [7:0] $end +$var wire 32 ^+ product_ext [31:0] $end +$var wire 16 _+ product [15:0] $end +$var wire 32 `+ acc_out [31:0] $end +$var parameter 32 a+ ACC_WIDTH $end +$var parameter 32 b+ DATA_WIDTH $end +$var parameter 64 c+ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 d+ i $end +$scope module u_mac $end +$var wire 32 e+ acc_in [31:0] $end +$var wire 8 f+ w [7:0] $end +$var wire 8 g+ x [7:0] $end +$var wire 32 h+ product_ext [31:0] $end +$var wire 16 i+ product [15:0] $end +$var wire 32 j+ acc_out [31:0] $end +$var parameter 32 k+ ACC_WIDTH $end +$var parameter 32 l+ DATA_WIDTH $end +$var parameter 64 m+ PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 n+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 o+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 p+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 q+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 r+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 s+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 t+ i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 u+ i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 v+ level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 w+ node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 x+ node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 y+ node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 z+ node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 {+ level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 |+ node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 }+ node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 ~+ level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 !, node $end $upscope $end -$scope module mac7 $end -$var wire 40 *+ acc_in [39:0] $end -$var wire 16 ++ w [15:0] $end -$var wire 16 ,+ x [15:0] $end -$var wire 40 -+ product_ext [39:0] $end -$var wire 32 .+ product [31:0] $end -$var wire 40 /+ acc_out [39:0] $end -$var parameter 32 0+ ACC_WIDTH $end -$var parameter 32 1+ DATA_WIDTH $end -$var parameter 64 2+ PROD_WIDTH $end $upscope $end $upscope $end $upscope $end @@ -1181,2412 +1672,2069 @@ $upscope $end $enddefinitions $end $comment Show the parameter values. $end $dumpall -b100000 2+ +b0 !, +b10 ~+ +b1 }+ +b0 |+ +b1 {+ +b11 z+ +b10 y+ +b1 x+ +b0 w+ +b0 v+ +b111 u+ +b110 t+ +b101 s+ +b100 r+ +b11 q+ +b10 p+ +b1 o+ +b0 n+ +b10000 m+ +b1000 l+ +b100000 k+ +b111 d+ +b10000 c+ +b1000 b+ +b100000 a+ +b110 Z+ +b10000 Y+ +b1000 X+ +b100000 W+ +b101 P+ +b10000 O+ +b1000 N+ +b100000 M+ +b100 F+ +b10000 E+ +b1000 D+ +b100000 C+ +b11 <+ +b10000 ;+ +b1000 :+ +b100000 9+ +b10 2+ b10000 1+ -b101000 0+ -b100000 )+ -b10000 (+ -b101000 '+ -b100000 ~* -b10000 }* -b101000 |* -b100000 u* -b10000 t* -b101000 s* -b100000 l* -b10000 k* -b101000 j* -b100000 c* -b10000 b* -b101000 a* -b100000 Z* -b10000 Y* -b101000 X* -b100000 Q* -b10000 P* -b101000 O* -b10000 H* -b101000 G* +b1000 0+ +b100000 /+ +b1 (+ +b10000 '+ +b1000 &+ +b100000 %+ +b0 |* +b11 {* +b1000 z* +b1000 y* +b100000 x* +b1000 n* +b100000 m* +b10 l* +b100 k* +b1000 j* +b100000 i* +b111 `* +b0 _* +b10 ^* +b1 ]* +b0 \* +b1 [* +b11 Z* +b10 Y* +b1 X* +b0 W* +b0 V* +b111 U* +b110 T* +b101 S* +b100 R* +b11 Q* +b10 P* +b1 O* +b0 N* +b10000 M* +b1000 L* +b100000 K* +b111 D* +b10000 C* +b1000 B* +b100000 A* +b110 :* +b10000 9* +b1000 8* +b100000 7* +b101 0* +b10000 /* b1000 .* -b1000000 -* -b11 ,* -b1000 +* -b1000 ** -b10000 )* -b101000 (* -b111 {) -b100000 z) +b100000 -* +b100 &* +b10000 %* +b1000 $* +b100000 #* +b11 z) b10000 y) -b101000 x) -b100000 q) -b10000 p) -b101000 o) -b100000 h) -b10000 g) -b101000 f) -b100000 _) -b10000 ^) -b101000 ]) -b100000 V) -b10000 U) -b101000 T) +b1000 x) +b100000 w) +b10 p) +b10000 o) +b1000 n) +b100000 m) +b1 f) +b10000 e) +b1000 d) +b100000 c) +b0 \) +b11 [) +b1000 Z) +b1000 Y) +b100000 X) +b1000 N) b100000 M) -b10000 L) -b101000 K) -b100000 D) -b10000 C) -b101000 B) -b100000 ;) -b10000 :) -b101000 9) -b10000 2) -b101000 1) +b10 L) +b100 K) +b1000 J) +b100000 I) +b110 @) +b0 ?) +b10 >) +b1 =) +b0 <) +b1 ;) +b11 :) +b10 9) +b1 8) +b0 7) +b0 6) +b111 5) +b110 4) +b101 3) +b100 2) +b11 1) +b10 0) +b1 /) +b0 .) +b10000 -) +b1000 ,) +b100000 +) +b111 $) +b10000 #) +b1000 ") +b100000 !) +b110 x( +b10000 w( b1000 v( -b1000000 u( -b11 t( -b1000 s( -b1000 r( -b10000 q( -b101000 p( -b110 e( -b100000 d( +b100000 u( +b101 n( +b10000 m( +b1000 l( +b100000 k( +b100 d( b10000 c( -b101000 b( -b100000 [( -b10000 Z( -b101000 Y( -b100000 R( -b10000 Q( -b101000 P( -b100000 I( -b10000 H( -b101000 G( -b100000 @( -b10000 ?( -b101000 >( -b100000 7( -b10000 6( -b101000 5( -b100000 .( -b10000 -( -b101000 ,( -b100000 %( -b10000 $( -b101000 #( -b10000 z' -b101000 y' +b1000 b( +b100000 a( +b11 Z( +b10000 Y( +b1000 X( +b100000 W( +b10 P( +b10000 O( +b1000 N( +b100000 M( +b1 F( +b10000 E( +b1000 D( +b100000 C( +b0 <( +b11 ;( +b1000 :( +b1000 9( +b100000 8( +b1000 .( +b100000 -( +b10 ,( +b100 +( +b1000 *( +b100000 )( +b101 ~' +b0 }' +b10 |' +b1 {' +b0 z' +b1 y' +b11 x' +b10 w' +b1 v' +b0 u' +b0 t' +b111 s' +b110 r' +b101 q' +b100 p' +b11 o' +b10 n' +b1 m' +b0 l' +b10000 k' +b1000 j' +b100000 i' +b111 b' +b10000 a' b1000 `' -b1000000 _' -b11 ^' -b1000 ]' -b1000 \' -b10000 [' -b101000 Z' -b101 O' -b100000 N' +b100000 _' +b110 X' +b10000 W' +b1000 V' +b100000 U' +b101 N' b10000 M' -b101000 L' -b100000 E' -b10000 D' -b101000 C' -b100000 <' -b10000 ;' -b101000 :' -b100000 3' -b10000 2' -b101000 1' -b100000 *' -b10000 )' -b101000 (' -b100000 !' -b10000 ~& -b101000 }& +b1000 L' +b100000 K' +b100 D' +b10000 C' +b1000 B' +b100000 A' +b11 :' +b10000 9' +b1000 8' +b100000 7' +b10 0' +b10000 /' +b1000 .' +b100000 -' +b1 &' +b10000 %' +b1000 $' +b100000 #' +b0 z& +b11 y& +b1000 x& +b1000 w& b100000 v& -b10000 u& -b101000 t& -b100000 m& -b10000 l& -b101000 k& -b10000 d& -b101000 c& +b1000 l& +b100000 k& +b10 j& +b100 i& +b1000 h& +b100000 g& +b100 ^& +b0 ]& +b10 \& +b1 [& +b0 Z& +b1 Y& +b11 X& +b10 W& +b1 V& +b0 U& +b0 T& +b111 S& +b110 R& +b101 Q& +b100 P& +b11 O& +b10 N& +b1 M& +b0 L& +b10000 K& b1000 J& -b1000000 I& -b11 H& -b1000 G& -b1000 F& -b10000 E& -b101000 D& -b100 9& -b100000 8& +b100000 I& +b111 B& +b10000 A& +b1000 @& +b100000 ?& +b110 8& b10000 7& -b101000 6& -b100000 /& -b10000 .& -b101000 -& -b100000 && -b10000 %& -b101000 $& -b100000 {% -b10000 z% -b101000 y% -b100000 r% -b10000 q% -b101000 p% -b100000 i% -b10000 h% -b101000 g% -b100000 `% -b10000 _% -b101000 ^% -b100000 W% -b10000 V% -b101000 U% -b10000 N% -b101000 M% -b1000 4% -b1000000 3% -b11 2% -b1000 1% -b1000 0% -b10000 /% -b101000 .% -b11 #% -b100000 "% +b1000 6& +b100000 5& +b101 .& +b10000 -& +b1000 ,& +b100000 +& +b100 $& +b10000 #& +b1000 "& +b100000 !& +b11 x% +b10000 w% +b1000 v% +b100000 u% +b10 n% +b10000 m% +b1000 l% +b100000 k% +b1 d% +b10000 c% +b1000 b% +b100000 a% +b0 Z% +b11 Y% +b1000 X% +b1000 W% +b100000 V% +b1000 L% +b100000 K% +b10 J% +b100 I% +b1000 H% +b100000 G% +b11 >% +b0 =% +b10 <% +b1 ;% +b0 :% +b1 9% +b11 8% +b10 7% +b1 6% +b0 5% +b0 4% +b111 3% +b110 2% +b101 1% +b100 0% +b11 /% +b10 .% +b1 -% +b0 ,% +b10000 +% +b1000 *% +b100000 )% +b111 "% b10000 !% -b101000 ~$ -b100000 w$ -b10000 v$ -b101000 u$ -b100000 n$ -b10000 m$ -b101000 l$ -b100000 e$ -b10000 d$ -b101000 c$ -b100000 \$ -b10000 [$ -b101000 Z$ -b100000 S$ -b10000 R$ -b101000 Q$ -b100000 J$ -b10000 I$ -b101000 H$ +b1000 ~$ +b100000 }$ +b110 v$ +b10000 u$ +b1000 t$ +b100000 s$ +b101 l$ +b10000 k$ +b1000 j$ +b100000 i$ +b100 b$ +b10000 a$ +b1000 `$ +b100000 _$ +b11 X$ +b10000 W$ +b1000 V$ +b100000 U$ +b10 N$ +b10000 M$ +b1000 L$ +b100000 K$ +b1 D$ +b10000 C$ +b1000 B$ b100000 A$ -b10000 @$ -b101000 ?$ -b10000 8$ -b101000 7$ -b1000 |# -b1000000 {# -b11 z# -b1000 y# -b1000 x# -b10000 w# -b101000 v# -b10 k# -b100000 j# +b0 :$ +b11 9$ +b1000 8$ +b1000 7$ +b100000 6$ +b1000 ,$ +b100000 +$ +b10 *$ +b100 )$ +b1000 ($ +b100000 '$ +b10 |# +b0 {# +b10 z# +b1 y# +b0 x# +b1 w# +b11 v# +b10 u# +b1 t# +b0 s# +b0 r# +b111 q# +b110 p# +b101 o# +b100 n# +b11 m# +b10 l# +b1 k# +b0 j# b10000 i# -b101000 h# -b100000 a# -b10000 `# -b101000 _# -b100000 X# -b10000 W# -b101000 V# -b100000 O# -b10000 N# -b101000 M# -b100000 F# -b10000 E# -b101000 D# -b100000 =# -b10000 <# -b101000 ;# -b100000 4# -b10000 3# -b101000 2# +b1000 h# +b100000 g# +b111 `# +b10000 _# +b1000 ^# +b100000 ]# +b110 V# +b10000 U# +b1000 T# +b100000 S# +b101 L# +b10000 K# +b1000 J# +b100000 I# +b100 B# +b10000 A# +b1000 @# +b100000 ?# +b11 8# +b10000 7# +b1000 6# +b100000 5# +b10 .# +b10000 -# +b1000 ,# b100000 +# -b10000 *# -b101000 )# -b10000 "# -b101000 !# +b1 $# +b10000 ## +b1000 "# +b100000 !# +b0 x" +b11 w" +b1000 v" +b1000 u" +b100000 t" +b1000 j" +b100000 i" +b10 h" +b100 g" b1000 f" -b1000000 e" -b11 d" -b1000 c" -b1000 b" -b10000 a" -b101000 `" -b1 U" -b100000 T" -b10000 S" -b101000 R" -b100000 K" -b10000 J" -b101000 I" -b100000 B" -b10000 A" -b101000 @" -b100000 9" -b10000 8" -b101000 7" -b100000 0" -b10000 /" -b101000 ." -b100000 '" -b10000 &" -b101000 %" -b100000 | -b10000 { -b101000 z +b100000 e" +b1 \" +b0 [" +b10 Z" +b1 Y" +b0 X" +b1 W" +b11 V" +b10 U" +b1 T" +b0 S" +b0 R" +b111 Q" +b110 P" +b101 O" +b100 N" +b11 M" +b10 L" +b1 K" +b0 J" +b10000 I" +b1000 H" +b100000 G" +b111 @" +b10000 ?" +b1000 >" +b100000 =" +b110 6" +b10000 5" +b1000 4" +b100000 3" +b101 ," +b10000 +" +b1000 *" +b100000 )" +b100 "" +b10000 !" +b1000 ~ +b100000 } +b11 v +b10000 u +b1000 t b100000 s -b10000 r -b101000 q -b10000 j -b101000 i -b1000 P -b1000000 O -b11 N -b1000 M -b1000 L -b10000 K -b101000 J -b0 ? -b1000 > -b1000 = -b1000000 < +b10 l +b10000 k +b1000 j +b100000 i +b1 b +b10000 a +b1000 ` +b100000 _ +b0 X +b11 W +b1000 V +b1000 U +b100000 T +b1000 J +b100000 I +b10 H +b100 G +b1000 F +b100000 E +b0 < b1000 ; -b10000 : -b101000 9 -b1000 ) +b1000 : +b100000 9 +b1000 8 +b100000 7 b1000 ( -b1000000 ' -b1000 & -b10000 % -b101000 $ +b1000 ' +b100000 & +b1000 % +b100000 $ $end #0 $dumpvars -bx /+ +bx j+ +bx i+ +bx h+ +bx g+ +bx f+ +b0 e+ +bx `+ +bx _+ +bx ^+ +bx ]+ +bx \+ +b0 [+ +bx V+ +bx U+ +bx T+ +bx S+ +bx R+ +b0 Q+ +bx L+ +bx K+ +bx J+ +bx I+ +bx H+ +b0 G+ +bx B+ +bx A+ +bx @+ +bx ?+ +bx >+ +b0 =+ +bx 8+ +bx 7+ +bx 6+ +bx 5+ +bx 4+ +b0 3+ bx .+ bx -+ bx ,+ bx ++ -b0 *+ -bx &+ -bx %+ +bx *+ +b0 )+ bx $+ bx #+ bx "+ -b0 !+ -bx {* -bx z* -bx y* -bx x* +bx !+ +bx ~* +b0 }* bx w* -b0 v* +bx v* +bx u* +bx t* +bx s* bx r* -bx q* -bx p* +xq* +xp* bx o* -bx n* -b0 m* -bx i* bx h* -bx g* +b0 g* bx f* bx e* -b0 d* -bx `* -bx _* -bx ^* -bx ]* -bx \* -b0 [* -bx W* -bx V* -bx U* -bx T* -bx S* -b0 R* -bx N* -bx M* -bx L* -bx K* +bx d* +b0 c* +b0 b* +b0 a* bx J* -b0 I* +bx I* +bx H* +bx G* bx F* -bx E* -bx D* -bx C* -bx B* -bx A* +b0 E* bx @* bx ?* bx >* bx =* bx <* -bx ;* -bx :* -bx 9* -bx 8* -bx 7* +b0 ;* bx 6* bx 5* bx 4* bx 3* bx 2* -x1* -x0* -bx /* -bx '* -b0 &* -bx %* -bx $* -bx #* +b0 1* +bx ,* +bx +* +bx ** +bx )* +bx (* +b0 '* bx "* -b0 !* -b0 ~) -b0 }) -b0 |) -bx w) +bx !* +bx ~) +bx }) +bx |) +b0 {) bx v) bx u) bx t) bx s) -b0 r) -bx n) -bx m) +bx r) +b0 q) bx l) bx k) bx j) -b0 i) -bx e) -bx d) -bx c) +bx i) +bx h) +b0 g) bx b) bx a) -b0 `) -bx \) -bx [) -bx Z) -bx Y) -bx X) -b0 W) +bx `) +bx _) +bx ^) +b0 ]) +bx W) +bx V) +bx U) +bx T) bx S) bx R) -bx Q) -bx P) +xQ) +xP) bx O) -b0 N) -bx J) -bx I) bx H) -bx G) +b0 G) bx F) -b0 E) -bx A) -bx @) -bx ?) -bx >) -bx =) -b0 <) -bx 8) -bx 7) -bx 6) -bx 5) -bx 4) -b0 3) -bx 0) -bx /) -bx .) -bx -) -bx ,) -bx +) +bx E) +bx D) +b0 C) +b0 B) +b0 A) bx *) bx )) bx () bx ') bx &) -bx %) -bx $) -bx #) -bx ") -bx !) +b0 %) bx ~( bx }( bx |( bx {( bx z( -xy( -xx( -bx w( -bx o( -b0 n( -bx m( -bx l( -bx k( +b0 y( +bx t( +bx s( +bx r( +bx q( +bx p( +b0 o( bx j( -b0 i( -b0 h( -b0 g( -b0 f( -bx a( +bx i( +bx h( +bx g( +bx f( +b0 e( bx `( bx _( bx ^( bx ]( -b0 \( -bx X( -bx W( +bx \( +b0 [( bx V( bx U( bx T( -b0 S( -bx O( -bx N( -bx M( +bx S( +bx R( +b0 Q( bx L( bx K( -b0 J( -bx F( -bx E( -bx D( -bx C( +bx J( +bx I( +bx H( +b0 G( bx B( -b0 A( -bx =( -bx <( -bx ;( -bx :( -bx 9( -b0 8( +bx A( +bx @( +bx ?( +bx >( +b0 =( +bx 7( +bx 6( +bx 5( bx 4( bx 3( bx 2( -bx 1( -bx 0( -b0 /( -bx +( -bx *( -bx )( +x1( +x0( +bx /( bx (( -bx '( -b0 &( -bx "( -bx !( -bx ~' -bx }' -bx |' -b0 {' -bx x' -bx w' -bx v' -bx u' -bx t' -bx s' -bx r' -bx q' -bx p' -bx o' -bx n' -bx m' -bx l' -bx k' -bx j' -bx i' +b0 '( +bx &( +bx %( +bx $( +b0 #( +b0 "( +b0 !( bx h' bx g' bx f' bx e' bx d' -xc' -xb' -bx a' -bx Y' -b0 X' -bx W' -bx V' -bx U' +b0 c' +bx ^' +bx ]' +bx \' +bx [' +bx Z' +b0 Y' bx T' -b0 S' -b0 R' -b0 Q' -b0 P' -bx K' +bx S' +bx R' +bx Q' +bx P' +b0 O' bx J' bx I' bx H' bx G' -b0 F' -bx B' -bx A' +bx F' +b0 E' bx @' bx ?' bx >' -b0 =' -bx 9' -bx 8' -bx 7' +bx =' +bx <' +b0 ;' bx 6' bx 5' -b0 4' -bx 0' -bx /' -bx .' -bx -' +bx 4' +bx 3' +bx 2' +b0 1' bx ,' -b0 +' -bx '' -bx &' -bx %' -bx $' -bx #' -b0 "' +bx +' +bx *' +bx )' +bx (' +b0 '' +bx "' +bx !' +bx ~& +bx }& bx |& -bx {& -bx z& -bx y& -bx x& -b0 w& +b0 {& +bx u& +bx t& bx s& bx r& bx q& bx p& -bx o& -b0 n& -bx j& -bx i& -bx h& -bx g& +xo& +xn& +bx m& bx f& b0 e& +bx d& +bx c& bx b& -bx a& -bx `& -bx _& -bx ^& -bx ]& -bx \& -bx [& -bx Z& -bx Y& -bx X& -bx W& -bx V& -bx U& -bx T& -bx S& -bx R& -bx Q& -bx P& -bx O& -bx N& -xM& -xL& -bx K& -bx C& -b0 B& -bx A& -bx @& -bx ?& +b0 a& +b0 `& +b0 _& +bx H& +bx G& +bx F& +bx E& +bx D& +b0 C& bx >& -b0 =& -b0 <& -b0 ;& -b0 :& -bx 5& +bx =& +bx <& +bx ;& +bx :& +b0 9& bx 4& bx 3& bx 2& bx 1& -b0 0& -bx ,& -bx +& +bx 0& +b0 /& bx *& bx )& bx (& -b0 '& -bx #& -bx "& -bx !& +bx '& +bx && +b0 %& bx ~% bx }% -b0 |% -bx x% -bx w% -bx v% -bx u% +bx |% +bx {% +bx z% +b0 y% bx t% -b0 s% -bx o% -bx n% -bx m% -bx l% -bx k% -b0 j% +bx s% +bx r% +bx q% +bx p% +b0 o% +bx j% +bx i% +bx h% +bx g% bx f% -bx e% -bx d% -bx c% -bx b% -b0 a% +b0 e% +bx `% +bx _% +bx ^% bx ]% bx \% -bx [% -bx Z% -bx Y% -b0 X% +b0 [% +bx U% bx T% bx S% bx R% bx Q% bx P% -b0 O% -bx L% -bx K% -bx J% -bx I% -bx H% -bx G% +xO% +xN% +bx M% bx F% -bx E% +b0 E% bx D% bx C% bx B% -bx A% -bx @% -bx ?% -bx >% -bx =% -bx <% -bx ;% -bx :% -bx 9% -bx 8% -x7% -x6% -bx 5% -bx -% -b0 ,% -bx +% -bx *% -bx )% +b0 A% +b0 @% +b0 ?% bx (% -b0 '% -b0 &% -b0 %% -b0 $% -bx }$ +bx '% +bx &% +bx %% +bx $% +b0 #% bx |$ bx {$ bx z$ bx y$ -b0 x$ -bx t$ -bx s$ +bx x$ +b0 w$ bx r$ bx q$ bx p$ -b0 o$ -bx k$ -bx j$ -bx i$ +bx o$ +bx n$ +b0 m$ bx h$ bx g$ -b0 f$ -bx b$ -bx a$ -bx `$ -bx _$ +bx f$ +bx e$ +bx d$ +b0 c$ bx ^$ -b0 ]$ -bx Y$ -bx X$ -bx W$ -bx V$ -bx U$ -b0 T$ +bx ]$ +bx \$ +bx [$ +bx Z$ +b0 Y$ +bx T$ +bx S$ +bx R$ +bx Q$ bx P$ -bx O$ -bx N$ -bx M$ -bx L$ -b0 K$ +b0 O$ +bx J$ +bx I$ +bx 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-b111 T -b10000000000000000000000 G -b10000000000000000000000 I -b10000000000000000000000 h -b1110000000000000000000 Q -b1110000000000000000000 V -1+ -#100 -0+ -#105 +b0 u* +b10 N +b11000 B +b11000 D +b11000 S +b10000 K +b10000 P +b10 n" +b1001000 b" +b1001000 d" +b1001000 s" +b110000 k" +b110000 p" +b10 0$ +b11111111111111111111111111101000 $$ +b11111111111111111111111111101000 &$ +b11111111111111111111111111101000 5$ +b11111111111111111111111111110000 -$ +b11111111111111111111111111110000 2$ +b10 P% +b11000000 D% +b11000000 F% +b11000000 U% +b10000000 M% +b10000000 R% +b10 p& +b10 2( +b10 R) +b1110 F) +b11000 H) +b11000 W) +b10000 O) +b10000 T) +b10 r* +b10101 f* +b10000 h* +b10000 w* +b10000 o* +b10000 t* +1* +#50000 +0* +#55000 +b11 r* +b11 R) +b10110 F) +b100000 H) +b100000 W) +b11000 O) +b11000 T) +b11 2( +b11 p& +b11 P% +b100000000 D% +b100000000 F% +b100000000 U% +b11000000 M% +b11000000 R% +b11 0$ +b11111111111111111111111111100000 $$ +b11111111111111111111111111100000 &$ +b11111111111111111111111111100000 5$ +b11111111111111111111111111101000 -$ +b11111111111111111111111111101000 2$ +b11 n" +b1100000 b" +b1100000 d" +b1100000 s" +b1001000 k" +b1001000 p" +b11 N +b100000 B +b100000 D +b100000 S +b11000 K +b11000 P +1* +#60000 +0* +#65000 1" -b11111111 7 +b11111111 5 0# -b0 8 -b10001000000000011111100000000000000000000000000000001000000000111111111111111000000000000000000100000000000000100000000000000 ! -b10001000000000011111100000000000000000000000000000001000000000111111111111111000000000000000000100000000000000100000000000000 6 -b100100000000000 F -b10010000000000 \" -b1111111111111111111111111101110000000000 r# -b1001000000000000 *% -b1000000000 @& -b1111111111111111111111111111111000000000 V' -b100011000000000 l( -b1010000000000 $* -1S -0R -b100000000000000 U -b10010000000000000000000 G -b10010000000000000000000 I -b10010000000000000000000 h -b10000000000000000000000 Q -b10000000000000000000000 V -1i" -0h" -b10000000000000 k" -b1001000000000000000000 ]" -b1001000000000000000000 _" -b1001000000000000000000 ~" -b1000000000000000000000 g" -b1000000000000000000000 l" -1!$ -0~# -b1111111111111111110111000000000000000000 s# -b1111111111111111110111000000000000000000 u# -b1111111111111111110111000000000000000000 6$ -b1111111111111111111000000000000000000000 }# -b1111111111111111111000000000000000000000 $$ -17% -06% -b111111111111111 9% -b100100000000000000000000 +% -b100100000000000000000000 -% -b100100000000000000000000 L% -b100000000000000000000000 5% -b100000000000000000000000 :% -1M& -0L& -b100000000 O& -b100000000000000000 A& -b10000000000000000 C& -b10000000000000000 b& -b10000000000000000 K& -b10000000000000000 P& -1c' -0b' -b1111111111111111111111100000000000000000 W' -b1111111111111111111111110000000000000000 Y' -b1111111111111111111111110000000000000000 x' -b1111111111111111111111110000000000000000 a' -b1111111111111111111111110000000000000000 f' -1y( -0x( -b11111100000000 {( -b10001100000000000000000 m( -b10001110000000000000000 o( -b10001110000000000000000 0) -b1111110000000000000000 w( -b1111110000000000000000 |( -11* -00* -b1000100000000 3* -b101000000000000000000 %* -b100110000000000000000 '* -b100110000000000000000 F* -b100010000000000000000 /* -b100010000000000000000 4* -1+ -#110 -0+ -#115 +b0 6 +b1010100010110000000000000010101111111000000000110000000100000 ! +b1010100010110000000000000010101111111000000000110000000100000 4 +1M +0L +b100000 O +b101000 B +b101000 D +b101000 S +b100000 K +b100000 P +1m" +0l" +b1100000 o" +b1111000 b" +b1111000 d" +b1111000 s" +b1100000 k" +b1100000 p" +1/$ +0.$ +b11111111111111111111111111011000 $$ +b11111111111111111111111111011000 &$ +b11111111111111111111111111011000 5$ +b11111111111111111111111111100000 -$ +b11111111111111111111111111100000 2$ +1O% +0N% +b1111111 Q% +b101000000 D% +b101000000 F% +b101000000 U% +b100000000 M% +b100000000 R% +1o& +0n& +b101 q& +b1010 d& +b101 f& +b101 u& +b101 m& +b101 r& +11( +00( +b11111111111111111111111111110110 &( +b11111111111111111111111111111011 (( +b11111111111111111111111111111011 7( +b11111111111111111111111111111011 /( +b11111111111111111111111111111011 4( +1Q) +0P) +b10110 S) +b10100 F) +b11110 H) +b11110 W) +b10110 O) +b10110 T) +1q* +0p* +b10101 s* +b11010 f* +b10101 h* +b10101 w* +b10101 o* +b10101 t* +1* +#70000 +0* +#75000 0" -b0 7 -01* -0y( -0c' -0M& -07% -0!$ -0i" -0S -1+ +b0 5 +0q* +0Q) +01( +0o& +0O% +0/$ +0m" +0M +1* diff --git a/sim/layer_sim b/sim/layer_sim index 48f040f..9575877 100755 --- a/sim/layer_sim +++ b/sim/layer_sim @@ -1,3916 +1,6745 @@ #! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp :ivl_version "13.0 (stable)" "(v13_0)"; :ivl_delay_selection "TYPICAL"; -:vpi_time_precision + 0; +:vpi_time_precision - 12; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi"; -S_0x102e61f00 .scope package, "$unit" "$unit" 2 1; +S_0x102e30650 .scope package, "$unit" "$unit" 2 1; .timescale 0 0; -S_0x102e63dc0 .scope module, "tb" "tb" 3 1; +S_0x102e26840 .scope module, "memory_interface" "memory_interface" 3 1; .timescale 0 0; -P_0x102e63ae0 .param/l "ACC_WIDTH" 0 3 8, +C4<00000000000000000000000000101000>; -P_0x102e63b20 .param/l "DATA_WIDTH" 0 3 3, +C4<00000000000000000000000000010000>; -P_0x102e63b60 .param/l "FRAC_BITS" 0 3 4, +C4<00000000000000000000000000001000>; -P_0x102e63ba0 .param/l "N_INPUTS" 0 3 5, +C4<00000000000000000000000001000000>; -P_0x102e63be0 .param/l "N_NEURONS" 0 3 6, +C4<00000000000000000000000000001000>; -P_0x102e63c20 .param/l "PARALLEL" 0 3 7, +C4<00000000000000000000000000001000>; -v0x8d2d17700_0 .var/s "bias_bus", 127 0; -v0x8d2d177a0_0 .net "busy", 0 0, L_0x8d323ce60; 1 drivers -v0x8d2d17840_0 .var "clk", 0 0; -v0x8d2d178e0_0 .net "done", 0 0, L_0x8d323cf00; 1 drivers -v0x8d2d17980_0 .var/i "errors", 31 0; -v0x8d2d17a20_0 .var/i "i", 31 0; -v0x8d2d17ac0_0 .var "rst", 0 0; -v0x8d2d17b60_0 .var "start", 0 0; -v0x8d2d17c00_0 .var/s "weights_bus", 8191 0; -v0x8d2d17ca0_0 .var/s "x_bus", 1023 0; -v0x8d2d17d40_0 .net/s "y_bus", 127 0, L_0x8d3239040; 1 drivers -S_0x102e5b4b0 .scope module, "dut" "layer" 3 39, 4 1 0, S_0x102e63dc0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 16 "wdata"; + .port_info 6 /INPUT 1 "lb_n"; + .port_info 7 /INPUT 1 "ub_n"; + .port_info 8 /OUTPUT 16 "rdata"; + .port_info 9 /OUTPUT 1 "ready"; + .port_info 10 /OUTPUT 1 "mem_req"; + .port_info 11 /OUTPUT 1 "mem_wr"; + .port_info 12 /OUTPUT 22 "mem_addr"; + .port_info 13 /OUTPUT 16 "mem_wdata"; + .port_info 14 /OUTPUT 1 "mem_lb_n"; + .port_info 15 /OUTPUT 1 "mem_ub_n"; + .port_info 16 /INPUT 16 "mem_rdata"; + .port_info 17 /INPUT 1 "mem_ready"; +P_0x84acc8000 .param/l "ADDR_WIDTH" 0 3 2, +C4<00000000000000000000000000010110>; +P_0x84acc8040 .param/l "DATA_WIDTH" 0 3 3, +C4<00000000000000000000000000010000>; +P_0x84acc8080 .param/l "STATE_IDLE" 1 3 28, C4<00>; +P_0x84acc80c0 .param/l "STATE_WAIT" 1 3 29, C4<01>; +o0x84a844010 .functor BUFZ 22, c4; HiZ drive +v0x84b0c4c80_0 .net "addr", 21 0, o0x84a844010; 0 drivers +o0x84a844040 .functor BUFZ 1, c4; HiZ drive +v0x84b0c4d20_0 .net "clk", 0 0, o0x84a844040; 0 drivers +o0x84a844070 .functor BUFZ 1, c4; HiZ drive +v0x84b0c4dc0_0 .net "lb_n", 0 0, o0x84a844070; 0 drivers +v0x84b0c4e60_0 .var "mem_addr", 21 0; +v0x84b0c4f00_0 .var "mem_lb_n", 0 0; +o0x84a844100 .functor BUFZ 16, c4; HiZ drive +v0x84b0c4fa0_0 .net "mem_rdata", 15 0, o0x84a844100; 0 drivers +o0x84a844130 .functor BUFZ 1, c4; HiZ drive +v0x84b0c5040_0 .net "mem_ready", 0 0, o0x84a844130; 0 drivers +v0x84b0c50e0_0 .var "mem_req", 0 0; +v0x84b0c5180_0 .var "mem_ub_n", 0 0; +v0x84b0c5220_0 .var "mem_wdata", 15 0; +v0x84b0c52c0_0 .var "mem_wr", 0 0; +v0x84b0c5360_0 .var "rdata", 15 0; +v0x84b0c5400_0 .var "ready", 0 0; +o0x84a844280 .functor BUFZ 1, c4; HiZ drive +v0x84b0c54a0_0 .net "req", 0 0, o0x84a844280; 0 drivers +o0x84a8442b0 .functor BUFZ 1, c4; HiZ drive +v0x84b0c5540_0 .net "rst", 0 0, o0x84a8442b0; 0 drivers +v0x84b0c55e0_0 .var "state", 1 0; +o0x84a844310 .functor BUFZ 1, c4; HiZ drive +v0x84b0c5680_0 .net "ub_n", 0 0, o0x84a844310; 0 drivers +o0x84a844340 .functor BUFZ 16, c4; HiZ drive +v0x84b0c5720_0 .net "wdata", 15 0, o0x84a844340; 0 drivers +o0x84a844370 .functor BUFZ 1, c4; HiZ drive +v0x84b0c57c0_0 .net "wr", 0 0, o0x84a844370; 0 drivers +E_0x84ae46340 .event posedge, v0x84b0c4d20_0; +S_0x102e314f0 .scope module, "memory_model" "memory_model" 4 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 16 "wdata"; + .port_info 6 /OUTPUT 16 "rdata"; + .port_info 7 /OUTPUT 1 "ready"; +P_0x84acc8100 .param/l "ADDR_WIDTH" 0 4 2, +C4<00000000000000000000000000010110>; +P_0x84acc8140 .param/l "DATA_WIDTH" 0 4 3, +C4<00000000000000000000000000010000>; +P_0x84acc8180 .param/l "DEPTH" 0 4 4, +C4<00000000000000000001000000000000>; +P_0x84acc81c0 .param/l "READ_LATENCY" 0 4 5, +C4<00000000000000000000000000000010>; +o0x84a844700 .functor BUFZ 22, c4; HiZ drive +v0x84b0c5860_0 .net "addr", 21 0, o0x84a844700; 0 drivers +v0x84b0c5900_0 .var "busy", 0 0; +o0x84a844760 .functor BUFZ 1, c4; HiZ drive +v0x84b0c59a0_0 .net "clk", 0 0, o0x84a844760; 0 drivers +v0x84b0c5a40_0 .var/i "delay_count", 31 0; +v0x84b0c5ae0_0 .var/i "i", 31 0; +v0x84b0c5b80 .array "mem", 4095 0, 15 0; +v0x84b0c5c20_0 .var "pending_addr", 21 0; +v0x84b0c5cc0_0 .var "pending_wdata", 15 0; +v0x84b0c5d60_0 .var "pending_wr", 0 0; +v0x84b0c5e00_0 .var "rdata", 15 0; +v0x84b0c5ea0_0 .var "ready", 0 0; +o0x84a8448e0 .functor BUFZ 1, c4; HiZ drive +v0x84b0c5f40_0 .net "req", 0 0, o0x84a8448e0; 0 drivers +o0x84a844910 .functor BUFZ 1, c4; HiZ drive +v0x84b0c5fe0_0 .net "rst", 0 0, o0x84a844910; 0 drivers +o0x84a844940 .functor BUFZ 16, c4; HiZ drive +v0x84b0c6080_0 .net "wdata", 15 0, o0x84a844940; 0 drivers +o0x84a844970 .functor BUFZ 1, c4; HiZ drive +v0x84b0c6120_0 .net "wr", 0 0, o0x84a844970; 0 drivers +E_0x84ae46380 .event posedge, v0x84b0c59a0_0; +S_0x102e269c0 .scope module, "neuron_memory" "neuron_memory" 5 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /OUTPUT 1 "mem_req"; + .port_info 4 /OUTPUT 1 "mem_wr"; + .port_info 5 /OUTPUT 22 "mem_addr"; + .port_info 6 /OUTPUT 8 "mem_wdata"; + .port_info 7 /INPUT 8 "mem_rdata"; + .port_info 8 /INPUT 1 "mem_ready"; + .port_info 9 /INPUT 22 "x_base"; + .port_info 10 /INPUT 22 "w_base"; + .port_info 11 /INPUT 22 "bias_addr"; + .port_info 12 /OUTPUT 8 "y"; + .port_info 13 /OUTPUT 1 "busy"; + .port_info 14 /OUTPUT 1 "done"; +P_0x102e2fd50 .param/l "ACC_WIDTH" 0 5 8, +C4<00000000000000000000000000100000>; +P_0x102e2fd90 .param/l "ADDR_WIDTH" 0 5 4, +C4<00000000000000000000000000010110>; +P_0x102e2fdd0 .param/l "DATA_WIDTH" 0 5 5, +C4<00000000000000000000000000001000>; +P_0x102e2fe10 .param/l "N_INPUTS" 0 5 6, +C4<00000000000000000000000000100000>; +P_0x102e2fe50 .param/l "PARALLEL" 0 5 7, +C4<00000000000000000000000000001000>; +P_0x102e2fe90 .param/l "STATE_IDLE" 1 5 49, C4<0000>; +P_0x102e2fed0 .param/l "STATE_READ_BIAS" 1 5 52, C4<0011>; +P_0x102e2ff10 .param/l "STATE_READ_W" 1 5 51, C4<0010>; +P_0x102e2ff50 .param/l "STATE_READ_X" 1 5 50, C4<0001>; +P_0x102e2ff90 .param/l "STATE_START_N" 1 5 53, C4<0100>; +P_0x102e2ffd0 .param/l "STATE_WAIT_N" 1 5 54, C4<0101>; +L_0x84ac3ee60 .functor BUFZ 1, v0x84b154e60_0, C4<0>, C4<0>, C4<0>; +L_0x84ac3eed0 .functor BUFZ 1, v0x84b155040_0, C4<0>, C4<0>, C4<0>; +L_0x84ac3ef40 .functor BUFZ 22, v0x84b15e120_0, C4<0000000000000000000000>, C4<0000000000000000000000>, C4<0000000000000000000000>; +L_0x84ac3efb0 .functor BUFZ 8, v0x84b15e800_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x84b15de00_0 .net *"_ivl_131", 0 0, L_0x84ae38c80; 1 drivers +L_0x84a878010 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x84b15dea0_0 .net/2u *"_ivl_132", 7 0, L_0x84a878010; 1 drivers +v0x84b15df40_0 .net *"_ivl_134", 15 0, L_0x84b192080; 1 drivers +L_0x84a878058 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x84b15dfe0_0 .net/2u *"_ivl_136", 7 0, L_0x84a878058; 1 drivers +v0x84b15e080_0 .net *"_ivl_138", 15 0, L_0x84b192120; 1 drivers +v0x84b15e120_0 .var "access_addr", 21 0; +v0x84b15e1c0_0 .net "access_mem_addr", 21 0, v0x84b154be0_0; 1 drivers +v0x84b15e260_0 .net "access_mem_lb_n", 0 0, v0x84b154c80_0; 1 drivers +v0x84b15e300_0 .net "access_mem_rdata", 15 0, L_0x84b12a3a0; 1 drivers +v0x84b15e3a0_0 .net "access_mem_req", 0 0, v0x84b154e60_0; 1 drivers +v0x84b15e440_0 .net "access_mem_ub_n", 0 0, v0x84b154f00_0; 1 drivers +v0x84b15e4e0_0 .net "access_mem_wdata", 15 0, v0x84b154fa0_0; 1 drivers +v0x84b15e580_0 .net "access_mem_wr", 0 0, v0x84b155040_0; 1 drivers +v0x84b15e620_0 .net/s "access_rdata", 7 0, v0x84b1550e0_0; 1 drivers +v0x84b15e6c0_0 .net "access_ready", 0 0, v0x84b155180_0; 1 drivers +v0x84b15e760_0 .var "access_req", 0 0; +v0x84b15e800_0 .var/s "access_wdata", 7 0; +v0x84b15e8a0_0 .var "access_wr", 0 0; +o0x84a848120 .functor BUFZ 22, c4; HiZ drive +v0x84b15e940_0 .net "bias_addr", 21 0, o0x84a848120; 0 drivers +v0x84b15e9e0_0 .var/s "bias_reg", 7 0; +v0x84b15ea80_0 .var "busy", 0 0; +o0x84a845780 .functor BUFZ 1, c4; HiZ drive +v0x84b15eb20_0 .net "clk", 0 0, o0x84a845780; 0 drivers +v0x84b15ebc0_0 .var "done", 0 0; +v0x84b15ec60_0 .var "index", 5 0; +v0x84b15ed00_0 .net "mem_addr", 21 0, L_0x84ac3ef40; 1 drivers +o0x84a848210 .functor BUFZ 8, c4; HiZ drive +v0x84b15eda0_0 .net/s "mem_rdata", 7 0, o0x84a848210; 0 drivers +o0x84a845840 .functor BUFZ 1, c4; HiZ drive +v0x84b15ee40_0 .net "mem_ready", 0 0, o0x84a845840; 0 drivers +v0x84b15eee0_0 .net "mem_req", 0 0, L_0x84ac3ee60; 1 drivers +v0x84b15ef80_0 .net/s "mem_wdata", 7 0, L_0x84ac3efb0; 1 drivers +v0x84b15f020_0 .net "mem_wr", 0 0, L_0x84ac3eed0; 1 drivers +v0x84b15f0c0_0 .net "neuron_busy", 0 0, v0x84b15d680_0; 1 drivers +v0x84b15f160_0 .net "neuron_done", 0 0, v0x84b15d7c0_0; 1 drivers +v0x84b15f200_0 .var "neuron_start", 0 0; +v0x84b15f2a0_0 .net/s "neuron_y", 7 0, v0x84b15dd60_0; 1 drivers +o0x84a8459c0 .functor BUFZ 1, c4; HiZ drive +v0x84b15f340_0 .net "rst", 0 0, o0x84a8459c0; 0 drivers +o0x84a8482d0 .functor BUFZ 1, c4; HiZ drive +v0x84b15f3e0_0 .net "start", 0 0, o0x84a8482d0; 0 drivers +v0x84b15f480_0 .var "state", 3 0; +o0x84a848330 .functor BUFZ 22, c4; HiZ drive +v0x84b15f520_0 .net "w_base", 21 0, o0x84a848330; 0 drivers +v0x84b15f5c0_0 .net/s "w_bus", 255 0, L_0x84b191fe0; 1 drivers +v0x84b15f660 .array/s "w_mem", 31 0, 7 0; +o0x84a848960 .functor BUFZ 22, c4; HiZ drive +v0x84b15f700_0 .net "x_base", 21 0, o0x84a848960; 0 drivers +v0x84b15f7a0_0 .net/s "x_bus", 255 0, L_0x84b191f40; 1 drivers +v0x84b15f840 .array/s "x_mem", 31 0, 7 0; +v0x84b15f8e0_0 .var/s "y", 7 0; +v0x84b15f840_0 .array/port v0x84b15f840, 0; +v0x84b15f840_1 .array/port v0x84b15f840, 1; +v0x84b15f840_2 .array/port v0x84b15f840, 2; +v0x84b15f840_3 .array/port v0x84b15f840, 3; +LS_0x84b191f40_0_0 .concat8 [ 8 8 8 8], v0x84b15f840_0, v0x84b15f840_1, v0x84b15f840_2, v0x84b15f840_3; +v0x84b15f840_4 .array/port v0x84b15f840, 4; +v0x84b15f840_5 .array/port v0x84b15f840, 5; +v0x84b15f840_6 .array/port v0x84b15f840, 6; +v0x84b15f840_7 .array/port v0x84b15f840, 7; +LS_0x84b191f40_0_4 .concat8 [ 8 8 8 8], v0x84b15f840_4, v0x84b15f840_5, v0x84b15f840_6, v0x84b15f840_7; +v0x84b15f840_8 .array/port v0x84b15f840, 8; +v0x84b15f840_9 .array/port v0x84b15f840, 9; +v0x84b15f840_10 .array/port v0x84b15f840, 10; +v0x84b15f840_11 .array/port v0x84b15f840, 11; +LS_0x84b191f40_0_8 .concat8 [ 8 8 8 8], v0x84b15f840_8, v0x84b15f840_9, v0x84b15f840_10, v0x84b15f840_11; +v0x84b15f840_12 .array/port v0x84b15f840, 12; +v0x84b15f840_13 .array/port v0x84b15f840, 13; +v0x84b15f840_14 .array/port v0x84b15f840, 14; +v0x84b15f840_15 .array/port v0x84b15f840, 15; +LS_0x84b191f40_0_12 .concat8 [ 8 8 8 8], v0x84b15f840_12, v0x84b15f840_13, v0x84b15f840_14, v0x84b15f840_15; +v0x84b15f840_16 .array/port v0x84b15f840, 16; +v0x84b15f840_17 .array/port v0x84b15f840, 17; +v0x84b15f840_18 .array/port v0x84b15f840, 18; +v0x84b15f840_19 .array/port v0x84b15f840, 19; +LS_0x84b191f40_0_16 .concat8 [ 8 8 8 8], v0x84b15f840_16, v0x84b15f840_17, v0x84b15f840_18, v0x84b15f840_19; +v0x84b15f840_20 .array/port v0x84b15f840, 20; +v0x84b15f840_21 .array/port v0x84b15f840, 21; +v0x84b15f840_22 .array/port v0x84b15f840, 22; +v0x84b15f840_23 .array/port v0x84b15f840, 23; +LS_0x84b191f40_0_20 .concat8 [ 8 8 8 8], v0x84b15f840_20, v0x84b15f840_21, v0x84b15f840_22, v0x84b15f840_23; +v0x84b15f840_24 .array/port v0x84b15f840, 24; +v0x84b15f840_25 .array/port v0x84b15f840, 25; +v0x84b15f840_26 .array/port v0x84b15f840, 26; +v0x84b15f840_27 .array/port v0x84b15f840, 27; +LS_0x84b191f40_0_24 .concat8 [ 8 8 8 8], v0x84b15f840_24, v0x84b15f840_25, v0x84b15f840_26, v0x84b15f840_27; +v0x84b15f840_28 .array/port v0x84b15f840, 28; +v0x84b15f840_29 .array/port v0x84b15f840, 29; +v0x84b15f840_30 .array/port v0x84b15f840, 30; +v0x84b15f840_31 .array/port v0x84b15f840, 31; +LS_0x84b191f40_0_28 .concat8 [ 8 8 8 8], v0x84b15f840_28, v0x84b15f840_29, v0x84b15f840_30, v0x84b15f840_31; +LS_0x84b191f40_1_0 .concat8 [ 32 32 32 32], LS_0x84b191f40_0_0, LS_0x84b191f40_0_4, LS_0x84b191f40_0_8, LS_0x84b191f40_0_12; +LS_0x84b191f40_1_4 .concat8 [ 32 32 32 32], LS_0x84b191f40_0_16, LS_0x84b191f40_0_20, LS_0x84b191f40_0_24, LS_0x84b191f40_0_28; +L_0x84b191f40 .concat8 [ 128 128 0 0], LS_0x84b191f40_1_0, LS_0x84b191f40_1_4; +v0x84b15f660_0 .array/port v0x84b15f660, 0; +v0x84b15f660_1 .array/port v0x84b15f660, 1; +v0x84b15f660_2 .array/port v0x84b15f660, 2; +v0x84b15f660_3 .array/port v0x84b15f660, 3; +LS_0x84b191fe0_0_0 .concat8 [ 8 8 8 8], v0x84b15f660_0, v0x84b15f660_1, v0x84b15f660_2, v0x84b15f660_3; +v0x84b15f660_4 .array/port v0x84b15f660, 4; +v0x84b15f660_5 .array/port v0x84b15f660, 5; +v0x84b15f660_6 .array/port v0x84b15f660, 6; +v0x84b15f660_7 .array/port v0x84b15f660, 7; +LS_0x84b191fe0_0_4 .concat8 [ 8 8 8 8], v0x84b15f660_4, v0x84b15f660_5, v0x84b15f660_6, v0x84b15f660_7; +v0x84b15f660_8 .array/port v0x84b15f660, 8; +v0x84b15f660_9 .array/port v0x84b15f660, 9; +v0x84b15f660_10 .array/port v0x84b15f660, 10; +v0x84b15f660_11 .array/port v0x84b15f660, 11; +LS_0x84b191fe0_0_8 .concat8 [ 8 8 8 8], v0x84b15f660_8, v0x84b15f660_9, v0x84b15f660_10, v0x84b15f660_11; +v0x84b15f660_12 .array/port v0x84b15f660, 12; +v0x84b15f660_13 .array/port v0x84b15f660, 13; +v0x84b15f660_14 .array/port v0x84b15f660, 14; +v0x84b15f660_15 .array/port v0x84b15f660, 15; +LS_0x84b191fe0_0_12 .concat8 [ 8 8 8 8], v0x84b15f660_12, v0x84b15f660_13, v0x84b15f660_14, v0x84b15f660_15; +v0x84b15f660_16 .array/port v0x84b15f660, 16; +v0x84b15f660_17 .array/port v0x84b15f660, 17; +v0x84b15f660_18 .array/port v0x84b15f660, 18; +v0x84b15f660_19 .array/port v0x84b15f660, 19; +LS_0x84b191fe0_0_16 .concat8 [ 8 8 8 8], v0x84b15f660_16, v0x84b15f660_17, v0x84b15f660_18, v0x84b15f660_19; +v0x84b15f660_20 .array/port v0x84b15f660, 20; +v0x84b15f660_21 .array/port v0x84b15f660, 21; +v0x84b15f660_22 .array/port v0x84b15f660, 22; +v0x84b15f660_23 .array/port v0x84b15f660, 23; +LS_0x84b191fe0_0_20 .concat8 [ 8 8 8 8], v0x84b15f660_20, v0x84b15f660_21, v0x84b15f660_22, v0x84b15f660_23; +v0x84b15f660_24 .array/port v0x84b15f660, 24; +v0x84b15f660_25 .array/port v0x84b15f660, 25; +v0x84b15f660_26 .array/port v0x84b15f660, 26; +v0x84b15f660_27 .array/port v0x84b15f660, 27; +LS_0x84b191fe0_0_24 .concat8 [ 8 8 8 8], v0x84b15f660_24, v0x84b15f660_25, v0x84b15f660_26, v0x84b15f660_27; +v0x84b15f660_28 .array/port v0x84b15f660, 28; +v0x84b15f660_29 .array/port v0x84b15f660, 29; +v0x84b15f660_30 .array/port v0x84b15f660, 30; +v0x84b15f660_31 .array/port v0x84b15f660, 31; +LS_0x84b191fe0_0_28 .concat8 [ 8 8 8 8], v0x84b15f660_28, v0x84b15f660_29, v0x84b15f660_30, v0x84b15f660_31; +LS_0x84b191fe0_1_0 .concat8 [ 32 32 32 32], LS_0x84b191fe0_0_0, LS_0x84b191fe0_0_4, LS_0x84b191fe0_0_8, LS_0x84b191fe0_0_12; +LS_0x84b191fe0_1_4 .concat8 [ 32 32 32 32], LS_0x84b191fe0_0_16, LS_0x84b191fe0_0_20, LS_0x84b191fe0_0_24, LS_0x84b191fe0_0_28; +L_0x84b191fe0 .concat8 [ 128 128 0 0], LS_0x84b191fe0_1_0, LS_0x84b191fe0_1_4; +L_0x84ae38c80 .part v0x84b15e120_0, 0, 1; +L_0x84b192080 .concat [ 8 8 0 0], L_0x84a878010, o0x84a848210; +L_0x84b192120 .concat [ 8 8 0 0], o0x84a848210, L_0x84a878058; +L_0x84b12a3a0 .functor MUXZ 16, L_0x84b192120, L_0x84b192080, L_0x84ae38c80, C4<>; +S_0x102e246e0 .scope generate, "GEN_BUS[0]" "GEN_BUS[0]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150340 .param/l "i" 1 5 79, +C4<00>; +v0x84b0c61c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_0; 1 drivers +v0x84b0c6260_0 .net *"_ivl_5", 7 0, v0x84b15f660_0; 1 drivers +S_0x102e24860 .scope generate, "GEN_BUS[1]" "GEN_BUS[1]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150380 .param/l "i" 1 5 79, +C4<01>; +v0x84b0c6300_0 .net *"_ivl_2", 7 0, v0x84b15f840_1; 1 drivers +v0x84b0c63a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_1; 1 drivers +S_0x102e23bb0 .scope generate, "GEN_BUS[2]" "GEN_BUS[2]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1503c0 .param/l "i" 1 5 79, +C4<010>; +v0x84b0c6440_0 .net *"_ivl_2", 7 0, v0x84b15f840_2; 1 drivers +v0x84b0c64e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_2; 1 drivers +S_0x102e23d30 .scope generate, "GEN_BUS[3]" "GEN_BUS[3]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150400 .param/l "i" 1 5 79, +C4<011>; +v0x84b0c6580_0 .net *"_ivl_2", 7 0, v0x84b15f840_3; 1 drivers +v0x84b0c6620_0 .net *"_ivl_5", 7 0, v0x84b15f660_3; 1 drivers +S_0x102e213b0 .scope generate, "GEN_BUS[4]" "GEN_BUS[4]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150440 .param/l "i" 1 5 79, +C4<0100>; +v0x84b0c66c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_4; 1 drivers +v0x84b0c6760_0 .net *"_ivl_5", 7 0, v0x84b15f660_4; 1 drivers +S_0x102e21530 .scope generate, "GEN_BUS[5]" "GEN_BUS[5]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150480 .param/l "i" 1 5 79, +C4<0101>; +v0x84b0c6800_0 .net *"_ivl_2", 7 0, v0x84b15f840_5; 1 drivers +v0x84b0c68a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_5; 1 drivers +S_0x102e22170 .scope generate, "GEN_BUS[6]" "GEN_BUS[6]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1504c0 .param/l "i" 1 5 79, +C4<0110>; +v0x84b0c6940_0 .net *"_ivl_2", 7 0, v0x84b15f840_6; 1 drivers +v0x84b0c69e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_6; 1 drivers +S_0x102e222f0 .scope generate, "GEN_BUS[7]" "GEN_BUS[7]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150500 .param/l "i" 1 5 79, +C4<0111>; +v0x84b0c6a80_0 .net *"_ivl_2", 7 0, v0x84b15f840_7; 1 drivers +v0x84b0c6b20_0 .net *"_ivl_5", 7 0, v0x84b15f660_7; 1 drivers +S_0x102e1f770 .scope generate, "GEN_BUS[8]" "GEN_BUS[8]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150540 .param/l "i" 1 5 79, +C4<01000>; +v0x84b0c6bc0_0 .net *"_ivl_2", 7 0, v0x84b15f840_8; 1 drivers +v0x84b0c6c60_0 .net *"_ivl_5", 7 0, v0x84b15f660_8; 1 drivers +S_0x102e1f8f0 .scope generate, "GEN_BUS[9]" "GEN_BUS[9]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150580 .param/l "i" 1 5 79, +C4<01001>; +v0x84b0c6d00_0 .net *"_ivl_2", 7 0, v0x84b15f840_9; 1 drivers +v0x84b0c6da0_0 .net *"_ivl_5", 7 0, v0x84b15f660_9; 1 drivers +S_0x84ae7c000 .scope generate, "GEN_BUS[10]" "GEN_BUS[10]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1505c0 .param/l "i" 1 5 79, +C4<01010>; +v0x84b0c6e40_0 .net *"_ivl_2", 7 0, v0x84b15f840_10; 1 drivers +v0x84b0c6ee0_0 .net *"_ivl_5", 7 0, v0x84b15f660_10; 1 drivers +S_0x84ae7c180 .scope generate, "GEN_BUS[11]" "GEN_BUS[11]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150600 .param/l "i" 1 5 79, +C4<01011>; +v0x84b0c6f80_0 .net *"_ivl_2", 7 0, v0x84b15f840_11; 1 drivers +v0x84b0c7020_0 .net *"_ivl_5", 7 0, v0x84b15f660_11; 1 drivers +S_0x84ae7c300 .scope generate, "GEN_BUS[12]" "GEN_BUS[12]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150640 .param/l "i" 1 5 79, +C4<01100>; +v0x84b0c70c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_12; 1 drivers +v0x84b0c7160_0 .net *"_ivl_5", 7 0, v0x84b15f660_12; 1 drivers +S_0x84ae7c480 .scope generate, "GEN_BUS[13]" "GEN_BUS[13]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150680 .param/l "i" 1 5 79, +C4<01101>; +v0x84b0c7200_0 .net *"_ivl_2", 7 0, v0x84b15f840_13; 1 drivers +v0x84b0c72a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_13; 1 drivers +S_0x84ae7c600 .scope generate, "GEN_BUS[14]" "GEN_BUS[14]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1506c0 .param/l "i" 1 5 79, +C4<01110>; +v0x84b0c7340_0 .net *"_ivl_2", 7 0, v0x84b15f840_14; 1 drivers +v0x84b0c73e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_14; 1 drivers +S_0x84ae7c780 .scope generate, "GEN_BUS[15]" "GEN_BUS[15]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150700 .param/l "i" 1 5 79, +C4<01111>; +v0x84b0c7480_0 .net *"_ivl_2", 7 0, v0x84b15f840_15; 1 drivers +v0x84b0c7520_0 .net *"_ivl_5", 7 0, v0x84b15f660_15; 1 drivers +S_0x84ae7c900 .scope generate, "GEN_BUS[16]" "GEN_BUS[16]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150740 .param/l "i" 1 5 79, +C4<010000>; +v0x84b0c75c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_16; 1 drivers +v0x84b0c7660_0 .net *"_ivl_5", 7 0, v0x84b15f660_16; 1 drivers +S_0x84ae7ca80 .scope generate, "GEN_BUS[17]" "GEN_BUS[17]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150780 .param/l "i" 1 5 79, +C4<010001>; +v0x84b0c7700_0 .net *"_ivl_2", 7 0, v0x84b15f840_17; 1 drivers +v0x84b0c77a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_17; 1 drivers +S_0x84ae7cc00 .scope generate, "GEN_BUS[18]" "GEN_BUS[18]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1507c0 .param/l "i" 1 5 79, +C4<010010>; +v0x84b0c7840_0 .net *"_ivl_2", 7 0, v0x84b15f840_18; 1 drivers +v0x84b0c78e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_18; 1 drivers +S_0x84ae7cd80 .scope generate, "GEN_BUS[19]" "GEN_BUS[19]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150800 .param/l "i" 1 5 79, +C4<010011>; +v0x84b0c7980_0 .net *"_ivl_2", 7 0, v0x84b15f840_19; 1 drivers +v0x84b0c7a20_0 .net *"_ivl_5", 7 0, v0x84b15f660_19; 1 drivers +S_0x84ae7cf00 .scope generate, "GEN_BUS[20]" "GEN_BUS[20]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150840 .param/l "i" 1 5 79, +C4<010100>; +v0x84b0c7ac0_0 .net *"_ivl_2", 7 0, v0x84b15f840_20; 1 drivers +v0x84b0c7b60_0 .net *"_ivl_5", 7 0, v0x84b15f660_20; 1 drivers +S_0x84ae7d080 .scope generate, "GEN_BUS[21]" "GEN_BUS[21]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150880 .param/l "i" 1 5 79, +C4<010101>; +v0x84b0c7c00_0 .net *"_ivl_2", 7 0, v0x84b15f840_21; 1 drivers +v0x84b0c7ca0_0 .net *"_ivl_5", 7 0, v0x84b15f660_21; 1 drivers +S_0x84ae7d200 .scope generate, "GEN_BUS[22]" "GEN_BUS[22]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1508c0 .param/l "i" 1 5 79, +C4<010110>; +v0x84b0c7d40_0 .net *"_ivl_2", 7 0, v0x84b15f840_22; 1 drivers +v0x84b0c7de0_0 .net *"_ivl_5", 7 0, v0x84b15f660_22; 1 drivers +S_0x84ae7d380 .scope generate, "GEN_BUS[23]" "GEN_BUS[23]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150900 .param/l "i" 1 5 79, +C4<010111>; +v0x84b0c7e80_0 .net *"_ivl_2", 7 0, v0x84b15f840_23; 1 drivers +v0x84b0c7f20_0 .net *"_ivl_5", 7 0, v0x84b15f660_23; 1 drivers +S_0x84ae7d500 .scope generate, "GEN_BUS[24]" "GEN_BUS[24]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150940 .param/l "i" 1 5 79, +C4<011000>; +v0x84b154000_0 .net *"_ivl_2", 7 0, v0x84b15f840_24; 1 drivers +v0x84b1540a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_24; 1 drivers +S_0x84ae7d680 .scope generate, "GEN_BUS[25]" "GEN_BUS[25]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150980 .param/l "i" 1 5 79, +C4<011001>; +v0x84b154140_0 .net *"_ivl_2", 7 0, v0x84b15f840_25; 1 drivers +v0x84b1541e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_25; 1 drivers +S_0x84ae7d800 .scope generate, "GEN_BUS[26]" "GEN_BUS[26]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b1509c0 .param/l "i" 1 5 79, +C4<011010>; +v0x84b154280_0 .net *"_ivl_2", 7 0, v0x84b15f840_26; 1 drivers +v0x84b154320_0 .net *"_ivl_5", 7 0, v0x84b15f660_26; 1 drivers +S_0x84ae7d980 .scope generate, "GEN_BUS[27]" "GEN_BUS[27]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150a00 .param/l "i" 1 5 79, +C4<011011>; +v0x84b1543c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_27; 1 drivers +v0x84b154460_0 .net *"_ivl_5", 7 0, v0x84b15f660_27; 1 drivers +S_0x84ae7db00 .scope generate, "GEN_BUS[28]" "GEN_BUS[28]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150a40 .param/l "i" 1 5 79, +C4<011100>; +v0x84b154500_0 .net *"_ivl_2", 7 0, v0x84b15f840_28; 1 drivers +v0x84b1545a0_0 .net *"_ivl_5", 7 0, v0x84b15f660_28; 1 drivers +S_0x84ae7dc80 .scope generate, "GEN_BUS[29]" "GEN_BUS[29]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150a80 .param/l "i" 1 5 79, +C4<011101>; +v0x84b154640_0 .net *"_ivl_2", 7 0, v0x84b15f840_29; 1 drivers +v0x84b1546e0_0 .net *"_ivl_5", 7 0, v0x84b15f660_29; 1 drivers +S_0x84ae7de00 .scope generate, "GEN_BUS[30]" "GEN_BUS[30]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150ac0 .param/l "i" 1 5 79, +C4<011110>; +v0x84b154780_0 .net *"_ivl_2", 7 0, v0x84b15f840_30; 1 drivers +v0x84b154820_0 .net *"_ivl_5", 7 0, v0x84b15f660_30; 1 drivers +S_0x84ae7df80 .scope generate, "GEN_BUS[31]" "GEN_BUS[31]" 5 79, 5 79 0, S_0x102e269c0; + .timescale -9 -12; +P_0x84b150b00 .param/l "i" 1 5 79, +C4<011111>; +v0x84b1548c0_0 .net *"_ivl_2", 7 0, v0x84b15f840_31; 1 drivers +v0x84b154960_0 .net *"_ivl_5", 7 0, v0x84b15f660_31; 1 drivers +S_0x84ae7e100 .scope module, "u_mem" "int8_memory_access" 5 142, 6 1 0, S_0x102e269c0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 8 "wdata"; + .port_info 6 /OUTPUT 8 "rdata"; + .port_info 7 /OUTPUT 1 "ready"; + .port_info 8 /OUTPUT 1 "mem_req"; + .port_info 9 /OUTPUT 1 "mem_wr"; + .port_info 10 /OUTPUT 22 "mem_addr"; + .port_info 11 /OUTPUT 16 "mem_wdata"; + .port_info 12 /OUTPUT 1 "mem_lb_n"; + .port_info 13 /OUTPUT 1 "mem_ub_n"; + .port_info 14 /INPUT 16 "mem_rdata"; + .port_info 15 /INPUT 1 "mem_ready"; +P_0x102e33f80 .param/l "ADDR_WIDTH" 0 6 2, +C4<00000000000000000000000000010110>; +P_0x102e33fc0 .param/l "STATE_IDLE" 1 6 40, C4<00>; +P_0x102e34000 .param/l "STATE_WAIT" 1 6 41, C4<01>; +v0x84b154a00_0 .net "addr", 21 0, v0x84b15e120_0; 1 drivers +v0x84b154aa0_0 .var "addr_reg", 21 0; +v0x84b154b40_0 .net "clk", 0 0, o0x84a845780; alias, 0 drivers +v0x84b154be0_0 .var "mem_addr", 21 0; +v0x84b154c80_0 .var "mem_lb_n", 0 0; +v0x84b154d20_0 .net "mem_rdata", 15 0, L_0x84b12a3a0; alias, 1 drivers +v0x84b154dc0_0 .net "mem_ready", 0 0, o0x84a845840; alias, 0 drivers +v0x84b154e60_0 .var "mem_req", 0 0; +v0x84b154f00_0 .var "mem_ub_n", 0 0; +v0x84b154fa0_0 .var "mem_wdata", 15 0; +v0x84b155040_0 .var "mem_wr", 0 0; +v0x84b1550e0_0 .var/s "rdata", 7 0; +v0x84b155180_0 .var "ready", 0 0; +v0x84b155220_0 .net "req", 0 0, v0x84b15e760_0; 1 drivers +v0x84b1552c0_0 .net "rst", 0 0, o0x84a8459c0; alias, 0 drivers +v0x84b155360_0 .var "state", 1 0; +v0x84b155400_0 .net/s "wdata", 7 0, v0x84b15e800_0; 1 drivers +v0x84b1554a0_0 .net "wr", 0 0, v0x84b15e8a0_0; 1 drivers +E_0x84ae463c0 .event posedge, v0x84b154b40_0; +S_0x84ae7e280 .scope module, "u_neuron" "neuron_parallel" 5 203, 7 1 0, S_0x102e269c0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x84ae7e400 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84ae7e440 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84ae7e480 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84ae7e4c0 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84ae7e500 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84ae7e540 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b15cb40_0 .net *"_ivl_0", 31 0, L_0x84b1921c0; 1 drivers +v0x84b15cbe0_0 .net *"_ivl_11", 31 0, L_0x84b192300; 1 drivers +v0x84b15cc80_0 .net *"_ivl_14", 31 0, L_0x84b1923a0; 1 drivers +L_0x84a878178 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b15cd20_0 .net *"_ivl_17", 29 0, L_0x84a878178; 1 drivers +L_0x84a8781c0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b15cdc0_0 .net/2u *"_ivl_18", 31 0, L_0x84a8781c0; 1 drivers +v0x84b15ce60_0 .net *"_ivl_21", 31 0, L_0x84b192440; 1 drivers +L_0x84a878208 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b15cf00_0 .net/2u *"_ivl_22", 31 0, L_0x84a878208; 1 drivers +v0x84b15cfa0_0 .net *"_ivl_25", 31 0, L_0x84b1924e0; 1 drivers +v0x84b15d040_0 .net *"_ivl_29", 0 0, L_0x84ae3a4e0; 1 drivers +L_0x84a8780a0 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b15d0e0_0 .net *"_ivl_3", 29 0, L_0x84a8780a0; 1 drivers +v0x84b15d180_0 .net *"_ivl_31", 23 0, L_0x84ae3a580; 1 drivers +L_0x84a8780e8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b15d220_0 .net/2u *"_ivl_4", 31 0, L_0x84a8780e8; 1 drivers +v0x84b15d2c0_0 .net *"_ivl_7", 31 0, L_0x84b192260; 1 drivers +L_0x84a878130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b15d360_0 .net/2u *"_ivl_8", 31 0, L_0x84a878130; 1 drivers +v0x84b15d400_0 .var/s "acc", 31 0; +v0x84b15d4a0_0 .net/s "acc_next", 31 0, L_0x84ac8a4e0; 1 drivers +v0x84b15d540_0 .net/s "bias", 7 0, v0x84b15e9e0_0; 1 drivers +v0x84b15d5e0_0 .net/s "bias_ext", 31 0, L_0x84b193a20; 1 drivers +v0x84b15d680_0 .var "busy", 0 0; +v0x84b15d720_0 .net "clk", 0 0, o0x84a845780; alias, 0 drivers +v0x84b15d7c0_0 .var "done", 0 0; +v0x84b15d860_0 .net/s "final_acc", 31 0, L_0x84ac8a580; 1 drivers +v0x84b15d900_0 .var "group_index", 1 0; +v0x84b15d9a0_0 .net "rst", 0 0, o0x84a8459c0; alias, 0 drivers +v0x84b15da40_0 .net "start", 0 0, v0x84b15f200_0; 1 drivers +v0x84b15dae0_0 .net/s "w_bus", 255 0, L_0x84b191fe0; alias, 1 drivers +v0x84b15db80_0 .net/s "w_group", 63 0, L_0x84ae39040; 1 drivers +v0x84b15dc20_0 .net/s "x_bus", 255 0, L_0x84b191f40; alias, 1 drivers +v0x84b15dcc0_0 .net/s "x_group", 63 0, L_0x84ae38fa0; 1 drivers +v0x84b15dd60_0 .var/s "y", 7 0; +L_0x84b1921c0 .concat [ 2 30 0 0], v0x84b15d900_0, L_0x84a8780a0; +L_0x84b192260 .arith/mult 32, L_0x84b1921c0, L_0x84a8780e8; +L_0x84b192300 .arith/mult 32, L_0x84b192260, L_0x84a878130; +L_0x84ae38fa0 .part/v L_0x84b191f40, L_0x84b192300, 64; +L_0x84b1923a0 .concat [ 2 30 0 0], v0x84b15d900_0, L_0x84a878178; +L_0x84b192440 .arith/mult 32, L_0x84b1923a0, L_0x84a8781c0; +L_0x84b1924e0 .arith/mult 32, L_0x84b192440, L_0x84a878208; +L_0x84ae39040 .part/v L_0x84b191fe0, L_0x84b1924e0, 64; +L_0x84ae3a4e0 .part v0x84b15e9e0_0, 7, 1; +L_0x84ae3a580 .repeat 24, 24, L_0x84ae3a4e0; +L_0x84b193a20 .concat [ 8 24 0 0], v0x84b15e9e0_0, L_0x84ae3a580; +L_0x84ac8a580 .arith/sum 32, L_0x84ac8a4e0, L_0x84b193a20; +S_0x84ae7e580 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84ae7e280; + .timescale 0 0; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8200 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8240 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8280 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc82c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b15c780_0 .net/s "acc_in", 31 0, v0x84b15d400_0; 1 drivers +v0x84b15c820_0 .net/s "acc_out", 31 0, L_0x84ac8a4e0; alias, 1 drivers +v0x84b15c8c0 .array "products", 7 0; +v0x84b15c8c0_0 .net/s v0x84b15c8c0 0, 31 0, L_0x84ac89e00; 1 drivers +v0x84b15c8c0_1 .net/s v0x84b15c8c0 1, 31 0, L_0x84ac89c20; 1 drivers +v0x84b15c8c0_2 .net/s v0x84b15c8c0 2, 31 0, L_0x84ac89ae0; 1 drivers +v0x84b15c8c0_3 .net/s v0x84b15c8c0 3, 31 0, L_0x84ac89cc0; 1 drivers +v0x84b15c8c0_4 .net/s v0x84b15c8c0 4, 31 0, L_0x84ac89d60; 1 drivers +v0x84b15c8c0_5 .net/s v0x84b15c8c0 5, 31 0, L_0x84ac89ea0; 1 drivers +v0x84b15c8c0_6 .net/s v0x84b15c8c0 6, 31 0, L_0x84ac89f40; 1 drivers +v0x84b15c8c0_7 .net/s v0x84b15c8c0 7, 31 0, L_0x84ac89fe0; 1 drivers +v0x84b15c960 .array "tree", 31 0; +v0x84b15c960_0 .net/s v0x84b15c960 0, 31 0, L_0x84ac3f020; 1 drivers +v0x84b15c960_1 .net/s v0x84b15c960 1, 31 0, L_0x84ac3f090; 1 drivers +v0x84b15c960_2 .net/s v0x84b15c960 2, 31 0, L_0x84ac3f100; 1 drivers +v0x84b15c960_3 .net/s v0x84b15c960 3, 31 0, L_0x84ac3f170; 1 drivers +v0x84b15c960_4 .net/s v0x84b15c960 4, 31 0, L_0x84ac3f1e0; 1 drivers +v0x84b15c960_5 .net/s v0x84b15c960 5, 31 0, L_0x84ac3f250; 1 drivers +v0x84b15c960_6 .net/s v0x84b15c960 6, 31 0, L_0x84ac3f2c0; 1 drivers +v0x84b15c960_7 .net/s v0x84b15c960 7, 31 0, L_0x84ac3f330; 1 drivers +v0x84b15c960_8 .net/s v0x84b15c960 8, 31 0, L_0x84ac8a080; 1 drivers +v0x84b15c960_9 .net/s v0x84b15c960 9, 31 0, L_0x84ac8a120; 1 drivers +v0x84b15c960_10 .net/s v0x84b15c960 10, 31 0, L_0x84ac8a1c0; 1 drivers +v0x84b15c960_11 .net/s v0x84b15c960 11, 31 0, L_0x84ac8a260; 1 drivers +o0x84a847520 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_12 .net/s v0x84b15c960 12, 31 0, o0x84a847520; 0 drivers +o0x84a847550 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_13 .net/s v0x84b15c960 13, 31 0, o0x84a847550; 0 drivers +o0x84a847580 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_14 .net/s v0x84b15c960 14, 31 0, o0x84a847580; 0 drivers +o0x84a8475b0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_15 .net/s v0x84b15c960 15, 31 0, o0x84a8475b0; 0 drivers +v0x84b15c960_16 .net/s v0x84b15c960 16, 31 0, L_0x84ac8a300; 1 drivers +v0x84b15c960_17 .net/s v0x84b15c960 17, 31 0, L_0x84ac8a3a0; 1 drivers +o0x84a847640 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_18 .net/s v0x84b15c960 18, 31 0, o0x84a847640; 0 drivers +o0x84a847670 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_19 .net/s v0x84b15c960 19, 31 0, o0x84a847670; 0 drivers +o0x84a8476a0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_20 .net/s v0x84b15c960 20, 31 0, o0x84a8476a0; 0 drivers +o0x84a8476d0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_21 .net/s v0x84b15c960 21, 31 0, o0x84a8476d0; 0 drivers +o0x84a847700 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_22 .net/s v0x84b15c960 22, 31 0, o0x84a847700; 0 drivers +o0x84a847730 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_23 .net/s v0x84b15c960 23, 31 0, o0x84a847730; 0 drivers +v0x84b15c960_24 .net/s v0x84b15c960 24, 31 0, L_0x84ac8a440; 1 drivers +o0x84a847790 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_25 .net/s v0x84b15c960 25, 31 0, o0x84a847790; 0 drivers +o0x84a8477c0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_26 .net/s v0x84b15c960 26, 31 0, o0x84a8477c0; 0 drivers +o0x84a8477f0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_27 .net/s v0x84b15c960 27, 31 0, o0x84a8477f0; 0 drivers +o0x84a847820 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_28 .net/s v0x84b15c960 28, 31 0, o0x84a847820; 0 drivers +o0x84a847850 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_29 .net/s v0x84b15c960 29, 31 0, o0x84a847850; 0 drivers +o0x84a847880 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_30 .net/s v0x84b15c960 30, 31 0, o0x84a847880; 0 drivers +o0x84a8478b0 .functor BUFZ 32, c4; HiZ drive +v0x84b15c960_31 .net/s v0x84b15c960 31, 31 0, o0x84a8478b0; 0 drivers +v0x84b15ca00_0 .net/s "w_bus", 63 0, L_0x84ae39040; alias, 1 drivers +v0x84b15caa0_0 .net/s "x_bus", 63 0, L_0x84ae38fa0; alias, 1 drivers +L_0x84ae39220 .part L_0x84ae38fa0, 0, 8; +L_0x84ae392c0 .part L_0x84ae39040, 0, 8; +L_0x84ae394a0 .part L_0x84ae38fa0, 8, 8; +L_0x84ae39540 .part L_0x84ae39040, 8, 8; +L_0x84ae39720 .part L_0x84ae38fa0, 16, 8; +L_0x84ae397c0 .part L_0x84ae39040, 16, 8; +L_0x84ae399a0 .part L_0x84ae38fa0, 24, 8; +L_0x84ae39a40 .part L_0x84ae39040, 24, 8; +L_0x84ae39c20 .part L_0x84ae38fa0, 32, 8; +L_0x84ae39cc0 .part L_0x84ae39040, 32, 8; +L_0x84ae39ea0 .part L_0x84ae38fa0, 40, 8; +L_0x84ae39f40 .part L_0x84ae39040, 40, 8; +L_0x84ae3a120 .part L_0x84ae38fa0, 48, 8; +L_0x84ae3a1c0 .part L_0x84ae39040, 48, 8; +L_0x84ae3a3a0 .part L_0x84ae38fa0, 56, 8; +L_0x84ae3a440 .part L_0x84ae39040, 56, 8; +L_0x84ac8a4e0 .arith/sum 32, v0x84b15d400_0, L_0x84ac8a440; +S_0x84ae7e700 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150b40 .param/l "i" 1 8 20, +C4<00>; +S_0x84ae7e880 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7e700; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x102e18c20 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x102e18c60 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x102e18ca0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b155540_0 .net/s *"_ivl_0", 15 0, L_0x84b192580; 1 drivers +v0x84b1555e0_0 .net/s *"_ivl_2", 15 0, L_0x84b192620; 1 drivers +v0x84b155680_0 .net *"_ivl_7", 0 0, L_0x84ae390e0; 1 drivers +v0x84b155720_0 .net *"_ivl_9", 15 0, L_0x84ae39180; 1 drivers +L_0x84a878250 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1557c0_0 .net/s "acc_in", 31 0, L_0x84a878250; 1 drivers +v0x84b155860_0 .net/s "acc_out", 31 0, L_0x84ac89e00; alias, 1 drivers +v0x84b155900_0 .net/s "product", 15 0, L_0x84b1926c0; 1 drivers +v0x84b1559a0_0 .net/s "product_ext", 31 0, L_0x84b192760; 1 drivers +v0x84b155a40_0 .net/s "w", 7 0, L_0x84ae392c0; 1 drivers +v0x84b155ae0_0 .net/s "x", 7 0, L_0x84ae39220; 1 drivers +L_0x84b192580 .extend/s 16, L_0x84ae39220; +L_0x84b192620 .extend/s 16, L_0x84ae392c0; +L_0x84b1926c0 .arith/mult 16, L_0x84b192580, L_0x84b192620; +L_0x84ae390e0 .part L_0x84b1926c0, 15, 1; +L_0x84ae39180 .repeat 16, 16, L_0x84ae390e0; +L_0x84b192760 .concat [ 16 16 0 0], L_0x84b1926c0, L_0x84ae39180; +L_0x84ac89e00 .arith/sum 32, L_0x84a878250, L_0x84b192760; +S_0x84ae7ea00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150b80 .param/l "i" 1 8 20, +C4<01>; +S_0x84ae7eb80 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7ea00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x102e304d0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x102e30510 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x102e30550 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b155b80_0 .net/s *"_ivl_0", 15 0, L_0x84b192800; 1 drivers +v0x84b155c20_0 .net/s *"_ivl_2", 15 0, L_0x84b1928a0; 1 drivers +v0x84b155cc0_0 .net *"_ivl_7", 0 0, L_0x84ae39360; 1 drivers +v0x84b155d60_0 .net *"_ivl_9", 15 0, L_0x84ae39400; 1 drivers +L_0x84a878298 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b155e00_0 .net/s "acc_in", 31 0, L_0x84a878298; 1 drivers +v0x84b155ea0_0 .net/s "acc_out", 31 0, L_0x84ac89c20; alias, 1 drivers +v0x84b155f40_0 .net/s "product", 15 0, L_0x84b192940; 1 drivers +v0x84b155fe0_0 .net/s "product_ext", 31 0, L_0x84b1929e0; 1 drivers +v0x84b156080_0 .net/s "w", 7 0, L_0x84ae39540; 1 drivers +v0x84b156120_0 .net/s "x", 7 0, L_0x84ae394a0; 1 drivers +L_0x84b192800 .extend/s 16, L_0x84ae394a0; +L_0x84b1928a0 .extend/s 16, L_0x84ae39540; +L_0x84b192940 .arith/mult 16, L_0x84b192800, L_0x84b1928a0; +L_0x84ae39360 .part L_0x84b192940, 15, 1; +L_0x84ae39400 .repeat 16, 16, L_0x84ae39360; +L_0x84b1929e0 .concat [ 16 16 0 0], L_0x84b192940, L_0x84ae39400; +L_0x84ac89c20 .arith/sum 32, L_0x84a878298, L_0x84b1929e0; +S_0x84ae7ed00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150bc0 .param/l "i" 1 8 20, +C4<010>; +S_0x84ae7ee80 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7ed00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x102e26340 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x102e26380 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x102e263c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1561c0_0 .net/s *"_ivl_0", 15 0, L_0x84b192a80; 1 drivers +v0x84b156260_0 .net/s *"_ivl_2", 15 0, L_0x84b192b20; 1 drivers +v0x84b156300_0 .net *"_ivl_7", 0 0, L_0x84ae395e0; 1 drivers +v0x84b1563a0_0 .net *"_ivl_9", 15 0, L_0x84ae39680; 1 drivers +L_0x84a8782e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b156440_0 .net/s "acc_in", 31 0, L_0x84a8782e0; 1 drivers +v0x84b1564e0_0 .net/s "acc_out", 31 0, L_0x84ac89ae0; alias, 1 drivers +v0x84b156580_0 .net/s "product", 15 0, L_0x84b192bc0; 1 drivers +v0x84b156620_0 .net/s "product_ext", 31 0, L_0x84b192c60; 1 drivers +v0x84b1566c0_0 .net/s "w", 7 0, L_0x84ae397c0; 1 drivers +v0x84b156760_0 .net/s "x", 7 0, L_0x84ae39720; 1 drivers +L_0x84b192a80 .extend/s 16, L_0x84ae39720; +L_0x84b192b20 .extend/s 16, L_0x84ae397c0; +L_0x84b192bc0 .arith/mult 16, L_0x84b192a80, L_0x84b192b20; +L_0x84ae395e0 .part L_0x84b192bc0, 15, 1; +L_0x84ae39680 .repeat 16, 16, L_0x84ae395e0; +L_0x84b192c60 .concat [ 16 16 0 0], L_0x84b192bc0, L_0x84ae39680; +L_0x84ac89ae0 .arith/sum 32, L_0x84a8782e0, L_0x84b192c60; +S_0x84ae7f000 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150c00 .param/l "i" 1 8 20, +C4<011>; +S_0x84ae7f180 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7f000; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158000 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158040 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158080 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b156800_0 .net/s *"_ivl_0", 15 0, L_0x84b192d00; 1 drivers +v0x84b1568a0_0 .net/s *"_ivl_2", 15 0, L_0x84b192da0; 1 drivers +v0x84b156940_0 .net *"_ivl_7", 0 0, L_0x84ae39860; 1 drivers +v0x84b1569e0_0 .net *"_ivl_9", 15 0, L_0x84ae39900; 1 drivers +L_0x84a878328 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b156a80_0 .net/s "acc_in", 31 0, L_0x84a878328; 1 drivers +v0x84b156b20_0 .net/s "acc_out", 31 0, L_0x84ac89cc0; alias, 1 drivers +v0x84b156bc0_0 .net/s "product", 15 0, L_0x84b192e40; 1 drivers +v0x84b156c60_0 .net/s "product_ext", 31 0, L_0x84b192ee0; 1 drivers +v0x84b156d00_0 .net/s "w", 7 0, L_0x84ae39a40; 1 drivers +v0x84b156da0_0 .net/s "x", 7 0, L_0x84ae399a0; 1 drivers +L_0x84b192d00 .extend/s 16, L_0x84ae399a0; +L_0x84b192da0 .extend/s 16, L_0x84ae39a40; +L_0x84b192e40 .arith/mult 16, L_0x84b192d00, L_0x84b192da0; +L_0x84ae39860 .part L_0x84b192e40, 15, 1; +L_0x84ae39900 .repeat 16, 16, L_0x84ae39860; +L_0x84b192ee0 .concat [ 16 16 0 0], L_0x84b192e40, L_0x84ae39900; +L_0x84ac89cc0 .arith/sum 32, L_0x84a878328, L_0x84b192ee0; +S_0x84ae7f300 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150c40 .param/l "i" 1 8 20, +C4<0100>; +S_0x84ae7f480 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7f300; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1580c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158100 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158140 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b156e40_0 .net/s *"_ivl_0", 15 0, L_0x84b192f80; 1 drivers +v0x84b156ee0_0 .net/s *"_ivl_2", 15 0, L_0x84b193020; 1 drivers +v0x84b156f80_0 .net *"_ivl_7", 0 0, L_0x84ae39ae0; 1 drivers +v0x84b157020_0 .net *"_ivl_9", 15 0, L_0x84ae39b80; 1 drivers +L_0x84a878370 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1570c0_0 .net/s "acc_in", 31 0, L_0x84a878370; 1 drivers +v0x84b157160_0 .net/s "acc_out", 31 0, L_0x84ac89d60; alias, 1 drivers +v0x84b157200_0 .net/s "product", 15 0, L_0x84b1930c0; 1 drivers +v0x84b1572a0_0 .net/s "product_ext", 31 0, L_0x84b193160; 1 drivers +v0x84b157340_0 .net/s "w", 7 0, L_0x84ae39cc0; 1 drivers +v0x84b1573e0_0 .net/s "x", 7 0, L_0x84ae39c20; 1 drivers +L_0x84b192f80 .extend/s 16, L_0x84ae39c20; +L_0x84b193020 .extend/s 16, L_0x84ae39cc0; +L_0x84b1930c0 .arith/mult 16, L_0x84b192f80, L_0x84b193020; +L_0x84ae39ae0 .part L_0x84b1930c0, 15, 1; +L_0x84ae39b80 .repeat 16, 16, L_0x84ae39ae0; +L_0x84b193160 .concat [ 16 16 0 0], L_0x84b1930c0, L_0x84ae39b80; +L_0x84ac89d60 .arith/sum 32, L_0x84a878370, L_0x84b193160; +S_0x84ae7f600 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150c80 .param/l "i" 1 8 20, +C4<0101>; +S_0x84ae7f780 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7f600; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158180 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1581c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158200 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b157480_0 .net/s *"_ivl_0", 15 0, L_0x84b193200; 1 drivers +v0x84b157520_0 .net/s *"_ivl_2", 15 0, L_0x84b1932a0; 1 drivers +v0x84b1575c0_0 .net *"_ivl_7", 0 0, L_0x84ae39d60; 1 drivers +v0x84b157660_0 .net *"_ivl_9", 15 0, L_0x84ae39e00; 1 drivers +L_0x84a8783b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b157700_0 .net/s "acc_in", 31 0, L_0x84a8783b8; 1 drivers +v0x84b1577a0_0 .net/s "acc_out", 31 0, L_0x84ac89ea0; alias, 1 drivers +v0x84b157840_0 .net/s "product", 15 0, L_0x84b193340; 1 drivers +v0x84b1578e0_0 .net/s "product_ext", 31 0, L_0x84b1933e0; 1 drivers +v0x84b157980_0 .net/s "w", 7 0, L_0x84ae39f40; 1 drivers +v0x84b157a20_0 .net/s "x", 7 0, L_0x84ae39ea0; 1 drivers +L_0x84b193200 .extend/s 16, L_0x84ae39ea0; +L_0x84b1932a0 .extend/s 16, L_0x84ae39f40; +L_0x84b193340 .arith/mult 16, L_0x84b193200, L_0x84b1932a0; +L_0x84ae39d60 .part L_0x84b193340, 15, 1; +L_0x84ae39e00 .repeat 16, 16, L_0x84ae39d60; +L_0x84b1933e0 .concat [ 16 16 0 0], L_0x84b193340, L_0x84ae39e00; +L_0x84ac89ea0 .arith/sum 32, L_0x84a8783b8, L_0x84b1933e0; +S_0x84ae7f900 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150cc0 .param/l "i" 1 8 20, +C4<0110>; +S_0x84ae7fa80 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7f900; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158240 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158280 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1582c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b157ac0_0 .net/s *"_ivl_0", 15 0, L_0x84b193480; 1 drivers +v0x84b157b60_0 .net/s *"_ivl_2", 15 0, L_0x84b193520; 1 drivers +v0x84b157c00_0 .net *"_ivl_7", 0 0, L_0x84ae39fe0; 1 drivers +v0x84b157ca0_0 .net *"_ivl_9", 15 0, L_0x84ae3a080; 1 drivers +L_0x84a878400 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b157d40_0 .net/s "acc_in", 31 0, L_0x84a878400; 1 drivers +v0x84b157de0_0 .net/s "acc_out", 31 0, L_0x84ac89f40; alias, 1 drivers +v0x84b157e80_0 .net/s "product", 15 0, L_0x84b1935c0; 1 drivers +v0x84b157f20_0 .net/s "product_ext", 31 0, L_0x84b193660; 1 drivers +v0x84b15c000_0 .net/s "w", 7 0, L_0x84ae3a1c0; 1 drivers +v0x84b15c0a0_0 .net/s "x", 7 0, L_0x84ae3a120; 1 drivers +L_0x84b193480 .extend/s 16, L_0x84ae3a120; +L_0x84b193520 .extend/s 16, L_0x84ae3a1c0; +L_0x84b1935c0 .arith/mult 16, L_0x84b193480, L_0x84b193520; +L_0x84ae39fe0 .part L_0x84b1935c0, 15, 1; +L_0x84ae3a080 .repeat 16, 16, L_0x84ae39fe0; +L_0x84b193660 .concat [ 16 16 0 0], L_0x84b1935c0, L_0x84ae3a080; +L_0x84ac89f40 .arith/sum 32, L_0x84a878400, L_0x84b193660; +S_0x84ae7fc00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150d00 .param/l "i" 1 8 20, +C4<0111>; +S_0x84ae7fd80 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae7fc00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158300 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158340 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158380 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b15c140_0 .net/s *"_ivl_0", 15 0, L_0x84b193700; 1 drivers +v0x84b15c1e0_0 .net/s *"_ivl_2", 15 0, L_0x84b1937a0; 1 drivers +v0x84b15c280_0 .net *"_ivl_7", 0 0, L_0x84ae3a260; 1 drivers +v0x84b15c320_0 .net *"_ivl_9", 15 0, L_0x84ae3a300; 1 drivers +L_0x84a878448 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b15c3c0_0 .net/s "acc_in", 31 0, L_0x84a878448; 1 drivers +v0x84b15c460_0 .net/s "acc_out", 31 0, L_0x84ac89fe0; alias, 1 drivers +v0x84b15c500_0 .net/s "product", 15 0, L_0x84b193840; 1 drivers +v0x84b15c5a0_0 .net/s "product_ext", 31 0, L_0x84b1938e0; 1 drivers +v0x84b15c640_0 .net/s "w", 7 0, L_0x84ae3a440; 1 drivers +v0x84b15c6e0_0 .net/s "x", 7 0, L_0x84ae3a3a0; 1 drivers +L_0x84b193700 .extend/s 16, L_0x84ae3a3a0; +L_0x84b1937a0 .extend/s 16, L_0x84ae3a440; +L_0x84b193840 .arith/mult 16, L_0x84b193700, L_0x84b1937a0; +L_0x84ae3a260 .part L_0x84b193840, 15, 1; +L_0x84ae3a300 .repeat 16, 16, L_0x84ae3a260; +L_0x84b1938e0 .concat [ 16 16 0 0], L_0x84b193840, L_0x84ae3a300; +L_0x84ac89fe0 .arith/sum 32, L_0x84a878448, L_0x84b1938e0; +S_0x84ae84000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150d40 .param/l "i" 1 8 80, +C4<00>; +L_0x84ac3f020 .functor BUFZ 32, L_0x84ac89e00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150d80 .param/l "i" 1 8 80, +C4<01>; +L_0x84ac3f090 .functor BUFZ 32, L_0x84ac89c20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150dc0 .param/l "i" 1 8 80, +C4<010>; +L_0x84ac3f100 .functor BUFZ 32, L_0x84ac89ae0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150e00 .param/l "i" 1 8 80, +C4<011>; +L_0x84ac3f170 .functor BUFZ 32, L_0x84ac89cc0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150e40 .param/l "i" 1 8 80, +C4<0100>; +L_0x84ac3f1e0 .functor BUFZ 32, L_0x84ac89d60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150e80 .param/l "i" 1 8 80, +C4<0101>; +L_0x84ac3f250 .functor BUFZ 32, L_0x84ac89ea0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150ec0 .param/l "i" 1 8 80, +C4<0110>; +L_0x84ac3f2c0 .functor BUFZ 32, L_0x84ac89f40, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84a80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150f00 .param/l "i" 1 8 80, +C4<0111>; +L_0x84ac3f330 .functor BUFZ 32, L_0x84ac89fe0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae84c00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b150f40 .param/l "level" 1 8 92, +C4<00>; +S_0x84ae84d80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae84c00; + .timescale 0 0; +P_0x84b150f80 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8a080 .arith/sum 32, L_0x84ac3f020, L_0x84ac3f090; +S_0x84ae84f00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae84c00; + .timescale 0 0; +P_0x84b150fc0 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8a120 .arith/sum 32, L_0x84ac3f100, L_0x84ac3f170; +S_0x84ae85080 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84ae84c00; + .timescale 0 0; +P_0x84b151000 .param/l "node" 1 8 94, +C4<010>; +L_0x84ac8a1c0 .arith/sum 32, L_0x84ac3f1e0, L_0x84ac3f250; +S_0x84ae85200 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84ae84c00; + .timescale 0 0; +P_0x84b151040 .param/l "node" 1 8 94, +C4<011>; +L_0x84ac8a260 .arith/sum 32, L_0x84ac3f2c0, L_0x84ac3f330; +S_0x84ae85380 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b151080 .param/l "level" 1 8 92, +C4<01>; +S_0x84ae85500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae85380; + .timescale 0 0; +P_0x84b1510c0 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8a300 .arith/sum 32, L_0x84ac8a080, L_0x84ac8a120; +S_0x84ae85680 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae85380; + .timescale 0 0; +P_0x84b151100 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8a3a0 .arith/sum 32, L_0x84ac8a1c0, L_0x84ac8a260; +S_0x84ae85800 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84ae7e580; + .timescale 0 0; +P_0x84b151140 .param/l "level" 1 8 92, +C4<010>; +S_0x84ae85980 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae85800; + .timescale 0 0; +P_0x84b151180 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8a440 .arith/sum 32, L_0x84ac8a300, L_0x84ac8a3a0; +S_0x102e24c70 .scope module, "psram_controller" "psram_controller" 10 1; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "mem_req"; + .port_info 3 /INPUT 1 "mem_wr"; + .port_info 4 /INPUT 22 "mem_addr"; + .port_info 5 /INPUT 16 "mem_wdata"; + .port_info 6 /INPUT 1 "mem_lb_n"; + .port_info 7 /INPUT 1 "mem_ub_n"; + .port_info 8 /OUTPUT 16 "mem_rdata"; + .port_info 9 /OUTPUT 1 "mem_ready"; + .port_info 10 /OUTPUT 22 "psram_a"; + .port_info 11 /INOUT 16 "psram_dq"; + .port_info 12 /OUTPUT 1 "psram_ce_n"; + .port_info 13 /OUTPUT 1 "psram_oe_n"; + .port_info 14 /OUTPUT 1 "psram_we_n"; + .port_info 15 /OUTPUT 1 "psram_lb_n"; + .port_info 16 /OUTPUT 1 "psram_ub_n"; + .port_info 17 /OUTPUT 1 "psram_zz_n"; +P_0x102e301d0 .param/l "ACCESS_CYCLES" 1 10 43, +C4<00000000000000000000000000000110>; +P_0x102e30210 .param/l "ADDR_WIDTH" 0 10 2, +C4<00000000000000000000000000010110>; +P_0x102e30250 .param/l "CLK_FREQ_MHZ" 0 10 4, +C4<00000000000000000000000001010000>; +P_0x102e30290 .param/l "COUNTER_WIDTH" 1 10 49, +C4<00000000000000000000000000001110>; +P_0x102e302d0 .param/l "DATA_WIDTH" 0 10 3, +C4<00000000000000000000000000010000>; +P_0x102e30310 .param/l "INIT_CYCLES" 1 10 46, +C4<00000000000000000010111011100000>; +P_0x102e30350 .param/l "STATE_IDLE" 1 10 58, C4<001>; +P_0x102e30390 .param/l "STATE_INIT" 1 10 57, C4<000>; +P_0x102e303d0 .param/l "STATE_READ" 1 10 59, C4<010>; +P_0x102e30410 .param/l "STATE_WRITE" 1 10 60, C4<011>; +P_0x102e30450 .param/l "STATE_WRITE_WAIT" 1 10 61, C4<100>; +o0x84a849290 .functor BUFZ 16, c4; HiZ drive +; Elide local net with no drivers, v0x84b15f980_0 name=_ivl_0 +v0x84b15fa20_0 .var "address_reg", 21 0; +o0x84a8492f0 .functor BUFZ 1, c4; HiZ drive +v0x84b15fac0_0 .net "clk", 0 0, o0x84a8492f0; 0 drivers +v0x84b15fb60_0 .var "counter", 13 0; +v0x84b15fc00_0 .var "dq_oe", 0 0; +v0x84b15fca0_0 .var "dq_out", 15 0; +v0x84b15fd40_0 .var "lb_reg", 0 0; +o0x84a8493e0 .functor BUFZ 22, c4; HiZ drive +v0x84b15fde0_0 .net "mem_addr", 21 0, o0x84a8493e0; 0 drivers +o0x84a849410 .functor BUFZ 1, c4; HiZ drive +v0x84b15fe80_0 .net "mem_lb_n", 0 0, o0x84a849410; 0 drivers +v0x84b15ff20_0 .var "mem_rdata", 15 0; +v0x84b160000_0 .var "mem_ready", 0 0; +o0x84a8494a0 .functor BUFZ 1, c4; HiZ drive +v0x84b1600a0_0 .net "mem_req", 0 0, o0x84a8494a0; 0 drivers +o0x84a8494d0 .functor BUFZ 1, c4; HiZ drive +v0x84b160140_0 .net "mem_ub_n", 0 0, o0x84a8494d0; 0 drivers +o0x84a849500 .functor BUFZ 16, c4; HiZ drive +v0x84b1601e0_0 .net "mem_wdata", 15 0, o0x84a849500; 0 drivers +o0x84a849530 .functor BUFZ 1, c4; HiZ drive +v0x84b160280_0 .net "mem_wr", 0 0, o0x84a849530; 0 drivers +v0x84b160320_0 .var "psram_a", 21 0; +v0x84b1603c0_0 .var "psram_ce_n", 0 0; +v0x84b160460_0 .net "psram_dq", 15 0, L_0x84b12a440; 1 drivers +v0x84b160500_0 .var "psram_lb_n", 0 0; +v0x84b1605a0_0 .var "psram_oe_n", 0 0; +v0x84b160640_0 .var "psram_ub_n", 0 0; +v0x84b1606e0_0 .var "psram_we_n", 0 0; +v0x84b160780_0 .var "psram_zz_n", 0 0; +o0x84a8496e0 .functor BUFZ 1, c4; HiZ drive +v0x84b160820_0 .net "rst", 0 0, o0x84a8496e0; 0 drivers +v0x84b1608c0_0 .var "state", 2 0; +v0x84b160960_0 .var "ub_reg", 0 0; +v0x84b160a00_0 .var "wdata_reg", 15 0; +v0x84b160aa0_0 .var "wr_reg", 0 0; +E_0x84ae46640 .event posedge, v0x84b15fac0_0; +L_0x84b12a440 .functor MUXZ 16, o0x84a849290, v0x84b15fca0_0, v0x84b15fc00_0, C4<>; +S_0x102e24df0 .scope module, "tb" "tb" 11 3; + .timescale -9 -12; +P_0x84b131f40 .param/l "ACC_WIDTH" 0 11 9, +C4<00000000000000000000000000100000>; +P_0x84b131f80 .param/l "DATA_WIDTH" 0 11 5, +C4<00000000000000000000000000001000>; +P_0x84b131fc0 .param/l "N_INPUTS" 0 11 6, +C4<00000000000000000000000000100000>; +P_0x84b132000 .param/l "N_NEURONS" 0 11 7, +C4<00000000000000000000000000001000>; +P_0x84b132040 .param/l "PARALLEL" 0 11 8, +C4<00000000000000000000000000001000>; +v0x84b191860_0 .var/s "bias_bus", 63 0; +v0x84b191900_0 .net "busy", 0 0, L_0x84aee9d60; 1 drivers +v0x84b1919a0_0 .var "clk", 0 0; +v0x84b191a40_0 .net "done", 0 0, L_0x84aee9e00; 1 drivers +v0x84b191ae0_0 .var/i "errors", 31 0; +v0x84b191b80_0 .var/i "i", 31 0; +v0x84b191c20_0 .var "rst", 0 0; +v0x84b191cc0_0 .var "start", 0 0; +v0x84b191d60_0 .var/s "weights_bus", 2047 0; +v0x84b191e00_0 .var/s "x_bus", 255 0; +v0x84b191ea0_0 .net/s "y_bus", 63 0, L_0x84b1a43c0; 1 drivers +S_0x84ae85b00 .scope module, "dut" "layer" 11 38, 12 1 0, S_0x102e24df0; .timescale 0 0; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 8192 "weights_bus"; - .port_info 5 /INPUT 128 "bias_bus"; - .port_info 6 /OUTPUT 128 "y_bus"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 2048 "weights_bus"; + .port_info 5 /INPUT 64 "bias_bus"; + .port_info 6 /OUTPUT 64 "y_bus"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e5b630 .param/l "ACC_WIDTH" 0 4 7, +C4<00000000000000000000000000101000>; -P_0x102e5b670 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; -P_0x102e5b6b0 .param/l "FRAC_BITS" 0 4 3, +C4<00000000000000000000000000001000>; -P_0x102e5b6f0 .param/l "N_INPUTS" 0 4 4, +C4<00000000000000000000000001000000>; -P_0x102e5b730 .param/l "N_NEURONS" 0 4 5, +C4<00000000000000000000000000001000>; -P_0x102e5b770 .param/l "PARALLEL" 0 4 6, +C4<00000000000000000000000000001000>; -v0x8d2d16ee0_0 .net/s "bias_bus", 127 0, v0x8d2d17700_0; 1 drivers -v0x8d2d16f80_0 .net "busy", 0 0, L_0x8d323ce60; alias, 1 drivers -v0x8d2d17020_0 .net "clk", 0 0, v0x8d2d17840_0; 1 drivers -v0x8d2d170c0_0 .net "done", 0 0, L_0x8d323cf00; alias, 1 drivers -v0x8d2d17160_0 .net "neuron_busy", 7 0, L_0x8d32390e0; 1 drivers -v0x8d2d17200_0 .net "neuron_done", 7 0, L_0x8d3239180; 1 drivers -v0x8d2d172a0_0 .net "rst", 0 0, v0x8d2d17ac0_0; 1 drivers -v0x8d2d17340_0 .net "start", 0 0, v0x8d2d17b60_0; 1 drivers -v0x8d2d173e0_0 .net/s "weights_bus", 8191 0, v0x8d2d17c00_0; 1 drivers -v0x8d2d17480_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; 1 drivers -v0x8d2d17520_0 .net/s "y_bus", 127 0, L_0x8d3239040; alias, 1 drivers -L_0x8d321c500 .part v0x8d2d17c00_0, 0, 1024; -L_0x8d321c5a0 .part v0x8d2d17700_0, 0, 16; -L_0x8d321d860 .part v0x8d2d17c00_0, 1024, 1024; -L_0x8d321d900 .part v0x8d2d17700_0, 16, 16; -L_0x8d321ebc0 .part v0x8d2d17c00_0, 2048, 1024; -L_0x8d321ec60 .part v0x8d2d17700_0, 32, 16; -L_0x8d321ff20 .part v0x8d2d17c00_0, 3072, 1024; -L_0x8d322c000 .part v0x8d2d17700_0, 48, 16; -L_0x8d322d2c0 .part v0x8d2d17c00_0, 4096, 1024; -L_0x8d322d360 .part v0x8d2d17700_0, 64, 16; -L_0x8d322e620 .part v0x8d2d17c00_0, 5120, 1024; -L_0x8d322e6c0 .part v0x8d2d17700_0, 80, 16; -L_0x8d322f980 .part v0x8d2d17c00_0, 6144, 1024; -L_0x8d322fa20 .part v0x8d2d17700_0, 96, 16; -L_0x8d323cd20 .part v0x8d2d17c00_0, 7168, 1024; -L_0x8d323cdc0 .part v0x8d2d17700_0, 112, 16; -LS_0x8d3239040_0_0 .concat8 [ 16 16 16 16], v0x8d2cedd60_0, v0x8d2cf3200_0, v0x8d2cfc6e0_0, v0x8d2d01b80_0; -LS_0x8d3239040_0_4 .concat8 [ 16 16 16 16], v0x8d2d07020_0, v0x8d2d0c500_0, v0x8d2d119a0_0, v0x8d2d16e40_0; -L_0x8d3239040 .concat8 [ 64 64 0 0], LS_0x8d3239040_0_0, LS_0x8d3239040_0_4; -LS_0x8d32390e0_0_0 .concat8 [ 1 1 1 1], v0x8d2ced5e0_0, v0x8d2cf2a80_0, v0x8d2cf7f20_0, v0x8d2d01400_0; -LS_0x8d32390e0_0_4 .concat8 [ 1 1 1 1], v0x8d2d068a0_0, v0x8d2d0bd40_0, v0x8d2d11220_0, v0x8d2d166c0_0; -L_0x8d32390e0 .concat8 [ 4 4 0 0], LS_0x8d32390e0_0_0, LS_0x8d32390e0_0_4; -LS_0x8d3239180_0_0 .concat8 [ 1 1 1 1], v0x8d2ced720_0, v0x8d2cf2bc0_0, v0x8d2cfc0a0_0, v0x8d2d01540_0; -LS_0x8d3239180_0_4 .concat8 [ 1 1 1 1], v0x8d2d069e0_0, v0x8d2d0be80_0, v0x8d2d11360_0, v0x8d2d16800_0; -L_0x8d3239180 .concat8 [ 4 4 0 0], LS_0x8d3239180_0_0, LS_0x8d3239180_0_4; -L_0x8d323ce60 .reduce/or L_0x8d32390e0; -L_0x8d323cf00 .reduce/and L_0x8d3239180; -S_0x102e57820 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 4 35, 4 35 0, S_0x102e5b4b0; - .timescale 0 0; -P_0x8d2c3b0c0 .param/l "n" 1 4 35, +C4<00>; -S_0x102e579a0 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x102e57820; +P_0x84b130a00 .param/l "ACC_WIDTH" 0 12 6, +C4<00000000000000000000000000100000>; +P_0x84b130a40 .param/l "DATA_WIDTH" 0 12 2, +C4<00000000000000000000000000001000>; +P_0x84b130a80 .param/l "N_INPUTS" 0 12 3, +C4<00000000000000000000000000100000>; +P_0x84b130ac0 .param/l "N_NEURONS" 0 12 4, +C4<00000000000000000000000000001000>; +P_0x84b130b00 .param/l "PARALLEL" 0 12 5, +C4<00000000000000000000000000001000>; +v0x84b191180_0 .net/s "bias_bus", 63 0, v0x84b191860_0; 1 drivers +v0x84b191220_0 .net "busy", 0 0, L_0x84aee9d60; alias, 1 drivers +v0x84b1912c0_0 .net "clk", 0 0, v0x84b1919a0_0; 1 drivers +v0x84b191360_0 .net "done", 0 0, L_0x84aee9e00; alias, 1 drivers +v0x84b191400_0 .net "neuron_busy", 7 0, L_0x84b1a4500; 1 drivers +v0x84b1914a0_0 .net "neuron_done", 7 0, L_0x84b1a45a0; 1 drivers +v0x84b191540_0 .net "rst", 0 0, v0x84b191c20_0; 1 drivers +v0x84b1915e0_0 .net "start", 0 0, v0x84b191cc0_0; 1 drivers +v0x84b191680_0 .net/s "weights_bus", 2047 0, v0x84b191d60_0; 1 drivers +v0x84b191720_0 .net/s "x_bus", 255 0, v0x84b191e00_0; 1 drivers +v0x84b1917c0_0 .net/s "y_bus", 63 0, L_0x84b1a43c0; alias, 1 drivers +L_0x84ae3bca0 .part v0x84b191d60_0, 0, 256; +L_0x84ae3bd40 .part v0x84b191860_0, 0, 8; +L_0x84aeccd20 .part v0x84b191d60_0, 256, 256; +L_0x84aeccdc0 .part v0x84b191860_0, 8, 8; +L_0x84aece4e0 .part v0x84b191d60_0, 512, 256; +L_0x84aece580 .part v0x84b191860_0, 16, 8; +L_0x84aecfca0 .part v0x84b191d60_0, 768, 256; +L_0x84aecfd40 .part v0x84b191860_0, 24, 8; +L_0x84aee14a0 .part v0x84b191d60_0, 1024, 256; +L_0x84aee1540 .part v0x84b191860_0, 32, 8; +L_0x84aee2c60 .part v0x84b191d60_0, 1280, 256; +L_0x84aee2d00 .part v0x84b191860_0, 40, 8; +L_0x84aee8460 .part v0x84b191d60_0, 1536, 256; +L_0x84aee8500 .part v0x84b191860_0, 48, 8; +L_0x84aee9c20 .part v0x84b191d60_0, 1792, 256; +L_0x84aee9cc0 .part v0x84b191860_0, 56, 8; +LS_0x84b1a43c0_0_0 .concat8 [ 8 8 8 8], v0x84b169360_0, v0x84b16dc20_0, v0x84b1724e0_0, v0x84b176da0_0; +LS_0x84b1a43c0_0_4 .concat8 [ 8 8 8 8], v0x84b17f660_0, v0x84b183f20_0, v0x84b18c820_0, v0x84b1910e0_0; +L_0x84b1a43c0 .concat8 [ 32 32 0 0], LS_0x84b1a43c0_0_0, LS_0x84b1a43c0_0_4; +LS_0x84b1a4500_0_0 .concat8 [ 1 1 1 1], v0x84b168c80_0, v0x84b16d540_0, v0x84b171e00_0, v0x84b1766c0_0; +LS_0x84b1a4500_0_4 .concat8 [ 1 1 1 1], v0x84b17ef80_0, v0x84b183840_0, v0x84b18c140_0, v0x84b190a00_0; +L_0x84b1a4500 .concat8 [ 4 4 0 0], LS_0x84b1a4500_0_0, LS_0x84b1a4500_0_4; +LS_0x84b1a45a0_0_0 .concat8 [ 1 1 1 1], v0x84b168dc0_0, v0x84b16d680_0, v0x84b171f40_0, v0x84b176800_0; +LS_0x84b1a45a0_0_4 .concat8 [ 1 1 1 1], v0x84b17f0c0_0, v0x84b183980_0, v0x84b18c280_0, v0x84b190b40_0; +L_0x84b1a45a0 .concat8 [ 4 4 0 0], LS_0x84b1a45a0_0_0, LS_0x84b1a45a0_0_4; +L_0x84aee9d60 .reduce/or L_0x84b1a4500; +L_0x84aee9e00 .reduce/and L_0x84b1a45a0; +S_0x84ae85c80 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 12 34, 12 34 0, S_0x84ae85b00; .timescale 0 0; +P_0x84b1511c0 .param/l "n" 1 12 34, +C4<00>; +S_0x84ae85e00 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84ae85c80; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e50910 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e50950 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e50990 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e509d0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e50a10 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e50a50 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e50a90 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c150 .functor BUFZ 16, L_0x8d321c5a0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2cec780_0 .net *"_ivl_0", 31 0, L_0x8d30c3e80; 1 drivers -v0x8d2cec820_0 .net *"_ivl_11", 31 0, L_0x8d2d17e80; 1 drivers -v0x8d2cec8c0_0 .net *"_ivl_14", 31 0, L_0x8d30c3f20; 1 drivers -L_0x8d28540e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cec960_0 .net *"_ivl_17", 28 0, L_0x8d28540e8; 1 drivers -L_0x8d2854130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2ceca00_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854130; 1 drivers -v0x8d2cecaa0_0 .net *"_ivl_21", 31 0, L_0x8d2d17f20; 1 drivers -L_0x8d2854178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2cecb40_0 .net/2u *"_ivl_22", 31 0, L_0x8d2854178; 1 drivers -v0x8d2cecbe0_0 .net *"_ivl_25", 31 0, L_0x8d2d18000; 1 drivers -L_0x8d2854010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cecc80_0 .net *"_ivl_3", 28 0, L_0x8d2854010; 1 drivers -v0x8d2cecd20_0 .net *"_ivl_31", 0 0, L_0x8d321c320; 1 drivers -v0x8d2cecdc0_0 .net *"_ivl_33", 23 0, L_0x8d2d194a0; 1 drivers -v0x8d2cece60_0 .net *"_ivl_36", 39 0, L_0x8d3194fa0; 1 drivers -v0x8d2cecf00_0 .net *"_ivl_38", 31 0, L_0x8d321c3c0; 1 drivers -L_0x8d2854058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2cecfa0_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854058; 1 drivers -L_0x8d2854400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2ced040_0 .net *"_ivl_40", 7 0, L_0x8d2854400; 1 drivers -v0x8d2ced0e0_0 .net *"_ivl_46", 31 0, L_0x8d321c460; 1 drivers -v0x8d2ced180_0 .net *"_ivl_7", 31 0, L_0x8d2d17de0; 1 drivers -L_0x8d28540a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2ced220_0 .net/2u *"_ivl_8", 31 0, L_0x8d28540a0; 1 drivers -v0x8d2ced2c0_0 .var/s "acc", 39 0; -v0x8d2ced360_0 .net/s "acc_next", 39 0, L_0x8d3194e60; 1 drivers -v0x8d2ced400_0 .net/s "bias", 15 0, L_0x8d321c5a0; 1 drivers -v0x8d2ced4a0_0 .net/s "bias_ext", 39 0, L_0x8d3194f00; 1 drivers -v0x8d2ced540_0 .net/s "bias_ext_small", 15 0, L_0x8d307c150; 1 drivers -v0x8d2ced5e0_0 .var "busy", 0 0; -v0x8d2ced680_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2ced720_0 .var "done", 0 0; -v0x8d2ced7c0_0 .net/s "final_acc", 39 0, L_0x8d3195040; 1 drivers -v0x8d2ced860_0 .net/s "final_value", 39 0, L_0x8d2d19540; 1 drivers -v0x8d2ced900_0 .var "group_index", 2 0; -v0x8d2ced9a0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2ceda40_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2cedae0_0 .net/s "w_bus", 1023 0, L_0x8d321c500; 1 drivers -v0x8d2cedb80_0 .net/s "w_group", 127 0, L_0x8d318b5c0; 1 drivers -v0x8d2cedc20_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2cedcc0_0 .net/s "x_group", 127 0, L_0x8d318b8e0; 1 drivers -v0x8d2cedd60_0 .var/s "y", 15 0; -E_0x8d2ce4340 .event posedge, v0x8d2ced680_0; -L_0x8d30c3e80 .concat [ 3 29 0 0], v0x8d2ced900_0, L_0x8d2854010; -L_0x8d2d17de0 .arith/mult 32, L_0x8d30c3e80, L_0x8d2854058; -L_0x8d2d17e80 .arith/mult 32, L_0x8d2d17de0, L_0x8d28540a0; -L_0x8d318b8e0 .part/v v0x8d2d17ca0_0, L_0x8d2d17e80, 128; -L_0x8d30c3f20 .concat [ 3 29 0 0], v0x8d2ced900_0, L_0x8d28540e8; -L_0x8d2d17f20 .arith/mult 32, L_0x8d30c3f20, L_0x8d2854130; -L_0x8d2d18000 .arith/mult 32, L_0x8d2d17f20, L_0x8d2854178; -L_0x8d318b5c0 .part/v L_0x8d321c500, L_0x8d2d18000, 128; -L_0x8d321c320 .part L_0x8d307c150, 15, 1; -L_0x8d2d194a0 .repeat 24, 24, L_0x8d321c320; -L_0x8d3194f00 .concat [ 16 24 0 0], L_0x8d307c150, L_0x8d2d194a0; -L_0x8d321c3c0 .part L_0x8d3194f00, 0, 32; -L_0x8d3194fa0 .concat [ 8 32 0 0], L_0x8d2854400, L_0x8d321c3c0; -L_0x8d3195040 .arith/sum 40, L_0x8d3194e60, L_0x8d3194fa0; -L_0x8d321c460 .part L_0x8d3195040, 8, 32; -L_0x8d2d19540 .extend/s 40, L_0x8d321c460; -S_0x102e52fe0 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x102e579a0; +P_0x84ae85f80 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84ae85fc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84ae86000 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84ae86040 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84ae86080 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84ae860c0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b168140_0 .net *"_ivl_0", 31 0, L_0x84b193ac0; 1 drivers +v0x84b1681e0_0 .net *"_ivl_11", 31 0, L_0x84b193c00; 1 drivers +v0x84b168280_0 .net *"_ivl_14", 31 0, L_0x84b193ca0; 1 drivers +L_0x84a878568 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b168320_0 .net *"_ivl_17", 29 0, L_0x84a878568; 1 drivers +L_0x84a8785b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1683c0_0 .net/2u *"_ivl_18", 31 0, L_0x84a8785b0; 1 drivers +v0x84b168460_0 .net *"_ivl_21", 31 0, L_0x84b193d40; 1 drivers +L_0x84a8785f8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b168500_0 .net/2u *"_ivl_22", 31 0, L_0x84a8785f8; 1 drivers +v0x84b1685a0_0 .net *"_ivl_25", 31 0, L_0x84b193de0; 1 drivers +v0x84b168640_0 .net *"_ivl_29", 0 0, L_0x84ae3bb60; 1 drivers +L_0x84a878490 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1686e0_0 .net *"_ivl_3", 29 0, L_0x84a878490; 1 drivers +v0x84b168780_0 .net *"_ivl_31", 23 0, L_0x84ae3bc00; 1 drivers +L_0x84a8784d8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b168820_0 .net/2u *"_ivl_4", 31 0, L_0x84a8784d8; 1 drivers +v0x84b1688c0_0 .net *"_ivl_7", 31 0, L_0x84b193b60; 1 drivers +L_0x84a878520 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b168960_0 .net/2u *"_ivl_8", 31 0, L_0x84a878520; 1 drivers +v0x84b168a00_0 .var/s "acc", 31 0; +v0x84b168aa0_0 .net/s "acc_next", 31 0, L_0x84ac8af80; 1 drivers +v0x84b168b40_0 .net/s "bias", 7 0, L_0x84ae3bd40; 1 drivers +v0x84b168be0_0 .net/s "bias_ext", 31 0, L_0x84b195360; 1 drivers +v0x84b168c80_0 .var "busy", 0 0; +v0x84b168d20_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b168dc0_0 .var "done", 0 0; +v0x84b168e60_0 .net/s "final_acc", 31 0, L_0x84ac8b020; 1 drivers +v0x84b168f00_0 .var "group_index", 1 0; +v0x84b168fa0_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b169040_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b1690e0_0 .net/s "w_bus", 255 0, L_0x84ae3bca0; 1 drivers +v0x84b169180_0 .net/s "w_group", 63 0, L_0x84ae3a6c0; 1 drivers +v0x84b169220_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b1692c0_0 .net/s "x_group", 63 0, L_0x84ae3a620; 1 drivers +v0x84b169360_0 .var/s "y", 7 0; +E_0x84ae46680 .event posedge, v0x84b168d20_0; +L_0x84b193ac0 .concat [ 2 30 0 0], v0x84b168f00_0, L_0x84a878490; +L_0x84b193b60 .arith/mult 32, L_0x84b193ac0, L_0x84a8784d8; +L_0x84b193c00 .arith/mult 32, L_0x84b193b60, L_0x84a878520; +L_0x84ae3a620 .part/v v0x84b191e00_0, L_0x84b193c00, 64; +L_0x84b193ca0 .concat [ 2 30 0 0], v0x84b168f00_0, L_0x84a878568; +L_0x84b193d40 .arith/mult 32, L_0x84b193ca0, L_0x84a8785b0; +L_0x84b193de0 .arith/mult 32, L_0x84b193d40, L_0x84a8785f8; +L_0x84ae3a6c0 .part/v L_0x84ae3bca0, L_0x84b193de0, 64; +L_0x84ae3bb60 .part L_0x84ae3bd40, 7, 1; +L_0x84ae3bc00 .repeat 24, 24, L_0x84ae3bb60; +L_0x84b195360 .concat [ 8 24 0 0], L_0x84ae3bd40, L_0x84ae3bc00; +L_0x84ac8b020 .arith/sum 32, L_0x84ac8af80, L_0x84b195360; +S_0x84ae86100 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84ae85e00; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a0640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2c9bb60_0 .net/s "acc_in", 39 0, v0x8d2ced2c0_0; 1 drivers -v0x8d2c9bc00_0 .net/s "acc_out", 39 0, L_0x8d3194e60; alias, 1 drivers -v0x8d2c9bca0_0 .net/s "m0", 39 0, L_0x8d31940a0; 1 drivers -v0x8d2c9bd40_0 .net/s "m1", 39 0, L_0x8d31941e0; 1 drivers -v0x8d2c9bde0_0 .net/s "m2", 39 0, L_0x8d3194320; 1 drivers -v0x8d2c9be80_0 .net/s "m3", 39 0, L_0x8d3194460; 1 drivers -v0x8d2c9bf20_0 .net/s "m4", 39 0, L_0x8d31945a0; 1 drivers -v0x8d2cec000_0 .net/s "m5", 39 0, L_0x8d31946e0; 1 drivers -v0x8d2cec0a0_0 .net/s "m6", 39 0, L_0x8d3194820; 1 drivers -v0x8d2cec140_0 .net/s "m7", 39 0, L_0x8d3194960; 1 drivers -v0x8d2cec1e0_0 .net/s "s0", 39 0, L_0x8d3194a00; 1 drivers -v0x8d2cec280_0 .net/s "s1", 39 0, L_0x8d3194aa0; 1 drivers -v0x8d2cec320_0 .net/s "s2", 39 0, L_0x8d3194b40; 1 drivers -v0x8d2cec3c0_0 .net/s "s3", 39 0, L_0x8d3194be0; 1 drivers -v0x8d2cec460_0 .net/s "s4", 39 0, L_0x8d3194c80; 1 drivers -v0x8d2cec500_0 .net/s "s5", 39 0, L_0x8d3194d20; 1 drivers -v0x8d2cec5a0_0 .net/s "sum", 39 0, L_0x8d3194dc0; 1 drivers -v0x8d2cec640_0 .net/s "w_bus", 127 0, L_0x8d318b5c0; alias, 1 drivers -v0x8d2cec6e0_0 .net/s "x_bus", 127 0, L_0x8d318b8e0; alias, 1 drivers -L_0x8d318ba20 .part L_0x8d318b8e0, 0, 16; -L_0x8d318bac0 .part L_0x8d318b5c0, 0, 16; -L_0x8d318bc00 .part L_0x8d318b8e0, 16, 16; -L_0x8d318bca0 .part L_0x8d318b5c0, 16, 16; -L_0x8d318bde0 .part L_0x8d318b8e0, 32, 16; -L_0x8d318be80 .part L_0x8d318b5c0, 32, 16; -L_0x8d3064460 .part L_0x8d318b8e0, 48, 16; -L_0x8d3064500 .part L_0x8d318b5c0, 48, 16; -L_0x8d317b7a0 .part L_0x8d318b8e0, 64, 16; -L_0x8d316f980 .part L_0x8d318b5c0, 64, 16; -L_0x8d313fd40 .part L_0x8d318b8e0, 80, 16; -L_0x8d3137f20 .part L_0x8d318b5c0, 80, 16; -L_0x8d321c000 .part L_0x8d318b8e0, 96, 16; -L_0x8d321c0a0 .part L_0x8d318b5c0, 96, 16; -L_0x8d321c1e0 .part L_0x8d318b8e0, 112, 16; -L_0x8d321c280 .part L_0x8d318b5c0, 112, 16; -L_0x8d3194a00 .arith/sum 40, L_0x8d31940a0, L_0x8d31941e0; -L_0x8d3194aa0 .arith/sum 40, L_0x8d3194320, L_0x8d3194460; -L_0x8d3194b40 .arith/sum 40, L_0x8d31945a0, L_0x8d31946e0; -L_0x8d3194be0 .arith/sum 40, L_0x8d3194820, L_0x8d3194960; -L_0x8d3194c80 .arith/sum 40, L_0x8d3194a00, L_0x8d3194aa0; -L_0x8d3194d20 .arith/sum 40, L_0x8d3194b40, L_0x8d3194be0; -L_0x8d3194dc0 .arith/sum 40, L_0x8d3194c80, L_0x8d3194d20; -L_0x8d3194e60 .arith/sum 40, v0x8d2ced2c0_0, L_0x8d3194dc0; -S_0x102e53160 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x102e52fe0; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8300 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8340 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8380 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc83c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b163d40_0 .net/s "acc_in", 31 0, v0x84b168a00_0; 1 drivers +v0x84b163de0_0 .net/s "acc_out", 31 0, L_0x84ac8af80; alias, 1 drivers +v0x84b163e80 .array "products", 7 0; +v0x84b163e80_0 .net/s v0x84b163e80 0, 31 0, L_0x84ac8a620; 1 drivers +v0x84b163e80_1 .net/s v0x84b163e80 1, 31 0, L_0x84ac8a6c0; 1 drivers +v0x84b163e80_2 .net/s v0x84b163e80 2, 31 0, L_0x84ac8a760; 1 drivers +v0x84b163e80_3 .net/s v0x84b163e80 3, 31 0, L_0x84ac8a800; 1 drivers +v0x84b163e80_4 .net/s v0x84b163e80 4, 31 0, L_0x84ac8a8a0; 1 drivers +v0x84b163e80_5 .net/s v0x84b163e80 5, 31 0, L_0x84ac8a940; 1 drivers +v0x84b163e80_6 .net/s v0x84b163e80 6, 31 0, L_0x84ac8a9e0; 1 drivers +v0x84b163e80_7 .net/s v0x84b163e80 7, 31 0, L_0x84ac8aa80; 1 drivers +v0x84b163f20 .array "tree", 31 0; +v0x84b163f20_0 .net/s v0x84b163f20 0, 31 0, L_0x84ac3f3a0; 1 drivers +v0x84b163f20_1 .net/s v0x84b163f20 1, 31 0, L_0x84ac3f410; 1 drivers +v0x84b163f20_2 .net/s v0x84b163f20 2, 31 0, L_0x84ac3f480; 1 drivers +v0x84b163f20_3 .net/s v0x84b163f20 3, 31 0, L_0x84ac3f4f0; 1 drivers +v0x84b163f20_4 .net/s v0x84b163f20 4, 31 0, L_0x84ac3f560; 1 drivers +v0x84b163f20_5 .net/s v0x84b163f20 5, 31 0, L_0x84ac3f5d0; 1 drivers +v0x84b163f20_6 .net/s v0x84b163f20 6, 31 0, L_0x84ac3f640; 1 drivers +v0x84b163f20_7 .net/s v0x84b163f20 7, 31 0, L_0x84ac3f6b0; 1 drivers +v0x84b163f20_8 .net/s v0x84b163f20 8, 31 0, L_0x84ac8ab20; 1 drivers +v0x84b163f20_9 .net/s v0x84b163f20 9, 31 0, L_0x84ac8abc0; 1 drivers +v0x84b163f20_10 .net/s v0x84b163f20 10, 31 0, L_0x84ac8ac60; 1 drivers +v0x84b163f20_11 .net/s v0x84b163f20 11, 31 0, L_0x84ac8ad00; 1 drivers +o0x84a84b2d0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_12 .net/s v0x84b163f20 12, 31 0, o0x84a84b2d0; 0 drivers +o0x84a84b300 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_13 .net/s v0x84b163f20 13, 31 0, o0x84a84b300; 0 drivers +o0x84a84b330 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_14 .net/s v0x84b163f20 14, 31 0, o0x84a84b330; 0 drivers +o0x84a84b360 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_15 .net/s v0x84b163f20 15, 31 0, o0x84a84b360; 0 drivers +v0x84b163f20_16 .net/s v0x84b163f20 16, 31 0, L_0x84ac8ada0; 1 drivers +v0x84b163f20_17 .net/s v0x84b163f20 17, 31 0, L_0x84ac8ae40; 1 drivers +o0x84a84b3f0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_18 .net/s v0x84b163f20 18, 31 0, o0x84a84b3f0; 0 drivers +o0x84a84b420 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_19 .net/s v0x84b163f20 19, 31 0, o0x84a84b420; 0 drivers +o0x84a84b450 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_20 .net/s v0x84b163f20 20, 31 0, o0x84a84b450; 0 drivers +o0x84a84b480 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_21 .net/s v0x84b163f20 21, 31 0, o0x84a84b480; 0 drivers +o0x84a84b4b0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_22 .net/s v0x84b163f20 22, 31 0, o0x84a84b4b0; 0 drivers +o0x84a84b4e0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_23 .net/s v0x84b163f20 23, 31 0, o0x84a84b4e0; 0 drivers +v0x84b163f20_24 .net/s v0x84b163f20 24, 31 0, L_0x84ac8aee0; 1 drivers +o0x84a84b540 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_25 .net/s v0x84b163f20 25, 31 0, o0x84a84b540; 0 drivers +o0x84a84b570 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_26 .net/s v0x84b163f20 26, 31 0, o0x84a84b570; 0 drivers +o0x84a84b5a0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_27 .net/s v0x84b163f20 27, 31 0, o0x84a84b5a0; 0 drivers +o0x84a84b5d0 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_28 .net/s v0x84b163f20 28, 31 0, o0x84a84b5d0; 0 drivers +o0x84a84b600 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_29 .net/s v0x84b163f20 29, 31 0, o0x84a84b600; 0 drivers +o0x84a84b630 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_30 .net/s v0x84b163f20 30, 31 0, o0x84a84b630; 0 drivers +o0x84a84b660 .functor BUFZ 32, c4; HiZ drive +v0x84b163f20_31 .net/s v0x84b163f20 31, 31 0, o0x84a84b660; 0 drivers +v0x84b168000_0 .net/s "w_bus", 63 0, L_0x84ae3a6c0; alias, 1 drivers +v0x84b1680a0_0 .net/s "x_bus", 63 0, L_0x84ae3a620; alias, 1 drivers +L_0x84ae3a8a0 .part L_0x84ae3a620, 0, 8; +L_0x84ae3a940 .part L_0x84ae3a6c0, 0, 8; +L_0x84ae3ab20 .part L_0x84ae3a620, 8, 8; +L_0x84ae3abc0 .part L_0x84ae3a6c0, 8, 8; +L_0x84ae3ada0 .part L_0x84ae3a620, 16, 8; +L_0x84ae3ae40 .part L_0x84ae3a6c0, 16, 8; +L_0x84ae3b020 .part L_0x84ae3a620, 24, 8; +L_0x84ae3b0c0 .part L_0x84ae3a6c0, 24, 8; +L_0x84ae3b2a0 .part L_0x84ae3a620, 32, 8; +L_0x84ae3b340 .part L_0x84ae3a6c0, 32, 8; +L_0x84ae3b520 .part L_0x84ae3a620, 40, 8; +L_0x84ae3b5c0 .part L_0x84ae3a6c0, 40, 8; +L_0x84ae3b7a0 .part L_0x84ae3a620, 48, 8; +L_0x84ae3b840 .part L_0x84ae3a6c0, 48, 8; +L_0x84ae3ba20 .part L_0x84ae3a620, 56, 8; +L_0x84ae3bac0 .part L_0x84ae3a6c0, 56, 8; +L_0x84ac8af80 .arith/sum 32, v0x84b168a00_0, L_0x84ac8aee0; +S_0x84ae86280 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84ae86100; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c0c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c98960_0 .net/s *"_ivl_0", 31 0, L_0x8d2d180a0; 1 drivers -v0x8d2c98a00_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18140; 1 drivers -v0x8d2c98aa0_0 .net *"_ivl_7", 0 0, L_0x8d318b980; 1 drivers -v0x8d2c98b40_0 .net *"_ivl_9", 7 0, L_0x8d2d18280; 1 drivers -L_0x8d28541c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c98be0_0 .net/s "acc_in", 39 0, L_0x8d28541c0; 1 drivers -v0x8d2c98c80_0 .net/s "acc_out", 39 0, L_0x8d31940a0; alias, 1 drivers -v0x8d2c98d20_0 .net/s "product", 31 0, L_0x8d2d181e0; 1 drivers -v0x8d2c98dc0_0 .net/s "product_ext", 39 0, L_0x8d3194000; 1 drivers -v0x8d2c98e60_0 .net/s "w", 15 0, L_0x8d318bac0; 1 drivers -v0x8d2c98f00_0 .net/s "x", 15 0, L_0x8d318ba20; 1 drivers -L_0x8d2d180a0 .extend/s 32, L_0x8d318ba20; -L_0x8d2d18140 .extend/s 32, L_0x8d318bac0; -L_0x8d2d181e0 .arith/mult 32, L_0x8d2d180a0, L_0x8d2d18140; -L_0x8d318b980 .part L_0x8d2d181e0, 31, 1; -L_0x8d2d18280 .repeat 8, 8, L_0x8d318b980; -L_0x8d3194000 .concat [ 32 8 0 0], L_0x8d2d181e0, L_0x8d2d18280; -L_0x8d31940a0 .arith/sum 40, L_0x8d28541c0, L_0x8d3194000; -S_0x102e5aa50 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x102e52fe0; +P_0x84b151200 .param/l "i" 1 8 20, +C4<00>; +S_0x84ae86400 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae86280; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c1c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c98fa0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18320; 1 drivers -v0x8d2c99040_0 .net/s *"_ivl_2", 31 0, L_0x8d2d183c0; 1 drivers -v0x8d2c990e0_0 .net *"_ivl_7", 0 0, L_0x8d318bb60; 1 drivers -v0x8d2c99180_0 .net *"_ivl_9", 7 0, L_0x8d2d18500; 1 drivers -L_0x8d2854208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c99220_0 .net/s "acc_in", 39 0, L_0x8d2854208; 1 drivers -v0x8d2c992c0_0 .net/s "acc_out", 39 0, L_0x8d31941e0; alias, 1 drivers -v0x8d2c99360_0 .net/s "product", 31 0, L_0x8d2d18460; 1 drivers -v0x8d2c99400_0 .net/s "product_ext", 39 0, L_0x8d3194140; 1 drivers -v0x8d2c994a0_0 .net/s "w", 15 0, L_0x8d318bca0; 1 drivers -v0x8d2c99540_0 .net/s "x", 15 0, L_0x8d318bc00; 1 drivers -L_0x8d2d18320 .extend/s 32, L_0x8d318bc00; -L_0x8d2d183c0 .extend/s 32, L_0x8d318bca0; -L_0x8d2d18460 .arith/mult 32, L_0x8d2d18320, L_0x8d2d183c0; -L_0x8d318bb60 .part L_0x8d2d18460, 31, 1; -L_0x8d2d18500 .repeat 8, 8, L_0x8d318bb60; -L_0x8d3194140 .concat [ 32 8 0 0], L_0x8d2d18460, L_0x8d2d18500; -L_0x8d31941e0 .arith/sum 40, L_0x8d2854208, L_0x8d3194140; -S_0x102e5abd0 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x102e52fe0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1583c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158400 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158440 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b160b40_0 .net/s *"_ivl_0", 15 0, L_0x84b193e80; 1 drivers +v0x84b160be0_0 .net/s *"_ivl_2", 15 0, L_0x84b193f20; 1 drivers +v0x84b160c80_0 .net *"_ivl_7", 0 0, L_0x84ae3a760; 1 drivers +v0x84b160d20_0 .net *"_ivl_9", 15 0, L_0x84ae3a800; 1 drivers +L_0x84a878640 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b160dc0_0 .net/s "acc_in", 31 0, L_0x84a878640; 1 drivers +v0x84b160e60_0 .net/s "acc_out", 31 0, L_0x84ac8a620; alias, 1 drivers +v0x84b160f00_0 .net/s "product", 15 0, L_0x84b194000; 1 drivers +v0x84b160fa0_0 .net/s "product_ext", 31 0, L_0x84b1940a0; 1 drivers +v0x84b161040_0 .net/s "w", 7 0, L_0x84ae3a940; 1 drivers +v0x84b1610e0_0 .net/s "x", 7 0, L_0x84ae3a8a0; 1 drivers +L_0x84b193e80 .extend/s 16, L_0x84ae3a8a0; +L_0x84b193f20 .extend/s 16, L_0x84ae3a940; +L_0x84b194000 .arith/mult 16, L_0x84b193e80, L_0x84b193f20; +L_0x84ae3a760 .part L_0x84b194000, 15, 1; +L_0x84ae3a800 .repeat 16, 16, L_0x84ae3a760; +L_0x84b1940a0 .concat [ 16 16 0 0], L_0x84b194000, L_0x84ae3a800; +L_0x84ac8a620 .arith/sum 32, L_0x84a878640, L_0x84b1940a0; +S_0x84ae86580 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84ae86100; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c2c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c995e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d185a0; 1 drivers -v0x8d2c99680_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18640; 1 drivers -v0x8d2c99720_0 .net *"_ivl_7", 0 0, L_0x8d318bd40; 1 drivers -v0x8d2c997c0_0 .net *"_ivl_9", 7 0, L_0x8d2d18780; 1 drivers -L_0x8d2854250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c99860_0 .net/s "acc_in", 39 0, L_0x8d2854250; 1 drivers -v0x8d2c99900_0 .net/s "acc_out", 39 0, L_0x8d3194320; alias, 1 drivers -v0x8d2c999a0_0 .net/s "product", 31 0, L_0x8d2d186e0; 1 drivers -v0x8d2c99a40_0 .net/s "product_ext", 39 0, L_0x8d3194280; 1 drivers -v0x8d2c99ae0_0 .net/s "w", 15 0, L_0x8d318be80; 1 drivers -v0x8d2c99b80_0 .net/s "x", 15 0, L_0x8d318bde0; 1 drivers -L_0x8d2d185a0 .extend/s 32, L_0x8d318bde0; -L_0x8d2d18640 .extend/s 32, L_0x8d318be80; -L_0x8d2d186e0 .arith/mult 32, L_0x8d2d185a0, L_0x8d2d18640; -L_0x8d318bd40 .part L_0x8d2d186e0, 31, 1; -L_0x8d2d18780 .repeat 8, 8, L_0x8d318bd40; -L_0x8d3194280 .concat [ 32 8 0 0], L_0x8d2d186e0, L_0x8d2d18780; -L_0x8d3194320 .arith/sum 40, L_0x8d2854250, L_0x8d3194280; -S_0x102e65950 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x102e52fe0; +P_0x84b151240 .param/l "i" 1 8 20, +C4<01>; +S_0x84ae86700 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae86580; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c99c20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18820; 1 drivers -v0x8d2c99cc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d188c0; 1 drivers -v0x8d2c99d60_0 .net *"_ivl_7", 0 0, L_0x8d318bf20; 1 drivers -v0x8d2c99e00_0 .net *"_ivl_9", 7 0, L_0x8d2d18a00; 1 drivers -L_0x8d2854298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c99ea0_0 .net/s "acc_in", 39 0, L_0x8d2854298; 1 drivers -v0x8d2c99f40_0 .net/s "acc_out", 39 0, L_0x8d3194460; alias, 1 drivers -v0x8d2c99fe0_0 .net/s "product", 31 0, L_0x8d2d18960; 1 drivers -v0x8d2c9a080_0 .net/s "product_ext", 39 0, L_0x8d31943c0; 1 drivers -v0x8d2c9a120_0 .net/s "w", 15 0, L_0x8d3064500; 1 drivers -v0x8d2c9a1c0_0 .net/s "x", 15 0, L_0x8d3064460; 1 drivers -L_0x8d2d18820 .extend/s 32, L_0x8d3064460; -L_0x8d2d188c0 .extend/s 32, L_0x8d3064500; -L_0x8d2d18960 .arith/mult 32, L_0x8d2d18820, L_0x8d2d188c0; -L_0x8d318bf20 .part L_0x8d2d18960, 31, 1; -L_0x8d2d18a00 .repeat 8, 8, L_0x8d318bf20; -L_0x8d31943c0 .concat [ 32 8 0 0], L_0x8d2d18960, L_0x8d2d18a00; -L_0x8d3194460 .arith/sum 40, L_0x8d2854298, L_0x8d31943c0; -S_0x8d31fc000 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x102e52fe0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158480 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1584c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158500 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b161180_0 .net/s *"_ivl_0", 15 0, L_0x84b194140; 1 drivers +v0x84b161220_0 .net/s *"_ivl_2", 15 0, L_0x84b1941e0; 1 drivers +v0x84b1612c0_0 .net *"_ivl_7", 0 0, L_0x84ae3a9e0; 1 drivers +v0x84b161360_0 .net *"_ivl_9", 15 0, L_0x84ae3aa80; 1 drivers +L_0x84a878688 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b161400_0 .net/s "acc_in", 31 0, L_0x84a878688; 1 drivers +v0x84b1614a0_0 .net/s "acc_out", 31 0, L_0x84ac8a6c0; alias, 1 drivers +v0x84b161540_0 .net/s "product", 15 0, L_0x84b194280; 1 drivers +v0x84b1615e0_0 .net/s "product_ext", 31 0, L_0x84b194320; 1 drivers +v0x84b161680_0 .net/s "w", 7 0, L_0x84ae3abc0; 1 drivers +v0x84b161720_0 .net/s "x", 7 0, L_0x84ae3ab20; 1 drivers +L_0x84b194140 .extend/s 16, L_0x84ae3ab20; +L_0x84b1941e0 .extend/s 16, L_0x84ae3abc0; +L_0x84b194280 .arith/mult 16, L_0x84b194140, L_0x84b1941e0; +L_0x84ae3a9e0 .part L_0x84b194280, 15, 1; +L_0x84ae3aa80 .repeat 16, 16, L_0x84ae3a9e0; +L_0x84b194320 .concat [ 16 16 0 0], L_0x84b194280, L_0x84ae3aa80; +L_0x84ac8a6c0 .arith/sum 32, L_0x84a878688, L_0x84b194320; +S_0x84ae86880 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84ae86100; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c3c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c9a260_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18aa0; 1 drivers -v0x8d2c9a300_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18b40; 1 drivers -v0x8d2c9a3a0_0 .net *"_ivl_7", 0 0, L_0x8d3064640; 1 drivers -v0x8d2c9a440_0 .net *"_ivl_9", 7 0, L_0x8d2d18c80; 1 drivers -L_0x8d28542e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c9a4e0_0 .net/s "acc_in", 39 0, L_0x8d28542e0; 1 drivers -v0x8d2c9a580_0 .net/s "acc_out", 39 0, L_0x8d31945a0; alias, 1 drivers -v0x8d2c9a620_0 .net/s "product", 31 0, L_0x8d2d18be0; 1 drivers -v0x8d2c9a6c0_0 .net/s "product_ext", 39 0, L_0x8d3194500; 1 drivers -v0x8d2c9a760_0 .net/s "w", 15 0, L_0x8d316f980; 1 drivers -v0x8d2c9a800_0 .net/s "x", 15 0, L_0x8d317b7a0; 1 drivers -L_0x8d2d18aa0 .extend/s 32, L_0x8d317b7a0; -L_0x8d2d18b40 .extend/s 32, L_0x8d316f980; -L_0x8d2d18be0 .arith/mult 32, L_0x8d2d18aa0, L_0x8d2d18b40; -L_0x8d3064640 .part L_0x8d2d18be0, 31, 1; -L_0x8d2d18c80 .repeat 8, 8, L_0x8d3064640; -L_0x8d3194500 .concat [ 32 8 0 0], L_0x8d2d18be0, L_0x8d2d18c80; -L_0x8d31945a0 .arith/sum 40, L_0x8d28542e0, L_0x8d3194500; -S_0x8d31fc180 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x102e52fe0; +P_0x84b151280 .param/l "i" 1 8 20, +C4<010>; +S_0x84ae86a00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae86880; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c4c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c9a8a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18d20; 1 drivers -v0x8d2c9a940_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18dc0; 1 drivers -v0x8d2c9a9e0_0 .net *"_ivl_7", 0 0, L_0x8d315fb60; 1 drivers -v0x8d2c9aa80_0 .net *"_ivl_9", 7 0, L_0x8d2d18f00; 1 drivers -L_0x8d2854328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c9ab20_0 .net/s "acc_in", 39 0, L_0x8d2854328; 1 drivers -v0x8d2c9abc0_0 .net/s "acc_out", 39 0, L_0x8d31946e0; alias, 1 drivers -v0x8d2c9ac60_0 .net/s "product", 31 0, L_0x8d2d18e60; 1 drivers -v0x8d2c9ad00_0 .net/s "product_ext", 39 0, L_0x8d3194640; 1 drivers -v0x8d2c9ada0_0 .net/s "w", 15 0, L_0x8d3137f20; 1 drivers -v0x8d2c9ae40_0 .net/s "x", 15 0, L_0x8d313fd40; 1 drivers -L_0x8d2d18d20 .extend/s 32, L_0x8d313fd40; -L_0x8d2d18dc0 .extend/s 32, L_0x8d3137f20; -L_0x8d2d18e60 .arith/mult 32, L_0x8d2d18d20, L_0x8d2d18dc0; -L_0x8d315fb60 .part L_0x8d2d18e60, 31, 1; -L_0x8d2d18f00 .repeat 8, 8, L_0x8d315fb60; -L_0x8d3194640 .concat [ 32 8 0 0], L_0x8d2d18e60, L_0x8d2d18f00; -L_0x8d31946e0 .arith/sum 40, L_0x8d2854328, L_0x8d3194640; -S_0x8d31fc300 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x102e52fe0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158540 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158580 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1585c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1617c0_0 .net/s *"_ivl_0", 15 0, L_0x84b1943c0; 1 drivers +v0x84b161860_0 .net/s *"_ivl_2", 15 0, L_0x84b194460; 1 drivers +v0x84b161900_0 .net *"_ivl_7", 0 0, L_0x84ae3ac60; 1 drivers +v0x84b1619a0_0 .net *"_ivl_9", 15 0, L_0x84ae3ad00; 1 drivers +L_0x84a8786d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b161a40_0 .net/s "acc_in", 31 0, L_0x84a8786d0; 1 drivers +v0x84b161ae0_0 .net/s "acc_out", 31 0, L_0x84ac8a760; alias, 1 drivers +v0x84b161b80_0 .net/s "product", 15 0, L_0x84b194500; 1 drivers +v0x84b161c20_0 .net/s "product_ext", 31 0, L_0x84b1945a0; 1 drivers +v0x84b161cc0_0 .net/s "w", 7 0, L_0x84ae3ae40; 1 drivers +v0x84b161d60_0 .net/s "x", 7 0, L_0x84ae3ada0; 1 drivers +L_0x84b1943c0 .extend/s 16, L_0x84ae3ada0; +L_0x84b194460 .extend/s 16, L_0x84ae3ae40; +L_0x84b194500 .arith/mult 16, L_0x84b1943c0, L_0x84b194460; +L_0x84ae3ac60 .part L_0x84b194500, 15, 1; +L_0x84ae3ad00 .repeat 16, 16, L_0x84ae3ac60; +L_0x84b1945a0 .concat [ 16 16 0 0], L_0x84b194500, L_0x84ae3ad00; +L_0x84ac8a760 .arith/sum 32, L_0x84a8786d0, L_0x84b1945a0; +S_0x84ae86b80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84ae86100; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c5c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c9aee0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18fa0; 1 drivers -v0x8d2c9af80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19040; 1 drivers -v0x8d2c9b020_0 .net *"_ivl_7", 0 0, L_0x8d3134140; 1 drivers -v0x8d2c9b0c0_0 .net *"_ivl_9", 7 0, L_0x8d2d19180; 1 drivers -L_0x8d2854370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c9b160_0 .net/s "acc_in", 39 0, L_0x8d2854370; 1 drivers -v0x8d2c9b200_0 .net/s "acc_out", 39 0, L_0x8d3194820; alias, 1 drivers -v0x8d2c9b2a0_0 .net/s "product", 31 0, L_0x8d2d190e0; 1 drivers -v0x8d2c9b340_0 .net/s "product_ext", 39 0, L_0x8d3194780; 1 drivers -v0x8d2c9b3e0_0 .net/s "w", 15 0, L_0x8d321c0a0; 1 drivers -v0x8d2c9b480_0 .net/s "x", 15 0, L_0x8d321c000; 1 drivers -L_0x8d2d18fa0 .extend/s 32, L_0x8d321c000; -L_0x8d2d19040 .extend/s 32, L_0x8d321c0a0; -L_0x8d2d190e0 .arith/mult 32, L_0x8d2d18fa0, L_0x8d2d19040; -L_0x8d3134140 .part L_0x8d2d190e0, 31, 1; -L_0x8d2d19180 .repeat 8, 8, L_0x8d3134140; -L_0x8d3194780 .concat [ 32 8 0 0], L_0x8d2d190e0, L_0x8d2d19180; -L_0x8d3194820 .arith/sum 40, L_0x8d2854370, L_0x8d3194780; -S_0x8d31fc480 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x102e52fe0; +P_0x84b1512c0 .param/l "i" 1 8 20, +C4<011>; +S_0x84ae86d00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae86b80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c600 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c640 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c680 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2c9b520_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19220; 1 drivers -v0x8d2c9b5c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d192c0; 1 drivers -v0x8d2c9b660_0 .net *"_ivl_7", 0 0, L_0x8d321c140; 1 drivers -v0x8d2c9b700_0 .net *"_ivl_9", 7 0, L_0x8d2d19400; 1 drivers -L_0x8d28543b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2c9b7a0_0 .net/s "acc_in", 39 0, L_0x8d28543b8; 1 drivers -v0x8d2c9b840_0 .net/s "acc_out", 39 0, L_0x8d3194960; alias, 1 drivers -v0x8d2c9b8e0_0 .net/s "product", 31 0, L_0x8d2d19360; 1 drivers -v0x8d2c9b980_0 .net/s "product_ext", 39 0, L_0x8d31948c0; 1 drivers -v0x8d2c9ba20_0 .net/s "w", 15 0, L_0x8d321c280; 1 drivers -v0x8d2c9bac0_0 .net/s "x", 15 0, L_0x8d321c1e0; 1 drivers -L_0x8d2d19220 .extend/s 32, L_0x8d321c1e0; -L_0x8d2d192c0 .extend/s 32, L_0x8d321c280; -L_0x8d2d19360 .arith/mult 32, L_0x8d2d19220, L_0x8d2d192c0; -L_0x8d321c140 .part L_0x8d2d19360, 31, 1; -L_0x8d2d19400 .repeat 8, 8, L_0x8d321c140; -L_0x8d31948c0 .concat [ 32 8 0 0], L_0x8d2d19360, L_0x8d2d19400; -L_0x8d3194960 .arith/sum 40, L_0x8d28543b8, L_0x8d31948c0; -S_0x8d31fc600 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158600 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158640 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158680 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b161e00_0 .net/s *"_ivl_0", 15 0, L_0x84b194640; 1 drivers +v0x84b161ea0_0 .net/s *"_ivl_2", 15 0, L_0x84b1946e0; 1 drivers +v0x84b161f40_0 .net *"_ivl_7", 0 0, L_0x84ae3aee0; 1 drivers +v0x84b161fe0_0 .net *"_ivl_9", 15 0, L_0x84ae3af80; 1 drivers +L_0x84a878718 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b162080_0 .net/s "acc_in", 31 0, L_0x84a878718; 1 drivers +v0x84b162120_0 .net/s "acc_out", 31 0, L_0x84ac8a800; alias, 1 drivers +v0x84b1621c0_0 .net/s "product", 15 0, L_0x84b194780; 1 drivers +v0x84b162260_0 .net/s "product_ext", 31 0, L_0x84b194820; 1 drivers +v0x84b162300_0 .net/s "w", 7 0, L_0x84ae3b0c0; 1 drivers +v0x84b1623a0_0 .net/s "x", 7 0, L_0x84ae3b020; 1 drivers +L_0x84b194640 .extend/s 16, L_0x84ae3b020; +L_0x84b1946e0 .extend/s 16, L_0x84ae3b0c0; +L_0x84b194780 .arith/mult 16, L_0x84b194640, L_0x84b1946e0; +L_0x84ae3aee0 .part L_0x84b194780, 15, 1; +L_0x84ae3af80 .repeat 16, 16, L_0x84ae3aee0; +L_0x84b194820 .concat [ 16 16 0 0], L_0x84b194780, L_0x84ae3af80; +L_0x84ac8a800 .arith/sum 32, L_0x84a878718, L_0x84b194820; +S_0x84ae86e80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84ae86100; .timescale 0 0; -P_0x8d2c3b100 .param/l "n" 1 4 35, +C4<01>; -S_0x8d31fc780 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fc600; +P_0x84b151300 .param/l "i" 1 8 20, +C4<0100>; +S_0x84ae87000 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae86e80; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1586c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158700 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158740 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b162440_0 .net/s *"_ivl_0", 15 0, L_0x84b1948c0; 1 drivers +v0x84b1624e0_0 .net/s *"_ivl_2", 15 0, L_0x84b194960; 1 drivers +v0x84b162580_0 .net *"_ivl_7", 0 0, L_0x84ae3b160; 1 drivers +v0x84b162620_0 .net *"_ivl_9", 15 0, L_0x84ae3b200; 1 drivers +L_0x84a878760 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1626c0_0 .net/s "acc_in", 31 0, L_0x84a878760; 1 drivers +v0x84b162760_0 .net/s "acc_out", 31 0, L_0x84ac8a8a0; alias, 1 drivers +v0x84b162800_0 .net/s "product", 15 0, L_0x84b194a00; 1 drivers +v0x84b1628a0_0 .net/s "product_ext", 31 0, L_0x84b194aa0; 1 drivers +v0x84b162940_0 .net/s "w", 7 0, L_0x84ae3b340; 1 drivers +v0x84b1629e0_0 .net/s "x", 7 0, L_0x84ae3b2a0; 1 drivers +L_0x84b1948c0 .extend/s 16, L_0x84ae3b2a0; +L_0x84b194960 .extend/s 16, L_0x84ae3b340; +L_0x84b194a00 .arith/mult 16, L_0x84b1948c0, L_0x84b194960; +L_0x84ae3b160 .part L_0x84b194a00, 15, 1; +L_0x84ae3b200 .repeat 16, 16, L_0x84ae3b160; +L_0x84b194aa0 .concat [ 16 16 0 0], L_0x84b194a00, L_0x84ae3b200; +L_0x84ac8a8a0 .arith/sum 32, L_0x84a878760, L_0x84b194aa0; +S_0x84ae87180 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151340 .param/l "i" 1 8 20, +C4<0101>; +S_0x84ae87300 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae87180; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158780 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1587c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158800 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b162a80_0 .net/s *"_ivl_0", 15 0, L_0x84b194b40; 1 drivers +v0x84b162b20_0 .net/s *"_ivl_2", 15 0, L_0x84b194be0; 1 drivers +v0x84b162bc0_0 .net *"_ivl_7", 0 0, L_0x84ae3b3e0; 1 drivers +v0x84b162c60_0 .net *"_ivl_9", 15 0, L_0x84ae3b480; 1 drivers +L_0x84a8787a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b162d00_0 .net/s "acc_in", 31 0, L_0x84a8787a8; 1 drivers +v0x84b162da0_0 .net/s "acc_out", 31 0, L_0x84ac8a940; alias, 1 drivers +v0x84b162e40_0 .net/s "product", 15 0, L_0x84b194c80; 1 drivers +v0x84b162ee0_0 .net/s "product_ext", 31 0, L_0x84b194d20; 1 drivers +v0x84b162f80_0 .net/s "w", 7 0, L_0x84ae3b5c0; 1 drivers +v0x84b163020_0 .net/s "x", 7 0, L_0x84ae3b520; 1 drivers +L_0x84b194b40 .extend/s 16, L_0x84ae3b520; +L_0x84b194be0 .extend/s 16, L_0x84ae3b5c0; +L_0x84b194c80 .arith/mult 16, L_0x84b194b40, L_0x84b194be0; +L_0x84ae3b3e0 .part L_0x84b194c80, 15, 1; +L_0x84ae3b480 .repeat 16, 16, L_0x84ae3b3e0; +L_0x84b194d20 .concat [ 16 16 0 0], L_0x84b194c80, L_0x84ae3b480; +L_0x84ac8a940 .arith/sum 32, L_0x84a8787a8, L_0x84b194d20; +S_0x84ae87480 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151380 .param/l "i" 1 8 20, +C4<0110>; +S_0x84ae87600 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae87480; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158840 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158880 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1588c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1630c0_0 .net/s *"_ivl_0", 15 0, L_0x84b194dc0; 1 drivers +v0x84b163160_0 .net/s *"_ivl_2", 15 0, L_0x84b194e60; 1 drivers +v0x84b163200_0 .net *"_ivl_7", 0 0, L_0x84ae3b660; 1 drivers +v0x84b1632a0_0 .net *"_ivl_9", 15 0, L_0x84ae3b700; 1 drivers +L_0x84a8787f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b163340_0 .net/s "acc_in", 31 0, L_0x84a8787f0; 1 drivers +v0x84b1633e0_0 .net/s "acc_out", 31 0, L_0x84ac8a9e0; alias, 1 drivers +v0x84b163480_0 .net/s "product", 15 0, L_0x84b194f00; 1 drivers +v0x84b163520_0 .net/s "product_ext", 31 0, L_0x84b194fa0; 1 drivers +v0x84b1635c0_0 .net/s "w", 7 0, L_0x84ae3b840; 1 drivers +v0x84b163660_0 .net/s "x", 7 0, L_0x84ae3b7a0; 1 drivers +L_0x84b194dc0 .extend/s 16, L_0x84ae3b7a0; +L_0x84b194e60 .extend/s 16, L_0x84ae3b840; +L_0x84b194f00 .arith/mult 16, L_0x84b194dc0, L_0x84b194e60; +L_0x84ae3b660 .part L_0x84b194f00, 15, 1; +L_0x84ae3b700 .repeat 16, 16, L_0x84ae3b660; +L_0x84b194fa0 .concat [ 16 16 0 0], L_0x84b194f00, L_0x84ae3b700; +L_0x84ac8a9e0 .arith/sum 32, L_0x84a8787f0, L_0x84b194fa0; +S_0x84ae87780 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b1513c0 .param/l "i" 1 8 20, +C4<0111>; +S_0x84ae87900 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae87780; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158900 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158940 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158980 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b163700_0 .net/s *"_ivl_0", 15 0, L_0x84b195040; 1 drivers +v0x84b1637a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1950e0; 1 drivers +v0x84b163840_0 .net *"_ivl_7", 0 0, L_0x84ae3b8e0; 1 drivers +v0x84b1638e0_0 .net *"_ivl_9", 15 0, L_0x84ae3b980; 1 drivers +L_0x84a878838 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b163980_0 .net/s "acc_in", 31 0, L_0x84a878838; 1 drivers +v0x84b163a20_0 .net/s "acc_out", 31 0, L_0x84ac8aa80; alias, 1 drivers +v0x84b163ac0_0 .net/s "product", 15 0, L_0x84b195180; 1 drivers +v0x84b163b60_0 .net/s "product_ext", 31 0, L_0x84b195220; 1 drivers +v0x84b163c00_0 .net/s "w", 7 0, L_0x84ae3bac0; 1 drivers +v0x84b163ca0_0 .net/s "x", 7 0, L_0x84ae3ba20; 1 drivers +L_0x84b195040 .extend/s 16, L_0x84ae3ba20; +L_0x84b1950e0 .extend/s 16, L_0x84ae3bac0; +L_0x84b195180 .arith/mult 16, L_0x84b195040, L_0x84b1950e0; +L_0x84ae3b8e0 .part L_0x84b195180, 15, 1; +L_0x84ae3b980 .repeat 16, 16, L_0x84ae3b8e0; +L_0x84b195220 .concat [ 16 16 0 0], L_0x84b195180, L_0x84ae3b980; +L_0x84ac8aa80 .arith/sum 32, L_0x84a878838, L_0x84b195220; +S_0x84ae87a80 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151400 .param/l "i" 1 8 80, +C4<00>; +L_0x84ac3f3a0 .functor BUFZ 32, L_0x84ac8a620, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae87c00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151440 .param/l "i" 1 8 80, +C4<01>; +L_0x84ac3f410 .functor BUFZ 32, L_0x84ac8a6c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae87d80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151480 .param/l "i" 1 8 80, +C4<010>; +L_0x84ac3f480 .functor BUFZ 32, L_0x84ac8a760, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88000 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b1514c0 .param/l "i" 1 8 80, +C4<011>; +L_0x84ac3f4f0 .functor BUFZ 32, L_0x84ac8a800, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88180 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151500 .param/l "i" 1 8 80, +C4<0100>; +L_0x84ac3f560 .functor BUFZ 32, L_0x84ac8a8a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88300 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151540 .param/l "i" 1 8 80, +C4<0101>; +L_0x84ac3f5d0 .functor BUFZ 32, L_0x84ac8a940, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88480 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151580 .param/l "i" 1 8 80, +C4<0110>; +L_0x84ac3f640 .functor BUFZ 32, L_0x84ac8a9e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88600 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b1515c0 .param/l "i" 1 8 80, +C4<0111>; +L_0x84ac3f6b0 .functor BUFZ 32, L_0x84ac8aa80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae88780 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151600 .param/l "level" 1 8 92, +C4<00>; +S_0x84ae88900 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae88780; + .timescale 0 0; +P_0x84b151640 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8ab20 .arith/sum 32, L_0x84ac3f3a0, L_0x84ac3f410; +S_0x84ae88a80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae88780; + .timescale 0 0; +P_0x84b151680 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8abc0 .arith/sum 32, L_0x84ac3f480, L_0x84ac3f4f0; +S_0x84ae88c00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84ae88780; + .timescale 0 0; +P_0x84b1516c0 .param/l "node" 1 8 94, +C4<010>; +L_0x84ac8ac60 .arith/sum 32, L_0x84ac3f560, L_0x84ac3f5d0; +S_0x84ae88d80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84ae88780; + .timescale 0 0; +P_0x84b151700 .param/l "node" 1 8 94, +C4<011>; +L_0x84ac8ad00 .arith/sum 32, L_0x84ac3f640, L_0x84ac3f6b0; +S_0x84ae88f00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151740 .param/l "level" 1 8 92, +C4<01>; +S_0x84ae89080 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae88f00; + .timescale 0 0; +P_0x84b151780 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8ada0 .arith/sum 32, L_0x84ac8ab20, L_0x84ac8abc0; +S_0x84ae89200 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae88f00; + .timescale 0 0; +P_0x84b1517c0 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8ae40 .arith/sum 32, L_0x84ac8ac60, L_0x84ac8ad00; +S_0x84ae89380 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84ae86100; + .timescale 0 0; +P_0x84b151800 .param/l "level" 1 8 92, +C4<010>; +S_0x84ae89500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae89380; + .timescale 0 0; +P_0x84b151840 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8aee0 .arith/sum 32, L_0x84ac8ada0, L_0x84ac8ae40; +S_0x84ae89680 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b151880 .param/l "n" 1 12 34, +C4<01>; +S_0x84ae89800 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84ae89680; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e662f0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e66330 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e66370 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e663b0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e663f0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e66430 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e66470 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c1c0 .functor BUFZ 16, L_0x8d321d900, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2cf1c20_0 .net *"_ivl_0", 31 0, L_0x8d31950e0; 1 drivers -v0x8d2cf1cc0_0 .net *"_ivl_11", 31 0, L_0x8d2d19680; 1 drivers -v0x8d2cf1d60_0 .net *"_ivl_14", 31 0, L_0x8d3195180; 1 drivers -L_0x8d2854520 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf1e00_0 .net *"_ivl_17", 28 0, L_0x8d2854520; 1 drivers -L_0x8d2854568 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf1ea0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854568; 1 drivers -v0x8d2cf1f40_0 .net *"_ivl_21", 31 0, L_0x8d2d19720; 1 drivers -L_0x8d28545b0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf1fe0_0 .net/2u *"_ivl_22", 31 0, L_0x8d28545b0; 1 drivers -v0x8d2cf2080_0 .net *"_ivl_25", 31 0, L_0x8d2d197c0; 1 drivers -L_0x8d2854448 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf2120_0 .net *"_ivl_3", 28 0, L_0x8d2854448; 1 drivers -v0x8d2cf21c0_0 .net *"_ivl_31", 0 0, L_0x8d321d680; 1 drivers -v0x8d2cf2260_0 .net *"_ivl_33", 23 0, L_0x8d2d1ac60; 1 drivers -v0x8d2cf2300_0 .net *"_ivl_36", 39 0, L_0x8d31961c0; 1 drivers -v0x8d2cf23a0_0 .net *"_ivl_38", 31 0, L_0x8d321d720; 1 drivers -L_0x8d2854490 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf2440_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854490; 1 drivers -L_0x8d2854838 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf24e0_0 .net *"_ivl_40", 7 0, L_0x8d2854838; 1 drivers -v0x8d2cf2580_0 .net *"_ivl_46", 31 0, L_0x8d321d7c0; 1 drivers -v0x8d2cf2620_0 .net *"_ivl_7", 31 0, L_0x8d2d195e0; 1 drivers -L_0x8d28544d8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf26c0_0 .net/2u *"_ivl_8", 31 0, L_0x8d28544d8; 1 drivers -v0x8d2cf2760_0 .var/s "acc", 39 0; -v0x8d2cf2800_0 .net/s "acc_next", 39 0, L_0x8d3196080; 1 drivers -v0x8d2cf28a0_0 .net/s "bias", 15 0, L_0x8d321d900; 1 drivers -v0x8d2cf2940_0 .net/s "bias_ext", 39 0, L_0x8d3196120; 1 drivers -v0x8d2cf29e0_0 .net/s "bias_ext_small", 15 0, L_0x8d307c1c0; 1 drivers -v0x8d2cf2a80_0 .var "busy", 0 0; -v0x8d2cf2b20_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2cf2bc0_0 .var "done", 0 0; -v0x8d2cf2c60_0 .net/s "final_acc", 39 0, L_0x8d3196260; 1 drivers -v0x8d2cf2d00_0 .net/s "final_value", 39 0, L_0x8d2d1ad00; 1 drivers -v0x8d2cf2da0_0 .var "group_index", 2 0; -v0x8d2cf2e40_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2cf2ee0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2cf2f80_0 .net/s "w_bus", 1023 0, L_0x8d321d860; 1 drivers -v0x8d2cf3020_0 .net/s "w_group", 127 0, L_0x8d321c6e0; 1 drivers -v0x8d2cf30c0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2cf3160_0 .net/s "x_group", 127 0, L_0x8d321c640; 1 drivers -v0x8d2cf3200_0 .var/s "y", 15 0; -L_0x8d31950e0 .concat [ 3 29 0 0], v0x8d2cf2da0_0, L_0x8d2854448; -L_0x8d2d195e0 .arith/mult 32, L_0x8d31950e0, L_0x8d2854490; -L_0x8d2d19680 .arith/mult 32, L_0x8d2d195e0, L_0x8d28544d8; -L_0x8d321c640 .part/v v0x8d2d17ca0_0, L_0x8d2d19680, 128; -L_0x8d3195180 .concat [ 3 29 0 0], v0x8d2cf2da0_0, L_0x8d2854520; -L_0x8d2d19720 .arith/mult 32, L_0x8d3195180, L_0x8d2854568; -L_0x8d2d197c0 .arith/mult 32, L_0x8d2d19720, L_0x8d28545b0; -L_0x8d321c6e0 .part/v L_0x8d321d860, L_0x8d2d197c0, 128; -L_0x8d321d680 .part L_0x8d307c1c0, 15, 1; -L_0x8d2d1ac60 .repeat 24, 24, L_0x8d321d680; -L_0x8d3196120 .concat [ 16 24 0 0], L_0x8d307c1c0, L_0x8d2d1ac60; -L_0x8d321d720 .part L_0x8d3196120, 0, 32; -L_0x8d31961c0 .concat [ 8 32 0 0], L_0x8d2854838, L_0x8d321d720; -L_0x8d3196260 .arith/sum 40, L_0x8d3196080, L_0x8d31961c0; -L_0x8d321d7c0 .part L_0x8d3196260, 8, 32; -L_0x8d2d1ad00 .extend/s 40, L_0x8d321d7c0; -S_0x8d31fc900 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fc780; +P_0x84ae89980 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84ae899c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84ae89a00 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84ae89a40 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84ae89a80 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84ae89ac0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b16ca00_0 .net *"_ivl_0", 31 0, L_0x84b195400; 1 drivers +v0x84b16caa0_0 .net *"_ivl_11", 31 0, L_0x84b195540; 1 drivers +v0x84b16cb40_0 .net *"_ivl_14", 31 0, L_0x84b1955e0; 1 drivers +L_0x84a878958 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16cbe0_0 .net *"_ivl_17", 29 0, L_0x84a878958; 1 drivers +L_0x84a8789a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b16cc80_0 .net/2u *"_ivl_18", 31 0, L_0x84a8789a0; 1 drivers +v0x84b16cd20_0 .net *"_ivl_21", 31 0, L_0x84b195680; 1 drivers +L_0x84a8789e8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b16cdc0_0 .net/2u *"_ivl_22", 31 0, L_0x84a8789e8; 1 drivers +v0x84b16ce60_0 .net *"_ivl_25", 31 0, L_0x84b195720; 1 drivers +v0x84b16cf00_0 .net *"_ivl_29", 0 0, L_0x84aeccbe0; 1 drivers +L_0x84a878880 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16cfa0_0 .net *"_ivl_3", 29 0, L_0x84a878880; 1 drivers +v0x84b16d040_0 .net *"_ivl_31", 23 0, L_0x84aeccc80; 1 drivers +L_0x84a8788c8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b16d0e0_0 .net/2u *"_ivl_4", 31 0, L_0x84a8788c8; 1 drivers +v0x84b16d180_0 .net *"_ivl_7", 31 0, L_0x84b1954a0; 1 drivers +L_0x84a878910 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b16d220_0 .net/2u *"_ivl_8", 31 0, L_0x84a878910; 1 drivers +v0x84b16d2c0_0 .var/s "acc", 31 0; +v0x84b16d360_0 .net/s "acc_next", 31 0, L_0x84ac8ba20; 1 drivers +v0x84b16d400_0 .net/s "bias", 7 0, L_0x84aeccdc0; 1 drivers +v0x84b16d4a0_0 .net/s "bias_ext", 31 0, L_0x84b196c60; 1 drivers +v0x84b16d540_0 .var "busy", 0 0; +v0x84b16d5e0_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b16d680_0 .var "done", 0 0; +v0x84b16d720_0 .net/s "final_acc", 31 0, L_0x84ac8bac0; 1 drivers +v0x84b16d7c0_0 .var "group_index", 1 0; +v0x84b16d860_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b16d900_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b16d9a0_0 .net/s "w_bus", 255 0, L_0x84aeccd20; 1 drivers +v0x84b16da40_0 .net/s "w_group", 63 0, L_0x84ae3be80; 1 drivers +v0x84b16dae0_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b16db80_0 .net/s "x_group", 63 0, L_0x84ae3bde0; 1 drivers +v0x84b16dc20_0 .var/s "y", 7 0; +L_0x84b195400 .concat [ 2 30 0 0], v0x84b16d7c0_0, L_0x84a878880; +L_0x84b1954a0 .arith/mult 32, L_0x84b195400, L_0x84a8788c8; +L_0x84b195540 .arith/mult 32, L_0x84b1954a0, L_0x84a878910; +L_0x84ae3bde0 .part/v v0x84b191e00_0, L_0x84b195540, 64; +L_0x84b1955e0 .concat [ 2 30 0 0], v0x84b16d7c0_0, L_0x84a878958; +L_0x84b195680 .arith/mult 32, L_0x84b1955e0, L_0x84a8789a0; +L_0x84b195720 .arith/mult 32, L_0x84b195680, L_0x84a8789e8; +L_0x84ae3be80 .part/v L_0x84aeccd20, L_0x84b195720, 64; +L_0x84aeccbe0 .part L_0x84aeccdc0, 7, 1; +L_0x84aeccc80 .repeat 24, 24, L_0x84aeccbe0; +L_0x84b196c60 .concat [ 8 24 0 0], L_0x84aeccdc0, L_0x84aeccc80; +L_0x84ac8bac0 .arith/sum 32, L_0x84ac8ba20, L_0x84b196c60; +S_0x84ae89b00 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84ae89800; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0680 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a06c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2cf1040_0 .net/s "acc_in", 39 0, v0x8d2cf2760_0; 1 drivers -v0x8d2cf10e0_0 .net/s "acc_out", 39 0, L_0x8d3196080; alias, 1 drivers -v0x8d2cf1180_0 .net/s "m0", 39 0, L_0x8d31952c0; 1 drivers -v0x8d2cf1220_0 .net/s "m1", 39 0, L_0x8d3195400; 1 drivers -v0x8d2cf12c0_0 .net/s "m2", 39 0, L_0x8d3195540; 1 drivers -v0x8d2cf1360_0 .net/s "m3", 39 0, L_0x8d3195680; 1 drivers -v0x8d2cf1400_0 .net/s "m4", 39 0, L_0x8d31957c0; 1 drivers -v0x8d2cf14a0_0 .net/s "m5", 39 0, L_0x8d3195900; 1 drivers -v0x8d2cf1540_0 .net/s "m6", 39 0, L_0x8d3195a40; 1 drivers -v0x8d2cf15e0_0 .net/s "m7", 39 0, L_0x8d3195b80; 1 drivers -v0x8d2cf1680_0 .net/s "s0", 39 0, L_0x8d3195c20; 1 drivers -v0x8d2cf1720_0 .net/s "s1", 39 0, L_0x8d3195cc0; 1 drivers -v0x8d2cf17c0_0 .net/s "s2", 39 0, L_0x8d3195d60; 1 drivers -v0x8d2cf1860_0 .net/s "s3", 39 0, L_0x8d3195e00; 1 drivers -v0x8d2cf1900_0 .net/s "s4", 39 0, L_0x8d3195ea0; 1 drivers -v0x8d2cf19a0_0 .net/s "s5", 39 0, L_0x8d3195f40; 1 drivers -v0x8d2cf1a40_0 .net/s "sum", 39 0, L_0x8d3195fe0; 1 drivers -v0x8d2cf1ae0_0 .net/s "w_bus", 127 0, L_0x8d321c6e0; alias, 1 drivers -v0x8d2cf1b80_0 .net/s "x_bus", 127 0, L_0x8d321c640; alias, 1 drivers -L_0x8d321c820 .part L_0x8d321c640, 0, 16; -L_0x8d321c8c0 .part L_0x8d321c6e0, 0, 16; -L_0x8d321ca00 .part L_0x8d321c640, 16, 16; -L_0x8d321caa0 .part L_0x8d321c6e0, 16, 16; -L_0x8d321cbe0 .part L_0x8d321c640, 32, 16; -L_0x8d321cc80 .part L_0x8d321c6e0, 32, 16; -L_0x8d321cdc0 .part L_0x8d321c640, 48, 16; -L_0x8d321ce60 .part L_0x8d321c6e0, 48, 16; -L_0x8d321cfa0 .part L_0x8d321c640, 64, 16; -L_0x8d321d040 .part L_0x8d321c6e0, 64, 16; -L_0x8d321d180 .part L_0x8d321c640, 80, 16; -L_0x8d321d220 .part L_0x8d321c6e0, 80, 16; -L_0x8d321d360 .part L_0x8d321c640, 96, 16; -L_0x8d321d400 .part L_0x8d321c6e0, 96, 16; -L_0x8d321d540 .part L_0x8d321c640, 112, 16; -L_0x8d321d5e0 .part L_0x8d321c6e0, 112, 16; -L_0x8d3195c20 .arith/sum 40, L_0x8d31952c0, L_0x8d3195400; -L_0x8d3195cc0 .arith/sum 40, L_0x8d3195540, L_0x8d3195680; -L_0x8d3195d60 .arith/sum 40, L_0x8d31957c0, L_0x8d3195900; -L_0x8d3195e00 .arith/sum 40, L_0x8d3195a40, L_0x8d3195b80; -L_0x8d3195ea0 .arith/sum 40, L_0x8d3195c20, L_0x8d3195cc0; -L_0x8d3195f40 .arith/sum 40, L_0x8d3195d60, L_0x8d3195e00; -L_0x8d3195fe0 .arith/sum 40, L_0x8d3195ea0, L_0x8d3195f40; -L_0x8d3196080 .arith/sum 40, v0x8d2cf2760_0, L_0x8d3195fe0; -S_0x8d31fca80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fc900; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8400 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8440 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8480 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc84c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b16c640_0 .net/s "acc_in", 31 0, v0x84b16d2c0_0; 1 drivers +v0x84b16c6e0_0 .net/s "acc_out", 31 0, L_0x84ac8ba20; alias, 1 drivers +v0x84b16c780 .array "products", 7 0; +v0x84b16c780_0 .net/s v0x84b16c780 0, 31 0, L_0x84ac8b0c0; 1 drivers +v0x84b16c780_1 .net/s v0x84b16c780 1, 31 0, L_0x84ac8b160; 1 drivers +v0x84b16c780_2 .net/s v0x84b16c780 2, 31 0, L_0x84ac8b200; 1 drivers +v0x84b16c780_3 .net/s v0x84b16c780 3, 31 0, L_0x84ac8b2a0; 1 drivers +v0x84b16c780_4 .net/s v0x84b16c780 4, 31 0, L_0x84ac8b340; 1 drivers +v0x84b16c780_5 .net/s v0x84b16c780 5, 31 0, L_0x84ac8b3e0; 1 drivers +v0x84b16c780_6 .net/s v0x84b16c780 6, 31 0, L_0x84ac8b480; 1 drivers +v0x84b16c780_7 .net/s v0x84b16c780 7, 31 0, L_0x84ac8b520; 1 drivers +v0x84b16c820 .array "tree", 31 0; +v0x84b16c820_0 .net/s v0x84b16c820 0, 31 0, L_0x84ac3f720; 1 drivers +v0x84b16c820_1 .net/s v0x84b16c820 1, 31 0, L_0x84ac3f790; 1 drivers +v0x84b16c820_2 .net/s v0x84b16c820 2, 31 0, L_0x84ac3f800; 1 drivers +v0x84b16c820_3 .net/s v0x84b16c820 3, 31 0, L_0x84ac3f870; 1 drivers +v0x84b16c820_4 .net/s v0x84b16c820 4, 31 0, L_0x84ac3f8e0; 1 drivers +v0x84b16c820_5 .net/s v0x84b16c820 5, 31 0, L_0x84ac3f950; 1 drivers +v0x84b16c820_6 .net/s v0x84b16c820 6, 31 0, L_0x84ac3f9c0; 1 drivers +v0x84b16c820_7 .net/s v0x84b16c820 7, 31 0, L_0x84ac3fa30; 1 drivers +v0x84b16c820_8 .net/s v0x84b16c820 8, 31 0, L_0x84ac8b5c0; 1 drivers +v0x84b16c820_9 .net/s v0x84b16c820 9, 31 0, L_0x84ac8b660; 1 drivers +v0x84b16c820_10 .net/s v0x84b16c820 10, 31 0, L_0x84ac8b700; 1 drivers +v0x84b16c820_11 .net/s v0x84b16c820 11, 31 0, L_0x84ac8b7a0; 1 drivers +o0x84a84d5e0 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_12 .net/s v0x84b16c820 12, 31 0, o0x84a84d5e0; 0 drivers +o0x84a84d610 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_13 .net/s v0x84b16c820 13, 31 0, o0x84a84d610; 0 drivers +o0x84a84d640 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_14 .net/s v0x84b16c820 14, 31 0, o0x84a84d640; 0 drivers +o0x84a84d670 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_15 .net/s v0x84b16c820 15, 31 0, o0x84a84d670; 0 drivers +v0x84b16c820_16 .net/s v0x84b16c820 16, 31 0, L_0x84ac8b840; 1 drivers +v0x84b16c820_17 .net/s v0x84b16c820 17, 31 0, L_0x84ac8b8e0; 1 drivers +o0x84a84d700 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_18 .net/s v0x84b16c820 18, 31 0, o0x84a84d700; 0 drivers +o0x84a84d730 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_19 .net/s v0x84b16c820 19, 31 0, o0x84a84d730; 0 drivers +o0x84a84d760 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_20 .net/s v0x84b16c820 20, 31 0, o0x84a84d760; 0 drivers +o0x84a84d790 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_21 .net/s v0x84b16c820 21, 31 0, o0x84a84d790; 0 drivers +o0x84a84d7c0 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_22 .net/s v0x84b16c820 22, 31 0, o0x84a84d7c0; 0 drivers +o0x84a84d7f0 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_23 .net/s v0x84b16c820 23, 31 0, o0x84a84d7f0; 0 drivers +v0x84b16c820_24 .net/s v0x84b16c820 24, 31 0, L_0x84ac8b980; 1 drivers +o0x84a84d850 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_25 .net/s v0x84b16c820 25, 31 0, o0x84a84d850; 0 drivers +o0x84a84d880 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_26 .net/s v0x84b16c820 26, 31 0, o0x84a84d880; 0 drivers +o0x84a84d8b0 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_27 .net/s v0x84b16c820 27, 31 0, o0x84a84d8b0; 0 drivers +o0x84a84d8e0 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_28 .net/s v0x84b16c820 28, 31 0, o0x84a84d8e0; 0 drivers +o0x84a84d910 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_29 .net/s v0x84b16c820 29, 31 0, o0x84a84d910; 0 drivers +o0x84a84d940 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_30 .net/s v0x84b16c820 30, 31 0, o0x84a84d940; 0 drivers +o0x84a84d970 .functor BUFZ 32, c4; HiZ drive +v0x84b16c820_31 .net/s v0x84b16c820 31, 31 0, o0x84a84d970; 0 drivers +v0x84b16c8c0_0 .net/s "w_bus", 63 0, L_0x84ae3be80; alias, 1 drivers +v0x84b16c960_0 .net/s "x_bus", 63 0, L_0x84ae3bde0; alias, 1 drivers +L_0x84ae04780 .part L_0x84ae3bde0, 0, 8; +L_0x84adec500 .part L_0x84ae3be80, 0, 8; +L_0x84ad8fd40 .part L_0x84ae3bde0, 8, 8; +L_0x84ad5b7a0 .part L_0x84ae3be80, 8, 8; +L_0x84ad5b520 .part L_0x84ae3bde0, 16, 8; +L_0x84ad5b480 .part L_0x84ae3be80, 16, 8; +L_0x84aecc0a0 .part L_0x84ae3bde0, 24, 8; +L_0x84aecc140 .part L_0x84ae3be80, 24, 8; +L_0x84aecc320 .part L_0x84ae3bde0, 32, 8; +L_0x84aecc3c0 .part L_0x84ae3be80, 32, 8; +L_0x84aecc5a0 .part L_0x84ae3bde0, 40, 8; +L_0x84aecc640 .part L_0x84ae3be80, 40, 8; +L_0x84aecc820 .part L_0x84ae3bde0, 48, 8; +L_0x84aecc8c0 .part L_0x84ae3be80, 48, 8; +L_0x84aeccaa0 .part L_0x84ae3bde0, 56, 8; +L_0x84aeccb40 .part L_0x84ae3be80, 56, 8; +L_0x84ac8ba20 .arith/sum 32, v0x84b16d2c0_0, L_0x84ac8b980; +S_0x84ae89c80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84ae89b00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c6c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cede00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19860; 1 drivers -v0x8d2cedea0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19900; 1 drivers -v0x8d2cedf40_0 .net *"_ivl_7", 0 0, L_0x8d321c780; 1 drivers -v0x8d2cedfe0_0 .net *"_ivl_9", 7 0, L_0x8d2d19a40; 1 drivers -L_0x8d28545f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cee080_0 .net/s "acc_in", 39 0, L_0x8d28545f8; 1 drivers -v0x8d2cee120_0 .net/s "acc_out", 39 0, L_0x8d31952c0; alias, 1 drivers -v0x8d2cee1c0_0 .net/s "product", 31 0, L_0x8d2d199a0; 1 drivers -v0x8d2cee260_0 .net/s "product_ext", 39 0, L_0x8d3195220; 1 drivers -v0x8d2cee300_0 .net/s "w", 15 0, L_0x8d321c8c0; 1 drivers -v0x8d2cee3a0_0 .net/s "x", 15 0, L_0x8d321c820; 1 drivers -L_0x8d2d19860 .extend/s 32, L_0x8d321c820; -L_0x8d2d19900 .extend/s 32, L_0x8d321c8c0; -L_0x8d2d199a0 .arith/mult 32, L_0x8d2d19860, L_0x8d2d19900; -L_0x8d321c780 .part L_0x8d2d199a0, 31, 1; -L_0x8d2d19a40 .repeat 8, 8, L_0x8d321c780; -L_0x8d3195220 .concat [ 32 8 0 0], L_0x8d2d199a0, L_0x8d2d19a40; -L_0x8d31952c0 .arith/sum 40, L_0x8d28545f8, L_0x8d3195220; -S_0x8d31fcc00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fc900; +P_0x84b1518c0 .param/l "i" 1 8 20, +C4<00>; +S_0x84ae89e00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae89c80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c7c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cee440_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19ae0; 1 drivers -v0x8d2cee4e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19b80; 1 drivers -v0x8d2cee580_0 .net *"_ivl_7", 0 0, L_0x8d321c960; 1 drivers -v0x8d2cee620_0 .net *"_ivl_9", 7 0, L_0x8d2d19cc0; 1 drivers -L_0x8d2854640 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cee6c0_0 .net/s "acc_in", 39 0, L_0x8d2854640; 1 drivers -v0x8d2cee760_0 .net/s "acc_out", 39 0, L_0x8d3195400; alias, 1 drivers -v0x8d2cee800_0 .net/s "product", 31 0, L_0x8d2d19c20; 1 drivers -v0x8d2cee8a0_0 .net/s "product_ext", 39 0, L_0x8d3195360; 1 drivers -v0x8d2cee940_0 .net/s "w", 15 0, L_0x8d321caa0; 1 drivers -v0x8d2cee9e0_0 .net/s "x", 15 0, L_0x8d321ca00; 1 drivers -L_0x8d2d19ae0 .extend/s 32, L_0x8d321ca00; -L_0x8d2d19b80 .extend/s 32, L_0x8d321caa0; -L_0x8d2d19c20 .arith/mult 32, L_0x8d2d19ae0, L_0x8d2d19b80; -L_0x8d321c960 .part L_0x8d2d19c20, 31, 1; -L_0x8d2d19cc0 .repeat 8, 8, L_0x8d321c960; -L_0x8d3195360 .concat [ 32 8 0 0], L_0x8d2d19c20, L_0x8d2d19cc0; -L_0x8d3195400 .arith/sum 40, L_0x8d2854640, L_0x8d3195360; -S_0x8d31fcd80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fc900; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1589c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158a00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158a40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b169400_0 .net/s *"_ivl_0", 15 0, L_0x84b1957c0; 1 drivers +v0x84b1694a0_0 .net/s *"_ivl_2", 15 0, L_0x84b195860; 1 drivers +v0x84b169540_0 .net *"_ivl_7", 0 0, L_0x84ae3bf20; 1 drivers +v0x84b1695e0_0 .net *"_ivl_9", 15 0, L_0x84ae20a00; 1 drivers +L_0x84a878a30 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b169680_0 .net/s "acc_in", 31 0, L_0x84a878a30; 1 drivers +v0x84b169720_0 .net/s "acc_out", 31 0, L_0x84ac8b0c0; alias, 1 drivers +v0x84b1697c0_0 .net/s "product", 15 0, L_0x84b195900; 1 drivers +v0x84b169860_0 .net/s "product_ext", 31 0, L_0x84b1959a0; 1 drivers +v0x84b169900_0 .net/s "w", 7 0, L_0x84adec500; 1 drivers +v0x84b1699a0_0 .net/s "x", 7 0, L_0x84ae04780; 1 drivers +L_0x84b1957c0 .extend/s 16, L_0x84ae04780; +L_0x84b195860 .extend/s 16, L_0x84adec500; +L_0x84b195900 .arith/mult 16, L_0x84b1957c0, L_0x84b195860; +L_0x84ae3bf20 .part L_0x84b195900, 15, 1; +L_0x84ae20a00 .repeat 16, 16, L_0x84ae3bf20; +L_0x84b1959a0 .concat [ 16 16 0 0], L_0x84b195900, L_0x84ae20a00; +L_0x84ac8b0c0 .arith/sum 32, L_0x84a878a30, L_0x84b1959a0; +S_0x84ae89f80 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84ae89b00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c8c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2ceea80_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19d60; 1 drivers -v0x8d2ceeb20_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19e00; 1 drivers -v0x8d2ceebc0_0 .net *"_ivl_7", 0 0, L_0x8d321cb40; 1 drivers -v0x8d2ceec60_0 .net *"_ivl_9", 7 0, L_0x8d2d19f40; 1 drivers -L_0x8d2854688 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2ceed00_0 .net/s "acc_in", 39 0, L_0x8d2854688; 1 drivers -v0x8d2ceeda0_0 .net/s "acc_out", 39 0, L_0x8d3195540; alias, 1 drivers -v0x8d2ceee40_0 .net/s "product", 31 0, L_0x8d2d19ea0; 1 drivers -v0x8d2ceeee0_0 .net/s "product_ext", 39 0, L_0x8d31954a0; 1 drivers -v0x8d2ceef80_0 .net/s "w", 15 0, L_0x8d321cc80; 1 drivers -v0x8d2cef020_0 .net/s "x", 15 0, L_0x8d321cbe0; 1 drivers -L_0x8d2d19d60 .extend/s 32, L_0x8d321cbe0; -L_0x8d2d19e00 .extend/s 32, L_0x8d321cc80; -L_0x8d2d19ea0 .arith/mult 32, L_0x8d2d19d60, L_0x8d2d19e00; -L_0x8d321cb40 .part L_0x8d2d19ea0, 31, 1; -L_0x8d2d19f40 .repeat 8, 8, L_0x8d321cb40; -L_0x8d31954a0 .concat [ 32 8 0 0], L_0x8d2d19ea0, L_0x8d2d19f40; -L_0x8d3195540 .arith/sum 40, L_0x8d2854688, L_0x8d31954a0; -S_0x8d31fcf00 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fc900; +P_0x84b151900 .param/l "i" 1 8 20, +C4<01>; +S_0x84ae8a100 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae89f80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306c940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306c980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cef0c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19fe0; 1 drivers -v0x8d2cef160_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a080; 1 drivers -v0x8d2cef200_0 .net *"_ivl_7", 0 0, L_0x8d321cd20; 1 drivers -v0x8d2cef2a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a1c0; 1 drivers -L_0x8d28546d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cef340_0 .net/s "acc_in", 39 0, L_0x8d28546d0; 1 drivers -v0x8d2cef3e0_0 .net/s "acc_out", 39 0, L_0x8d3195680; alias, 1 drivers -v0x8d2cef480_0 .net/s "product", 31 0, L_0x8d2d1a120; 1 drivers -v0x8d2cef520_0 .net/s "product_ext", 39 0, L_0x8d31955e0; 1 drivers -v0x8d2cef5c0_0 .net/s "w", 15 0, L_0x8d321ce60; 1 drivers -v0x8d2cef660_0 .net/s "x", 15 0, L_0x8d321cdc0; 1 drivers -L_0x8d2d19fe0 .extend/s 32, L_0x8d321cdc0; -L_0x8d2d1a080 .extend/s 32, L_0x8d321ce60; -L_0x8d2d1a120 .arith/mult 32, L_0x8d2d19fe0, L_0x8d2d1a080; -L_0x8d321cd20 .part L_0x8d2d1a120, 31, 1; -L_0x8d2d1a1c0 .repeat 8, 8, L_0x8d321cd20; -L_0x8d31955e0 .concat [ 32 8 0 0], L_0x8d2d1a120, L_0x8d2d1a1c0; -L_0x8d3195680 .arith/sum 40, L_0x8d28546d0, L_0x8d31955e0; -S_0x8d31fd080 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fc900; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158a80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158ac0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158b00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b169a40_0 .net/s *"_ivl_0", 15 0, L_0x84b195a40; 1 drivers +v0x84b169ae0_0 .net/s *"_ivl_2", 15 0, L_0x84b195ae0; 1 drivers +v0x84b169b80_0 .net *"_ivl_7", 0 0, L_0x84add8280; 1 drivers +v0x84b169c20_0 .net *"_ivl_9", 15 0, L_0x84adc0000; 1 drivers +L_0x84a878a78 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b169cc0_0 .net/s "acc_in", 31 0, L_0x84a878a78; 1 drivers +v0x84b169d60_0 .net/s "acc_out", 31 0, L_0x84ac8b160; alias, 1 drivers +v0x84b169e00_0 .net/s "product", 15 0, L_0x84b195b80; 1 drivers +v0x84b169ea0_0 .net/s "product_ext", 31 0, L_0x84b195c20; 1 drivers +v0x84b169f40_0 .net/s "w", 7 0, L_0x84ad5b7a0; 1 drivers +v0x84b169fe0_0 .net/s "x", 7 0, L_0x84ad8fd40; 1 drivers +L_0x84b195a40 .extend/s 16, L_0x84ad8fd40; +L_0x84b195ae0 .extend/s 16, L_0x84ad5b7a0; +L_0x84b195b80 .arith/mult 16, L_0x84b195a40, L_0x84b195ae0; +L_0x84add8280 .part L_0x84b195b80, 15, 1; +L_0x84adc0000 .repeat 16, 16, L_0x84add8280; +L_0x84b195c20 .concat [ 16 16 0 0], L_0x84b195b80, L_0x84adc0000; +L_0x84ac8b160 .arith/sum 32, L_0x84a878a78, L_0x84b195c20; +S_0x84ae8a280 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84ae89b00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306c9c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ca00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ca40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cef700_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a260; 1 drivers -v0x8d2cef7a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a300; 1 drivers -v0x8d2cef840_0 .net *"_ivl_7", 0 0, L_0x8d321cf00; 1 drivers -v0x8d2cef8e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a440; 1 drivers -L_0x8d2854718 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cef980_0 .net/s "acc_in", 39 0, L_0x8d2854718; 1 drivers -v0x8d2cefa20_0 .net/s "acc_out", 39 0, L_0x8d31957c0; alias, 1 drivers -v0x8d2cefac0_0 .net/s "product", 31 0, L_0x8d2d1a3a0; 1 drivers -v0x8d2cefb60_0 .net/s "product_ext", 39 0, L_0x8d3195720; 1 drivers -v0x8d2cefc00_0 .net/s "w", 15 0, L_0x8d321d040; 1 drivers -v0x8d2cefca0_0 .net/s "x", 15 0, L_0x8d321cfa0; 1 drivers -L_0x8d2d1a260 .extend/s 32, L_0x8d321cfa0; -L_0x8d2d1a300 .extend/s 32, L_0x8d321d040; -L_0x8d2d1a3a0 .arith/mult 32, L_0x8d2d1a260, L_0x8d2d1a300; -L_0x8d321cf00 .part L_0x8d2d1a3a0, 31, 1; -L_0x8d2d1a440 .repeat 8, 8, L_0x8d321cf00; -L_0x8d3195720 .concat [ 32 8 0 0], L_0x8d2d1a3a0, L_0x8d2d1a440; -L_0x8d31957c0 .arith/sum 40, L_0x8d2854718, L_0x8d3195720; -S_0x8d31fd200 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fc900; +P_0x84b151940 .param/l "i" 1 8 20, +C4<010>; +S_0x84ae8a400 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8a280; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ca80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cb00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cefd40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a4e0; 1 drivers -v0x8d2cefde0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a580; 1 drivers -v0x8d2cefe80_0 .net *"_ivl_7", 0 0, L_0x8d321d0e0; 1 drivers -v0x8d2ceff20_0 .net *"_ivl_9", 7 0, L_0x8d2d1a6c0; 1 drivers -L_0x8d2854760 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf0000_0 .net/s "acc_in", 39 0, L_0x8d2854760; 1 drivers -v0x8d2cf00a0_0 .net/s "acc_out", 39 0, L_0x8d3195900; alias, 1 drivers -v0x8d2cf0140_0 .net/s "product", 31 0, L_0x8d2d1a620; 1 drivers -v0x8d2cf01e0_0 .net/s "product_ext", 39 0, L_0x8d3195860; 1 drivers -v0x8d2cf0280_0 .net/s "w", 15 0, L_0x8d321d220; 1 drivers -v0x8d2cf0320_0 .net/s "x", 15 0, L_0x8d321d180; 1 drivers -L_0x8d2d1a4e0 .extend/s 32, L_0x8d321d180; -L_0x8d2d1a580 .extend/s 32, L_0x8d321d220; -L_0x8d2d1a620 .arith/mult 32, L_0x8d2d1a4e0, L_0x8d2d1a580; -L_0x8d321d0e0 .part L_0x8d2d1a620, 31, 1; -L_0x8d2d1a6c0 .repeat 8, 8, L_0x8d321d0e0; -L_0x8d3195860 .concat [ 32 8 0 0], L_0x8d2d1a620, L_0x8d2d1a6c0; -L_0x8d3195900 .arith/sum 40, L_0x8d2854760, L_0x8d3195860; -S_0x8d31fd380 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fc900; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158b40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158b80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158bc0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16a080_0 .net/s *"_ivl_0", 15 0, L_0x84b195cc0; 1 drivers +v0x84b16a120_0 .net/s *"_ivl_2", 15 0, L_0x84b195d60; 1 drivers +v0x84b16a1c0_0 .net *"_ivl_7", 0 0, L_0x84ad5b840; 1 drivers +v0x84b16a260_0 .net *"_ivl_9", 15 0, L_0x84ad5b980; 1 drivers +L_0x84a878ac0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16a300_0 .net/s "acc_in", 31 0, L_0x84a878ac0; 1 drivers +v0x84b16a3a0_0 .net/s "acc_out", 31 0, L_0x84ac8b200; alias, 1 drivers +v0x84b16a440_0 .net/s "product", 15 0, L_0x84b195e00; 1 drivers +v0x84b16a4e0_0 .net/s "product_ext", 31 0, L_0x84b195ea0; 1 drivers +v0x84b16a580_0 .net/s "w", 7 0, L_0x84ad5b480; 1 drivers +v0x84b16a620_0 .net/s "x", 7 0, L_0x84ad5b520; 1 drivers +L_0x84b195cc0 .extend/s 16, L_0x84ad5b520; +L_0x84b195d60 .extend/s 16, L_0x84ad5b480; +L_0x84b195e00 .arith/mult 16, L_0x84b195cc0, L_0x84b195d60; +L_0x84ad5b840 .part L_0x84b195e00, 15, 1; +L_0x84ad5b980 .repeat 16, 16, L_0x84ad5b840; +L_0x84b195ea0 .concat [ 16 16 0 0], L_0x84b195e00, L_0x84ad5b980; +L_0x84ac8b200 .arith/sum 32, L_0x84a878ac0, L_0x84b195ea0; +S_0x84ae8a580 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84ae89b00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306cb40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cb80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cbc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf03c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a760; 1 drivers -v0x8d2cf0460_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a800; 1 drivers -v0x8d2cf0500_0 .net *"_ivl_7", 0 0, L_0x8d321d2c0; 1 drivers -v0x8d2cf05a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a940; 1 drivers -L_0x8d28547a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf0640_0 .net/s "acc_in", 39 0, L_0x8d28547a8; 1 drivers -v0x8d2cf06e0_0 .net/s "acc_out", 39 0, L_0x8d3195a40; alias, 1 drivers -v0x8d2cf0780_0 .net/s "product", 31 0, L_0x8d2d1a8a0; 1 drivers -v0x8d2cf0820_0 .net/s "product_ext", 39 0, L_0x8d31959a0; 1 drivers -v0x8d2cf08c0_0 .net/s "w", 15 0, L_0x8d321d400; 1 drivers -v0x8d2cf0960_0 .net/s "x", 15 0, L_0x8d321d360; 1 drivers -L_0x8d2d1a760 .extend/s 32, L_0x8d321d360; -L_0x8d2d1a800 .extend/s 32, L_0x8d321d400; -L_0x8d2d1a8a0 .arith/mult 32, L_0x8d2d1a760, L_0x8d2d1a800; -L_0x8d321d2c0 .part L_0x8d2d1a8a0, 31, 1; -L_0x8d2d1a940 .repeat 8, 8, L_0x8d321d2c0; -L_0x8d31959a0 .concat [ 32 8 0 0], L_0x8d2d1a8a0, L_0x8d2d1a940; -L_0x8d3195a40 .arith/sum 40, L_0x8d28547a8, L_0x8d31959a0; -S_0x8d31fd500 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fc900; +P_0x84b151980 .param/l "i" 1 8 20, +C4<011>; +S_0x84ae8a700 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8a580; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306cc00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cc40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cc80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf0a00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a9e0; 1 drivers -v0x8d2cf0aa0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1aa80; 1 drivers -v0x8d2cf0b40_0 .net *"_ivl_7", 0 0, L_0x8d321d4a0; 1 drivers -v0x8d2cf0be0_0 .net *"_ivl_9", 7 0, L_0x8d2d1abc0; 1 drivers -L_0x8d28547f0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf0c80_0 .net/s "acc_in", 39 0, L_0x8d28547f0; 1 drivers -v0x8d2cf0d20_0 .net/s "acc_out", 39 0, L_0x8d3195b80; alias, 1 drivers -v0x8d2cf0dc0_0 .net/s "product", 31 0, L_0x8d2d1ab20; 1 drivers -v0x8d2cf0e60_0 .net/s "product_ext", 39 0, L_0x8d3195ae0; 1 drivers -v0x8d2cf0f00_0 .net/s "w", 15 0, L_0x8d321d5e0; 1 drivers -v0x8d2cf0fa0_0 .net/s "x", 15 0, L_0x8d321d540; 1 drivers -L_0x8d2d1a9e0 .extend/s 32, L_0x8d321d540; -L_0x8d2d1aa80 .extend/s 32, L_0x8d321d5e0; -L_0x8d2d1ab20 .arith/mult 32, L_0x8d2d1a9e0, L_0x8d2d1aa80; -L_0x8d321d4a0 .part L_0x8d2d1ab20, 31, 1; -L_0x8d2d1abc0 .repeat 8, 8, L_0x8d321d4a0; -L_0x8d3195ae0 .concat [ 32 8 0 0], L_0x8d2d1ab20, L_0x8d2d1abc0; -L_0x8d3195b80 .arith/sum 40, L_0x8d28547f0, L_0x8d3195ae0; -S_0x8d31fd680 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158c00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158c40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158c80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16a6c0_0 .net/s *"_ivl_0", 15 0, L_0x84b195f40; 1 drivers +v0x84b16a760_0 .net/s *"_ivl_2", 15 0, L_0x84b195fe0; 1 drivers +v0x84b16a800_0 .net *"_ivl_7", 0 0, L_0x84ad5b5c0; 1 drivers +v0x84b16a8a0_0 .net *"_ivl_9", 15 0, L_0x84aecc000; 1 drivers +L_0x84a878b08 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16a940_0 .net/s "acc_in", 31 0, L_0x84a878b08; 1 drivers +v0x84b16a9e0_0 .net/s "acc_out", 31 0, L_0x84ac8b2a0; alias, 1 drivers +v0x84b16aa80_0 .net/s "product", 15 0, L_0x84b196080; 1 drivers +v0x84b16ab20_0 .net/s "product_ext", 31 0, L_0x84b196120; 1 drivers +v0x84b16abc0_0 .net/s "w", 7 0, L_0x84aecc140; 1 drivers +v0x84b16ac60_0 .net/s "x", 7 0, L_0x84aecc0a0; 1 drivers +L_0x84b195f40 .extend/s 16, L_0x84aecc0a0; +L_0x84b195fe0 .extend/s 16, L_0x84aecc140; +L_0x84b196080 .arith/mult 16, L_0x84b195f40, L_0x84b195fe0; +L_0x84ad5b5c0 .part L_0x84b196080, 15, 1; +L_0x84aecc000 .repeat 16, 16, L_0x84ad5b5c0; +L_0x84b196120 .concat [ 16 16 0 0], L_0x84b196080, L_0x84aecc000; +L_0x84ac8b2a0 .arith/sum 32, L_0x84a878b08, L_0x84b196120; +S_0x84ae8a880 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84ae89b00; .timescale 0 0; -P_0x8d2c3b140 .param/l "n" 1 4 35, +C4<010>; -S_0x8d31fd800 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fd680; +P_0x84b1519c0 .param/l "i" 1 8 20, +C4<0100>; +S_0x84ae8aa00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8a880; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158cc0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158d00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158d40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16ad00_0 .net/s *"_ivl_0", 15 0, L_0x84b1961c0; 1 drivers +v0x84b16ada0_0 .net/s *"_ivl_2", 15 0, L_0x84b196260; 1 drivers +v0x84b16ae40_0 .net *"_ivl_7", 0 0, L_0x84aecc1e0; 1 drivers +v0x84b16aee0_0 .net *"_ivl_9", 15 0, L_0x84aecc280; 1 drivers +L_0x84a878b50 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16af80_0 .net/s "acc_in", 31 0, L_0x84a878b50; 1 drivers +v0x84b16b020_0 .net/s "acc_out", 31 0, L_0x84ac8b340; alias, 1 drivers +v0x84b16b0c0_0 .net/s "product", 15 0, L_0x84b196300; 1 drivers +v0x84b16b160_0 .net/s "product_ext", 31 0, L_0x84b1963a0; 1 drivers +v0x84b16b200_0 .net/s "w", 7 0, L_0x84aecc3c0; 1 drivers +v0x84b16b2a0_0 .net/s "x", 7 0, L_0x84aecc320; 1 drivers +L_0x84b1961c0 .extend/s 16, L_0x84aecc320; +L_0x84b196260 .extend/s 16, L_0x84aecc3c0; +L_0x84b196300 .arith/mult 16, L_0x84b1961c0, L_0x84b196260; +L_0x84aecc1e0 .part L_0x84b196300, 15, 1; +L_0x84aecc280 .repeat 16, 16, L_0x84aecc1e0; +L_0x84b1963a0 .concat [ 16 16 0 0], L_0x84b196300, L_0x84aecc280; +L_0x84ac8b340 .arith/sum 32, L_0x84a878b50, L_0x84b1963a0; +S_0x84ae8ab80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151a00 .param/l "i" 1 8 20, +C4<0101>; +S_0x84ae8ad00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8ab80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158d80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158dc0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158e00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16b340_0 .net/s *"_ivl_0", 15 0, L_0x84b196440; 1 drivers +v0x84b16b3e0_0 .net/s *"_ivl_2", 15 0, L_0x84b1964e0; 1 drivers +v0x84b16b480_0 .net *"_ivl_7", 0 0, L_0x84aecc460; 1 drivers +v0x84b16b520_0 .net *"_ivl_9", 15 0, L_0x84aecc500; 1 drivers +L_0x84a878b98 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16b5c0_0 .net/s "acc_in", 31 0, L_0x84a878b98; 1 drivers +v0x84b16b660_0 .net/s "acc_out", 31 0, L_0x84ac8b3e0; alias, 1 drivers +v0x84b16b700_0 .net/s "product", 15 0, L_0x84b196580; 1 drivers +v0x84b16b7a0_0 .net/s "product_ext", 31 0, L_0x84b196620; 1 drivers +v0x84b16b840_0 .net/s "w", 7 0, L_0x84aecc640; 1 drivers +v0x84b16b8e0_0 .net/s "x", 7 0, L_0x84aecc5a0; 1 drivers +L_0x84b196440 .extend/s 16, L_0x84aecc5a0; +L_0x84b1964e0 .extend/s 16, L_0x84aecc640; +L_0x84b196580 .arith/mult 16, L_0x84b196440, L_0x84b1964e0; +L_0x84aecc460 .part L_0x84b196580, 15, 1; +L_0x84aecc500 .repeat 16, 16, L_0x84aecc460; +L_0x84b196620 .concat [ 16 16 0 0], L_0x84b196580, L_0x84aecc500; +L_0x84ac8b3e0 .arith/sum 32, L_0x84a878b98, L_0x84b196620; +S_0x84ae8ae80 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151a40 .param/l "i" 1 8 20, +C4<0110>; +S_0x84ae8b000 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8ae80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158e40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158e80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158ec0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16b980_0 .net/s *"_ivl_0", 15 0, L_0x84b1966c0; 1 drivers +v0x84b16ba20_0 .net/s *"_ivl_2", 15 0, L_0x84b196760; 1 drivers +v0x84b16bac0_0 .net *"_ivl_7", 0 0, L_0x84aecc6e0; 1 drivers +v0x84b16bb60_0 .net *"_ivl_9", 15 0, L_0x84aecc780; 1 drivers +L_0x84a878be0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16bc00_0 .net/s "acc_in", 31 0, L_0x84a878be0; 1 drivers +v0x84b16bca0_0 .net/s "acc_out", 31 0, L_0x84ac8b480; alias, 1 drivers +v0x84b16bd40_0 .net/s "product", 15 0, L_0x84b196800; 1 drivers +v0x84b16bde0_0 .net/s "product_ext", 31 0, L_0x84b1968a0; 1 drivers +v0x84b16be80_0 .net/s "w", 7 0, L_0x84aecc8c0; 1 drivers +v0x84b16bf20_0 .net/s "x", 7 0, L_0x84aecc820; 1 drivers +L_0x84b1966c0 .extend/s 16, L_0x84aecc820; +L_0x84b196760 .extend/s 16, L_0x84aecc8c0; +L_0x84b196800 .arith/mult 16, L_0x84b1966c0, L_0x84b196760; +L_0x84aecc6e0 .part L_0x84b196800, 15, 1; +L_0x84aecc780 .repeat 16, 16, L_0x84aecc6e0; +L_0x84b1968a0 .concat [ 16 16 0 0], L_0x84b196800, L_0x84aecc780; +L_0x84ac8b480 .arith/sum 32, L_0x84a878be0, L_0x84b1968a0; +S_0x84ae8b180 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151a80 .param/l "i" 1 8 20, +C4<0111>; +S_0x84ae8b300 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae8b180; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158f00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b158f40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b158f80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16c000_0 .net/s *"_ivl_0", 15 0, L_0x84b196940; 1 drivers +v0x84b16c0a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1969e0; 1 drivers +v0x84b16c140_0 .net *"_ivl_7", 0 0, L_0x84aecc960; 1 drivers +v0x84b16c1e0_0 .net *"_ivl_9", 15 0, L_0x84aecca00; 1 drivers +L_0x84a878c28 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16c280_0 .net/s "acc_in", 31 0, L_0x84a878c28; 1 drivers +v0x84b16c320_0 .net/s "acc_out", 31 0, L_0x84ac8b520; alias, 1 drivers +v0x84b16c3c0_0 .net/s "product", 15 0, L_0x84b196a80; 1 drivers +v0x84b16c460_0 .net/s "product_ext", 31 0, L_0x84b196b20; 1 drivers +v0x84b16c500_0 .net/s "w", 7 0, L_0x84aeccb40; 1 drivers +v0x84b16c5a0_0 .net/s "x", 7 0, L_0x84aeccaa0; 1 drivers +L_0x84b196940 .extend/s 16, L_0x84aeccaa0; +L_0x84b1969e0 .extend/s 16, L_0x84aeccb40; +L_0x84b196a80 .arith/mult 16, L_0x84b196940, L_0x84b1969e0; +L_0x84aecc960 .part L_0x84b196a80, 15, 1; +L_0x84aecca00 .repeat 16, 16, L_0x84aecc960; +L_0x84b196b20 .concat [ 16 16 0 0], L_0x84b196a80, L_0x84aecca00; +L_0x84ac8b520 .arith/sum 32, L_0x84a878c28, L_0x84b196b20; +S_0x84ae8b480 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151ac0 .param/l "i" 1 8 80, +C4<00>; +L_0x84ac3f720 .functor BUFZ 32, L_0x84ac8b0c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8b600 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151b00 .param/l "i" 1 8 80, +C4<01>; +L_0x84ac3f790 .functor BUFZ 32, L_0x84ac8b160, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8b780 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151b40 .param/l "i" 1 8 80, +C4<010>; +L_0x84ac3f800 .functor BUFZ 32, L_0x84ac8b200, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8b900 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151b80 .param/l "i" 1 8 80, +C4<011>; +L_0x84ac3f870 .functor BUFZ 32, L_0x84ac8b2a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8ba80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151bc0 .param/l "i" 1 8 80, +C4<0100>; +L_0x84ac3f8e0 .functor BUFZ 32, L_0x84ac8b340, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8bc00 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151c00 .param/l "i" 1 8 80, +C4<0101>; +L_0x84ac3f950 .functor BUFZ 32, L_0x84ac8b3e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae8bd80 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151c40 .param/l "i" 1 8 80, +C4<0110>; +L_0x84ac3f9c0 .functor BUFZ 32, L_0x84ac8b480, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae94000 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151c80 .param/l "i" 1 8 80, +C4<0111>; +L_0x84ac3fa30 .functor BUFZ 32, L_0x84ac8b520, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae94180 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151cc0 .param/l "level" 1 8 92, +C4<00>; +S_0x84ae94300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae94180; + .timescale 0 0; +P_0x84b151d00 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8b5c0 .arith/sum 32, L_0x84ac3f720, L_0x84ac3f790; +S_0x84ae94480 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae94180; + .timescale 0 0; +P_0x84b151d40 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8b660 .arith/sum 32, L_0x84ac3f800, L_0x84ac3f870; +S_0x84ae94600 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84ae94180; + .timescale 0 0; +P_0x84b151d80 .param/l "node" 1 8 94, +C4<010>; +L_0x84ac8b700 .arith/sum 32, L_0x84ac3f8e0, L_0x84ac3f950; +S_0x84ae94780 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84ae94180; + .timescale 0 0; +P_0x84b151dc0 .param/l "node" 1 8 94, +C4<011>; +L_0x84ac8b7a0 .arith/sum 32, L_0x84ac3f9c0, L_0x84ac3fa30; +S_0x84ae94900 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151e00 .param/l "level" 1 8 92, +C4<01>; +S_0x84ae94a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae94900; + .timescale 0 0; +P_0x84b151e40 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8b840 .arith/sum 32, L_0x84ac8b5c0, L_0x84ac8b660; +S_0x84ae94c00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae94900; + .timescale 0 0; +P_0x84b151e80 .param/l "node" 1 8 94, +C4<01>; +L_0x84ac8b8e0 .arith/sum 32, L_0x84ac8b700, L_0x84ac8b7a0; +S_0x84ae94d80 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84ae89b00; + .timescale 0 0; +P_0x84b151ec0 .param/l "level" 1 8 92, +C4<010>; +S_0x84ae94f00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae94d80; + .timescale 0 0; +P_0x84b151f00 .param/l "node" 1 8 94, +C4<00>; +L_0x84ac8b980 .arith/sum 32, L_0x84ac8b840, L_0x84ac8b8e0; +S_0x84ae95080 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b151f40 .param/l "n" 1 12 34, +C4<010>; +S_0x84ae95200 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84ae95080; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e666b0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e666f0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e66730 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e66770 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e667b0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e667f0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e66830 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c230 .functor BUFZ 16, L_0x8d321ec60, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2cf70c0_0 .net *"_ivl_0", 31 0, L_0x8d3196300; 1 drivers -v0x8d2cf7160_0 .net *"_ivl_11", 31 0, L_0x8d2d1ae40; 1 drivers -v0x8d2cf7200_0 .net *"_ivl_14", 31 0, L_0x8d31963a0; 1 drivers -L_0x8d2854958 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf72a0_0 .net *"_ivl_17", 28 0, L_0x8d2854958; 1 drivers -L_0x8d28549a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf7340_0 .net/2u *"_ivl_18", 31 0, L_0x8d28549a0; 1 drivers -v0x8d2cf73e0_0 .net *"_ivl_21", 31 0, L_0x8d2d1aee0; 1 drivers -L_0x8d28549e8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf7480_0 .net/2u *"_ivl_22", 31 0, L_0x8d28549e8; 1 drivers -v0x8d2cf7520_0 .net *"_ivl_25", 31 0, L_0x8d2d1af80; 1 drivers -L_0x8d2854880 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf75c0_0 .net *"_ivl_3", 28 0, L_0x8d2854880; 1 drivers -v0x8d2cf7660_0 .net *"_ivl_31", 0 0, L_0x8d321e9e0; 1 drivers -v0x8d2cf7700_0 .net *"_ivl_33", 23 0, L_0x8d2d1c460; 1 drivers -v0x8d2cf77a0_0 .net *"_ivl_36", 39 0, L_0x8d31973e0; 1 drivers -v0x8d2cf7840_0 .net *"_ivl_38", 31 0, L_0x8d321ea80; 1 drivers -L_0x8d28548c8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf78e0_0 .net/2u *"_ivl_4", 31 0, L_0x8d28548c8; 1 drivers -L_0x8d2854c70 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf7980_0 .net *"_ivl_40", 7 0, L_0x8d2854c70; 1 drivers -v0x8d2cf7a20_0 .net *"_ivl_46", 31 0, L_0x8d321eb20; 1 drivers -v0x8d2cf7ac0_0 .net *"_ivl_7", 31 0, L_0x8d2d1ada0; 1 drivers -L_0x8d2854910 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf7b60_0 .net/2u *"_ivl_8", 31 0, L_0x8d2854910; 1 drivers -v0x8d2cf7c00_0 .var/s "acc", 39 0; -v0x8d2cf7ca0_0 .net/s "acc_next", 39 0, L_0x8d31972a0; 1 drivers -v0x8d2cf7d40_0 .net/s "bias", 15 0, L_0x8d321ec60; 1 drivers -v0x8d2cf7de0_0 .net/s "bias_ext", 39 0, L_0x8d3197340; 1 drivers -v0x8d2cf7e80_0 .net/s "bias_ext_small", 15 0, L_0x8d307c230; 1 drivers -v0x8d2cf7f20_0 .var "busy", 0 0; -v0x8d2cfc000_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2cfc0a0_0 .var "done", 0 0; -v0x8d2cfc140_0 .net/s "final_acc", 39 0, L_0x8d3197480; 1 drivers -v0x8d2cfc1e0_0 .net/s "final_value", 39 0, L_0x8d2d1c500; 1 drivers -v0x8d2cfc280_0 .var "group_index", 2 0; -v0x8d2cfc320_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2cfc3c0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2cfc460_0 .net/s "w_bus", 1023 0, L_0x8d321ebc0; 1 drivers -v0x8d2cfc500_0 .net/s "w_group", 127 0, L_0x8d321da40; 1 drivers -v0x8d2cfc5a0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2cfc640_0 .net/s "x_group", 127 0, L_0x8d321d9a0; 1 drivers -v0x8d2cfc6e0_0 .var/s "y", 15 0; -L_0x8d3196300 .concat [ 3 29 0 0], v0x8d2cfc280_0, L_0x8d2854880; -L_0x8d2d1ada0 .arith/mult 32, L_0x8d3196300, L_0x8d28548c8; -L_0x8d2d1ae40 .arith/mult 32, L_0x8d2d1ada0, L_0x8d2854910; -L_0x8d321d9a0 .part/v v0x8d2d17ca0_0, L_0x8d2d1ae40, 128; -L_0x8d31963a0 .concat [ 3 29 0 0], v0x8d2cfc280_0, L_0x8d2854958; -L_0x8d2d1aee0 .arith/mult 32, L_0x8d31963a0, L_0x8d28549a0; -L_0x8d2d1af80 .arith/mult 32, L_0x8d2d1aee0, L_0x8d28549e8; -L_0x8d321da40 .part/v L_0x8d321ebc0, L_0x8d2d1af80, 128; -L_0x8d321e9e0 .part L_0x8d307c230, 15, 1; -L_0x8d2d1c460 .repeat 24, 24, L_0x8d321e9e0; -L_0x8d3197340 .concat [ 16 24 0 0], L_0x8d307c230, L_0x8d2d1c460; -L_0x8d321ea80 .part L_0x8d3197340, 0, 32; -L_0x8d31973e0 .concat [ 8 32 0 0], L_0x8d2854c70, L_0x8d321ea80; -L_0x8d3197480 .arith/sum 40, L_0x8d31972a0, L_0x8d31973e0; -L_0x8d321eb20 .part L_0x8d3197480, 8, 32; -L_0x8d2d1c500 .extend/s 40, L_0x8d321eb20; -S_0x8d31fd980 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fd800; +P_0x84ae95380 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84ae953c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84ae95400 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84ae95440 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84ae95480 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84ae954c0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b1712c0_0 .net *"_ivl_0", 31 0, L_0x84b196d00; 1 drivers +v0x84b171360_0 .net *"_ivl_11", 31 0, L_0x84b196e40; 1 drivers +v0x84b171400_0 .net *"_ivl_14", 31 0, L_0x84b196ee0; 1 drivers +L_0x84a878d48 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1714a0_0 .net *"_ivl_17", 29 0, L_0x84a878d48; 1 drivers +L_0x84a878d90 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b171540_0 .net/2u *"_ivl_18", 31 0, L_0x84a878d90; 1 drivers +v0x84b1715e0_0 .net *"_ivl_21", 31 0, L_0x84b196f80; 1 drivers +L_0x84a878dd8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b171680_0 .net/2u *"_ivl_22", 31 0, L_0x84a878dd8; 1 drivers +v0x84b171720_0 .net *"_ivl_25", 31 0, L_0x84b197020; 1 drivers +v0x84b1717c0_0 .net *"_ivl_29", 0 0, L_0x84aece3a0; 1 drivers +L_0x84a878c70 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b171860_0 .net *"_ivl_3", 29 0, L_0x84a878c70; 1 drivers +v0x84b171900_0 .net *"_ivl_31", 23 0, L_0x84aece440; 1 drivers +L_0x84a878cb8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1719a0_0 .net/2u *"_ivl_4", 31 0, L_0x84a878cb8; 1 drivers +v0x84b171a40_0 .net *"_ivl_7", 31 0, L_0x84b196da0; 1 drivers +L_0x84a878d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b171ae0_0 .net/2u *"_ivl_8", 31 0, L_0x84a878d00; 1 drivers +v0x84b171b80_0 .var/s "acc", 31 0; +v0x84b171c20_0 .net/s "acc_next", 31 0, L_0x84aed0500; 1 drivers +v0x84b171cc0_0 .net/s "bias", 7 0, L_0x84aece580; 1 drivers +v0x84b171d60_0 .net/s "bias_ext", 31 0, L_0x84b1985a0; 1 drivers +v0x84b171e00_0 .var "busy", 0 0; +v0x84b171ea0_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b171f40_0 .var "done", 0 0; +v0x84b171fe0_0 .net/s "final_acc", 31 0, L_0x84aed05a0; 1 drivers +v0x84b172080_0 .var "group_index", 1 0; +v0x84b172120_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b1721c0_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b172260_0 .net/s "w_bus", 255 0, L_0x84aece4e0; 1 drivers +v0x84b172300_0 .net/s "w_group", 63 0, L_0x84aeccf00; 1 drivers +v0x84b1723a0_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b172440_0 .net/s "x_group", 63 0, L_0x84aecce60; 1 drivers +v0x84b1724e0_0 .var/s "y", 7 0; +L_0x84b196d00 .concat [ 2 30 0 0], v0x84b172080_0, L_0x84a878c70; +L_0x84b196da0 .arith/mult 32, L_0x84b196d00, L_0x84a878cb8; +L_0x84b196e40 .arith/mult 32, L_0x84b196da0, L_0x84a878d00; +L_0x84aecce60 .part/v v0x84b191e00_0, L_0x84b196e40, 64; +L_0x84b196ee0 .concat [ 2 30 0 0], v0x84b172080_0, L_0x84a878d48; +L_0x84b196f80 .arith/mult 32, L_0x84b196ee0, L_0x84a878d90; +L_0x84b197020 .arith/mult 32, L_0x84b196f80, L_0x84a878dd8; +L_0x84aeccf00 .part/v L_0x84aece4e0, L_0x84b197020, 64; +L_0x84aece3a0 .part L_0x84aece580, 7, 1; +L_0x84aece440 .repeat 24, 24, L_0x84aece3a0; +L_0x84b1985a0 .concat [ 8 24 0 0], L_0x84aece580, L_0x84aece440; +L_0x84aed05a0 .arith/sum 32, L_0x84aed0500, L_0x84b1985a0; +S_0x84ae95500 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84ae95200; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0700 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a0740 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2cf64e0_0 .net/s "acc_in", 39 0, v0x8d2cf7c00_0; 1 drivers -v0x8d2cf6580_0 .net/s "acc_out", 39 0, L_0x8d31972a0; alias, 1 drivers -v0x8d2cf6620_0 .net/s "m0", 39 0, L_0x8d31964e0; 1 drivers -v0x8d2cf66c0_0 .net/s "m1", 39 0, L_0x8d3196620; 1 drivers -v0x8d2cf6760_0 .net/s "m2", 39 0, L_0x8d3196760; 1 drivers -v0x8d2cf6800_0 .net/s "m3", 39 0, L_0x8d31968a0; 1 drivers -v0x8d2cf68a0_0 .net/s "m4", 39 0, L_0x8d31969e0; 1 drivers -v0x8d2cf6940_0 .net/s "m5", 39 0, L_0x8d3196b20; 1 drivers -v0x8d2cf69e0_0 .net/s "m6", 39 0, L_0x8d3196c60; 1 drivers -v0x8d2cf6a80_0 .net/s "m7", 39 0, L_0x8d3196da0; 1 drivers -v0x8d2cf6b20_0 .net/s "s0", 39 0, L_0x8d3196e40; 1 drivers -v0x8d2cf6bc0_0 .net/s "s1", 39 0, L_0x8d3196ee0; 1 drivers -v0x8d2cf6c60_0 .net/s "s2", 39 0, L_0x8d3196f80; 1 drivers -v0x8d2cf6d00_0 .net/s "s3", 39 0, L_0x8d3197020; 1 drivers -v0x8d2cf6da0_0 .net/s "s4", 39 0, L_0x8d31970c0; 1 drivers -v0x8d2cf6e40_0 .net/s "s5", 39 0, L_0x8d3197160; 1 drivers -v0x8d2cf6ee0_0 .net/s "sum", 39 0, L_0x8d3197200; 1 drivers -v0x8d2cf6f80_0 .net/s "w_bus", 127 0, L_0x8d321da40; alias, 1 drivers -v0x8d2cf7020_0 .net/s "x_bus", 127 0, L_0x8d321d9a0; alias, 1 drivers -L_0x8d321db80 .part L_0x8d321d9a0, 0, 16; -L_0x8d321dc20 .part L_0x8d321da40, 0, 16; -L_0x8d321dd60 .part L_0x8d321d9a0, 16, 16; -L_0x8d321de00 .part L_0x8d321da40, 16, 16; -L_0x8d321df40 .part L_0x8d321d9a0, 32, 16; -L_0x8d321dfe0 .part L_0x8d321da40, 32, 16; -L_0x8d321e120 .part L_0x8d321d9a0, 48, 16; -L_0x8d321e1c0 .part L_0x8d321da40, 48, 16; -L_0x8d321e300 .part L_0x8d321d9a0, 64, 16; -L_0x8d321e3a0 .part L_0x8d321da40, 64, 16; -L_0x8d321e4e0 .part L_0x8d321d9a0, 80, 16; -L_0x8d321e580 .part L_0x8d321da40, 80, 16; -L_0x8d321e6c0 .part L_0x8d321d9a0, 96, 16; -L_0x8d321e760 .part L_0x8d321da40, 96, 16; -L_0x8d321e8a0 .part L_0x8d321d9a0, 112, 16; -L_0x8d321e940 .part L_0x8d321da40, 112, 16; -L_0x8d3196e40 .arith/sum 40, L_0x8d31964e0, L_0x8d3196620; -L_0x8d3196ee0 .arith/sum 40, L_0x8d3196760, L_0x8d31968a0; -L_0x8d3196f80 .arith/sum 40, L_0x8d31969e0, L_0x8d3196b20; -L_0x8d3197020 .arith/sum 40, L_0x8d3196c60, L_0x8d3196da0; -L_0x8d31970c0 .arith/sum 40, L_0x8d3196e40, L_0x8d3196ee0; -L_0x8d3197160 .arith/sum 40, L_0x8d3196f80, L_0x8d3197020; -L_0x8d3197200 .arith/sum 40, L_0x8d31970c0, L_0x8d3197160; -L_0x8d31972a0 .arith/sum 40, v0x8d2cf7c00_0, L_0x8d3197200; -S_0x8d31fdb00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fd980; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8500 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8540 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8580 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc85c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b170f00_0 .net/s "acc_in", 31 0, v0x84b171b80_0; 1 drivers +v0x84b170fa0_0 .net/s "acc_out", 31 0, L_0x84aed0500; alias, 1 drivers +v0x84b171040 .array "products", 7 0; +v0x84b171040_0 .net/s v0x84b171040 0, 31 0, L_0x84ac8bb60; 1 drivers +v0x84b171040_1 .net/s v0x84b171040 1, 31 0, L_0x84ac8bc00; 1 drivers +v0x84b171040_2 .net/s v0x84b171040 2, 31 0, L_0x84ac8bca0; 1 drivers +v0x84b171040_3 .net/s v0x84b171040 3, 31 0, L_0x84ac8bd40; 1 drivers +v0x84b171040_4 .net/s v0x84b171040 4, 31 0, L_0x84ac8bde0; 1 drivers +v0x84b171040_5 .net/s v0x84b171040 5, 31 0, L_0x84ac8be80; 1 drivers +v0x84b171040_6 .net/s v0x84b171040 6, 31 0, L_0x84ac8bf20; 1 drivers +v0x84b171040_7 .net/s v0x84b171040 7, 31 0, L_0x84aed0000; 1 drivers +v0x84b1710e0 .array "tree", 31 0; +v0x84b1710e0_0 .net/s v0x84b1710e0 0, 31 0, L_0x84ac3faa0; 1 drivers +v0x84b1710e0_1 .net/s v0x84b1710e0 1, 31 0, L_0x84ac3fb10; 1 drivers +v0x84b1710e0_2 .net/s v0x84b1710e0 2, 31 0, L_0x84ac3fb80; 1 drivers +v0x84b1710e0_3 .net/s v0x84b1710e0 3, 31 0, L_0x84ac3fbf0; 1 drivers +v0x84b1710e0_4 .net/s v0x84b1710e0 4, 31 0, L_0x84ac3fc60; 1 drivers +v0x84b1710e0_5 .net/s v0x84b1710e0 5, 31 0, L_0x84ac3fcd0; 1 drivers +v0x84b1710e0_6 .net/s v0x84b1710e0 6, 31 0, L_0x84ac3fd40; 1 drivers +v0x84b1710e0_7 .net/s v0x84b1710e0 7, 31 0, L_0x84ac3fdb0; 1 drivers +v0x84b1710e0_8 .net/s v0x84b1710e0 8, 31 0, L_0x84aed00a0; 1 drivers +v0x84b1710e0_9 .net/s v0x84b1710e0 9, 31 0, L_0x84aed0140; 1 drivers +v0x84b1710e0_10 .net/s v0x84b1710e0 10, 31 0, L_0x84aed01e0; 1 drivers +v0x84b1710e0_11 .net/s v0x84b1710e0 11, 31 0, L_0x84aed0280; 1 drivers +o0x84a84f830 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_12 .net/s v0x84b1710e0 12, 31 0, o0x84a84f830; 0 drivers +o0x84a84f860 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_13 .net/s v0x84b1710e0 13, 31 0, o0x84a84f860; 0 drivers +o0x84a84f890 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_14 .net/s v0x84b1710e0 14, 31 0, o0x84a84f890; 0 drivers +o0x84a84f8c0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_15 .net/s v0x84b1710e0 15, 31 0, o0x84a84f8c0; 0 drivers +v0x84b1710e0_16 .net/s v0x84b1710e0 16, 31 0, L_0x84aed0320; 1 drivers +v0x84b1710e0_17 .net/s v0x84b1710e0 17, 31 0, L_0x84aed03c0; 1 drivers +o0x84a84f950 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_18 .net/s v0x84b1710e0 18, 31 0, o0x84a84f950; 0 drivers +o0x84a84f980 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_19 .net/s v0x84b1710e0 19, 31 0, o0x84a84f980; 0 drivers +o0x84a84f9b0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_20 .net/s v0x84b1710e0 20, 31 0, o0x84a84f9b0; 0 drivers +o0x84a84f9e0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_21 .net/s v0x84b1710e0 21, 31 0, o0x84a84f9e0; 0 drivers +o0x84a84fa10 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_22 .net/s v0x84b1710e0 22, 31 0, o0x84a84fa10; 0 drivers +o0x84a84fa40 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_23 .net/s v0x84b1710e0 23, 31 0, o0x84a84fa40; 0 drivers +v0x84b1710e0_24 .net/s v0x84b1710e0 24, 31 0, L_0x84aed0460; 1 drivers +o0x84a84faa0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_25 .net/s v0x84b1710e0 25, 31 0, o0x84a84faa0; 0 drivers +o0x84a84fad0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_26 .net/s v0x84b1710e0 26, 31 0, o0x84a84fad0; 0 drivers +o0x84a84fb00 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_27 .net/s v0x84b1710e0 27, 31 0, o0x84a84fb00; 0 drivers +o0x84a84fb30 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_28 .net/s v0x84b1710e0 28, 31 0, o0x84a84fb30; 0 drivers +o0x84a84fb60 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_29 .net/s v0x84b1710e0 29, 31 0, o0x84a84fb60; 0 drivers +o0x84a84fb90 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_30 .net/s v0x84b1710e0 30, 31 0, o0x84a84fb90; 0 drivers +o0x84a84fbc0 .functor BUFZ 32, c4; HiZ drive +v0x84b1710e0_31 .net/s v0x84b1710e0 31, 31 0, o0x84a84fbc0; 0 drivers +v0x84b171180_0 .net/s "w_bus", 63 0, L_0x84aeccf00; alias, 1 drivers +v0x84b171220_0 .net/s "x_bus", 63 0, L_0x84aecce60; alias, 1 drivers +L_0x84aecd0e0 .part L_0x84aecce60, 0, 8; +L_0x84aecd180 .part L_0x84aeccf00, 0, 8; +L_0x84aecd360 .part L_0x84aecce60, 8, 8; +L_0x84aecd400 .part L_0x84aeccf00, 8, 8; +L_0x84aecd5e0 .part L_0x84aecce60, 16, 8; +L_0x84aecd680 .part L_0x84aeccf00, 16, 8; +L_0x84aecd860 .part L_0x84aecce60, 24, 8; +L_0x84aecd900 .part L_0x84aeccf00, 24, 8; +L_0x84aecdae0 .part L_0x84aecce60, 32, 8; +L_0x84aecdb80 .part L_0x84aeccf00, 32, 8; +L_0x84aecdd60 .part L_0x84aecce60, 40, 8; +L_0x84aecde00 .part L_0x84aeccf00, 40, 8; +L_0x84aecdfe0 .part L_0x84aecce60, 48, 8; +L_0x84aece080 .part L_0x84aeccf00, 48, 8; +L_0x84aece260 .part L_0x84aecce60, 56, 8; +L_0x84aece300 .part L_0x84aeccf00, 56, 8; +L_0x84aed0500 .arith/sum 32, v0x84b171b80_0, L_0x84aed0460; +S_0x84ae95680 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84ae95500; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ccc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cd00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cd40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf32a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b020; 1 drivers -v0x8d2cf3340_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b0c0; 1 drivers -v0x8d2cf33e0_0 .net *"_ivl_7", 0 0, L_0x8d321dae0; 1 drivers -v0x8d2cf3480_0 .net *"_ivl_9", 7 0, L_0x8d2d1b200; 1 drivers -L_0x8d2854a30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf3520_0 .net/s "acc_in", 39 0, L_0x8d2854a30; 1 drivers -v0x8d2cf35c0_0 .net/s "acc_out", 39 0, L_0x8d31964e0; alias, 1 drivers -v0x8d2cf3660_0 .net/s "product", 31 0, L_0x8d2d1b160; 1 drivers -v0x8d2cf3700_0 .net/s "product_ext", 39 0, L_0x8d3196440; 1 drivers -v0x8d2cf37a0_0 .net/s "w", 15 0, L_0x8d321dc20; 1 drivers -v0x8d2cf3840_0 .net/s "x", 15 0, L_0x8d321db80; 1 drivers -L_0x8d2d1b020 .extend/s 32, L_0x8d321db80; -L_0x8d2d1b0c0 .extend/s 32, L_0x8d321dc20; -L_0x8d2d1b160 .arith/mult 32, L_0x8d2d1b020, L_0x8d2d1b0c0; -L_0x8d321dae0 .part L_0x8d2d1b160, 31, 1; -L_0x8d2d1b200 .repeat 8, 8, L_0x8d321dae0; -L_0x8d3196440 .concat [ 32 8 0 0], L_0x8d2d1b160, L_0x8d2d1b200; -L_0x8d31964e0 .arith/sum 40, L_0x8d2854a30, L_0x8d3196440; -S_0x8d31fdc80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fd980; +P_0x84b151f80 .param/l "i" 1 8 20, +C4<00>; +S_0x84ae95800 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae95680; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306cd80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cdc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ce00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf38e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b2a0; 1 drivers -v0x8d2cf3980_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b340; 1 drivers -v0x8d2cf3a20_0 .net *"_ivl_7", 0 0, L_0x8d321dcc0; 1 drivers -v0x8d2cf3ac0_0 .net *"_ivl_9", 7 0, L_0x8d2d1b480; 1 drivers -L_0x8d2854a78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf3b60_0 .net/s "acc_in", 39 0, L_0x8d2854a78; 1 drivers -v0x8d2cf3c00_0 .net/s "acc_out", 39 0, L_0x8d3196620; alias, 1 drivers -v0x8d2cf3ca0_0 .net/s "product", 31 0, L_0x8d2d1b3e0; 1 drivers -v0x8d2cf3d40_0 .net/s "product_ext", 39 0, L_0x8d3196580; 1 drivers -v0x8d2cf3de0_0 .net/s "w", 15 0, L_0x8d321de00; 1 drivers -v0x8d2cf3e80_0 .net/s "x", 15 0, L_0x8d321dd60; 1 drivers -L_0x8d2d1b2a0 .extend/s 32, L_0x8d321dd60; -L_0x8d2d1b340 .extend/s 32, L_0x8d321de00; -L_0x8d2d1b3e0 .arith/mult 32, L_0x8d2d1b2a0, L_0x8d2d1b340; -L_0x8d321dcc0 .part L_0x8d2d1b3e0, 31, 1; -L_0x8d2d1b480 .repeat 8, 8, L_0x8d321dcc0; -L_0x8d3196580 .concat [ 32 8 0 0], L_0x8d2d1b3e0, L_0x8d2d1b480; -L_0x8d3196620 .arith/sum 40, L_0x8d2854a78, L_0x8d3196580; -S_0x8d31fde00 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fd980; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b158fc0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159000 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159040 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16dcc0_0 .net/s *"_ivl_0", 15 0, L_0x84b1970c0; 1 drivers +v0x84b16dd60_0 .net/s *"_ivl_2", 15 0, L_0x84b197160; 1 drivers +v0x84b16de00_0 .net *"_ivl_7", 0 0, L_0x84aeccfa0; 1 drivers +v0x84b16dea0_0 .net *"_ivl_9", 15 0, L_0x84aecd040; 1 drivers +L_0x84a878e20 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16df40_0 .net/s "acc_in", 31 0, L_0x84a878e20; 1 drivers +v0x84b16dfe0_0 .net/s "acc_out", 31 0, L_0x84ac8bb60; alias, 1 drivers +v0x84b16e080_0 .net/s "product", 15 0, L_0x84b197200; 1 drivers +v0x84b16e120_0 .net/s "product_ext", 31 0, L_0x84b1972a0; 1 drivers +v0x84b16e1c0_0 .net/s "w", 7 0, L_0x84aecd180; 1 drivers +v0x84b16e260_0 .net/s "x", 7 0, L_0x84aecd0e0; 1 drivers +L_0x84b1970c0 .extend/s 16, L_0x84aecd0e0; +L_0x84b197160 .extend/s 16, L_0x84aecd180; +L_0x84b197200 .arith/mult 16, L_0x84b1970c0, L_0x84b197160; +L_0x84aeccfa0 .part L_0x84b197200, 15, 1; +L_0x84aecd040 .repeat 16, 16, L_0x84aeccfa0; +L_0x84b1972a0 .concat [ 16 16 0 0], L_0x84b197200, L_0x84aecd040; +L_0x84ac8bb60 .arith/sum 32, L_0x84a878e20, L_0x84b1972a0; +S_0x84ae95980 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84ae95500; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ce40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ce80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf3f20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b520; 1 drivers -v0x8d2cf4000_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b5c0; 1 drivers -v0x8d2cf40a0_0 .net *"_ivl_7", 0 0, L_0x8d321dea0; 1 drivers -v0x8d2cf4140_0 .net *"_ivl_9", 7 0, L_0x8d2d1b700; 1 drivers -L_0x8d2854ac0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf41e0_0 .net/s "acc_in", 39 0, L_0x8d2854ac0; 1 drivers -v0x8d2cf4280_0 .net/s "acc_out", 39 0, L_0x8d3196760; alias, 1 drivers -v0x8d2cf4320_0 .net/s "product", 31 0, L_0x8d2d1b660; 1 drivers -v0x8d2cf43c0_0 .net/s "product_ext", 39 0, L_0x8d31966c0; 1 drivers -v0x8d2cf4460_0 .net/s "w", 15 0, L_0x8d321dfe0; 1 drivers -v0x8d2cf4500_0 .net/s "x", 15 0, L_0x8d321df40; 1 drivers -L_0x8d2d1b520 .extend/s 32, L_0x8d321df40; -L_0x8d2d1b5c0 .extend/s 32, L_0x8d321dfe0; -L_0x8d2d1b660 .arith/mult 32, L_0x8d2d1b520, L_0x8d2d1b5c0; -L_0x8d321dea0 .part L_0x8d2d1b660, 31, 1; -L_0x8d2d1b700 .repeat 8, 8, L_0x8d321dea0; -L_0x8d31966c0 .concat [ 32 8 0 0], L_0x8d2d1b660, L_0x8d2d1b700; -L_0x8d3196760 .arith/sum 40, L_0x8d2854ac0, L_0x8d31966c0; -S_0x8d31fdf80 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fd980; +P_0x84b151fc0 .param/l "i" 1 8 20, +C4<01>; +S_0x84ae95b00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae95980; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306cf00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306cf40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306cf80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf45a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b7a0; 1 drivers -v0x8d2cf4640_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b840; 1 drivers -v0x8d2cf46e0_0 .net *"_ivl_7", 0 0, L_0x8d321e080; 1 drivers -v0x8d2cf4780_0 .net *"_ivl_9", 7 0, L_0x8d2d1b980; 1 drivers -L_0x8d2854b08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf4820_0 .net/s "acc_in", 39 0, L_0x8d2854b08; 1 drivers -v0x8d2cf48c0_0 .net/s "acc_out", 39 0, L_0x8d31968a0; alias, 1 drivers -v0x8d2cf4960_0 .net/s "product", 31 0, L_0x8d2d1b8e0; 1 drivers -v0x8d2cf4a00_0 .net/s "product_ext", 39 0, L_0x8d3196800; 1 drivers -v0x8d2cf4aa0_0 .net/s "w", 15 0, L_0x8d321e1c0; 1 drivers -v0x8d2cf4b40_0 .net/s "x", 15 0, L_0x8d321e120; 1 drivers -L_0x8d2d1b7a0 .extend/s 32, L_0x8d321e120; -L_0x8d2d1b840 .extend/s 32, L_0x8d321e1c0; -L_0x8d2d1b8e0 .arith/mult 32, L_0x8d2d1b7a0, L_0x8d2d1b840; -L_0x8d321e080 .part L_0x8d2d1b8e0, 31, 1; -L_0x8d2d1b980 .repeat 8, 8, L_0x8d321e080; -L_0x8d3196800 .concat [ 32 8 0 0], L_0x8d2d1b8e0, L_0x8d2d1b980; -L_0x8d31968a0 .arith/sum 40, L_0x8d2854b08, L_0x8d3196800; -S_0x8d31fe100 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fd980; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159080 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1590c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159100 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16e300_0 .net/s *"_ivl_0", 15 0, L_0x84b197340; 1 drivers +v0x84b16e3a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1973e0; 1 drivers +v0x84b16e440_0 .net *"_ivl_7", 0 0, L_0x84aecd220; 1 drivers +v0x84b16e4e0_0 .net *"_ivl_9", 15 0, L_0x84aecd2c0; 1 drivers +L_0x84a878e68 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16e580_0 .net/s "acc_in", 31 0, L_0x84a878e68; 1 drivers +v0x84b16e620_0 .net/s "acc_out", 31 0, L_0x84ac8bc00; alias, 1 drivers +v0x84b16e6c0_0 .net/s "product", 15 0, L_0x84b197480; 1 drivers +v0x84b16e760_0 .net/s "product_ext", 31 0, L_0x84b197520; 1 drivers +v0x84b16e800_0 .net/s "w", 7 0, L_0x84aecd400; 1 drivers +v0x84b16e8a0_0 .net/s "x", 7 0, L_0x84aecd360; 1 drivers +L_0x84b197340 .extend/s 16, L_0x84aecd360; +L_0x84b1973e0 .extend/s 16, L_0x84aecd400; +L_0x84b197480 .arith/mult 16, L_0x84b197340, L_0x84b1973e0; +L_0x84aecd220 .part L_0x84b197480, 15, 1; +L_0x84aecd2c0 .repeat 16, 16, L_0x84aecd220; +L_0x84b197520 .concat [ 16 16 0 0], L_0x84b197480, L_0x84aecd2c0; +L_0x84ac8bc00 .arith/sum 32, L_0x84a878e68, L_0x84b197520; +S_0x84ae95c80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84ae95500; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306cfc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d000 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d040 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf4be0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ba20; 1 drivers -v0x8d2cf4c80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1bac0; 1 drivers -v0x8d2cf4d20_0 .net *"_ivl_7", 0 0, L_0x8d321e260; 1 drivers -v0x8d2cf4dc0_0 .net *"_ivl_9", 7 0, L_0x8d2d1bc00; 1 drivers -L_0x8d2854b50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf4e60_0 .net/s "acc_in", 39 0, L_0x8d2854b50; 1 drivers -v0x8d2cf4f00_0 .net/s "acc_out", 39 0, L_0x8d31969e0; alias, 1 drivers -v0x8d2cf4fa0_0 .net/s "product", 31 0, L_0x8d2d1bb60; 1 drivers -v0x8d2cf5040_0 .net/s "product_ext", 39 0, L_0x8d3196940; 1 drivers -v0x8d2cf50e0_0 .net/s "w", 15 0, L_0x8d321e3a0; 1 drivers -v0x8d2cf5180_0 .net/s "x", 15 0, L_0x8d321e300; 1 drivers -L_0x8d2d1ba20 .extend/s 32, L_0x8d321e300; -L_0x8d2d1bac0 .extend/s 32, L_0x8d321e3a0; -L_0x8d2d1bb60 .arith/mult 32, L_0x8d2d1ba20, L_0x8d2d1bac0; -L_0x8d321e260 .part L_0x8d2d1bb60, 31, 1; -L_0x8d2d1bc00 .repeat 8, 8, L_0x8d321e260; -L_0x8d3196940 .concat [ 32 8 0 0], L_0x8d2d1bb60, L_0x8d2d1bc00; -L_0x8d31969e0 .arith/sum 40, L_0x8d2854b50, L_0x8d3196940; -S_0x8d31fe280 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fd980; +P_0x84b152000 .param/l "i" 1 8 20, +C4<010>; +S_0x84ae95e00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae95c80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d080 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d0c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d100 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf5220_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1bca0; 1 drivers -v0x8d2cf52c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1bd40; 1 drivers -v0x8d2cf5360_0 .net *"_ivl_7", 0 0, L_0x8d321e440; 1 drivers -v0x8d2cf5400_0 .net *"_ivl_9", 7 0, L_0x8d2d1be80; 1 drivers -L_0x8d2854b98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf54a0_0 .net/s "acc_in", 39 0, L_0x8d2854b98; 1 drivers -v0x8d2cf5540_0 .net/s "acc_out", 39 0, L_0x8d3196b20; alias, 1 drivers -v0x8d2cf55e0_0 .net/s "product", 31 0, L_0x8d2d1bde0; 1 drivers -v0x8d2cf5680_0 .net/s "product_ext", 39 0, L_0x8d3196a80; 1 drivers -v0x8d2cf5720_0 .net/s "w", 15 0, L_0x8d321e580; 1 drivers -v0x8d2cf57c0_0 .net/s "x", 15 0, L_0x8d321e4e0; 1 drivers -L_0x8d2d1bca0 .extend/s 32, L_0x8d321e4e0; -L_0x8d2d1bd40 .extend/s 32, L_0x8d321e580; -L_0x8d2d1bde0 .arith/mult 32, L_0x8d2d1bca0, L_0x8d2d1bd40; -L_0x8d321e440 .part L_0x8d2d1bde0, 31, 1; -L_0x8d2d1be80 .repeat 8, 8, L_0x8d321e440; -L_0x8d3196a80 .concat [ 32 8 0 0], L_0x8d2d1bde0, L_0x8d2d1be80; -L_0x8d3196b20 .arith/sum 40, L_0x8d2854b98, L_0x8d3196a80; -S_0x8d31fe400 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fd980; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159140 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159180 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1591c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16e940_0 .net/s *"_ivl_0", 15 0, L_0x84b1975c0; 1 drivers +v0x84b16e9e0_0 .net/s *"_ivl_2", 15 0, L_0x84b197660; 1 drivers +v0x84b16ea80_0 .net *"_ivl_7", 0 0, L_0x84aecd4a0; 1 drivers +v0x84b16eb20_0 .net *"_ivl_9", 15 0, L_0x84aecd540; 1 drivers +L_0x84a878eb0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16ebc0_0 .net/s "acc_in", 31 0, L_0x84a878eb0; 1 drivers +v0x84b16ec60_0 .net/s "acc_out", 31 0, L_0x84ac8bca0; alias, 1 drivers +v0x84b16ed00_0 .net/s "product", 15 0, L_0x84b197700; 1 drivers +v0x84b16eda0_0 .net/s "product_ext", 31 0, L_0x84b1977a0; 1 drivers +v0x84b16ee40_0 .net/s "w", 7 0, L_0x84aecd680; 1 drivers +v0x84b16eee0_0 .net/s "x", 7 0, L_0x84aecd5e0; 1 drivers +L_0x84b1975c0 .extend/s 16, L_0x84aecd5e0; +L_0x84b197660 .extend/s 16, L_0x84aecd680; +L_0x84b197700 .arith/mult 16, L_0x84b1975c0, L_0x84b197660; +L_0x84aecd4a0 .part L_0x84b197700, 15, 1; +L_0x84aecd540 .repeat 16, 16, L_0x84aecd4a0; +L_0x84b1977a0 .concat [ 16 16 0 0], L_0x84b197700, L_0x84aecd540; +L_0x84ac8bca0 .arith/sum 32, L_0x84a878eb0, L_0x84b1977a0; +S_0x84ae95f80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84ae95500; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d140 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d180 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d1c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf5860_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1bf20; 1 drivers -v0x8d2cf5900_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c000; 1 drivers -v0x8d2cf59a0_0 .net *"_ivl_7", 0 0, L_0x8d321e620; 1 drivers -v0x8d2cf5a40_0 .net *"_ivl_9", 7 0, L_0x8d2d1c140; 1 drivers -L_0x8d2854be0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf5ae0_0 .net/s "acc_in", 39 0, L_0x8d2854be0; 1 drivers -v0x8d2cf5b80_0 .net/s "acc_out", 39 0, L_0x8d3196c60; alias, 1 drivers -v0x8d2cf5c20_0 .net/s "product", 31 0, L_0x8d2d1c0a0; 1 drivers -v0x8d2cf5cc0_0 .net/s "product_ext", 39 0, L_0x8d3196bc0; 1 drivers -v0x8d2cf5d60_0 .net/s "w", 15 0, L_0x8d321e760; 1 drivers -v0x8d2cf5e00_0 .net/s "x", 15 0, L_0x8d321e6c0; 1 drivers -L_0x8d2d1bf20 .extend/s 32, L_0x8d321e6c0; -L_0x8d2d1c000 .extend/s 32, L_0x8d321e760; -L_0x8d2d1c0a0 .arith/mult 32, L_0x8d2d1bf20, L_0x8d2d1c000; -L_0x8d321e620 .part L_0x8d2d1c0a0, 31, 1; -L_0x8d2d1c140 .repeat 8, 8, L_0x8d321e620; -L_0x8d3196bc0 .concat [ 32 8 0 0], L_0x8d2d1c0a0, L_0x8d2d1c140; -L_0x8d3196c60 .arith/sum 40, L_0x8d2854be0, L_0x8d3196bc0; -S_0x8d31fe580 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fd980; +P_0x84b152040 .param/l "i" 1 8 20, +C4<011>; +S_0x84ae96100 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae95f80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d200 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d240 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d280 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cf5ea0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1c1e0; 1 drivers -v0x8d2cf5f40_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c280; 1 drivers -v0x8d2cf5fe0_0 .net *"_ivl_7", 0 0, L_0x8d321e800; 1 drivers -v0x8d2cf6080_0 .net *"_ivl_9", 7 0, L_0x8d2d1c3c0; 1 drivers -L_0x8d2854c28 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cf6120_0 .net/s "acc_in", 39 0, L_0x8d2854c28; 1 drivers -v0x8d2cf61c0_0 .net/s "acc_out", 39 0, L_0x8d3196da0; alias, 1 drivers -v0x8d2cf6260_0 .net/s "product", 31 0, L_0x8d2d1c320; 1 drivers -v0x8d2cf6300_0 .net/s "product_ext", 39 0, L_0x8d3196d00; 1 drivers -v0x8d2cf63a0_0 .net/s "w", 15 0, L_0x8d321e940; 1 drivers -v0x8d2cf6440_0 .net/s "x", 15 0, L_0x8d321e8a0; 1 drivers -L_0x8d2d1c1e0 .extend/s 32, L_0x8d321e8a0; -L_0x8d2d1c280 .extend/s 32, L_0x8d321e940; -L_0x8d2d1c320 .arith/mult 32, L_0x8d2d1c1e0, L_0x8d2d1c280; -L_0x8d321e800 .part L_0x8d2d1c320, 31, 1; -L_0x8d2d1c3c0 .repeat 8, 8, L_0x8d321e800; -L_0x8d3196d00 .concat [ 32 8 0 0], L_0x8d2d1c320, L_0x8d2d1c3c0; -L_0x8d3196da0 .arith/sum 40, L_0x8d2854c28, L_0x8d3196d00; -S_0x8d31fe700 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159200 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159240 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159280 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16ef80_0 .net/s *"_ivl_0", 15 0, L_0x84b197840; 1 drivers +v0x84b16f020_0 .net/s *"_ivl_2", 15 0, L_0x84b1978e0; 1 drivers +v0x84b16f0c0_0 .net *"_ivl_7", 0 0, L_0x84aecd720; 1 drivers +v0x84b16f160_0 .net *"_ivl_9", 15 0, L_0x84aecd7c0; 1 drivers +L_0x84a878ef8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16f200_0 .net/s "acc_in", 31 0, L_0x84a878ef8; 1 drivers +v0x84b16f2a0_0 .net/s "acc_out", 31 0, L_0x84ac8bd40; alias, 1 drivers +v0x84b16f340_0 .net/s "product", 15 0, L_0x84b197980; 1 drivers +v0x84b16f3e0_0 .net/s "product_ext", 31 0, L_0x84b197a20; 1 drivers +v0x84b16f480_0 .net/s "w", 7 0, L_0x84aecd900; 1 drivers +v0x84b16f520_0 .net/s "x", 7 0, L_0x84aecd860; 1 drivers +L_0x84b197840 .extend/s 16, L_0x84aecd860; +L_0x84b1978e0 .extend/s 16, L_0x84aecd900; +L_0x84b197980 .arith/mult 16, L_0x84b197840, L_0x84b1978e0; +L_0x84aecd720 .part L_0x84b197980, 15, 1; +L_0x84aecd7c0 .repeat 16, 16, L_0x84aecd720; +L_0x84b197a20 .concat [ 16 16 0 0], L_0x84b197980, L_0x84aecd7c0; +L_0x84ac8bd40 .arith/sum 32, L_0x84a878ef8, L_0x84b197a20; +S_0x84ae96280 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84ae95500; .timescale 0 0; -P_0x8d2c3b180 .param/l "n" 1 4 35, +C4<011>; -S_0x8d31fe880 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fe700; +P_0x84b152080 .param/l "i" 1 8 20, +C4<0100>; +S_0x84ae96400 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae96280; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1592c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159300 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159340 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16f5c0_0 .net/s *"_ivl_0", 15 0, L_0x84b197ac0; 1 drivers +v0x84b16f660_0 .net/s *"_ivl_2", 15 0, L_0x84b197b60; 1 drivers +v0x84b16f700_0 .net *"_ivl_7", 0 0, L_0x84aecd9a0; 1 drivers +v0x84b16f7a0_0 .net *"_ivl_9", 15 0, L_0x84aecda40; 1 drivers +L_0x84a878f40 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16f840_0 .net/s "acc_in", 31 0, L_0x84a878f40; 1 drivers +v0x84b16f8e0_0 .net/s "acc_out", 31 0, L_0x84ac8bde0; alias, 1 drivers +v0x84b16f980_0 .net/s "product", 15 0, L_0x84b197c00; 1 drivers +v0x84b16fa20_0 .net/s "product_ext", 31 0, L_0x84b197ca0; 1 drivers +v0x84b16fac0_0 .net/s "w", 7 0, L_0x84aecdb80; 1 drivers +v0x84b16fb60_0 .net/s "x", 7 0, L_0x84aecdae0; 1 drivers +L_0x84b197ac0 .extend/s 16, L_0x84aecdae0; +L_0x84b197b60 .extend/s 16, L_0x84aecdb80; +L_0x84b197c00 .arith/mult 16, L_0x84b197ac0, L_0x84b197b60; +L_0x84aecd9a0 .part L_0x84b197c00, 15, 1; +L_0x84aecda40 .repeat 16, 16, L_0x84aecd9a0; +L_0x84b197ca0 .concat [ 16 16 0 0], L_0x84b197c00, L_0x84aecda40; +L_0x84ac8bde0 .arith/sum 32, L_0x84a878f40, L_0x84b197ca0; +S_0x84ae96580 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b1520c0 .param/l "i" 1 8 20, +C4<0101>; +S_0x84ae96700 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae96580; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159380 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1593c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159400 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b16fc00_0 .net/s *"_ivl_0", 15 0, L_0x84b197d40; 1 drivers +v0x84b16fca0_0 .net/s *"_ivl_2", 15 0, L_0x84b197de0; 1 drivers +v0x84b16fd40_0 .net *"_ivl_7", 0 0, L_0x84aecdc20; 1 drivers +v0x84b16fde0_0 .net *"_ivl_9", 15 0, L_0x84aecdcc0; 1 drivers +L_0x84a878f88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b16fe80_0 .net/s "acc_in", 31 0, L_0x84a878f88; 1 drivers +v0x84b16ff20_0 .net/s "acc_out", 31 0, L_0x84ac8be80; alias, 1 drivers +v0x84b170000_0 .net/s "product", 15 0, L_0x84b197e80; 1 drivers +v0x84b1700a0_0 .net/s "product_ext", 31 0, L_0x84b197f20; 1 drivers +v0x84b170140_0 .net/s "w", 7 0, L_0x84aecde00; 1 drivers +v0x84b1701e0_0 .net/s "x", 7 0, L_0x84aecdd60; 1 drivers +L_0x84b197d40 .extend/s 16, L_0x84aecdd60; +L_0x84b197de0 .extend/s 16, L_0x84aecde00; +L_0x84b197e80 .arith/mult 16, L_0x84b197d40, L_0x84b197de0; +L_0x84aecdc20 .part L_0x84b197e80, 15, 1; +L_0x84aecdcc0 .repeat 16, 16, L_0x84aecdc20; +L_0x84b197f20 .concat [ 16 16 0 0], L_0x84b197e80, L_0x84aecdcc0; +L_0x84ac8be80 .arith/sum 32, L_0x84a878f88, L_0x84b197f20; +S_0x84ae96880 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152100 .param/l "i" 1 8 20, +C4<0110>; +S_0x84ae96a00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae96880; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159440 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159480 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1594c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b170280_0 .net/s *"_ivl_0", 15 0, L_0x84b198000; 1 drivers +v0x84b170320_0 .net/s *"_ivl_2", 15 0, L_0x84b1980a0; 1 drivers +v0x84b1703c0_0 .net *"_ivl_7", 0 0, L_0x84aecdea0; 1 drivers +v0x84b170460_0 .net *"_ivl_9", 15 0, L_0x84aecdf40; 1 drivers +L_0x84a878fd0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b170500_0 .net/s "acc_in", 31 0, L_0x84a878fd0; 1 drivers +v0x84b1705a0_0 .net/s "acc_out", 31 0, L_0x84ac8bf20; alias, 1 drivers +v0x84b170640_0 .net/s "product", 15 0, L_0x84b198140; 1 drivers +v0x84b1706e0_0 .net/s "product_ext", 31 0, L_0x84b1981e0; 1 drivers +v0x84b170780_0 .net/s "w", 7 0, L_0x84aece080; 1 drivers +v0x84b170820_0 .net/s "x", 7 0, L_0x84aecdfe0; 1 drivers +L_0x84b198000 .extend/s 16, L_0x84aecdfe0; +L_0x84b1980a0 .extend/s 16, L_0x84aece080; +L_0x84b198140 .arith/mult 16, L_0x84b198000, L_0x84b1980a0; +L_0x84aecdea0 .part L_0x84b198140, 15, 1; +L_0x84aecdf40 .repeat 16, 16, L_0x84aecdea0; +L_0x84b1981e0 .concat [ 16 16 0 0], L_0x84b198140, L_0x84aecdf40; +L_0x84ac8bf20 .arith/sum 32, L_0x84a878fd0, L_0x84b1981e0; +S_0x84ae96b80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152140 .param/l "i" 1 8 20, +C4<0111>; +S_0x84ae96d00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae96b80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159500 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159540 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159580 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1708c0_0 .net/s *"_ivl_0", 15 0, L_0x84b198280; 1 drivers +v0x84b170960_0 .net/s *"_ivl_2", 15 0, L_0x84b198320; 1 drivers +v0x84b170a00_0 .net *"_ivl_7", 0 0, L_0x84aece120; 1 drivers +v0x84b170aa0_0 .net *"_ivl_9", 15 0, L_0x84aece1c0; 1 drivers +L_0x84a879018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b170b40_0 .net/s "acc_in", 31 0, L_0x84a879018; 1 drivers +v0x84b170be0_0 .net/s "acc_out", 31 0, L_0x84aed0000; alias, 1 drivers +v0x84b170c80_0 .net/s "product", 15 0, L_0x84b1983c0; 1 drivers +v0x84b170d20_0 .net/s "product_ext", 31 0, L_0x84b198460; 1 drivers +v0x84b170dc0_0 .net/s "w", 7 0, L_0x84aece300; 1 drivers +v0x84b170e60_0 .net/s "x", 7 0, L_0x84aece260; 1 drivers +L_0x84b198280 .extend/s 16, L_0x84aece260; +L_0x84b198320 .extend/s 16, L_0x84aece300; +L_0x84b1983c0 .arith/mult 16, L_0x84b198280, L_0x84b198320; +L_0x84aece120 .part L_0x84b1983c0, 15, 1; +L_0x84aece1c0 .repeat 16, 16, L_0x84aece120; +L_0x84b198460 .concat [ 16 16 0 0], L_0x84b1983c0, L_0x84aece1c0; +L_0x84aed0000 .arith/sum 32, L_0x84a879018, L_0x84b198460; +S_0x84ae96e80 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152180 .param/l "i" 1 8 80, +C4<00>; +L_0x84ac3faa0 .functor BUFZ 32, L_0x84ac8bb60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97000 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b1521c0 .param/l "i" 1 8 80, +C4<01>; +L_0x84ac3fb10 .functor BUFZ 32, L_0x84ac8bc00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97180 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152200 .param/l "i" 1 8 80, +C4<010>; +L_0x84ac3fb80 .functor BUFZ 32, L_0x84ac8bca0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97300 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152240 .param/l "i" 1 8 80, +C4<011>; +L_0x84ac3fbf0 .functor BUFZ 32, L_0x84ac8bd40, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97480 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152280 .param/l "i" 1 8 80, +C4<0100>; +L_0x84ac3fc60 .functor BUFZ 32, L_0x84ac8bde0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97600 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b1522c0 .param/l "i" 1 8 80, +C4<0101>; +L_0x84ac3fcd0 .functor BUFZ 32, L_0x84ac8be80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97780 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152300 .param/l "i" 1 8 80, +C4<0110>; +L_0x84ac3fd40 .functor BUFZ 32, L_0x84ac8bf20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97900 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152340 .param/l "i" 1 8 80, +C4<0111>; +L_0x84ac3fdb0 .functor BUFZ 32, L_0x84aed0000, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae97a80 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152380 .param/l "level" 1 8 92, +C4<00>; +S_0x84ae97c00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae97a80; + .timescale 0 0; +P_0x84b1523c0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed00a0 .arith/sum 32, L_0x84ac3faa0, L_0x84ac3fb10; +S_0x84ae97d80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae97a80; + .timescale 0 0; +P_0x84b152400 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed0140 .arith/sum 32, L_0x84ac3fb80, L_0x84ac3fbf0; +S_0x84ae9c000 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84ae97a80; + .timescale 0 0; +P_0x84b152440 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed01e0 .arith/sum 32, L_0x84ac3fc60, L_0x84ac3fcd0; +S_0x84ae9c180 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84ae97a80; + .timescale 0 0; +P_0x84b152480 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed0280 .arith/sum 32, L_0x84ac3fd40, L_0x84ac3fdb0; +S_0x84ae9c300 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b1524c0 .param/l "level" 1 8 92, +C4<01>; +S_0x84ae9c480 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae9c300; + .timescale 0 0; +P_0x84b152500 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed0320 .arith/sum 32, L_0x84aed00a0, L_0x84aed0140; +S_0x84ae9c600 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae9c300; + .timescale 0 0; +P_0x84b152540 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed03c0 .arith/sum 32, L_0x84aed01e0, L_0x84aed0280; +S_0x84ae9c780 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84ae95500; + .timescale 0 0; +P_0x84b152580 .param/l "level" 1 8 92, +C4<010>; +S_0x84ae9c900 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae9c780; + .timescale 0 0; +P_0x84b1525c0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed0460 .arith/sum 32, L_0x84aed0320, L_0x84aed03c0; +S_0x84ae9ca80 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b152600 .param/l "n" 1 12 34, +C4<011>; +S_0x84ae9cc00 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84ae9ca80; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e66a70 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e66ab0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e66af0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e66b30 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e66b70 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e66bb0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e66bf0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c2a0 .functor BUFZ 16, L_0x8d322c000, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2d005a0_0 .net *"_ivl_0", 31 0, L_0x8d3197520; 1 drivers -v0x8d2d00640_0 .net *"_ivl_11", 31 0, L_0x8d2d1c640; 1 drivers -v0x8d2d006e0_0 .net *"_ivl_14", 31 0, L_0x8d31975c0; 1 drivers -L_0x8d2854d90 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00780_0 .net *"_ivl_17", 28 0, L_0x8d2854d90; 1 drivers -L_0x8d2854dd8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00820_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854dd8; 1 drivers -v0x8d2d008c0_0 .net *"_ivl_21", 31 0, L_0x8d2d1c6e0; 1 drivers -L_0x8d2854e20 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00960_0 .net/2u *"_ivl_22", 31 0, L_0x8d2854e20; 1 drivers -v0x8d2d00a00_0 .net *"_ivl_25", 31 0, L_0x8d2d1c780; 1 drivers -L_0x8d2854cb8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00aa0_0 .net *"_ivl_3", 28 0, L_0x8d2854cb8; 1 drivers -v0x8d2d00b40_0 .net *"_ivl_31", 0 0, L_0x8d321fd40; 1 drivers -v0x8d2d00be0_0 .net *"_ivl_33", 23 0, L_0x8d2d1dc20; 1 drivers -v0x8d2d00c80_0 .net *"_ivl_36", 39 0, L_0x8d3228640; 1 drivers -v0x8d2d00d20_0 .net *"_ivl_38", 31 0, L_0x8d321fde0; 1 drivers -L_0x8d2854d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00dc0_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854d00; 1 drivers -L_0x8d28550a8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d00e60_0 .net *"_ivl_40", 7 0, L_0x8d28550a8; 1 drivers -v0x8d2d00f00_0 .net *"_ivl_46", 31 0, L_0x8d321fe80; 1 drivers -v0x8d2d00fa0_0 .net *"_ivl_7", 31 0, L_0x8d2d1c5a0; 1 drivers -L_0x8d2854d48 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d01040_0 .net/2u *"_ivl_8", 31 0, L_0x8d2854d48; 1 drivers -v0x8d2d010e0_0 .var/s "acc", 39 0; -v0x8d2d01180_0 .net/s "acc_next", 39 0, L_0x8d3228500; 1 drivers -v0x8d2d01220_0 .net/s "bias", 15 0, L_0x8d322c000; 1 drivers -v0x8d2d012c0_0 .net/s "bias_ext", 39 0, L_0x8d32285a0; 1 drivers -v0x8d2d01360_0 .net/s "bias_ext_small", 15 0, L_0x8d307c2a0; 1 drivers -v0x8d2d01400_0 .var "busy", 0 0; -v0x8d2d014a0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2d01540_0 .var "done", 0 0; -v0x8d2d015e0_0 .net/s "final_acc", 39 0, L_0x8d32286e0; 1 drivers -v0x8d2d01680_0 .net/s "final_value", 39 0, L_0x8d2d1dcc0; 1 drivers -v0x8d2d01720_0 .var "group_index", 2 0; -v0x8d2d017c0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2d01860_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2d01900_0 .net/s "w_bus", 1023 0, L_0x8d321ff20; 1 drivers -v0x8d2d019a0_0 .net/s "w_group", 127 0, L_0x8d321eda0; 1 drivers -v0x8d2d01a40_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2d01ae0_0 .net/s "x_group", 127 0, L_0x8d321ed00; 1 drivers -v0x8d2d01b80_0 .var/s "y", 15 0; -L_0x8d3197520 .concat [ 3 29 0 0], v0x8d2d01720_0, L_0x8d2854cb8; -L_0x8d2d1c5a0 .arith/mult 32, L_0x8d3197520, L_0x8d2854d00; -L_0x8d2d1c640 .arith/mult 32, L_0x8d2d1c5a0, L_0x8d2854d48; -L_0x8d321ed00 .part/v v0x8d2d17ca0_0, L_0x8d2d1c640, 128; -L_0x8d31975c0 .concat [ 3 29 0 0], v0x8d2d01720_0, L_0x8d2854d90; -L_0x8d2d1c6e0 .arith/mult 32, L_0x8d31975c0, L_0x8d2854dd8; -L_0x8d2d1c780 .arith/mult 32, L_0x8d2d1c6e0, L_0x8d2854e20; -L_0x8d321eda0 .part/v L_0x8d321ff20, L_0x8d2d1c780, 128; -L_0x8d321fd40 .part L_0x8d307c2a0, 15, 1; -L_0x8d2d1dc20 .repeat 24, 24, L_0x8d321fd40; -L_0x8d32285a0 .concat [ 16 24 0 0], L_0x8d307c2a0, L_0x8d2d1dc20; -L_0x8d321fde0 .part L_0x8d32285a0, 0, 32; -L_0x8d3228640 .concat [ 8 32 0 0], L_0x8d28550a8, L_0x8d321fde0; -L_0x8d32286e0 .arith/sum 40, L_0x8d3228500, L_0x8d3228640; -L_0x8d321fe80 .part L_0x8d32286e0, 8, 32; -L_0x8d2d1dcc0 .extend/s 40, L_0x8d321fe80; -S_0x8d31fea00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fe880; +P_0x84ae9cd80 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84ae9cdc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84ae9ce00 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84ae9ce40 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84ae9ce80 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84ae9cec0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b175b80_0 .net *"_ivl_0", 31 0, L_0x84b198640; 1 drivers +v0x84b175c20_0 .net *"_ivl_11", 31 0, L_0x84b198780; 1 drivers +v0x84b175cc0_0 .net *"_ivl_14", 31 0, L_0x84b198820; 1 drivers +L_0x84a879138 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b175d60_0 .net *"_ivl_17", 29 0, L_0x84a879138; 1 drivers +L_0x84a879180 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b175e00_0 .net/2u *"_ivl_18", 31 0, L_0x84a879180; 1 drivers +v0x84b175ea0_0 .net *"_ivl_21", 31 0, L_0x84b1988c0; 1 drivers +L_0x84a8791c8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b175f40_0 .net/2u *"_ivl_22", 31 0, L_0x84a8791c8; 1 drivers +v0x84b175fe0_0 .net *"_ivl_25", 31 0, L_0x84b198960; 1 drivers +v0x84b176080_0 .net *"_ivl_29", 0 0, L_0x84aecfb60; 1 drivers +L_0x84a879060 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b176120_0 .net *"_ivl_3", 29 0, L_0x84a879060; 1 drivers +v0x84b1761c0_0 .net *"_ivl_31", 23 0, L_0x84aecfc00; 1 drivers +L_0x84a8790a8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b176260_0 .net/2u *"_ivl_4", 31 0, L_0x84a8790a8; 1 drivers +v0x84b176300_0 .net *"_ivl_7", 31 0, L_0x84b1986e0; 1 drivers +L_0x84a8790f0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1763a0_0 .net/2u *"_ivl_8", 31 0, L_0x84a8790f0; 1 drivers +v0x84b176440_0 .var/s "acc", 31 0; +v0x84b1764e0_0 .net/s "acc_next", 31 0, L_0x84aed0fa0; 1 drivers +v0x84b176580_0 .net/s "bias", 7 0, L_0x84aecfd40; 1 drivers +v0x84b176620_0 .net/s "bias_ext", 31 0, L_0x84b199ea0; 1 drivers +v0x84b1766c0_0 .var "busy", 0 0; +v0x84b176760_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b176800_0 .var "done", 0 0; +v0x84b1768a0_0 .net/s "final_acc", 31 0, L_0x84aed1040; 1 drivers +v0x84b176940_0 .var "group_index", 1 0; +v0x84b1769e0_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b176a80_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b176b20_0 .net/s "w_bus", 255 0, L_0x84aecfca0; 1 drivers +v0x84b176bc0_0 .net/s "w_group", 63 0, L_0x84aece6c0; 1 drivers +v0x84b176c60_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b176d00_0 .net/s "x_group", 63 0, L_0x84aece620; 1 drivers +v0x84b176da0_0 .var/s "y", 7 0; +L_0x84b198640 .concat [ 2 30 0 0], v0x84b176940_0, L_0x84a879060; +L_0x84b1986e0 .arith/mult 32, L_0x84b198640, L_0x84a8790a8; +L_0x84b198780 .arith/mult 32, L_0x84b1986e0, L_0x84a8790f0; +L_0x84aece620 .part/v v0x84b191e00_0, L_0x84b198780, 64; +L_0x84b198820 .concat [ 2 30 0 0], v0x84b176940_0, L_0x84a879138; +L_0x84b1988c0 .arith/mult 32, L_0x84b198820, L_0x84a879180; +L_0x84b198960 .arith/mult 32, L_0x84b1988c0, L_0x84a8791c8; +L_0x84aece6c0 .part/v L_0x84aecfca0, L_0x84b198960, 64; +L_0x84aecfb60 .part L_0x84aecfd40, 7, 1; +L_0x84aecfc00 .repeat 24, 24, L_0x84aecfb60; +L_0x84b199ea0 .concat [ 8 24 0 0], L_0x84aecfd40, L_0x84aecfc00; +L_0x84aed1040 .arith/sum 32, L_0x84aed0fa0, L_0x84b199ea0; +S_0x84ae9cf00 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84ae9cc00; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a07c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2cff980_0 .net/s "acc_in", 39 0, v0x8d2d010e0_0; 1 drivers -v0x8d2cffa20_0 .net/s "acc_out", 39 0, L_0x8d3228500; alias, 1 drivers -v0x8d2cffac0_0 .net/s "m0", 39 0, L_0x8d3197700; 1 drivers -v0x8d2cffb60_0 .net/s "m1", 39 0, L_0x8d3197840; 1 drivers -v0x8d2cffc00_0 .net/s "m2", 39 0, L_0x8d3197980; 1 drivers -v0x8d2cffca0_0 .net/s "m3", 39 0, L_0x8d3197ac0; 1 drivers -v0x8d2cffd40_0 .net/s "m4", 39 0, L_0x8d3197c00; 1 drivers -v0x8d2cffde0_0 .net/s "m5", 39 0, L_0x8d3197d40; 1 drivers -v0x8d2cffe80_0 .net/s "m6", 39 0, L_0x8d3197e80; 1 drivers -v0x8d2cfff20_0 .net/s "m7", 39 0, L_0x8d3228000; 1 drivers -v0x8d2d00000_0 .net/s "s0", 39 0, L_0x8d32280a0; 1 drivers -v0x8d2d000a0_0 .net/s "s1", 39 0, L_0x8d3228140; 1 drivers -v0x8d2d00140_0 .net/s "s2", 39 0, L_0x8d32281e0; 1 drivers -v0x8d2d001e0_0 .net/s "s3", 39 0, L_0x8d3228280; 1 drivers -v0x8d2d00280_0 .net/s "s4", 39 0, L_0x8d3228320; 1 drivers -v0x8d2d00320_0 .net/s "s5", 39 0, L_0x8d32283c0; 1 drivers -v0x8d2d003c0_0 .net/s "sum", 39 0, L_0x8d3228460; 1 drivers -v0x8d2d00460_0 .net/s "w_bus", 127 0, L_0x8d321eda0; alias, 1 drivers -v0x8d2d00500_0 .net/s "x_bus", 127 0, L_0x8d321ed00; alias, 1 drivers -L_0x8d321eee0 .part L_0x8d321ed00, 0, 16; -L_0x8d321ef80 .part L_0x8d321eda0, 0, 16; -L_0x8d321f0c0 .part L_0x8d321ed00, 16, 16; -L_0x8d321f160 .part L_0x8d321eda0, 16, 16; -L_0x8d321f2a0 .part L_0x8d321ed00, 32, 16; -L_0x8d321f340 .part L_0x8d321eda0, 32, 16; -L_0x8d321f480 .part L_0x8d321ed00, 48, 16; -L_0x8d321f520 .part L_0x8d321eda0, 48, 16; -L_0x8d321f660 .part L_0x8d321ed00, 64, 16; -L_0x8d321f700 .part L_0x8d321eda0, 64, 16; -L_0x8d321f840 .part L_0x8d321ed00, 80, 16; -L_0x8d321f8e0 .part L_0x8d321eda0, 80, 16; -L_0x8d321fa20 .part L_0x8d321ed00, 96, 16; -L_0x8d321fac0 .part L_0x8d321eda0, 96, 16; -L_0x8d321fc00 .part L_0x8d321ed00, 112, 16; -L_0x8d321fca0 .part L_0x8d321eda0, 112, 16; -L_0x8d32280a0 .arith/sum 40, L_0x8d3197700, L_0x8d3197840; -L_0x8d3228140 .arith/sum 40, L_0x8d3197980, L_0x8d3197ac0; -L_0x8d32281e0 .arith/sum 40, L_0x8d3197c00, L_0x8d3197d40; -L_0x8d3228280 .arith/sum 40, L_0x8d3197e80, L_0x8d3228000; -L_0x8d3228320 .arith/sum 40, L_0x8d32280a0, L_0x8d3228140; -L_0x8d32283c0 .arith/sum 40, L_0x8d32281e0, L_0x8d3228280; -L_0x8d3228460 .arith/sum 40, L_0x8d3228320, L_0x8d32283c0; -L_0x8d3228500 .arith/sum 40, v0x8d2d010e0_0, L_0x8d3228460; -S_0x8d31feb80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fea00; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8600 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8640 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8680 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc86c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b1757c0_0 .net/s "acc_in", 31 0, v0x84b176440_0; 1 drivers +v0x84b175860_0 .net/s "acc_out", 31 0, L_0x84aed0fa0; alias, 1 drivers +v0x84b175900 .array "products", 7 0; +v0x84b175900_0 .net/s v0x84b175900 0, 31 0, L_0x84aed0640; 1 drivers +v0x84b175900_1 .net/s v0x84b175900 1, 31 0, L_0x84aed06e0; 1 drivers +v0x84b175900_2 .net/s v0x84b175900 2, 31 0, L_0x84aed0780; 1 drivers +v0x84b175900_3 .net/s v0x84b175900 3, 31 0, L_0x84aed0820; 1 drivers +v0x84b175900_4 .net/s v0x84b175900 4, 31 0, L_0x84aed08c0; 1 drivers +v0x84b175900_5 .net/s v0x84b175900 5, 31 0, L_0x84aed0960; 1 drivers +v0x84b175900_6 .net/s v0x84b175900 6, 31 0, L_0x84aed0a00; 1 drivers +v0x84b175900_7 .net/s v0x84b175900 7, 31 0, L_0x84aed0aa0; 1 drivers +v0x84b1759a0 .array "tree", 31 0; +v0x84b1759a0_0 .net/s v0x84b1759a0 0, 31 0, L_0x84ac3fe20; 1 drivers +v0x84b1759a0_1 .net/s v0x84b1759a0 1, 31 0, L_0x84ac3fe90; 1 drivers +v0x84b1759a0_2 .net/s v0x84b1759a0 2, 31 0, L_0x84ac3ff00; 1 drivers +v0x84b1759a0_3 .net/s v0x84b1759a0 3, 31 0, L_0x84ac3ff70; 1 drivers +v0x84b1759a0_4 .net/s v0x84b1759a0 4, 31 0, L_0x84aed8000; 1 drivers +v0x84b1759a0_5 .net/s v0x84b1759a0 5, 31 0, L_0x84aedc000; 1 drivers +v0x84b1759a0_6 .net/s v0x84b1759a0 6, 31 0, L_0x84aedc070; 1 drivers +v0x84b1759a0_7 .net/s v0x84b1759a0 7, 31 0, L_0x84aedc0e0; 1 drivers +v0x84b1759a0_8 .net/s v0x84b1759a0 8, 31 0, L_0x84aed0b40; 1 drivers +v0x84b1759a0_9 .net/s v0x84b1759a0 9, 31 0, L_0x84aed0be0; 1 drivers +v0x84b1759a0_10 .net/s v0x84b1759a0 10, 31 0, L_0x84aed0c80; 1 drivers +v0x84b1759a0_11 .net/s v0x84b1759a0 11, 31 0, L_0x84aed0d20; 1 drivers +o0x84a851a80 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_12 .net/s v0x84b1759a0 12, 31 0, o0x84a851a80; 0 drivers +o0x84a851ab0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_13 .net/s v0x84b1759a0 13, 31 0, o0x84a851ab0; 0 drivers +o0x84a851ae0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_14 .net/s v0x84b1759a0 14, 31 0, o0x84a851ae0; 0 drivers +o0x84a851b10 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_15 .net/s v0x84b1759a0 15, 31 0, o0x84a851b10; 0 drivers +v0x84b1759a0_16 .net/s v0x84b1759a0 16, 31 0, L_0x84aed0dc0; 1 drivers +v0x84b1759a0_17 .net/s v0x84b1759a0 17, 31 0, L_0x84aed0e60; 1 drivers +o0x84a851ba0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_18 .net/s v0x84b1759a0 18, 31 0, o0x84a851ba0; 0 drivers +o0x84a851bd0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_19 .net/s v0x84b1759a0 19, 31 0, o0x84a851bd0; 0 drivers +o0x84a851c00 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_20 .net/s v0x84b1759a0 20, 31 0, o0x84a851c00; 0 drivers +o0x84a851c30 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_21 .net/s v0x84b1759a0 21, 31 0, o0x84a851c30; 0 drivers +o0x84a851c60 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_22 .net/s v0x84b1759a0 22, 31 0, o0x84a851c60; 0 drivers +o0x84a851c90 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_23 .net/s v0x84b1759a0 23, 31 0, o0x84a851c90; 0 drivers +v0x84b1759a0_24 .net/s v0x84b1759a0 24, 31 0, L_0x84aed0f00; 1 drivers +o0x84a851cf0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_25 .net/s v0x84b1759a0 25, 31 0, o0x84a851cf0; 0 drivers +o0x84a851d20 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_26 .net/s v0x84b1759a0 26, 31 0, o0x84a851d20; 0 drivers +o0x84a851d50 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_27 .net/s v0x84b1759a0 27, 31 0, o0x84a851d50; 0 drivers +o0x84a851d80 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_28 .net/s v0x84b1759a0 28, 31 0, o0x84a851d80; 0 drivers +o0x84a851db0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_29 .net/s v0x84b1759a0 29, 31 0, o0x84a851db0; 0 drivers +o0x84a851de0 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_30 .net/s v0x84b1759a0 30, 31 0, o0x84a851de0; 0 drivers +o0x84a851e10 .functor BUFZ 32, c4; HiZ drive +v0x84b1759a0_31 .net/s v0x84b1759a0 31, 31 0, o0x84a851e10; 0 drivers +v0x84b175a40_0 .net/s "w_bus", 63 0, L_0x84aece6c0; alias, 1 drivers +v0x84b175ae0_0 .net/s "x_bus", 63 0, L_0x84aece620; alias, 1 drivers +L_0x84aece8a0 .part L_0x84aece620, 0, 8; +L_0x84aece940 .part L_0x84aece6c0, 0, 8; +L_0x84aeceb20 .part L_0x84aece620, 8, 8; +L_0x84aecebc0 .part L_0x84aece6c0, 8, 8; +L_0x84aeceda0 .part L_0x84aece620, 16, 8; +L_0x84aecee40 .part L_0x84aece6c0, 16, 8; +L_0x84aecf020 .part L_0x84aece620, 24, 8; +L_0x84aecf0c0 .part L_0x84aece6c0, 24, 8; +L_0x84aecf2a0 .part L_0x84aece620, 32, 8; +L_0x84aecf340 .part L_0x84aece6c0, 32, 8; +L_0x84aecf520 .part L_0x84aece620, 40, 8; +L_0x84aecf5c0 .part L_0x84aece6c0, 40, 8; +L_0x84aecf7a0 .part L_0x84aece620, 48, 8; +L_0x84aecf840 .part L_0x84aece6c0, 48, 8; +L_0x84aecfa20 .part L_0x84aece620, 56, 8; +L_0x84aecfac0 .part L_0x84aece6c0, 56, 8; +L_0x84aed0fa0 .arith/sum 32, v0x84b176440_0, L_0x84aed0f00; +S_0x84ae9d080 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84ae9cf00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d2c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d300 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d340 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfc780_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1c820; 1 drivers -v0x8d2cfc820_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c8c0; 1 drivers -v0x8d2cfc8c0_0 .net *"_ivl_7", 0 0, L_0x8d321ee40; 1 drivers -v0x8d2cfc960_0 .net *"_ivl_9", 7 0, L_0x8d2d1ca00; 1 drivers -L_0x8d2854e68 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfca00_0 .net/s "acc_in", 39 0, L_0x8d2854e68; 1 drivers -v0x8d2cfcaa0_0 .net/s "acc_out", 39 0, L_0x8d3197700; alias, 1 drivers -v0x8d2cfcb40_0 .net/s "product", 31 0, L_0x8d2d1c960; 1 drivers -v0x8d2cfcbe0_0 .net/s "product_ext", 39 0, L_0x8d3197660; 1 drivers -v0x8d2cfcc80_0 .net/s "w", 15 0, L_0x8d321ef80; 1 drivers -v0x8d2cfcd20_0 .net/s "x", 15 0, L_0x8d321eee0; 1 drivers -L_0x8d2d1c820 .extend/s 32, L_0x8d321eee0; -L_0x8d2d1c8c0 .extend/s 32, L_0x8d321ef80; -L_0x8d2d1c960 .arith/mult 32, L_0x8d2d1c820, L_0x8d2d1c8c0; -L_0x8d321ee40 .part L_0x8d2d1c960, 31, 1; -L_0x8d2d1ca00 .repeat 8, 8, L_0x8d321ee40; -L_0x8d3197660 .concat [ 32 8 0 0], L_0x8d2d1c960, L_0x8d2d1ca00; -L_0x8d3197700 .arith/sum 40, L_0x8d2854e68, L_0x8d3197660; -S_0x8d31fed00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fea00; +P_0x84b152640 .param/l "i" 1 8 20, +C4<00>; +S_0x84ae9d200 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9d080; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d380 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d3c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d400 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfcdc0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1caa0; 1 drivers -v0x8d2cfce60_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1cb40; 1 drivers -v0x8d2cfcf00_0 .net *"_ivl_7", 0 0, L_0x8d321f020; 1 drivers -v0x8d2cfcfa0_0 .net *"_ivl_9", 7 0, L_0x8d2d1cc80; 1 drivers -L_0x8d2854eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfd040_0 .net/s "acc_in", 39 0, L_0x8d2854eb0; 1 drivers -v0x8d2cfd0e0_0 .net/s "acc_out", 39 0, L_0x8d3197840; alias, 1 drivers -v0x8d2cfd180_0 .net/s "product", 31 0, L_0x8d2d1cbe0; 1 drivers -v0x8d2cfd220_0 .net/s "product_ext", 39 0, L_0x8d31977a0; 1 drivers -v0x8d2cfd2c0_0 .net/s "w", 15 0, L_0x8d321f160; 1 drivers -v0x8d2cfd360_0 .net/s "x", 15 0, L_0x8d321f0c0; 1 drivers -L_0x8d2d1caa0 .extend/s 32, L_0x8d321f0c0; -L_0x8d2d1cb40 .extend/s 32, L_0x8d321f160; -L_0x8d2d1cbe0 .arith/mult 32, L_0x8d2d1caa0, L_0x8d2d1cb40; -L_0x8d321f020 .part L_0x8d2d1cbe0, 31, 1; -L_0x8d2d1cc80 .repeat 8, 8, L_0x8d321f020; -L_0x8d31977a0 .concat [ 32 8 0 0], L_0x8d2d1cbe0, L_0x8d2d1cc80; -L_0x8d3197840 .arith/sum 40, L_0x8d2854eb0, L_0x8d31977a0; -S_0x8d31fee80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fea00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1595c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159600 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159640 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b172580_0 .net/s *"_ivl_0", 15 0, L_0x84b198a00; 1 drivers +v0x84b172620_0 .net/s *"_ivl_2", 15 0, L_0x84b198aa0; 1 drivers +v0x84b1726c0_0 .net *"_ivl_7", 0 0, L_0x84aece760; 1 drivers +v0x84b172760_0 .net *"_ivl_9", 15 0, L_0x84aece800; 1 drivers +L_0x84a879210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b172800_0 .net/s "acc_in", 31 0, L_0x84a879210; 1 drivers +v0x84b1728a0_0 .net/s "acc_out", 31 0, L_0x84aed0640; alias, 1 drivers +v0x84b172940_0 .net/s "product", 15 0, L_0x84b198b40; 1 drivers +v0x84b1729e0_0 .net/s "product_ext", 31 0, L_0x84b198be0; 1 drivers +v0x84b172a80_0 .net/s "w", 7 0, L_0x84aece940; 1 drivers +v0x84b172b20_0 .net/s "x", 7 0, L_0x84aece8a0; 1 drivers +L_0x84b198a00 .extend/s 16, L_0x84aece8a0; +L_0x84b198aa0 .extend/s 16, L_0x84aece940; +L_0x84b198b40 .arith/mult 16, L_0x84b198a00, L_0x84b198aa0; +L_0x84aece760 .part L_0x84b198b40, 15, 1; +L_0x84aece800 .repeat 16, 16, L_0x84aece760; +L_0x84b198be0 .concat [ 16 16 0 0], L_0x84b198b40, L_0x84aece800; +L_0x84aed0640 .arith/sum 32, L_0x84a879210, L_0x84b198be0; +S_0x84ae9d380 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84ae9cf00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d440 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d480 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d4c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfd400_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1cd20; 1 drivers -v0x8d2cfd4a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1cdc0; 1 drivers -v0x8d2cfd540_0 .net *"_ivl_7", 0 0, L_0x8d321f200; 1 drivers -v0x8d2cfd5e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1cf00; 1 drivers -L_0x8d2854ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfd680_0 .net/s "acc_in", 39 0, L_0x8d2854ef8; 1 drivers -v0x8d2cfd720_0 .net/s "acc_out", 39 0, L_0x8d3197980; alias, 1 drivers -v0x8d2cfd7c0_0 .net/s "product", 31 0, L_0x8d2d1ce60; 1 drivers -v0x8d2cfd860_0 .net/s "product_ext", 39 0, L_0x8d31978e0; 1 drivers -v0x8d2cfd900_0 .net/s "w", 15 0, L_0x8d321f340; 1 drivers -v0x8d2cfd9a0_0 .net/s "x", 15 0, L_0x8d321f2a0; 1 drivers -L_0x8d2d1cd20 .extend/s 32, L_0x8d321f2a0; -L_0x8d2d1cdc0 .extend/s 32, L_0x8d321f340; -L_0x8d2d1ce60 .arith/mult 32, L_0x8d2d1cd20, L_0x8d2d1cdc0; -L_0x8d321f200 .part L_0x8d2d1ce60, 31, 1; -L_0x8d2d1cf00 .repeat 8, 8, L_0x8d321f200; -L_0x8d31978e0 .concat [ 32 8 0 0], L_0x8d2d1ce60, L_0x8d2d1cf00; -L_0x8d3197980 .arith/sum 40, L_0x8d2854ef8, L_0x8d31978e0; -S_0x8d31ff000 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fea00; +P_0x84b152680 .param/l "i" 1 8 20, +C4<01>; +S_0x84ae9d500 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9d380; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d500 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d540 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d580 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfda40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1cfa0; 1 drivers -v0x8d2cfdae0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d040; 1 drivers -v0x8d2cfdb80_0 .net *"_ivl_7", 0 0, L_0x8d321f3e0; 1 drivers -v0x8d2cfdc20_0 .net *"_ivl_9", 7 0, L_0x8d2d1d180; 1 drivers -L_0x8d2854f40 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfdcc0_0 .net/s "acc_in", 39 0, L_0x8d2854f40; 1 drivers -v0x8d2cfdd60_0 .net/s "acc_out", 39 0, L_0x8d3197ac0; alias, 1 drivers -v0x8d2cfde00_0 .net/s "product", 31 0, L_0x8d2d1d0e0; 1 drivers -v0x8d2cfdea0_0 .net/s "product_ext", 39 0, L_0x8d3197a20; 1 drivers -v0x8d2cfdf40_0 .net/s "w", 15 0, L_0x8d321f520; 1 drivers -v0x8d2cfdfe0_0 .net/s "x", 15 0, L_0x8d321f480; 1 drivers -L_0x8d2d1cfa0 .extend/s 32, L_0x8d321f480; -L_0x8d2d1d040 .extend/s 32, L_0x8d321f520; -L_0x8d2d1d0e0 .arith/mult 32, L_0x8d2d1cfa0, L_0x8d2d1d040; -L_0x8d321f3e0 .part L_0x8d2d1d0e0, 31, 1; -L_0x8d2d1d180 .repeat 8, 8, L_0x8d321f3e0; -L_0x8d3197a20 .concat [ 32 8 0 0], L_0x8d2d1d0e0, L_0x8d2d1d180; -L_0x8d3197ac0 .arith/sum 40, L_0x8d2854f40, L_0x8d3197a20; -S_0x8d31ff180 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fea00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159680 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1596c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159700 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b172bc0_0 .net/s *"_ivl_0", 15 0, L_0x84b198c80; 1 drivers +v0x84b172c60_0 .net/s *"_ivl_2", 15 0, L_0x84b198d20; 1 drivers +v0x84b172d00_0 .net *"_ivl_7", 0 0, L_0x84aece9e0; 1 drivers +v0x84b172da0_0 .net *"_ivl_9", 15 0, L_0x84aecea80; 1 drivers +L_0x84a879258 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b172e40_0 .net/s "acc_in", 31 0, L_0x84a879258; 1 drivers +v0x84b172ee0_0 .net/s "acc_out", 31 0, L_0x84aed06e0; alias, 1 drivers +v0x84b172f80_0 .net/s "product", 15 0, L_0x84b198dc0; 1 drivers +v0x84b173020_0 .net/s "product_ext", 31 0, L_0x84b198e60; 1 drivers +v0x84b1730c0_0 .net/s "w", 7 0, L_0x84aecebc0; 1 drivers +v0x84b173160_0 .net/s "x", 7 0, L_0x84aeceb20; 1 drivers +L_0x84b198c80 .extend/s 16, L_0x84aeceb20; +L_0x84b198d20 .extend/s 16, L_0x84aecebc0; +L_0x84b198dc0 .arith/mult 16, L_0x84b198c80, L_0x84b198d20; +L_0x84aece9e0 .part L_0x84b198dc0, 15, 1; +L_0x84aecea80 .repeat 16, 16, L_0x84aece9e0; +L_0x84b198e60 .concat [ 16 16 0 0], L_0x84b198dc0, L_0x84aecea80; +L_0x84aed06e0 .arith/sum 32, L_0x84a879258, L_0x84b198e60; +S_0x84ae9d680 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84ae9cf00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d5c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d600 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d640 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfe080_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d220; 1 drivers -v0x8d2cfe120_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d2c0; 1 drivers -v0x8d2cfe1c0_0 .net *"_ivl_7", 0 0, L_0x8d321f5c0; 1 drivers -v0x8d2cfe260_0 .net *"_ivl_9", 7 0, L_0x8d2d1d400; 1 drivers -L_0x8d2854f88 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfe300_0 .net/s "acc_in", 39 0, L_0x8d2854f88; 1 drivers -v0x8d2cfe3a0_0 .net/s "acc_out", 39 0, L_0x8d3197c00; alias, 1 drivers -v0x8d2cfe440_0 .net/s "product", 31 0, L_0x8d2d1d360; 1 drivers -v0x8d2cfe4e0_0 .net/s "product_ext", 39 0, L_0x8d3197b60; 1 drivers -v0x8d2cfe580_0 .net/s "w", 15 0, L_0x8d321f700; 1 drivers -v0x8d2cfe620_0 .net/s "x", 15 0, L_0x8d321f660; 1 drivers -L_0x8d2d1d220 .extend/s 32, L_0x8d321f660; -L_0x8d2d1d2c0 .extend/s 32, L_0x8d321f700; -L_0x8d2d1d360 .arith/mult 32, L_0x8d2d1d220, L_0x8d2d1d2c0; -L_0x8d321f5c0 .part L_0x8d2d1d360, 31, 1; -L_0x8d2d1d400 .repeat 8, 8, L_0x8d321f5c0; -L_0x8d3197b60 .concat [ 32 8 0 0], L_0x8d2d1d360, L_0x8d2d1d400; -L_0x8d3197c00 .arith/sum 40, L_0x8d2854f88, L_0x8d3197b60; -S_0x8d31ff300 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fea00; +P_0x84b1526c0 .param/l "i" 1 8 20, +C4<010>; +S_0x84ae9d800 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9d680; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d680 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d6c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d700 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfe6c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d4a0; 1 drivers -v0x8d2cfe760_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d540; 1 drivers -v0x8d2cfe800_0 .net *"_ivl_7", 0 0, L_0x8d321f7a0; 1 drivers -v0x8d2cfe8a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1d680; 1 drivers -L_0x8d2854fd0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfe940_0 .net/s "acc_in", 39 0, L_0x8d2854fd0; 1 drivers -v0x8d2cfe9e0_0 .net/s "acc_out", 39 0, L_0x8d3197d40; alias, 1 drivers -v0x8d2cfea80_0 .net/s "product", 31 0, L_0x8d2d1d5e0; 1 drivers -v0x8d2cfeb20_0 .net/s "product_ext", 39 0, L_0x8d3197ca0; 1 drivers -v0x8d2cfebc0_0 .net/s "w", 15 0, L_0x8d321f8e0; 1 drivers -v0x8d2cfec60_0 .net/s "x", 15 0, L_0x8d321f840; 1 drivers -L_0x8d2d1d4a0 .extend/s 32, L_0x8d321f840; -L_0x8d2d1d540 .extend/s 32, L_0x8d321f8e0; -L_0x8d2d1d5e0 .arith/mult 32, L_0x8d2d1d4a0, L_0x8d2d1d540; -L_0x8d321f7a0 .part L_0x8d2d1d5e0, 31, 1; -L_0x8d2d1d680 .repeat 8, 8, L_0x8d321f7a0; -L_0x8d3197ca0 .concat [ 32 8 0 0], L_0x8d2d1d5e0, L_0x8d2d1d680; -L_0x8d3197d40 .arith/sum 40, L_0x8d2854fd0, L_0x8d3197ca0; -S_0x8d31ff480 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fea00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159740 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159780 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b1597c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b173200_0 .net/s *"_ivl_0", 15 0, L_0x84b198f00; 1 drivers +v0x84b1732a0_0 .net/s *"_ivl_2", 15 0, L_0x84b198fa0; 1 drivers +v0x84b173340_0 .net *"_ivl_7", 0 0, L_0x84aecec60; 1 drivers +v0x84b1733e0_0 .net *"_ivl_9", 15 0, L_0x84aeced00; 1 drivers +L_0x84a8792a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b173480_0 .net/s "acc_in", 31 0, L_0x84a8792a0; 1 drivers +v0x84b173520_0 .net/s "acc_out", 31 0, L_0x84aed0780; alias, 1 drivers +v0x84b1735c0_0 .net/s "product", 15 0, L_0x84b199040; 1 drivers +v0x84b173660_0 .net/s "product_ext", 31 0, L_0x84b1990e0; 1 drivers +v0x84b173700_0 .net/s "w", 7 0, L_0x84aecee40; 1 drivers +v0x84b1737a0_0 .net/s "x", 7 0, L_0x84aeceda0; 1 drivers +L_0x84b198f00 .extend/s 16, L_0x84aeceda0; +L_0x84b198fa0 .extend/s 16, L_0x84aecee40; +L_0x84b199040 .arith/mult 16, L_0x84b198f00, L_0x84b198fa0; +L_0x84aecec60 .part L_0x84b199040, 15, 1; +L_0x84aeced00 .repeat 16, 16, L_0x84aecec60; +L_0x84b1990e0 .concat [ 16 16 0 0], L_0x84b199040, L_0x84aeced00; +L_0x84aed0780 .arith/sum 32, L_0x84a8792a0, L_0x84b1990e0; +S_0x84ae9d980 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84ae9cf00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d740 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d780 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d7c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cfed00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d720; 1 drivers -v0x8d2cfeda0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d7c0; 1 drivers -v0x8d2cfee40_0 .net *"_ivl_7", 0 0, L_0x8d321f980; 1 drivers -v0x8d2cfeee0_0 .net *"_ivl_9", 7 0, L_0x8d2d1d900; 1 drivers -L_0x8d2855018 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cfef80_0 .net/s "acc_in", 39 0, L_0x8d2855018; 1 drivers -v0x8d2cff020_0 .net/s "acc_out", 39 0, L_0x8d3197e80; alias, 1 drivers -v0x8d2cff0c0_0 .net/s "product", 31 0, L_0x8d2d1d860; 1 drivers -v0x8d2cff160_0 .net/s "product_ext", 39 0, L_0x8d3197de0; 1 drivers -v0x8d2cff200_0 .net/s "w", 15 0, L_0x8d321fac0; 1 drivers -v0x8d2cff2a0_0 .net/s "x", 15 0, L_0x8d321fa20; 1 drivers -L_0x8d2d1d720 .extend/s 32, L_0x8d321fa20; -L_0x8d2d1d7c0 .extend/s 32, L_0x8d321fac0; -L_0x8d2d1d860 .arith/mult 32, L_0x8d2d1d720, L_0x8d2d1d7c0; -L_0x8d321f980 .part L_0x8d2d1d860, 31, 1; -L_0x8d2d1d900 .repeat 8, 8, L_0x8d321f980; -L_0x8d3197de0 .concat [ 32 8 0 0], L_0x8d2d1d860, L_0x8d2d1d900; -L_0x8d3197e80 .arith/sum 40, L_0x8d2855018, L_0x8d3197de0; -S_0x8d31ff600 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fea00; +P_0x84b152700 .param/l "i" 1 8 20, +C4<011>; +S_0x84ae9db00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9d980; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d800 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d840 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d880 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2cff340_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d9a0; 1 drivers -v0x8d2cff3e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1da40; 1 drivers -v0x8d2cff480_0 .net *"_ivl_7", 0 0, L_0x8d321fb60; 1 drivers -v0x8d2cff520_0 .net *"_ivl_9", 7 0, L_0x8d2d1db80; 1 drivers -L_0x8d2855060 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2cff5c0_0 .net/s "acc_in", 39 0, L_0x8d2855060; 1 drivers -v0x8d2cff660_0 .net/s "acc_out", 39 0, L_0x8d3228000; alias, 1 drivers -v0x8d2cff700_0 .net/s "product", 31 0, L_0x8d2d1dae0; 1 drivers -v0x8d2cff7a0_0 .net/s "product_ext", 39 0, L_0x8d3197f20; 1 drivers -v0x8d2cff840_0 .net/s "w", 15 0, L_0x8d321fca0; 1 drivers -v0x8d2cff8e0_0 .net/s "x", 15 0, L_0x8d321fc00; 1 drivers -L_0x8d2d1d9a0 .extend/s 32, L_0x8d321fc00; -L_0x8d2d1da40 .extend/s 32, L_0x8d321fca0; -L_0x8d2d1dae0 .arith/mult 32, L_0x8d2d1d9a0, L_0x8d2d1da40; -L_0x8d321fb60 .part L_0x8d2d1dae0, 31, 1; -L_0x8d2d1db80 .repeat 8, 8, L_0x8d321fb60; -L_0x8d3197f20 .concat [ 32 8 0 0], L_0x8d2d1dae0, L_0x8d2d1db80; -L_0x8d3228000 .arith/sum 40, L_0x8d2855060, L_0x8d3197f20; -S_0x8d31ff780 .scope generate, "GEN_NEURON[4]" "GEN_NEURON[4]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159800 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159840 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159880 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b173840_0 .net/s *"_ivl_0", 15 0, L_0x84b199180; 1 drivers +v0x84b1738e0_0 .net/s *"_ivl_2", 15 0, L_0x84b199220; 1 drivers +v0x84b173980_0 .net *"_ivl_7", 0 0, L_0x84aeceee0; 1 drivers +v0x84b173a20_0 .net *"_ivl_9", 15 0, L_0x84aecef80; 1 drivers +L_0x84a8792e8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b173ac0_0 .net/s "acc_in", 31 0, L_0x84a8792e8; 1 drivers +v0x84b173b60_0 .net/s "acc_out", 31 0, L_0x84aed0820; alias, 1 drivers +v0x84b173c00_0 .net/s "product", 15 0, L_0x84b1992c0; 1 drivers +v0x84b173ca0_0 .net/s "product_ext", 31 0, L_0x84b199360; 1 drivers +v0x84b173d40_0 .net/s "w", 7 0, L_0x84aecf0c0; 1 drivers +v0x84b173de0_0 .net/s "x", 7 0, L_0x84aecf020; 1 drivers +L_0x84b199180 .extend/s 16, L_0x84aecf020; +L_0x84b199220 .extend/s 16, L_0x84aecf0c0; +L_0x84b1992c0 .arith/mult 16, L_0x84b199180, L_0x84b199220; +L_0x84aeceee0 .part L_0x84b1992c0, 15, 1; +L_0x84aecef80 .repeat 16, 16, L_0x84aeceee0; +L_0x84b199360 .concat [ 16 16 0 0], L_0x84b1992c0, L_0x84aecef80; +L_0x84aed0820 .arith/sum 32, L_0x84a8792e8, L_0x84b199360; +S_0x84ae9dc80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84ae9cf00; .timescale 0 0; -P_0x8d2c3b1c0 .param/l "n" 1 4 35, +C4<0100>; -S_0x8d31ff900 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31ff780; +P_0x84b152740 .param/l "i" 1 8 20, +C4<0100>; +S_0x84ae9de00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9dc80; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b1598c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159900 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159940 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b173e80_0 .net/s *"_ivl_0", 15 0, L_0x84b199400; 1 drivers +v0x84b173f20_0 .net/s *"_ivl_2", 15 0, L_0x84b1994a0; 1 drivers +v0x84b174000_0 .net *"_ivl_7", 0 0, L_0x84aecf160; 1 drivers +v0x84b1740a0_0 .net *"_ivl_9", 15 0, L_0x84aecf200; 1 drivers +L_0x84a879330 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b174140_0 .net/s "acc_in", 31 0, L_0x84a879330; 1 drivers +v0x84b1741e0_0 .net/s "acc_out", 31 0, L_0x84aed08c0; alias, 1 drivers +v0x84b174280_0 .net/s "product", 15 0, L_0x84b199540; 1 drivers +v0x84b174320_0 .net/s "product_ext", 31 0, L_0x84b1995e0; 1 drivers +v0x84b1743c0_0 .net/s "w", 7 0, L_0x84aecf340; 1 drivers +v0x84b174460_0 .net/s "x", 7 0, L_0x84aecf2a0; 1 drivers +L_0x84b199400 .extend/s 16, L_0x84aecf2a0; +L_0x84b1994a0 .extend/s 16, L_0x84aecf340; +L_0x84b199540 .arith/mult 16, L_0x84b199400, L_0x84b1994a0; +L_0x84aecf160 .part L_0x84b199540, 15, 1; +L_0x84aecf200 .repeat 16, 16, L_0x84aecf160; +L_0x84b1995e0 .concat [ 16 16 0 0], L_0x84b199540, L_0x84aecf200; +L_0x84aed08c0 .arith/sum 32, L_0x84a879330, L_0x84b1995e0; +S_0x84ae9df80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152780 .param/l "i" 1 8 20, +C4<0101>; +S_0x84ae9e100 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9df80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159980 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b1599c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159a00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b174500_0 .net/s *"_ivl_0", 15 0, L_0x84b199680; 1 drivers +v0x84b1745a0_0 .net/s *"_ivl_2", 15 0, L_0x84b199720; 1 drivers +v0x84b174640_0 .net *"_ivl_7", 0 0, L_0x84aecf3e0; 1 drivers +v0x84b1746e0_0 .net *"_ivl_9", 15 0, L_0x84aecf480; 1 drivers +L_0x84a879378 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b174780_0 .net/s "acc_in", 31 0, L_0x84a879378; 1 drivers +v0x84b174820_0 .net/s "acc_out", 31 0, L_0x84aed0960; alias, 1 drivers +v0x84b1748c0_0 .net/s "product", 15 0, L_0x84b1997c0; 1 drivers +v0x84b174960_0 .net/s "product_ext", 31 0, L_0x84b199860; 1 drivers +v0x84b174a00_0 .net/s "w", 7 0, L_0x84aecf5c0; 1 drivers +v0x84b174aa0_0 .net/s "x", 7 0, L_0x84aecf520; 1 drivers +L_0x84b199680 .extend/s 16, L_0x84aecf520; +L_0x84b199720 .extend/s 16, L_0x84aecf5c0; +L_0x84b1997c0 .arith/mult 16, L_0x84b199680, L_0x84b199720; +L_0x84aecf3e0 .part L_0x84b1997c0, 15, 1; +L_0x84aecf480 .repeat 16, 16, L_0x84aecf3e0; +L_0x84b199860 .concat [ 16 16 0 0], L_0x84b1997c0, L_0x84aecf480; +L_0x84aed0960 .arith/sum 32, L_0x84a879378, L_0x84b199860; +S_0x84ae9e280 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b1527c0 .param/l "i" 1 8 20, +C4<0110>; +S_0x84ae9e400 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9e280; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159a40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159a80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159ac0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b174b40_0 .net/s *"_ivl_0", 15 0, L_0x84b199900; 1 drivers +v0x84b174be0_0 .net/s *"_ivl_2", 15 0, L_0x84b1999a0; 1 drivers +v0x84b174c80_0 .net *"_ivl_7", 0 0, L_0x84aecf660; 1 drivers +v0x84b174d20_0 .net *"_ivl_9", 15 0, L_0x84aecf700; 1 drivers +L_0x84a8793c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b174dc0_0 .net/s "acc_in", 31 0, L_0x84a8793c0; 1 drivers +v0x84b174e60_0 .net/s "acc_out", 31 0, L_0x84aed0a00; alias, 1 drivers +v0x84b174f00_0 .net/s "product", 15 0, L_0x84b199a40; 1 drivers +v0x84b174fa0_0 .net/s "product_ext", 31 0, L_0x84b199ae0; 1 drivers +v0x84b175040_0 .net/s "w", 7 0, L_0x84aecf840; 1 drivers +v0x84b1750e0_0 .net/s "x", 7 0, L_0x84aecf7a0; 1 drivers +L_0x84b199900 .extend/s 16, L_0x84aecf7a0; +L_0x84b1999a0 .extend/s 16, L_0x84aecf840; +L_0x84b199a40 .arith/mult 16, L_0x84b199900, L_0x84b1999a0; +L_0x84aecf660 .part L_0x84b199a40, 15, 1; +L_0x84aecf700 .repeat 16, 16, L_0x84aecf660; +L_0x84b199ae0 .concat [ 16 16 0 0], L_0x84b199a40, L_0x84aecf700; +L_0x84aed0a00 .arith/sum 32, L_0x84a8793c0, L_0x84b199ae0; +S_0x84ae9e580 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152800 .param/l "i" 1 8 20, +C4<0111>; +S_0x84ae9e700 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84ae9e580; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159b00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159b40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159b80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b175180_0 .net/s *"_ivl_0", 15 0, L_0x84b199b80; 1 drivers +v0x84b175220_0 .net/s *"_ivl_2", 15 0, L_0x84b199c20; 1 drivers +v0x84b1752c0_0 .net *"_ivl_7", 0 0, L_0x84aecf8e0; 1 drivers +v0x84b175360_0 .net *"_ivl_9", 15 0, L_0x84aecf980; 1 drivers +L_0x84a879408 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b175400_0 .net/s "acc_in", 31 0, L_0x84a879408; 1 drivers +v0x84b1754a0_0 .net/s "acc_out", 31 0, L_0x84aed0aa0; alias, 1 drivers +v0x84b175540_0 .net/s "product", 15 0, L_0x84b199cc0; 1 drivers +v0x84b1755e0_0 .net/s "product_ext", 31 0, L_0x84b199d60; 1 drivers +v0x84b175680_0 .net/s "w", 7 0, L_0x84aecfac0; 1 drivers +v0x84b175720_0 .net/s "x", 7 0, L_0x84aecfa20; 1 drivers +L_0x84b199b80 .extend/s 16, L_0x84aecfa20; +L_0x84b199c20 .extend/s 16, L_0x84aecfac0; +L_0x84b199cc0 .arith/mult 16, L_0x84b199b80, L_0x84b199c20; +L_0x84aecf8e0 .part L_0x84b199cc0, 15, 1; +L_0x84aecf980 .repeat 16, 16, L_0x84aecf8e0; +L_0x84b199d60 .concat [ 16 16 0 0], L_0x84b199cc0, L_0x84aecf980; +L_0x84aed0aa0 .arith/sum 32, L_0x84a879408, L_0x84b199d60; +S_0x84ae9e880 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152840 .param/l "i" 1 8 80, +C4<00>; +L_0x84ac3fe20 .functor BUFZ 32, L_0x84aed0640, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9ea00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152880 .param/l "i" 1 8 80, +C4<01>; +L_0x84ac3fe90 .functor BUFZ 32, L_0x84aed06e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9eb80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b1528c0 .param/l "i" 1 8 80, +C4<010>; +L_0x84ac3ff00 .functor BUFZ 32, L_0x84aed0780, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9ed00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152900 .param/l "i" 1 8 80, +C4<011>; +L_0x84ac3ff70 .functor BUFZ 32, L_0x84aed0820, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9ee80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152940 .param/l "i" 1 8 80, +C4<0100>; +L_0x84aed8000 .functor BUFZ 32, L_0x84aed08c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9f000 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152980 .param/l "i" 1 8 80, +C4<0101>; +L_0x84aedc000 .functor BUFZ 32, L_0x84aed0960, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9f180 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b1529c0 .param/l "i" 1 8 80, +C4<0110>; +L_0x84aedc070 .functor BUFZ 32, L_0x84aed0a00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9f300 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152a00 .param/l "i" 1 8 80, +C4<0111>; +L_0x84aedc0e0 .functor BUFZ 32, L_0x84aed0aa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84ae9f480 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152a40 .param/l "level" 1 8 92, +C4<00>; +S_0x84ae9f600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae9f480; + .timescale 0 0; +P_0x84b152a80 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed0b40 .arith/sum 32, L_0x84ac3fe20, L_0x84ac3fe90; +S_0x84ae9f780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae9f480; + .timescale 0 0; +P_0x84b152ac0 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed0be0 .arith/sum 32, L_0x84ac3ff00, L_0x84ac3ff70; +S_0x84ae9f900 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84ae9f480; + .timescale 0 0; +P_0x84b152b00 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed0c80 .arith/sum 32, L_0x84aed8000, L_0x84aedc000; +S_0x84ae9fa80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84ae9f480; + .timescale 0 0; +P_0x84b152b40 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed0d20 .arith/sum 32, L_0x84aedc070, L_0x84aedc0e0; +S_0x84ae9fc00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152b80 .param/l "level" 1 8 92, +C4<01>; +S_0x84ae9fd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84ae9fc00; + .timescale 0 0; +P_0x84b152bc0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed0dc0 .arith/sum 32, L_0x84aed0b40, L_0x84aed0be0; +S_0x84aea0000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84ae9fc00; + .timescale 0 0; +P_0x84b152c00 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed0e60 .arith/sum 32, L_0x84aed0c80, L_0x84aed0d20; +S_0x84aea0180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84ae9cf00; + .timescale 0 0; +P_0x84b152c40 .param/l "level" 1 8 92, +C4<010>; +S_0x84aea0300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea0180; + .timescale 0 0; +P_0x84b152c80 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed0f00 .arith/sum 32, L_0x84aed0dc0, L_0x84aed0e60; +S_0x84aea0480 .scope generate, "GEN_NEURON[4]" "GEN_NEURON[4]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b152cc0 .param/l "n" 1 12 34, +C4<0100>; +S_0x84aea0600 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84aea0480; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e66e30 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e66e70 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e66eb0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e66ef0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e66f30 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e66f70 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e66fb0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c310 .functor BUFZ 16, L_0x8d322d360, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2d05a40_0 .net *"_ivl_0", 31 0, L_0x8d3228780; 1 drivers -v0x8d2d05ae0_0 .net *"_ivl_11", 31 0, L_0x8d2d1de00; 1 drivers -v0x8d2d05b80_0 .net *"_ivl_14", 31 0, L_0x8d3228820; 1 drivers -L_0x8d28551c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d05c20_0 .net *"_ivl_17", 28 0, L_0x8d28551c8; 1 drivers -L_0x8d2855210 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d05cc0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855210; 1 drivers -v0x8d2d05d60_0 .net *"_ivl_21", 31 0, L_0x8d2d1dea0; 1 drivers -L_0x8d2855258 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d05e00_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855258; 1 drivers -v0x8d2d05ea0_0 .net *"_ivl_25", 31 0, L_0x8d2d1df40; 1 drivers -L_0x8d28550f0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d05f40_0 .net *"_ivl_3", 28 0, L_0x8d28550f0; 1 drivers -v0x8d2d05fe0_0 .net *"_ivl_31", 0 0, L_0x8d322d0e0; 1 drivers -v0x8d2d06080_0 .net *"_ivl_33", 23 0, L_0x8d2d1f3e0; 1 drivers -v0x8d2d06120_0 .net *"_ivl_36", 39 0, L_0x8d3229860; 1 drivers -v0x8d2d061c0_0 .net *"_ivl_38", 31 0, L_0x8d322d180; 1 drivers -L_0x8d2855138 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d06260_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855138; 1 drivers -L_0x8d28554e0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d06300_0 .net *"_ivl_40", 7 0, L_0x8d28554e0; 1 drivers -v0x8d2d063a0_0 .net *"_ivl_46", 31 0, L_0x8d322d220; 1 drivers -v0x8d2d06440_0 .net *"_ivl_7", 31 0, L_0x8d2d1dd60; 1 drivers -L_0x8d2855180 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d064e0_0 .net/2u *"_ivl_8", 31 0, L_0x8d2855180; 1 drivers -v0x8d2d06580_0 .var/s "acc", 39 0; -v0x8d2d06620_0 .net/s "acc_next", 39 0, L_0x8d3229720; 1 drivers -v0x8d2d066c0_0 .net/s "bias", 15 0, L_0x8d322d360; 1 drivers -v0x8d2d06760_0 .net/s "bias_ext", 39 0, L_0x8d32297c0; 1 drivers -v0x8d2d06800_0 .net/s "bias_ext_small", 15 0, L_0x8d307c310; 1 drivers -v0x8d2d068a0_0 .var "busy", 0 0; -v0x8d2d06940_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2d069e0_0 .var "done", 0 0; -v0x8d2d06a80_0 .net/s "final_acc", 39 0, L_0x8d3229900; 1 drivers -v0x8d2d06b20_0 .net/s "final_value", 39 0, L_0x8d2d1f480; 1 drivers -v0x8d2d06bc0_0 .var "group_index", 2 0; -v0x8d2d06c60_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2d06d00_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2d06da0_0 .net/s "w_bus", 1023 0, L_0x8d322d2c0; 1 drivers -v0x8d2d06e40_0 .net/s "w_group", 127 0, L_0x8d322c140; 1 drivers -v0x8d2d06ee0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2d06f80_0 .net/s "x_group", 127 0, L_0x8d322c0a0; 1 drivers -v0x8d2d07020_0 .var/s "y", 15 0; -L_0x8d3228780 .concat [ 3 29 0 0], v0x8d2d06bc0_0, L_0x8d28550f0; -L_0x8d2d1dd60 .arith/mult 32, L_0x8d3228780, L_0x8d2855138; -L_0x8d2d1de00 .arith/mult 32, L_0x8d2d1dd60, L_0x8d2855180; -L_0x8d322c0a0 .part/v v0x8d2d17ca0_0, L_0x8d2d1de00, 128; -L_0x8d3228820 .concat [ 3 29 0 0], v0x8d2d06bc0_0, L_0x8d28551c8; -L_0x8d2d1dea0 .arith/mult 32, L_0x8d3228820, L_0x8d2855210; -L_0x8d2d1df40 .arith/mult 32, L_0x8d2d1dea0, L_0x8d2855258; -L_0x8d322c140 .part/v L_0x8d322d2c0, L_0x8d2d1df40, 128; -L_0x8d322d0e0 .part L_0x8d307c310, 15, 1; -L_0x8d2d1f3e0 .repeat 24, 24, L_0x8d322d0e0; -L_0x8d32297c0 .concat [ 16 24 0 0], L_0x8d307c310, L_0x8d2d1f3e0; -L_0x8d322d180 .part L_0x8d32297c0, 0, 32; -L_0x8d3229860 .concat [ 8 32 0 0], L_0x8d28554e0, L_0x8d322d180; -L_0x8d3229900 .arith/sum 40, L_0x8d3229720, L_0x8d3229860; -L_0x8d322d220 .part L_0x8d3229900, 8, 32; -L_0x8d2d1f480 .extend/s 40, L_0x8d322d220; -S_0x8d31ffa80 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31ff900; +P_0x84aea0780 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84aea07c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84aea0800 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84aea0840 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84aea0880 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84aea08c0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b17e440_0 .net *"_ivl_0", 31 0, L_0x84b199f40; 1 drivers +v0x84b17e4e0_0 .net *"_ivl_11", 31 0, L_0x84b19a080; 1 drivers +v0x84b17e580_0 .net *"_ivl_14", 31 0, L_0x84b19a120; 1 drivers +L_0x84a879528 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17e620_0 .net *"_ivl_17", 29 0, L_0x84a879528; 1 drivers +L_0x84a879570 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b17e6c0_0 .net/2u *"_ivl_18", 31 0, L_0x84a879570; 1 drivers +v0x84b17e760_0 .net *"_ivl_21", 31 0, L_0x84b19a1c0; 1 drivers +L_0x84a8795b8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b17e800_0 .net/2u *"_ivl_22", 31 0, L_0x84a8795b8; 1 drivers +v0x84b17e8a0_0 .net *"_ivl_25", 31 0, L_0x84b19a260; 1 drivers +v0x84b17e940_0 .net *"_ivl_29", 0 0, L_0x84aee1360; 1 drivers +L_0x84a879450 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17e9e0_0 .net *"_ivl_3", 29 0, L_0x84a879450; 1 drivers +v0x84b17ea80_0 .net *"_ivl_31", 23 0, L_0x84aee1400; 1 drivers +L_0x84a879498 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b17eb20_0 .net/2u *"_ivl_4", 31 0, L_0x84a879498; 1 drivers +v0x84b17ebc0_0 .net *"_ivl_7", 31 0, L_0x84b199fe0; 1 drivers +L_0x84a8794e0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b17ec60_0 .net/2u *"_ivl_8", 31 0, L_0x84a8794e0; 1 drivers +v0x84b17ed00_0 .var/s "acc", 31 0; +v0x84b17eda0_0 .net/s "acc_next", 31 0, L_0x84aed1a40; 1 drivers +v0x84b17ee40_0 .net/s "bias", 7 0, L_0x84aee1540; 1 drivers +v0x84b17eee0_0 .net/s "bias_ext", 31 0, L_0x84b19b7a0; 1 drivers +v0x84b17ef80_0 .var "busy", 0 0; +v0x84b17f020_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b17f0c0_0 .var "done", 0 0; +v0x84b17f160_0 .net/s "final_acc", 31 0, L_0x84aed1ae0; 1 drivers +v0x84b17f200_0 .var "group_index", 1 0; +v0x84b17f2a0_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b17f340_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b17f3e0_0 .net/s "w_bus", 255 0, L_0x84aee14a0; 1 drivers +v0x84b17f480_0 .net/s "w_group", 63 0, L_0x84aecfe80; 1 drivers +v0x84b17f520_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b17f5c0_0 .net/s "x_group", 63 0, L_0x84aecfde0; 1 drivers +v0x84b17f660_0 .var/s "y", 7 0; +L_0x84b199f40 .concat [ 2 30 0 0], v0x84b17f200_0, L_0x84a879450; +L_0x84b199fe0 .arith/mult 32, L_0x84b199f40, L_0x84a879498; +L_0x84b19a080 .arith/mult 32, L_0x84b199fe0, L_0x84a8794e0; +L_0x84aecfde0 .part/v v0x84b191e00_0, L_0x84b19a080, 64; +L_0x84b19a120 .concat [ 2 30 0 0], v0x84b17f200_0, L_0x84a879528; +L_0x84b19a1c0 .arith/mult 32, L_0x84b19a120, L_0x84a879570; +L_0x84b19a260 .arith/mult 32, L_0x84b19a1c0, L_0x84a8795b8; +L_0x84aecfe80 .part/v L_0x84aee14a0, L_0x84b19a260, 64; +L_0x84aee1360 .part L_0x84aee1540, 7, 1; +L_0x84aee1400 .repeat 24, 24, L_0x84aee1360; +L_0x84b19b7a0 .concat [ 8 24 0 0], L_0x84aee1540, L_0x84aee1400; +L_0x84aed1ae0 .arith/sum 32, L_0x84aed1a40, L_0x84b19b7a0; +S_0x84aea0900 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84aea0600; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0800 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a0840 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2d04e60_0 .net/s "acc_in", 39 0, v0x8d2d06580_0; 1 drivers -v0x8d2d04f00_0 .net/s "acc_out", 39 0, L_0x8d3229720; alias, 1 drivers -v0x8d2d04fa0_0 .net/s "m0", 39 0, L_0x8d3228960; 1 drivers -v0x8d2d05040_0 .net/s "m1", 39 0, L_0x8d3228aa0; 1 drivers -v0x8d2d050e0_0 .net/s "m2", 39 0, L_0x8d3228be0; 1 drivers -v0x8d2d05180_0 .net/s "m3", 39 0, L_0x8d3228d20; 1 drivers -v0x8d2d05220_0 .net/s "m4", 39 0, L_0x8d3228e60; 1 drivers -v0x8d2d052c0_0 .net/s "m5", 39 0, L_0x8d3228fa0; 1 drivers -v0x8d2d05360_0 .net/s "m6", 39 0, L_0x8d32290e0; 1 drivers -v0x8d2d05400_0 .net/s "m7", 39 0, L_0x8d3229220; 1 drivers -v0x8d2d054a0_0 .net/s "s0", 39 0, L_0x8d32292c0; 1 drivers -v0x8d2d05540_0 .net/s "s1", 39 0, L_0x8d3229360; 1 drivers -v0x8d2d055e0_0 .net/s "s2", 39 0, L_0x8d3229400; 1 drivers -v0x8d2d05680_0 .net/s "s3", 39 0, L_0x8d32294a0; 1 drivers -v0x8d2d05720_0 .net/s "s4", 39 0, L_0x8d3229540; 1 drivers -v0x8d2d057c0_0 .net/s "s5", 39 0, L_0x8d32295e0; 1 drivers -v0x8d2d05860_0 .net/s "sum", 39 0, L_0x8d3229680; 1 drivers -v0x8d2d05900_0 .net/s "w_bus", 127 0, L_0x8d322c140; alias, 1 drivers -v0x8d2d059a0_0 .net/s "x_bus", 127 0, L_0x8d322c0a0; alias, 1 drivers -L_0x8d322c280 .part L_0x8d322c0a0, 0, 16; -L_0x8d322c320 .part L_0x8d322c140, 0, 16; -L_0x8d322c460 .part L_0x8d322c0a0, 16, 16; -L_0x8d322c500 .part L_0x8d322c140, 16, 16; -L_0x8d322c640 .part L_0x8d322c0a0, 32, 16; -L_0x8d322c6e0 .part L_0x8d322c140, 32, 16; -L_0x8d322c820 .part L_0x8d322c0a0, 48, 16; -L_0x8d322c8c0 .part L_0x8d322c140, 48, 16; -L_0x8d322ca00 .part L_0x8d322c0a0, 64, 16; -L_0x8d322caa0 .part L_0x8d322c140, 64, 16; -L_0x8d322cbe0 .part L_0x8d322c0a0, 80, 16; -L_0x8d322cc80 .part L_0x8d322c140, 80, 16; -L_0x8d322cdc0 .part L_0x8d322c0a0, 96, 16; -L_0x8d322ce60 .part L_0x8d322c140, 96, 16; -L_0x8d322cfa0 .part L_0x8d322c0a0, 112, 16; -L_0x8d322d040 .part L_0x8d322c140, 112, 16; -L_0x8d32292c0 .arith/sum 40, L_0x8d3228960, L_0x8d3228aa0; -L_0x8d3229360 .arith/sum 40, L_0x8d3228be0, L_0x8d3228d20; -L_0x8d3229400 .arith/sum 40, L_0x8d3228e60, L_0x8d3228fa0; -L_0x8d32294a0 .arith/sum 40, L_0x8d32290e0, L_0x8d3229220; -L_0x8d3229540 .arith/sum 40, L_0x8d32292c0, L_0x8d3229360; -L_0x8d32295e0 .arith/sum 40, L_0x8d3229400, L_0x8d32294a0; -L_0x8d3229680 .arith/sum 40, L_0x8d3229540, L_0x8d32295e0; -L_0x8d3229720 .arith/sum 40, v0x8d2d06580_0, L_0x8d3229680; -S_0x8d31ffc00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31ffa80; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8700 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8740 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8780 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc87c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b17e080_0 .net/s "acc_in", 31 0, v0x84b17ed00_0; 1 drivers +v0x84b17e120_0 .net/s "acc_out", 31 0, L_0x84aed1a40; alias, 1 drivers +v0x84b17e1c0 .array "products", 7 0; +v0x84b17e1c0_0 .net/s v0x84b17e1c0 0, 31 0, L_0x84aed10e0; 1 drivers +v0x84b17e1c0_1 .net/s v0x84b17e1c0 1, 31 0, L_0x84aed1180; 1 drivers +v0x84b17e1c0_2 .net/s v0x84b17e1c0 2, 31 0, L_0x84aed1220; 1 drivers +v0x84b17e1c0_3 .net/s v0x84b17e1c0 3, 31 0, L_0x84aed12c0; 1 drivers +v0x84b17e1c0_4 .net/s v0x84b17e1c0 4, 31 0, L_0x84aed1360; 1 drivers +v0x84b17e1c0_5 .net/s v0x84b17e1c0 5, 31 0, L_0x84aed1400; 1 drivers +v0x84b17e1c0_6 .net/s v0x84b17e1c0 6, 31 0, L_0x84aed14a0; 1 drivers +v0x84b17e1c0_7 .net/s v0x84b17e1c0 7, 31 0, L_0x84aed1540; 1 drivers +v0x84b17e260 .array "tree", 31 0; +v0x84b17e260_0 .net/s v0x84b17e260 0, 31 0, L_0x84aedc150; 1 drivers +v0x84b17e260_1 .net/s v0x84b17e260 1, 31 0, L_0x84aedc1c0; 1 drivers +v0x84b17e260_2 .net/s v0x84b17e260 2, 31 0, L_0x84aedc230; 1 drivers +v0x84b17e260_3 .net/s v0x84b17e260 3, 31 0, L_0x84aedc2a0; 1 drivers +v0x84b17e260_4 .net/s v0x84b17e260 4, 31 0, L_0x84aedc310; 1 drivers +v0x84b17e260_5 .net/s v0x84b17e260 5, 31 0, L_0x84aedc380; 1 drivers +v0x84b17e260_6 .net/s v0x84b17e260 6, 31 0, L_0x84aedc3f0; 1 drivers +v0x84b17e260_7 .net/s v0x84b17e260 7, 31 0, L_0x84aedc460; 1 drivers +v0x84b17e260_8 .net/s v0x84b17e260 8, 31 0, L_0x84aed15e0; 1 drivers +v0x84b17e260_9 .net/s v0x84b17e260 9, 31 0, L_0x84aed1680; 1 drivers +v0x84b17e260_10 .net/s v0x84b17e260 10, 31 0, L_0x84aed1720; 1 drivers +v0x84b17e260_11 .net/s v0x84b17e260 11, 31 0, L_0x84aed17c0; 1 drivers +o0x84a853cd0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_12 .net/s v0x84b17e260 12, 31 0, o0x84a853cd0; 0 drivers +o0x84a853d00 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_13 .net/s v0x84b17e260 13, 31 0, o0x84a853d00; 0 drivers +o0x84a853d30 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_14 .net/s v0x84b17e260 14, 31 0, o0x84a853d30; 0 drivers +o0x84a853d60 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_15 .net/s v0x84b17e260 15, 31 0, o0x84a853d60; 0 drivers +v0x84b17e260_16 .net/s v0x84b17e260 16, 31 0, L_0x84aed1860; 1 drivers +v0x84b17e260_17 .net/s v0x84b17e260 17, 31 0, L_0x84aed1900; 1 drivers +o0x84a853df0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_18 .net/s v0x84b17e260 18, 31 0, o0x84a853df0; 0 drivers +o0x84a853e20 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_19 .net/s v0x84b17e260 19, 31 0, o0x84a853e20; 0 drivers +o0x84a853e50 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_20 .net/s v0x84b17e260 20, 31 0, o0x84a853e50; 0 drivers +o0x84a853e80 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_21 .net/s v0x84b17e260 21, 31 0, o0x84a853e80; 0 drivers +o0x84a853eb0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_22 .net/s v0x84b17e260 22, 31 0, o0x84a853eb0; 0 drivers +o0x84a853ee0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_23 .net/s v0x84b17e260 23, 31 0, o0x84a853ee0; 0 drivers +v0x84b17e260_24 .net/s v0x84b17e260 24, 31 0, L_0x84aed19a0; 1 drivers +o0x84a853f40 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_25 .net/s v0x84b17e260 25, 31 0, o0x84a853f40; 0 drivers +o0x84a853f70 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_26 .net/s v0x84b17e260 26, 31 0, o0x84a853f70; 0 drivers +o0x84a853fa0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_27 .net/s v0x84b17e260 27, 31 0, o0x84a853fa0; 0 drivers +o0x84a853fd0 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_28 .net/s v0x84b17e260 28, 31 0, o0x84a853fd0; 0 drivers +o0x84a854000 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_29 .net/s v0x84b17e260 29, 31 0, o0x84a854000; 0 drivers +o0x84a854030 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_30 .net/s v0x84b17e260 30, 31 0, o0x84a854030; 0 drivers +o0x84a854060 .functor BUFZ 32, c4; HiZ drive +v0x84b17e260_31 .net/s v0x84b17e260 31, 31 0, o0x84a854060; 0 drivers +v0x84b17e300_0 .net/s "w_bus", 63 0, L_0x84aecfe80; alias, 1 drivers +v0x84b17e3a0_0 .net/s "x_bus", 63 0, L_0x84aecfde0; alias, 1 drivers +L_0x84aee00a0 .part L_0x84aecfde0, 0, 8; +L_0x84aee0140 .part L_0x84aecfe80, 0, 8; +L_0x84aee0320 .part L_0x84aecfde0, 8, 8; +L_0x84aee03c0 .part L_0x84aecfe80, 8, 8; +L_0x84aee05a0 .part L_0x84aecfde0, 16, 8; +L_0x84aee0640 .part L_0x84aecfe80, 16, 8; +L_0x84aee0820 .part L_0x84aecfde0, 24, 8; +L_0x84aee08c0 .part L_0x84aecfe80, 24, 8; +L_0x84aee0aa0 .part L_0x84aecfde0, 32, 8; +L_0x84aee0b40 .part L_0x84aecfe80, 32, 8; +L_0x84aee0d20 .part L_0x84aecfde0, 40, 8; +L_0x84aee0dc0 .part L_0x84aecfe80, 40, 8; +L_0x84aee0fa0 .part L_0x84aecfde0, 48, 8; +L_0x84aee1040 .part L_0x84aecfe80, 48, 8; +L_0x84aee1220 .part L_0x84aecfde0, 56, 8; +L_0x84aee12c0 .part L_0x84aecfe80, 56, 8; +L_0x84aed1a40 .arith/sum 32, v0x84b17ed00_0, L_0x84aed19a0; +S_0x84aea0a80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84aea0900; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d8c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d900 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306d940 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d01c20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1dfe0; 1 drivers -v0x8d2d01cc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e080; 1 drivers -v0x8d2d01d60_0 .net *"_ivl_7", 0 0, L_0x8d322c1e0; 1 drivers -v0x8d2d01e00_0 .net *"_ivl_9", 7 0, L_0x8d2d1e1c0; 1 drivers -L_0x8d28552a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d01ea0_0 .net/s "acc_in", 39 0, L_0x8d28552a0; 1 drivers -v0x8d2d01f40_0 .net/s "acc_out", 39 0, L_0x8d3228960; alias, 1 drivers -v0x8d2d01fe0_0 .net/s "product", 31 0, L_0x8d2d1e120; 1 drivers -v0x8d2d02080_0 .net/s "product_ext", 39 0, L_0x8d32288c0; 1 drivers -v0x8d2d02120_0 .net/s "w", 15 0, L_0x8d322c320; 1 drivers -v0x8d2d021c0_0 .net/s "x", 15 0, L_0x8d322c280; 1 drivers -L_0x8d2d1dfe0 .extend/s 32, L_0x8d322c280; -L_0x8d2d1e080 .extend/s 32, L_0x8d322c320; -L_0x8d2d1e120 .arith/mult 32, L_0x8d2d1dfe0, L_0x8d2d1e080; -L_0x8d322c1e0 .part L_0x8d2d1e120, 31, 1; -L_0x8d2d1e1c0 .repeat 8, 8, L_0x8d322c1e0; -L_0x8d32288c0 .concat [ 32 8 0 0], L_0x8d2d1e120, L_0x8d2d1e1c0; -L_0x8d3228960 .arith/sum 40, L_0x8d28552a0, L_0x8d32288c0; -S_0x8d31ffd80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31ffa80; +P_0x84b152d00 .param/l "i" 1 8 20, +C4<00>; +S_0x84aea0c00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea0a80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306d980 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306d9c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306da00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d02260_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e260; 1 drivers -v0x8d2d02300_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e300; 1 drivers -v0x8d2d023a0_0 .net *"_ivl_7", 0 0, L_0x8d322c3c0; 1 drivers -v0x8d2d02440_0 .net *"_ivl_9", 7 0, L_0x8d2d1e440; 1 drivers -L_0x8d28552e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d024e0_0 .net/s "acc_in", 39 0, L_0x8d28552e8; 1 drivers -v0x8d2d02580_0 .net/s "acc_out", 39 0, L_0x8d3228aa0; alias, 1 drivers -v0x8d2d02620_0 .net/s "product", 31 0, L_0x8d2d1e3a0; 1 drivers -v0x8d2d026c0_0 .net/s "product_ext", 39 0, L_0x8d3228a00; 1 drivers -v0x8d2d02760_0 .net/s "w", 15 0, L_0x8d322c500; 1 drivers -v0x8d2d02800_0 .net/s "x", 15 0, L_0x8d322c460; 1 drivers -L_0x8d2d1e260 .extend/s 32, L_0x8d322c460; -L_0x8d2d1e300 .extend/s 32, L_0x8d322c500; -L_0x8d2d1e3a0 .arith/mult 32, L_0x8d2d1e260, L_0x8d2d1e300; -L_0x8d322c3c0 .part L_0x8d2d1e3a0, 31, 1; -L_0x8d2d1e440 .repeat 8, 8, L_0x8d322c3c0; -L_0x8d3228a00 .concat [ 32 8 0 0], L_0x8d2d1e3a0, L_0x8d2d1e440; -L_0x8d3228aa0 .arith/sum 40, L_0x8d28552e8, L_0x8d3228a00; -S_0x8d3208000 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31ffa80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159bc0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159c00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159c40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b176e40_0 .net/s *"_ivl_0", 15 0, L_0x84b19a300; 1 drivers +v0x84b176ee0_0 .net/s *"_ivl_2", 15 0, L_0x84b19a3a0; 1 drivers +v0x84b176f80_0 .net *"_ivl_7", 0 0, L_0x84aecff20; 1 drivers +v0x84b177020_0 .net *"_ivl_9", 15 0, L_0x84aee0000; 1 drivers +L_0x84a879600 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1770c0_0 .net/s "acc_in", 31 0, L_0x84a879600; 1 drivers +v0x84b177160_0 .net/s "acc_out", 31 0, L_0x84aed10e0; alias, 1 drivers +v0x84b177200_0 .net/s "product", 15 0, L_0x84b19a440; 1 drivers +v0x84b1772a0_0 .net/s "product_ext", 31 0, L_0x84b19a4e0; 1 drivers +v0x84b177340_0 .net/s "w", 7 0, L_0x84aee0140; 1 drivers +v0x84b1773e0_0 .net/s "x", 7 0, L_0x84aee00a0; 1 drivers +L_0x84b19a300 .extend/s 16, L_0x84aee00a0; +L_0x84b19a3a0 .extend/s 16, L_0x84aee0140; +L_0x84b19a440 .arith/mult 16, L_0x84b19a300, L_0x84b19a3a0; +L_0x84aecff20 .part L_0x84b19a440, 15, 1; +L_0x84aee0000 .repeat 16, 16, L_0x84aecff20; +L_0x84b19a4e0 .concat [ 16 16 0 0], L_0x84b19a440, L_0x84aee0000; +L_0x84aed10e0 .arith/sum 32, L_0x84a879600, L_0x84b19a4e0; +S_0x84aea0d80 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84aea0900; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306da40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306da80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306dac0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d028a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e4e0; 1 drivers -v0x8d2d02940_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e580; 1 drivers -v0x8d2d029e0_0 .net *"_ivl_7", 0 0, L_0x8d322c5a0; 1 drivers -v0x8d2d02a80_0 .net *"_ivl_9", 7 0, L_0x8d2d1e6c0; 1 drivers -L_0x8d2855330 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d02b20_0 .net/s "acc_in", 39 0, L_0x8d2855330; 1 drivers -v0x8d2d02bc0_0 .net/s "acc_out", 39 0, L_0x8d3228be0; alias, 1 drivers -v0x8d2d02c60_0 .net/s "product", 31 0, L_0x8d2d1e620; 1 drivers -v0x8d2d02d00_0 .net/s "product_ext", 39 0, L_0x8d3228b40; 1 drivers -v0x8d2d02da0_0 .net/s "w", 15 0, L_0x8d322c6e0; 1 drivers -v0x8d2d02e40_0 .net/s "x", 15 0, L_0x8d322c640; 1 drivers -L_0x8d2d1e4e0 .extend/s 32, L_0x8d322c640; -L_0x8d2d1e580 .extend/s 32, L_0x8d322c6e0; -L_0x8d2d1e620 .arith/mult 32, L_0x8d2d1e4e0, L_0x8d2d1e580; -L_0x8d322c5a0 .part L_0x8d2d1e620, 31, 1; -L_0x8d2d1e6c0 .repeat 8, 8, L_0x8d322c5a0; -L_0x8d3228b40 .concat [ 32 8 0 0], L_0x8d2d1e620, L_0x8d2d1e6c0; -L_0x8d3228be0 .arith/sum 40, L_0x8d2855330, L_0x8d3228b40; -S_0x8d3208180 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31ffa80; +P_0x84b152d40 .param/l "i" 1 8 20, +C4<01>; +S_0x84aea0f00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea0d80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306db00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306db40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306db80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d02ee0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e760; 1 drivers -v0x8d2d02f80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e800; 1 drivers -v0x8d2d03020_0 .net *"_ivl_7", 0 0, L_0x8d322c780; 1 drivers -v0x8d2d030c0_0 .net *"_ivl_9", 7 0, L_0x8d2d1e940; 1 drivers -L_0x8d2855378 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d03160_0 .net/s "acc_in", 39 0, L_0x8d2855378; 1 drivers -v0x8d2d03200_0 .net/s "acc_out", 39 0, L_0x8d3228d20; alias, 1 drivers -v0x8d2d032a0_0 .net/s "product", 31 0, L_0x8d2d1e8a0; 1 drivers -v0x8d2d03340_0 .net/s "product_ext", 39 0, L_0x8d3228c80; 1 drivers -v0x8d2d033e0_0 .net/s "w", 15 0, L_0x8d322c8c0; 1 drivers -v0x8d2d03480_0 .net/s "x", 15 0, L_0x8d322c820; 1 drivers -L_0x8d2d1e760 .extend/s 32, L_0x8d322c820; -L_0x8d2d1e800 .extend/s 32, L_0x8d322c8c0; -L_0x8d2d1e8a0 .arith/mult 32, L_0x8d2d1e760, L_0x8d2d1e800; -L_0x8d322c780 .part L_0x8d2d1e8a0, 31, 1; -L_0x8d2d1e940 .repeat 8, 8, L_0x8d322c780; -L_0x8d3228c80 .concat [ 32 8 0 0], L_0x8d2d1e8a0, L_0x8d2d1e940; -L_0x8d3228d20 .arith/sum 40, L_0x8d2855378, L_0x8d3228c80; -S_0x8d3208300 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31ffa80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159c80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159cc0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159d00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b177480_0 .net/s *"_ivl_0", 15 0, L_0x84b19a580; 1 drivers +v0x84b177520_0 .net/s *"_ivl_2", 15 0, L_0x84b19a620; 1 drivers +v0x84b1775c0_0 .net *"_ivl_7", 0 0, L_0x84aee01e0; 1 drivers +v0x84b177660_0 .net *"_ivl_9", 15 0, L_0x84aee0280; 1 drivers +L_0x84a879648 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b177700_0 .net/s "acc_in", 31 0, L_0x84a879648; 1 drivers +v0x84b1777a0_0 .net/s "acc_out", 31 0, L_0x84aed1180; alias, 1 drivers +v0x84b177840_0 .net/s "product", 15 0, L_0x84b19a6c0; 1 drivers +v0x84b1778e0_0 .net/s "product_ext", 31 0, L_0x84b19a760; 1 drivers +v0x84b177980_0 .net/s "w", 7 0, L_0x84aee03c0; 1 drivers +v0x84b177a20_0 .net/s "x", 7 0, L_0x84aee0320; 1 drivers +L_0x84b19a580 .extend/s 16, L_0x84aee0320; +L_0x84b19a620 .extend/s 16, L_0x84aee03c0; +L_0x84b19a6c0 .arith/mult 16, L_0x84b19a580, L_0x84b19a620; +L_0x84aee01e0 .part L_0x84b19a6c0, 15, 1; +L_0x84aee0280 .repeat 16, 16, L_0x84aee01e0; +L_0x84b19a760 .concat [ 16 16 0 0], L_0x84b19a6c0, L_0x84aee0280; +L_0x84aed1180 .arith/sum 32, L_0x84a879648, L_0x84b19a760; +S_0x84aea1080 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84aea0900; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306dbc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306dc00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306dc40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d03520_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e9e0; 1 drivers -v0x8d2d035c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ea80; 1 drivers -v0x8d2d03660_0 .net *"_ivl_7", 0 0, L_0x8d322c960; 1 drivers -v0x8d2d03700_0 .net *"_ivl_9", 7 0, L_0x8d2d1ebc0; 1 drivers -L_0x8d28553c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d037a0_0 .net/s "acc_in", 39 0, L_0x8d28553c0; 1 drivers -v0x8d2d03840_0 .net/s "acc_out", 39 0, L_0x8d3228e60; alias, 1 drivers -v0x8d2d038e0_0 .net/s "product", 31 0, L_0x8d2d1eb20; 1 drivers -v0x8d2d03980_0 .net/s "product_ext", 39 0, L_0x8d3228dc0; 1 drivers -v0x8d2d03a20_0 .net/s "w", 15 0, L_0x8d322caa0; 1 drivers -v0x8d2d03ac0_0 .net/s "x", 15 0, L_0x8d322ca00; 1 drivers -L_0x8d2d1e9e0 .extend/s 32, L_0x8d322ca00; -L_0x8d2d1ea80 .extend/s 32, L_0x8d322caa0; -L_0x8d2d1eb20 .arith/mult 32, L_0x8d2d1e9e0, L_0x8d2d1ea80; -L_0x8d322c960 .part L_0x8d2d1eb20, 31, 1; -L_0x8d2d1ebc0 .repeat 8, 8, L_0x8d322c960; -L_0x8d3228dc0 .concat [ 32 8 0 0], L_0x8d2d1eb20, L_0x8d2d1ebc0; -L_0x8d3228e60 .arith/sum 40, L_0x8d28553c0, L_0x8d3228dc0; -S_0x8d3208480 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31ffa80; +P_0x84b152d80 .param/l "i" 1 8 20, +C4<010>; +S_0x84aea1200 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1080; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306dc80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306dcc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306dd00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d03b60_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ec60; 1 drivers -v0x8d2d03c00_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ed00; 1 drivers -v0x8d2d03ca0_0 .net *"_ivl_7", 0 0, L_0x8d322cb40; 1 drivers -v0x8d2d03d40_0 .net *"_ivl_9", 7 0, L_0x8d2d1ee40; 1 drivers -L_0x8d2855408 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d03de0_0 .net/s "acc_in", 39 0, L_0x8d2855408; 1 drivers -v0x8d2d03e80_0 .net/s "acc_out", 39 0, L_0x8d3228fa0; alias, 1 drivers -v0x8d2d03f20_0 .net/s "product", 31 0, L_0x8d2d1eda0; 1 drivers -v0x8d2d04000_0 .net/s "product_ext", 39 0, L_0x8d3228f00; 1 drivers -v0x8d2d040a0_0 .net/s "w", 15 0, L_0x8d322cc80; 1 drivers -v0x8d2d04140_0 .net/s "x", 15 0, L_0x8d322cbe0; 1 drivers -L_0x8d2d1ec60 .extend/s 32, L_0x8d322cbe0; -L_0x8d2d1ed00 .extend/s 32, L_0x8d322cc80; -L_0x8d2d1eda0 .arith/mult 32, L_0x8d2d1ec60, L_0x8d2d1ed00; -L_0x8d322cb40 .part L_0x8d2d1eda0, 31, 1; -L_0x8d2d1ee40 .repeat 8, 8, L_0x8d322cb40; -L_0x8d3228f00 .concat [ 32 8 0 0], L_0x8d2d1eda0, L_0x8d2d1ee40; -L_0x8d3228fa0 .arith/sum 40, L_0x8d2855408, L_0x8d3228f00; -S_0x8d3208600 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31ffa80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159d40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159d80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159dc0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b177ac0_0 .net/s *"_ivl_0", 15 0, L_0x84b19a800; 1 drivers +v0x84b177b60_0 .net/s *"_ivl_2", 15 0, L_0x84b19a8a0; 1 drivers +v0x84b177c00_0 .net *"_ivl_7", 0 0, L_0x84aee0460; 1 drivers +v0x84b177ca0_0 .net *"_ivl_9", 15 0, L_0x84aee0500; 1 drivers +L_0x84a879690 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b177d40_0 .net/s "acc_in", 31 0, L_0x84a879690; 1 drivers +v0x84b177de0_0 .net/s "acc_out", 31 0, L_0x84aed1220; alias, 1 drivers +v0x84b177e80_0 .net/s "product", 15 0, L_0x84b19a940; 1 drivers +v0x84b177f20_0 .net/s "product_ext", 31 0, L_0x84b19a9e0; 1 drivers +v0x84b17c000_0 .net/s "w", 7 0, L_0x84aee0640; 1 drivers +v0x84b17c0a0_0 .net/s "x", 7 0, L_0x84aee05a0; 1 drivers +L_0x84b19a800 .extend/s 16, L_0x84aee05a0; +L_0x84b19a8a0 .extend/s 16, L_0x84aee0640; +L_0x84b19a940 .arith/mult 16, L_0x84b19a800, L_0x84b19a8a0; +L_0x84aee0460 .part L_0x84b19a940, 15, 1; +L_0x84aee0500 .repeat 16, 16, L_0x84aee0460; +L_0x84b19a9e0 .concat [ 16 16 0 0], L_0x84b19a940, L_0x84aee0500; +L_0x84aed1220 .arith/sum 32, L_0x84a879690, L_0x84b19a9e0; +S_0x84aea1380 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84aea0900; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306dd40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306dd80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ddc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d041e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1eee0; 1 drivers -v0x8d2d04280_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ef80; 1 drivers -v0x8d2d04320_0 .net *"_ivl_7", 0 0, L_0x8d322cd20; 1 drivers -v0x8d2d043c0_0 .net *"_ivl_9", 7 0, L_0x8d2d1f0c0; 1 drivers -L_0x8d2855450 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d04460_0 .net/s "acc_in", 39 0, L_0x8d2855450; 1 drivers -v0x8d2d04500_0 .net/s "acc_out", 39 0, L_0x8d32290e0; alias, 1 drivers -v0x8d2d045a0_0 .net/s "product", 31 0, L_0x8d2d1f020; 1 drivers -v0x8d2d04640_0 .net/s "product_ext", 39 0, L_0x8d3229040; 1 drivers -v0x8d2d046e0_0 .net/s "w", 15 0, L_0x8d322ce60; 1 drivers -v0x8d2d04780_0 .net/s "x", 15 0, L_0x8d322cdc0; 1 drivers -L_0x8d2d1eee0 .extend/s 32, L_0x8d322cdc0; -L_0x8d2d1ef80 .extend/s 32, L_0x8d322ce60; -L_0x8d2d1f020 .arith/mult 32, L_0x8d2d1eee0, L_0x8d2d1ef80; -L_0x8d322cd20 .part L_0x8d2d1f020, 31, 1; -L_0x8d2d1f0c0 .repeat 8, 8, L_0x8d322cd20; -L_0x8d3229040 .concat [ 32 8 0 0], L_0x8d2d1f020, L_0x8d2d1f0c0; -L_0x8d32290e0 .arith/sum 40, L_0x8d2855450, L_0x8d3229040; -S_0x8d3208780 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31ffa80; +P_0x84b152dc0 .param/l "i" 1 8 20, +C4<011>; +S_0x84aea1500 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1380; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306de00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306de40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306de80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d04820_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1f160; 1 drivers -v0x8d2d048c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1f200; 1 drivers -v0x8d2d04960_0 .net *"_ivl_7", 0 0, L_0x8d322cf00; 1 drivers -v0x8d2d04a00_0 .net *"_ivl_9", 7 0, L_0x8d2d1f340; 1 drivers -L_0x8d2855498 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d04aa0_0 .net/s "acc_in", 39 0, L_0x8d2855498; 1 drivers -v0x8d2d04b40_0 .net/s "acc_out", 39 0, L_0x8d3229220; alias, 1 drivers -v0x8d2d04be0_0 .net/s "product", 31 0, L_0x8d2d1f2a0; 1 drivers -v0x8d2d04c80_0 .net/s "product_ext", 39 0, L_0x8d3229180; 1 drivers -v0x8d2d04d20_0 .net/s "w", 15 0, L_0x8d322d040; 1 drivers -v0x8d2d04dc0_0 .net/s "x", 15 0, L_0x8d322cfa0; 1 drivers -L_0x8d2d1f160 .extend/s 32, L_0x8d322cfa0; -L_0x8d2d1f200 .extend/s 32, L_0x8d322d040; -L_0x8d2d1f2a0 .arith/mult 32, L_0x8d2d1f160, L_0x8d2d1f200; -L_0x8d322cf00 .part L_0x8d2d1f2a0, 31, 1; -L_0x8d2d1f340 .repeat 8, 8, L_0x8d322cf00; -L_0x8d3229180 .concat [ 32 8 0 0], L_0x8d2d1f2a0, L_0x8d2d1f340; -L_0x8d3229220 .arith/sum 40, L_0x8d2855498, L_0x8d3229180; -S_0x8d3208900 .scope generate, "GEN_NEURON[5]" "GEN_NEURON[5]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159e00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159e40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159e80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17c140_0 .net/s *"_ivl_0", 15 0, L_0x84b19aa80; 1 drivers +v0x84b17c1e0_0 .net/s *"_ivl_2", 15 0, L_0x84b19ab20; 1 drivers +v0x84b17c280_0 .net *"_ivl_7", 0 0, L_0x84aee06e0; 1 drivers +v0x84b17c320_0 .net *"_ivl_9", 15 0, L_0x84aee0780; 1 drivers +L_0x84a8796d8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17c3c0_0 .net/s "acc_in", 31 0, L_0x84a8796d8; 1 drivers +v0x84b17c460_0 .net/s "acc_out", 31 0, L_0x84aed12c0; alias, 1 drivers +v0x84b17c500_0 .net/s "product", 15 0, L_0x84b19abc0; 1 drivers +v0x84b17c5a0_0 .net/s "product_ext", 31 0, L_0x84b19ac60; 1 drivers +v0x84b17c640_0 .net/s "w", 7 0, L_0x84aee08c0; 1 drivers +v0x84b17c6e0_0 .net/s "x", 7 0, L_0x84aee0820; 1 drivers +L_0x84b19aa80 .extend/s 16, L_0x84aee0820; +L_0x84b19ab20 .extend/s 16, L_0x84aee08c0; +L_0x84b19abc0 .arith/mult 16, L_0x84b19aa80, L_0x84b19ab20; +L_0x84aee06e0 .part L_0x84b19abc0, 15, 1; +L_0x84aee0780 .repeat 16, 16, L_0x84aee06e0; +L_0x84b19ac60 .concat [ 16 16 0 0], L_0x84b19abc0, L_0x84aee0780; +L_0x84aed12c0 .arith/sum 32, L_0x84a8796d8, L_0x84b19ac60; +S_0x84aea1680 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84aea0900; .timescale 0 0; -P_0x8d2c3b200 .param/l "n" 1 4 35, +C4<0101>; -S_0x8d3208a80 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d3208900; +P_0x84b152e00 .param/l "i" 1 8 20, +C4<0100>; +S_0x84aea1800 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1680; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159ec0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159f00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b159f40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17c780_0 .net/s *"_ivl_0", 15 0, L_0x84b19ad00; 1 drivers +v0x84b17c820_0 .net/s *"_ivl_2", 15 0, L_0x84b19ada0; 1 drivers +v0x84b17c8c0_0 .net *"_ivl_7", 0 0, L_0x84aee0960; 1 drivers +v0x84b17c960_0 .net *"_ivl_9", 15 0, L_0x84aee0a00; 1 drivers +L_0x84a879720 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17ca00_0 .net/s "acc_in", 31 0, L_0x84a879720; 1 drivers +v0x84b17caa0_0 .net/s "acc_out", 31 0, L_0x84aed1360; alias, 1 drivers +v0x84b17cb40_0 .net/s "product", 15 0, L_0x84b19ae40; 1 drivers +v0x84b17cbe0_0 .net/s "product_ext", 31 0, L_0x84b19aee0; 1 drivers +v0x84b17cc80_0 .net/s "w", 7 0, L_0x84aee0b40; 1 drivers +v0x84b17cd20_0 .net/s "x", 7 0, L_0x84aee0aa0; 1 drivers +L_0x84b19ad00 .extend/s 16, L_0x84aee0aa0; +L_0x84b19ada0 .extend/s 16, L_0x84aee0b40; +L_0x84b19ae40 .arith/mult 16, L_0x84b19ad00, L_0x84b19ada0; +L_0x84aee0960 .part L_0x84b19ae40, 15, 1; +L_0x84aee0a00 .repeat 16, 16, L_0x84aee0960; +L_0x84b19aee0 .concat [ 16 16 0 0], L_0x84b19ae40, L_0x84aee0a00; +L_0x84aed1360 .arith/sum 32, L_0x84a879720, L_0x84b19aee0; +S_0x84aea1980 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152e40 .param/l "i" 1 8 20, +C4<0101>; +S_0x84aea1b00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1980; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b159f80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b159fc0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a000 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17cdc0_0 .net/s *"_ivl_0", 15 0, L_0x84b19af80; 1 drivers +v0x84b17ce60_0 .net/s *"_ivl_2", 15 0, L_0x84b19b020; 1 drivers +v0x84b17cf00_0 .net *"_ivl_7", 0 0, L_0x84aee0be0; 1 drivers +v0x84b17cfa0_0 .net *"_ivl_9", 15 0, L_0x84aee0c80; 1 drivers +L_0x84a879768 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17d040_0 .net/s "acc_in", 31 0, L_0x84a879768; 1 drivers +v0x84b17d0e0_0 .net/s "acc_out", 31 0, L_0x84aed1400; alias, 1 drivers +v0x84b17d180_0 .net/s "product", 15 0, L_0x84b19b0c0; 1 drivers +v0x84b17d220_0 .net/s "product_ext", 31 0, L_0x84b19b160; 1 drivers +v0x84b17d2c0_0 .net/s "w", 7 0, L_0x84aee0dc0; 1 drivers +v0x84b17d360_0 .net/s "x", 7 0, L_0x84aee0d20; 1 drivers +L_0x84b19af80 .extend/s 16, L_0x84aee0d20; +L_0x84b19b020 .extend/s 16, L_0x84aee0dc0; +L_0x84b19b0c0 .arith/mult 16, L_0x84b19af80, L_0x84b19b020; +L_0x84aee0be0 .part L_0x84b19b0c0, 15, 1; +L_0x84aee0c80 .repeat 16, 16, L_0x84aee0be0; +L_0x84b19b160 .concat [ 16 16 0 0], L_0x84b19b0c0, L_0x84aee0c80; +L_0x84aed1400 .arith/sum 32, L_0x84a879768, L_0x84b19b160; +S_0x84aea1c80 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152e80 .param/l "i" 1 8 20, +C4<0110>; +S_0x84aea1e00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1c80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a040 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a080 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a0c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17d400_0 .net/s *"_ivl_0", 15 0, L_0x84b19b200; 1 drivers +v0x84b17d4a0_0 .net/s *"_ivl_2", 15 0, L_0x84b19b2a0; 1 drivers +v0x84b17d540_0 .net *"_ivl_7", 0 0, L_0x84aee0e60; 1 drivers +v0x84b17d5e0_0 .net *"_ivl_9", 15 0, L_0x84aee0f00; 1 drivers +L_0x84a8797b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17d680_0 .net/s "acc_in", 31 0, L_0x84a8797b0; 1 drivers +v0x84b17d720_0 .net/s "acc_out", 31 0, L_0x84aed14a0; alias, 1 drivers +v0x84b17d7c0_0 .net/s "product", 15 0, L_0x84b19b340; 1 drivers +v0x84b17d860_0 .net/s "product_ext", 31 0, L_0x84b19b3e0; 1 drivers +v0x84b17d900_0 .net/s "w", 7 0, L_0x84aee1040; 1 drivers +v0x84b17d9a0_0 .net/s "x", 7 0, L_0x84aee0fa0; 1 drivers +L_0x84b19b200 .extend/s 16, L_0x84aee0fa0; +L_0x84b19b2a0 .extend/s 16, L_0x84aee1040; +L_0x84b19b340 .arith/mult 16, L_0x84b19b200, L_0x84b19b2a0; +L_0x84aee0e60 .part L_0x84b19b340, 15, 1; +L_0x84aee0f00 .repeat 16, 16, L_0x84aee0e60; +L_0x84b19b3e0 .concat [ 16 16 0 0], L_0x84b19b340, L_0x84aee0f00; +L_0x84aed14a0 .arith/sum 32, L_0x84a8797b0, L_0x84b19b3e0; +S_0x84aea1f80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152ec0 .param/l "i" 1 8 20, +C4<0111>; +S_0x84aea2100 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea1f80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a100 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a140 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a180 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17da40_0 .net/s *"_ivl_0", 15 0, L_0x84b19b480; 1 drivers +v0x84b17dae0_0 .net/s *"_ivl_2", 15 0, L_0x84b19b520; 1 drivers +v0x84b17db80_0 .net *"_ivl_7", 0 0, L_0x84aee10e0; 1 drivers +v0x84b17dc20_0 .net *"_ivl_9", 15 0, L_0x84aee1180; 1 drivers +L_0x84a8797f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17dcc0_0 .net/s "acc_in", 31 0, L_0x84a8797f8; 1 drivers +v0x84b17dd60_0 .net/s "acc_out", 31 0, L_0x84aed1540; alias, 1 drivers +v0x84b17de00_0 .net/s "product", 15 0, L_0x84b19b5c0; 1 drivers +v0x84b17dea0_0 .net/s "product_ext", 31 0, L_0x84b19b660; 1 drivers +v0x84b17df40_0 .net/s "w", 7 0, L_0x84aee12c0; 1 drivers +v0x84b17dfe0_0 .net/s "x", 7 0, L_0x84aee1220; 1 drivers +L_0x84b19b480 .extend/s 16, L_0x84aee1220; +L_0x84b19b520 .extend/s 16, L_0x84aee12c0; +L_0x84b19b5c0 .arith/mult 16, L_0x84b19b480, L_0x84b19b520; +L_0x84aee10e0 .part L_0x84b19b5c0, 15, 1; +L_0x84aee1180 .repeat 16, 16, L_0x84aee10e0; +L_0x84b19b660 .concat [ 16 16 0 0], L_0x84b19b5c0, L_0x84aee1180; +L_0x84aed1540 .arith/sum 32, L_0x84a8797f8, L_0x84b19b660; +S_0x84aea2280 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152f00 .param/l "i" 1 8 80, +C4<00>; +L_0x84aedc150 .functor BUFZ 32, L_0x84aed10e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2400 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152f40 .param/l "i" 1 8 80, +C4<01>; +L_0x84aedc1c0 .functor BUFZ 32, L_0x84aed1180, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2580 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152f80 .param/l "i" 1 8 80, +C4<010>; +L_0x84aedc230 .functor BUFZ 32, L_0x84aed1220, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2700 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b152fc0 .param/l "i" 1 8 80, +C4<011>; +L_0x84aedc2a0 .functor BUFZ 32, L_0x84aed12c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2880 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153000 .param/l "i" 1 8 80, +C4<0100>; +L_0x84aedc310 .functor BUFZ 32, L_0x84aed1360, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2a00 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153040 .param/l "i" 1 8 80, +C4<0101>; +L_0x84aedc380 .functor BUFZ 32, L_0x84aed1400, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2b80 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153080 .param/l "i" 1 8 80, +C4<0110>; +L_0x84aedc3f0 .functor BUFZ 32, L_0x84aed14a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2d00 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b1530c0 .param/l "i" 1 8 80, +C4<0111>; +L_0x84aedc460 .functor BUFZ 32, L_0x84aed1540, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea2e80 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153100 .param/l "level" 1 8 92, +C4<00>; +S_0x84aea3000 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea2e80; + .timescale 0 0; +P_0x84b153140 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed15e0 .arith/sum 32, L_0x84aedc150, L_0x84aedc1c0; +S_0x84aea3180 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aea2e80; + .timescale 0 0; +P_0x84b153180 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed1680 .arith/sum 32, L_0x84aedc230, L_0x84aedc2a0; +S_0x84aea3300 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84aea2e80; + .timescale 0 0; +P_0x84b1531c0 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed1720 .arith/sum 32, L_0x84aedc310, L_0x84aedc380; +S_0x84aea3480 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84aea2e80; + .timescale 0 0; +P_0x84b153200 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed17c0 .arith/sum 32, L_0x84aedc3f0, L_0x84aedc460; +S_0x84aea3600 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153240 .param/l "level" 1 8 92, +C4<01>; +S_0x84aea3780 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea3600; + .timescale 0 0; +P_0x84b153280 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed1860 .arith/sum 32, L_0x84aed15e0, L_0x84aed1680; +S_0x84aea3900 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aea3600; + .timescale 0 0; +P_0x84b1532c0 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed1900 .arith/sum 32, L_0x84aed1720, L_0x84aed17c0; +S_0x84aea3a80 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84aea0900; + .timescale 0 0; +P_0x84b153300 .param/l "level" 1 8 92, +C4<010>; +S_0x84aea3c00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea3a80; + .timescale 0 0; +P_0x84b153340 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed19a0 .arith/sum 32, L_0x84aed1860, L_0x84aed1900; +S_0x84aea3d80 .scope generate, "GEN_NEURON[5]" "GEN_NEURON[5]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b153380 .param/l "n" 1 12 34, +C4<0101>; +S_0x84aea4000 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84aea3d80; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e671f0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e67230 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e67270 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e672b0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e672f0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e67330 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e67370 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c380 .functor BUFZ 16, L_0x8d322e6c0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2d0aee0_0 .net *"_ivl_0", 31 0, L_0x8d32299a0; 1 drivers -v0x8d2d0af80_0 .net *"_ivl_11", 31 0, L_0x8d2d1f5c0; 1 drivers -v0x8d2d0b020_0 .net *"_ivl_14", 31 0, L_0x8d3229a40; 1 drivers -L_0x8d2855600 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b0c0_0 .net *"_ivl_17", 28 0, L_0x8d2855600; 1 drivers -L_0x8d2855648 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b160_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855648; 1 drivers -v0x8d2d0b200_0 .net *"_ivl_21", 31 0, L_0x8d2d1f660; 1 drivers -L_0x8d2855690 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b2a0_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855690; 1 drivers -v0x8d2d0b340_0 .net *"_ivl_25", 31 0, L_0x8d2d1f700; 1 drivers -L_0x8d2855528 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b3e0_0 .net *"_ivl_3", 28 0, L_0x8d2855528; 1 drivers -v0x8d2d0b480_0 .net *"_ivl_31", 0 0, L_0x8d322e440; 1 drivers -v0x8d2d0b520_0 .net *"_ivl_33", 23 0, L_0x8d2d20be0; 1 drivers -v0x8d2d0b5c0_0 .net *"_ivl_36", 39 0, L_0x8d322aa80; 1 drivers -v0x8d2d0b660_0 .net *"_ivl_38", 31 0, L_0x8d322e4e0; 1 drivers -L_0x8d2855570 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b700_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855570; 1 drivers -L_0x8d2855918 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b7a0_0 .net *"_ivl_40", 7 0, L_0x8d2855918; 1 drivers -v0x8d2d0b840_0 .net *"_ivl_46", 31 0, L_0x8d322e580; 1 drivers -v0x8d2d0b8e0_0 .net *"_ivl_7", 31 0, L_0x8d2d1f520; 1 drivers -L_0x8d28555b8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0b980_0 .net/2u *"_ivl_8", 31 0, L_0x8d28555b8; 1 drivers -v0x8d2d0ba20_0 .var/s "acc", 39 0; -v0x8d2d0bac0_0 .net/s "acc_next", 39 0, L_0x8d322a940; 1 drivers -v0x8d2d0bb60_0 .net/s "bias", 15 0, L_0x8d322e6c0; 1 drivers -v0x8d2d0bc00_0 .net/s "bias_ext", 39 0, L_0x8d322a9e0; 1 drivers -v0x8d2d0bca0_0 .net/s "bias_ext_small", 15 0, L_0x8d307c380; 1 drivers -v0x8d2d0bd40_0 .var "busy", 0 0; -v0x8d2d0bde0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2d0be80_0 .var "done", 0 0; -v0x8d2d0bf20_0 .net/s "final_acc", 39 0, L_0x8d322ab20; 1 drivers -v0x8d2d0c000_0 .net/s "final_value", 39 0, L_0x8d2d20c80; 1 drivers -v0x8d2d0c0a0_0 .var "group_index", 2 0; -v0x8d2d0c140_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2d0c1e0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2d0c280_0 .net/s "w_bus", 1023 0, L_0x8d322e620; 1 drivers -v0x8d2d0c320_0 .net/s "w_group", 127 0, L_0x8d322d4a0; 1 drivers -v0x8d2d0c3c0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2d0c460_0 .net/s "x_group", 127 0, L_0x8d322d400; 1 drivers -v0x8d2d0c500_0 .var/s "y", 15 0; -L_0x8d32299a0 .concat [ 3 29 0 0], v0x8d2d0c0a0_0, L_0x8d2855528; -L_0x8d2d1f520 .arith/mult 32, L_0x8d32299a0, L_0x8d2855570; -L_0x8d2d1f5c0 .arith/mult 32, L_0x8d2d1f520, L_0x8d28555b8; -L_0x8d322d400 .part/v v0x8d2d17ca0_0, L_0x8d2d1f5c0, 128; -L_0x8d3229a40 .concat [ 3 29 0 0], v0x8d2d0c0a0_0, L_0x8d2855600; -L_0x8d2d1f660 .arith/mult 32, L_0x8d3229a40, L_0x8d2855648; -L_0x8d2d1f700 .arith/mult 32, L_0x8d2d1f660, L_0x8d2855690; -L_0x8d322d4a0 .part/v L_0x8d322e620, L_0x8d2d1f700, 128; -L_0x8d322e440 .part L_0x8d307c380, 15, 1; -L_0x8d2d20be0 .repeat 24, 24, L_0x8d322e440; -L_0x8d322a9e0 .concat [ 16 24 0 0], L_0x8d307c380, L_0x8d2d20be0; -L_0x8d322e4e0 .part L_0x8d322a9e0, 0, 32; -L_0x8d322aa80 .concat [ 8 32 0 0], L_0x8d2855918, L_0x8d322e4e0; -L_0x8d322ab20 .arith/sum 40, L_0x8d322a940, L_0x8d322aa80; -L_0x8d322e580 .part L_0x8d322ab20, 8, 32; -L_0x8d2d20c80 .extend/s 40, L_0x8d322e580; -S_0x8d3208c00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d3208a80; +P_0x84aea4180 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84aea41c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84aea4200 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84aea4240 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84aea4280 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84aea42c0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b182d00_0 .net *"_ivl_0", 31 0, L_0x84b19b840; 1 drivers +v0x84b182da0_0 .net *"_ivl_11", 31 0, L_0x84b19b980; 1 drivers +v0x84b182e40_0 .net *"_ivl_14", 31 0, L_0x84b19ba20; 1 drivers +L_0x84a879918 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b182ee0_0 .net *"_ivl_17", 29 0, L_0x84a879918; 1 drivers +L_0x84a879960 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b182f80_0 .net/2u *"_ivl_18", 31 0, L_0x84a879960; 1 drivers +v0x84b183020_0 .net *"_ivl_21", 31 0, L_0x84b19bac0; 1 drivers +L_0x84a8799a8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1830c0_0 .net/2u *"_ivl_22", 31 0, L_0x84a8799a8; 1 drivers +v0x84b183160_0 .net *"_ivl_25", 31 0, L_0x84b19bb60; 1 drivers +v0x84b183200_0 .net *"_ivl_29", 0 0, L_0x84aee2b20; 1 drivers +L_0x84a879840 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1832a0_0 .net *"_ivl_3", 29 0, L_0x84a879840; 1 drivers +v0x84b183340_0 .net *"_ivl_31", 23 0, L_0x84aee2bc0; 1 drivers +L_0x84a879888 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1833e0_0 .net/2u *"_ivl_4", 31 0, L_0x84a879888; 1 drivers +v0x84b183480_0 .net *"_ivl_7", 31 0, L_0x84b19b8e0; 1 drivers +L_0x84a8798d0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b183520_0 .net/2u *"_ivl_8", 31 0, L_0x84a8798d0; 1 drivers +v0x84b1835c0_0 .var/s "acc", 31 0; +v0x84b183660_0 .net/s "acc_next", 31 0, L_0x84aed24e0; 1 drivers +v0x84b183700_0 .net/s "bias", 7 0, L_0x84aee2d00; 1 drivers +v0x84b1837a0_0 .net/s "bias_ext", 31 0, L_0x84b1a10e0; 1 drivers +v0x84b183840_0 .var "busy", 0 0; +v0x84b1838e0_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b183980_0 .var "done", 0 0; +v0x84b183a20_0 .net/s "final_acc", 31 0, L_0x84aed2580; 1 drivers +v0x84b183ac0_0 .var "group_index", 1 0; +v0x84b183b60_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b183c00_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b183ca0_0 .net/s "w_bus", 255 0, L_0x84aee2c60; 1 drivers +v0x84b183d40_0 .net/s "w_group", 63 0, L_0x84aee1680; 1 drivers +v0x84b183de0_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b183e80_0 .net/s "x_group", 63 0, L_0x84aee15e0; 1 drivers +v0x84b183f20_0 .var/s "y", 7 0; +L_0x84b19b840 .concat [ 2 30 0 0], v0x84b183ac0_0, L_0x84a879840; +L_0x84b19b8e0 .arith/mult 32, L_0x84b19b840, L_0x84a879888; +L_0x84b19b980 .arith/mult 32, L_0x84b19b8e0, L_0x84a8798d0; +L_0x84aee15e0 .part/v v0x84b191e00_0, L_0x84b19b980, 64; +L_0x84b19ba20 .concat [ 2 30 0 0], v0x84b183ac0_0, L_0x84a879918; +L_0x84b19bac0 .arith/mult 32, L_0x84b19ba20, L_0x84a879960; +L_0x84b19bb60 .arith/mult 32, L_0x84b19bac0, L_0x84a8799a8; +L_0x84aee1680 .part/v L_0x84aee2c60, L_0x84b19bb60, 64; +L_0x84aee2b20 .part L_0x84aee2d00, 7, 1; +L_0x84aee2bc0 .repeat 24, 24, L_0x84aee2b20; +L_0x84b1a10e0 .concat [ 8 24 0 0], L_0x84aee2d00, L_0x84aee2bc0; +L_0x84aed2580 .arith/sum 32, L_0x84aed24e0, L_0x84b1a10e0; +S_0x84aea4300 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84aea4000; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0880 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a08c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2d0a300_0 .net/s "acc_in", 39 0, v0x8d2d0ba20_0; 1 drivers -v0x8d2d0a3a0_0 .net/s "acc_out", 39 0, L_0x8d322a940; alias, 1 drivers -v0x8d2d0a440_0 .net/s "m0", 39 0, L_0x8d3229b80; 1 drivers -v0x8d2d0a4e0_0 .net/s "m1", 39 0, L_0x8d3229cc0; 1 drivers -v0x8d2d0a580_0 .net/s "m2", 39 0, L_0x8d3229e00; 1 drivers -v0x8d2d0a620_0 .net/s "m3", 39 0, L_0x8d3229f40; 1 drivers -v0x8d2d0a6c0_0 .net/s "m4", 39 0, L_0x8d322a080; 1 drivers -v0x8d2d0a760_0 .net/s "m5", 39 0, L_0x8d322a1c0; 1 drivers -v0x8d2d0a800_0 .net/s "m6", 39 0, L_0x8d322a300; 1 drivers -v0x8d2d0a8a0_0 .net/s "m7", 39 0, L_0x8d322a440; 1 drivers -v0x8d2d0a940_0 .net/s "s0", 39 0, L_0x8d322a4e0; 1 drivers -v0x8d2d0a9e0_0 .net/s "s1", 39 0, L_0x8d322a580; 1 drivers -v0x8d2d0aa80_0 .net/s "s2", 39 0, L_0x8d322a620; 1 drivers -v0x8d2d0ab20_0 .net/s "s3", 39 0, L_0x8d322a6c0; 1 drivers -v0x8d2d0abc0_0 .net/s "s4", 39 0, L_0x8d322a760; 1 drivers -v0x8d2d0ac60_0 .net/s "s5", 39 0, L_0x8d322a800; 1 drivers -v0x8d2d0ad00_0 .net/s "sum", 39 0, L_0x8d322a8a0; 1 drivers -v0x8d2d0ada0_0 .net/s "w_bus", 127 0, L_0x8d322d4a0; alias, 1 drivers -v0x8d2d0ae40_0 .net/s "x_bus", 127 0, L_0x8d322d400; alias, 1 drivers -L_0x8d322d5e0 .part L_0x8d322d400, 0, 16; -L_0x8d322d680 .part L_0x8d322d4a0, 0, 16; -L_0x8d322d7c0 .part L_0x8d322d400, 16, 16; -L_0x8d322d860 .part L_0x8d322d4a0, 16, 16; -L_0x8d322d9a0 .part L_0x8d322d400, 32, 16; -L_0x8d322da40 .part L_0x8d322d4a0, 32, 16; -L_0x8d322db80 .part L_0x8d322d400, 48, 16; -L_0x8d322dc20 .part L_0x8d322d4a0, 48, 16; -L_0x8d322dd60 .part L_0x8d322d400, 64, 16; -L_0x8d322de00 .part L_0x8d322d4a0, 64, 16; -L_0x8d322df40 .part L_0x8d322d400, 80, 16; -L_0x8d322dfe0 .part L_0x8d322d4a0, 80, 16; -L_0x8d322e120 .part L_0x8d322d400, 96, 16; -L_0x8d322e1c0 .part L_0x8d322d4a0, 96, 16; -L_0x8d322e300 .part L_0x8d322d400, 112, 16; -L_0x8d322e3a0 .part L_0x8d322d4a0, 112, 16; -L_0x8d322a4e0 .arith/sum 40, L_0x8d3229b80, L_0x8d3229cc0; -L_0x8d322a580 .arith/sum 40, L_0x8d3229e00, L_0x8d3229f40; -L_0x8d322a620 .arith/sum 40, L_0x8d322a080, L_0x8d322a1c0; -L_0x8d322a6c0 .arith/sum 40, L_0x8d322a300, L_0x8d322a440; -L_0x8d322a760 .arith/sum 40, L_0x8d322a4e0, L_0x8d322a580; -L_0x8d322a800 .arith/sum 40, L_0x8d322a620, L_0x8d322a6c0; -L_0x8d322a8a0 .arith/sum 40, L_0x8d322a760, L_0x8d322a800; -L_0x8d322a940 .arith/sum 40, v0x8d2d0ba20_0, L_0x8d322a8a0; -S_0x8d3208d80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d3208c00; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8800 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8840 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8880 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc88c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b182940_0 .net/s "acc_in", 31 0, v0x84b1835c0_0; 1 drivers +v0x84b1829e0_0 .net/s "acc_out", 31 0, L_0x84aed24e0; alias, 1 drivers +v0x84b182a80 .array "products", 7 0; +v0x84b182a80_0 .net/s v0x84b182a80 0, 31 0, L_0x84aed1b80; 1 drivers +v0x84b182a80_1 .net/s v0x84b182a80 1, 31 0, L_0x84aed1c20; 1 drivers +v0x84b182a80_2 .net/s v0x84b182a80 2, 31 0, L_0x84aed1cc0; 1 drivers +v0x84b182a80_3 .net/s v0x84b182a80 3, 31 0, L_0x84aed1d60; 1 drivers +v0x84b182a80_4 .net/s v0x84b182a80 4, 31 0, L_0x84aed1e00; 1 drivers +v0x84b182a80_5 .net/s v0x84b182a80 5, 31 0, L_0x84aed1ea0; 1 drivers +v0x84b182a80_6 .net/s v0x84b182a80 6, 31 0, L_0x84aed1f40; 1 drivers +v0x84b182a80_7 .net/s v0x84b182a80 7, 31 0, L_0x84aed1fe0; 1 drivers +v0x84b182b20 .array "tree", 31 0; +v0x84b182b20_0 .net/s v0x84b182b20 0, 31 0, L_0x84aedc4d0; 1 drivers +v0x84b182b20_1 .net/s v0x84b182b20 1, 31 0, L_0x84aedc540; 1 drivers +v0x84b182b20_2 .net/s v0x84b182b20 2, 31 0, L_0x84aedc5b0; 1 drivers +v0x84b182b20_3 .net/s v0x84b182b20 3, 31 0, L_0x84aedc620; 1 drivers +v0x84b182b20_4 .net/s v0x84b182b20 4, 31 0, L_0x84aedc690; 1 drivers +v0x84b182b20_5 .net/s v0x84b182b20 5, 31 0, L_0x84aedc700; 1 drivers +v0x84b182b20_6 .net/s v0x84b182b20 6, 31 0, L_0x84aedc770; 1 drivers +v0x84b182b20_7 .net/s v0x84b182b20 7, 31 0, L_0x84aedc7e0; 1 drivers +v0x84b182b20_8 .net/s v0x84b182b20 8, 31 0, L_0x84aed2080; 1 drivers +v0x84b182b20_9 .net/s v0x84b182b20 9, 31 0, L_0x84aed2120; 1 drivers +v0x84b182b20_10 .net/s v0x84b182b20 10, 31 0, L_0x84aed21c0; 1 drivers +v0x84b182b20_11 .net/s v0x84b182b20 11, 31 0, L_0x84aed2260; 1 drivers +o0x84a855f20 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_12 .net/s v0x84b182b20 12, 31 0, o0x84a855f20; 0 drivers +o0x84a855f50 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_13 .net/s v0x84b182b20 13, 31 0, o0x84a855f50; 0 drivers +o0x84a855f80 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_14 .net/s v0x84b182b20 14, 31 0, o0x84a855f80; 0 drivers +o0x84a855fb0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_15 .net/s v0x84b182b20 15, 31 0, o0x84a855fb0; 0 drivers +v0x84b182b20_16 .net/s v0x84b182b20 16, 31 0, L_0x84aed2300; 1 drivers +v0x84b182b20_17 .net/s v0x84b182b20 17, 31 0, L_0x84aed23a0; 1 drivers +o0x84a856040 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_18 .net/s v0x84b182b20 18, 31 0, o0x84a856040; 0 drivers +o0x84a856070 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_19 .net/s v0x84b182b20 19, 31 0, o0x84a856070; 0 drivers +o0x84a8560a0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_20 .net/s v0x84b182b20 20, 31 0, o0x84a8560a0; 0 drivers +o0x84a8560d0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_21 .net/s v0x84b182b20 21, 31 0, o0x84a8560d0; 0 drivers +o0x84a856100 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_22 .net/s v0x84b182b20 22, 31 0, o0x84a856100; 0 drivers +o0x84a856130 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_23 .net/s v0x84b182b20 23, 31 0, o0x84a856130; 0 drivers +v0x84b182b20_24 .net/s v0x84b182b20 24, 31 0, L_0x84aed2440; 1 drivers +o0x84a856190 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_25 .net/s v0x84b182b20 25, 31 0, o0x84a856190; 0 drivers +o0x84a8561c0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_26 .net/s v0x84b182b20 26, 31 0, o0x84a8561c0; 0 drivers +o0x84a8561f0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_27 .net/s v0x84b182b20 27, 31 0, o0x84a8561f0; 0 drivers +o0x84a856220 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_28 .net/s v0x84b182b20 28, 31 0, o0x84a856220; 0 drivers +o0x84a856250 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_29 .net/s v0x84b182b20 29, 31 0, o0x84a856250; 0 drivers +o0x84a856280 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_30 .net/s v0x84b182b20 30, 31 0, o0x84a856280; 0 drivers +o0x84a8562b0 .functor BUFZ 32, c4; HiZ drive +v0x84b182b20_31 .net/s v0x84b182b20 31, 31 0, o0x84a8562b0; 0 drivers +v0x84b182bc0_0 .net/s "w_bus", 63 0, L_0x84aee1680; alias, 1 drivers +v0x84b182c60_0 .net/s "x_bus", 63 0, L_0x84aee15e0; alias, 1 drivers +L_0x84aee1860 .part L_0x84aee15e0, 0, 8; +L_0x84aee1900 .part L_0x84aee1680, 0, 8; +L_0x84aee1ae0 .part L_0x84aee15e0, 8, 8; +L_0x84aee1b80 .part L_0x84aee1680, 8, 8; +L_0x84aee1d60 .part L_0x84aee15e0, 16, 8; +L_0x84aee1e00 .part L_0x84aee1680, 16, 8; +L_0x84aee1fe0 .part L_0x84aee15e0, 24, 8; +L_0x84aee2080 .part L_0x84aee1680, 24, 8; +L_0x84aee2260 .part L_0x84aee15e0, 32, 8; +L_0x84aee2300 .part L_0x84aee1680, 32, 8; +L_0x84aee24e0 .part L_0x84aee15e0, 40, 8; +L_0x84aee2580 .part L_0x84aee1680, 40, 8; +L_0x84aee2760 .part L_0x84aee15e0, 48, 8; +L_0x84aee2800 .part L_0x84aee1680, 48, 8; +L_0x84aee29e0 .part L_0x84aee15e0, 56, 8; +L_0x84aee2a80 .part L_0x84aee1680, 56, 8; +L_0x84aed24e0 .arith/sum 32, v0x84b1835c0_0, L_0x84aed2440; +S_0x84aea4480 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84aea4300; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306dec0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306df00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306df40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d070c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1f7a0; 1 drivers -v0x8d2d07160_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1f840; 1 drivers -v0x8d2d07200_0 .net *"_ivl_7", 0 0, L_0x8d322d540; 1 drivers -v0x8d2d072a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1f980; 1 drivers -L_0x8d28556d8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d07340_0 .net/s "acc_in", 39 0, L_0x8d28556d8; 1 drivers -v0x8d2d073e0_0 .net/s "acc_out", 39 0, L_0x8d3229b80; alias, 1 drivers -v0x8d2d07480_0 .net/s "product", 31 0, L_0x8d2d1f8e0; 1 drivers -v0x8d2d07520_0 .net/s "product_ext", 39 0, L_0x8d3229ae0; 1 drivers -v0x8d2d075c0_0 .net/s "w", 15 0, L_0x8d322d680; 1 drivers -v0x8d2d07660_0 .net/s "x", 15 0, L_0x8d322d5e0; 1 drivers -L_0x8d2d1f7a0 .extend/s 32, L_0x8d322d5e0; -L_0x8d2d1f840 .extend/s 32, L_0x8d322d680; -L_0x8d2d1f8e0 .arith/mult 32, L_0x8d2d1f7a0, L_0x8d2d1f840; -L_0x8d322d540 .part L_0x8d2d1f8e0, 31, 1; -L_0x8d2d1f980 .repeat 8, 8, L_0x8d322d540; -L_0x8d3229ae0 .concat [ 32 8 0 0], L_0x8d2d1f8e0, L_0x8d2d1f980; -L_0x8d3229b80 .arith/sum 40, L_0x8d28556d8, L_0x8d3229ae0; -S_0x8d3208f00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d3208c00; +P_0x84b1533c0 .param/l "i" 1 8 20, +C4<00>; +S_0x84aea4600 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea4480; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306df80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306dfc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e000 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d07700_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1fa20; 1 drivers -v0x8d2d077a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1fac0; 1 drivers -v0x8d2d07840_0 .net *"_ivl_7", 0 0, L_0x8d322d720; 1 drivers -v0x8d2d078e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1fc00; 1 drivers -L_0x8d2855720 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d07980_0 .net/s "acc_in", 39 0, L_0x8d2855720; 1 drivers -v0x8d2d07a20_0 .net/s "acc_out", 39 0, L_0x8d3229cc0; alias, 1 drivers -v0x8d2d07ac0_0 .net/s "product", 31 0, L_0x8d2d1fb60; 1 drivers -v0x8d2d07b60_0 .net/s "product_ext", 39 0, L_0x8d3229c20; 1 drivers -v0x8d2d07c00_0 .net/s "w", 15 0, L_0x8d322d860; 1 drivers -v0x8d2d07ca0_0 .net/s "x", 15 0, L_0x8d322d7c0; 1 drivers -L_0x8d2d1fa20 .extend/s 32, L_0x8d322d7c0; -L_0x8d2d1fac0 .extend/s 32, L_0x8d322d860; -L_0x8d2d1fb60 .arith/mult 32, L_0x8d2d1fa20, L_0x8d2d1fac0; -L_0x8d322d720 .part L_0x8d2d1fb60, 31, 1; -L_0x8d2d1fc00 .repeat 8, 8, L_0x8d322d720; -L_0x8d3229c20 .concat [ 32 8 0 0], L_0x8d2d1fb60, L_0x8d2d1fc00; -L_0x8d3229cc0 .arith/sum 40, L_0x8d2855720, L_0x8d3229c20; -S_0x8d3209080 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d3208c00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a1c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a200 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a240 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17f700_0 .net/s *"_ivl_0", 15 0, L_0x84b19bc00; 1 drivers +v0x84b17f7a0_0 .net/s *"_ivl_2", 15 0, L_0x84b19bca0; 1 drivers +v0x84b17f840_0 .net *"_ivl_7", 0 0, L_0x84aee1720; 1 drivers +v0x84b17f8e0_0 .net *"_ivl_9", 15 0, L_0x84aee17c0; 1 drivers +L_0x84a8799f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b17f980_0 .net/s "acc_in", 31 0, L_0x84a8799f0; 1 drivers +v0x84b17fa20_0 .net/s "acc_out", 31 0, L_0x84aed1b80; alias, 1 drivers +v0x84b17fac0_0 .net/s "product", 15 0, L_0x84b19bd40; 1 drivers +v0x84b17fb60_0 .net/s "product_ext", 31 0, L_0x84b19bde0; 1 drivers +v0x84b17fc00_0 .net/s "w", 7 0, L_0x84aee1900; 1 drivers +v0x84b17fca0_0 .net/s "x", 7 0, L_0x84aee1860; 1 drivers +L_0x84b19bc00 .extend/s 16, L_0x84aee1860; +L_0x84b19bca0 .extend/s 16, L_0x84aee1900; +L_0x84b19bd40 .arith/mult 16, L_0x84b19bc00, L_0x84b19bca0; +L_0x84aee1720 .part L_0x84b19bd40, 15, 1; +L_0x84aee17c0 .repeat 16, 16, L_0x84aee1720; +L_0x84b19bde0 .concat [ 16 16 0 0], L_0x84b19bd40, L_0x84aee17c0; +L_0x84aed1b80 .arith/sum 32, L_0x84a8799f0, L_0x84b19bde0; +S_0x84aea4780 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84aea4300; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e040 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e080 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e0c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d07d40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1fca0; 1 drivers -v0x8d2d07de0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1fd40; 1 drivers -v0x8d2d07e80_0 .net *"_ivl_7", 0 0, L_0x8d322d900; 1 drivers -v0x8d2d07f20_0 .net *"_ivl_9", 7 0, L_0x8d2d1fe80; 1 drivers -L_0x8d2855768 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d08000_0 .net/s "acc_in", 39 0, L_0x8d2855768; 1 drivers -v0x8d2d080a0_0 .net/s "acc_out", 39 0, L_0x8d3229e00; alias, 1 drivers -v0x8d2d08140_0 .net/s "product", 31 0, L_0x8d2d1fde0; 1 drivers -v0x8d2d081e0_0 .net/s "product_ext", 39 0, L_0x8d3229d60; 1 drivers -v0x8d2d08280_0 .net/s "w", 15 0, L_0x8d322da40; 1 drivers -v0x8d2d08320_0 .net/s "x", 15 0, L_0x8d322d9a0; 1 drivers -L_0x8d2d1fca0 .extend/s 32, L_0x8d322d9a0; -L_0x8d2d1fd40 .extend/s 32, L_0x8d322da40; -L_0x8d2d1fde0 .arith/mult 32, L_0x8d2d1fca0, L_0x8d2d1fd40; -L_0x8d322d900 .part L_0x8d2d1fde0, 31, 1; -L_0x8d2d1fe80 .repeat 8, 8, L_0x8d322d900; -L_0x8d3229d60 .concat [ 32 8 0 0], L_0x8d2d1fde0, L_0x8d2d1fe80; -L_0x8d3229e00 .arith/sum 40, L_0x8d2855768, L_0x8d3229d60; -S_0x8d3209200 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d3208c00; +P_0x84b153400 .param/l "i" 1 8 20, +C4<01>; +S_0x84aea4900 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea4780; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e100 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e140 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e180 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d083c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ff20; 1 drivers -v0x8d2d08460_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20000; 1 drivers -v0x8d2d08500_0 .net *"_ivl_7", 0 0, L_0x8d322dae0; 1 drivers -v0x8d2d085a0_0 .net *"_ivl_9", 7 0, L_0x8d2d20140; 1 drivers -L_0x8d28557b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d08640_0 .net/s "acc_in", 39 0, L_0x8d28557b0; 1 drivers -v0x8d2d086e0_0 .net/s "acc_out", 39 0, L_0x8d3229f40; alias, 1 drivers -v0x8d2d08780_0 .net/s "product", 31 0, L_0x8d2d200a0; 1 drivers -v0x8d2d08820_0 .net/s "product_ext", 39 0, L_0x8d3229ea0; 1 drivers -v0x8d2d088c0_0 .net/s "w", 15 0, L_0x8d322dc20; 1 drivers -v0x8d2d08960_0 .net/s "x", 15 0, L_0x8d322db80; 1 drivers -L_0x8d2d1ff20 .extend/s 32, L_0x8d322db80; -L_0x8d2d20000 .extend/s 32, L_0x8d322dc20; -L_0x8d2d200a0 .arith/mult 32, L_0x8d2d1ff20, L_0x8d2d20000; -L_0x8d322dae0 .part L_0x8d2d200a0, 31, 1; -L_0x8d2d20140 .repeat 8, 8, L_0x8d322dae0; -L_0x8d3229ea0 .concat [ 32 8 0 0], L_0x8d2d200a0, L_0x8d2d20140; -L_0x8d3229f40 .arith/sum 40, L_0x8d28557b0, L_0x8d3229ea0; -S_0x8d3209380 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d3208c00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a280 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a2c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a300 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b17fd40_0 .net/s *"_ivl_0", 15 0, L_0x84b19be80; 1 drivers +v0x84b17fde0_0 .net/s *"_ivl_2", 15 0, L_0x84b19bf20; 1 drivers +v0x84b17fe80_0 .net *"_ivl_7", 0 0, L_0x84aee19a0; 1 drivers +v0x84b17ff20_0 .net *"_ivl_9", 15 0, L_0x84aee1a40; 1 drivers +L_0x84a879a38 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b180000_0 .net/s "acc_in", 31 0, L_0x84a879a38; 1 drivers +v0x84b1800a0_0 .net/s "acc_out", 31 0, L_0x84aed1c20; alias, 1 drivers +v0x84b180140_0 .net/s "product", 15 0, L_0x84b1a0000; 1 drivers +v0x84b1801e0_0 .net/s "product_ext", 31 0, L_0x84b1a00a0; 1 drivers +v0x84b180280_0 .net/s "w", 7 0, L_0x84aee1b80; 1 drivers +v0x84b180320_0 .net/s "x", 7 0, L_0x84aee1ae0; 1 drivers +L_0x84b19be80 .extend/s 16, L_0x84aee1ae0; +L_0x84b19bf20 .extend/s 16, L_0x84aee1b80; +L_0x84b1a0000 .arith/mult 16, L_0x84b19be80, L_0x84b19bf20; +L_0x84aee19a0 .part L_0x84b1a0000, 15, 1; +L_0x84aee1a40 .repeat 16, 16, L_0x84aee19a0; +L_0x84b1a00a0 .concat [ 16 16 0 0], L_0x84b1a0000, L_0x84aee1a40; +L_0x84aed1c20 .arith/sum 32, L_0x84a879a38, L_0x84b1a00a0; +S_0x84aea4a80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84aea4300; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e1c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e200 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e240 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d08a00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d201e0; 1 drivers -v0x8d2d08aa0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20280; 1 drivers -v0x8d2d08b40_0 .net *"_ivl_7", 0 0, L_0x8d322dcc0; 1 drivers -v0x8d2d08be0_0 .net *"_ivl_9", 7 0, L_0x8d2d203c0; 1 drivers -L_0x8d28557f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d08c80_0 .net/s "acc_in", 39 0, L_0x8d28557f8; 1 drivers -v0x8d2d08d20_0 .net/s "acc_out", 39 0, L_0x8d322a080; alias, 1 drivers -v0x8d2d08dc0_0 .net/s "product", 31 0, L_0x8d2d20320; 1 drivers -v0x8d2d08e60_0 .net/s "product_ext", 39 0, L_0x8d3229fe0; 1 drivers -v0x8d2d08f00_0 .net/s "w", 15 0, L_0x8d322de00; 1 drivers -v0x8d2d08fa0_0 .net/s "x", 15 0, L_0x8d322dd60; 1 drivers -L_0x8d2d201e0 .extend/s 32, L_0x8d322dd60; -L_0x8d2d20280 .extend/s 32, L_0x8d322de00; -L_0x8d2d20320 .arith/mult 32, L_0x8d2d201e0, L_0x8d2d20280; -L_0x8d322dcc0 .part L_0x8d2d20320, 31, 1; -L_0x8d2d203c0 .repeat 8, 8, L_0x8d322dcc0; -L_0x8d3229fe0 .concat [ 32 8 0 0], L_0x8d2d20320, L_0x8d2d203c0; -L_0x8d322a080 .arith/sum 40, L_0x8d28557f8, L_0x8d3229fe0; -S_0x8d3209500 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d3208c00; +P_0x84b153440 .param/l "i" 1 8 20, +C4<010>; +S_0x84aea4c00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea4a80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e280 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e2c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e300 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d09040_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20460; 1 drivers -v0x8d2d090e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20500; 1 drivers -v0x8d2d09180_0 .net *"_ivl_7", 0 0, L_0x8d322dea0; 1 drivers -v0x8d2d09220_0 .net *"_ivl_9", 7 0, L_0x8d2d20640; 1 drivers -L_0x8d2855840 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d092c0_0 .net/s "acc_in", 39 0, L_0x8d2855840; 1 drivers -v0x8d2d09360_0 .net/s "acc_out", 39 0, L_0x8d322a1c0; alias, 1 drivers -v0x8d2d09400_0 .net/s "product", 31 0, L_0x8d2d205a0; 1 drivers -v0x8d2d094a0_0 .net/s "product_ext", 39 0, L_0x8d322a120; 1 drivers -v0x8d2d09540_0 .net/s "w", 15 0, L_0x8d322dfe0; 1 drivers -v0x8d2d095e0_0 .net/s "x", 15 0, L_0x8d322df40; 1 drivers -L_0x8d2d20460 .extend/s 32, L_0x8d322df40; -L_0x8d2d20500 .extend/s 32, L_0x8d322dfe0; -L_0x8d2d205a0 .arith/mult 32, L_0x8d2d20460, L_0x8d2d20500; -L_0x8d322dea0 .part L_0x8d2d205a0, 31, 1; -L_0x8d2d20640 .repeat 8, 8, L_0x8d322dea0; -L_0x8d322a120 .concat [ 32 8 0 0], L_0x8d2d205a0, L_0x8d2d20640; -L_0x8d322a1c0 .arith/sum 40, L_0x8d2855840, L_0x8d322a120; -S_0x8d3209680 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d3208c00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a340 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a380 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a3c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1803c0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a0140; 1 drivers +v0x84b180460_0 .net/s *"_ivl_2", 15 0, L_0x84b1a01e0; 1 drivers +v0x84b180500_0 .net *"_ivl_7", 0 0, L_0x84aee1c20; 1 drivers +v0x84b1805a0_0 .net *"_ivl_9", 15 0, L_0x84aee1cc0; 1 drivers +L_0x84a879a80 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b180640_0 .net/s "acc_in", 31 0, L_0x84a879a80; 1 drivers +v0x84b1806e0_0 .net/s "acc_out", 31 0, L_0x84aed1cc0; alias, 1 drivers +v0x84b180780_0 .net/s "product", 15 0, L_0x84b1a0280; 1 drivers +v0x84b180820_0 .net/s "product_ext", 31 0, L_0x84b1a0320; 1 drivers +v0x84b1808c0_0 .net/s "w", 7 0, L_0x84aee1e00; 1 drivers +v0x84b180960_0 .net/s "x", 7 0, L_0x84aee1d60; 1 drivers +L_0x84b1a0140 .extend/s 16, L_0x84aee1d60; +L_0x84b1a01e0 .extend/s 16, L_0x84aee1e00; +L_0x84b1a0280 .arith/mult 16, L_0x84b1a0140, L_0x84b1a01e0; +L_0x84aee1c20 .part L_0x84b1a0280, 15, 1; +L_0x84aee1cc0 .repeat 16, 16, L_0x84aee1c20; +L_0x84b1a0320 .concat [ 16 16 0 0], L_0x84b1a0280, L_0x84aee1cc0; +L_0x84aed1cc0 .arith/sum 32, L_0x84a879a80, L_0x84b1a0320; +S_0x84aea4d80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84aea4300; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e340 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e380 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e3c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d09680_0 .net/s *"_ivl_0", 31 0, L_0x8d2d206e0; 1 drivers -v0x8d2d09720_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20780; 1 drivers -v0x8d2d097c0_0 .net *"_ivl_7", 0 0, L_0x8d322e080; 1 drivers -v0x8d2d09860_0 .net *"_ivl_9", 7 0, L_0x8d2d208c0; 1 drivers -L_0x8d2855888 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d09900_0 .net/s "acc_in", 39 0, L_0x8d2855888; 1 drivers -v0x8d2d099a0_0 .net/s "acc_out", 39 0, L_0x8d322a300; alias, 1 drivers -v0x8d2d09a40_0 .net/s "product", 31 0, L_0x8d2d20820; 1 drivers -v0x8d2d09ae0_0 .net/s "product_ext", 39 0, L_0x8d322a260; 1 drivers -v0x8d2d09b80_0 .net/s "w", 15 0, L_0x8d322e1c0; 1 drivers -v0x8d2d09c20_0 .net/s "x", 15 0, L_0x8d322e120; 1 drivers -L_0x8d2d206e0 .extend/s 32, L_0x8d322e120; -L_0x8d2d20780 .extend/s 32, L_0x8d322e1c0; -L_0x8d2d20820 .arith/mult 32, L_0x8d2d206e0, L_0x8d2d20780; -L_0x8d322e080 .part L_0x8d2d20820, 31, 1; -L_0x8d2d208c0 .repeat 8, 8, L_0x8d322e080; -L_0x8d322a260 .concat [ 32 8 0 0], L_0x8d2d20820, L_0x8d2d208c0; -L_0x8d322a300 .arith/sum 40, L_0x8d2855888, L_0x8d322a260; -S_0x8d3209800 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d3208c00; +P_0x84b153480 .param/l "i" 1 8 20, +C4<011>; +S_0x84aea4f00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea4d80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e400 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e440 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e480 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d09cc0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20960; 1 drivers -v0x8d2d09d60_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20a00; 1 drivers -v0x8d2d09e00_0 .net *"_ivl_7", 0 0, L_0x8d322e260; 1 drivers -v0x8d2d09ea0_0 .net *"_ivl_9", 7 0, L_0x8d2d20b40; 1 drivers -L_0x8d28558d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d09f40_0 .net/s "acc_in", 39 0, L_0x8d28558d0; 1 drivers -v0x8d2d09fe0_0 .net/s "acc_out", 39 0, L_0x8d322a440; alias, 1 drivers -v0x8d2d0a080_0 .net/s "product", 31 0, L_0x8d2d20aa0; 1 drivers -v0x8d2d0a120_0 .net/s "product_ext", 39 0, L_0x8d322a3a0; 1 drivers -v0x8d2d0a1c0_0 .net/s "w", 15 0, L_0x8d322e3a0; 1 drivers -v0x8d2d0a260_0 .net/s "x", 15 0, L_0x8d322e300; 1 drivers -L_0x8d2d20960 .extend/s 32, L_0x8d322e300; -L_0x8d2d20a00 .extend/s 32, L_0x8d322e3a0; -L_0x8d2d20aa0 .arith/mult 32, L_0x8d2d20960, L_0x8d2d20a00; -L_0x8d322e260 .part L_0x8d2d20aa0, 31, 1; -L_0x8d2d20b40 .repeat 8, 8, L_0x8d322e260; -L_0x8d322a3a0 .concat [ 32 8 0 0], L_0x8d2d20aa0, L_0x8d2d20b40; -L_0x8d322a440 .arith/sum 40, L_0x8d28558d0, L_0x8d322a3a0; -S_0x8d3209980 .scope generate, "GEN_NEURON[6]" "GEN_NEURON[6]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a400 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a440 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a480 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b180a00_0 .net/s *"_ivl_0", 15 0, L_0x84b1a03c0; 1 drivers +v0x84b180aa0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a0460; 1 drivers +v0x84b180b40_0 .net *"_ivl_7", 0 0, L_0x84aee1ea0; 1 drivers +v0x84b180be0_0 .net *"_ivl_9", 15 0, L_0x84aee1f40; 1 drivers +L_0x84a879ac8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b180c80_0 .net/s "acc_in", 31 0, L_0x84a879ac8; 1 drivers +v0x84b180d20_0 .net/s "acc_out", 31 0, L_0x84aed1d60; alias, 1 drivers +v0x84b180dc0_0 .net/s "product", 15 0, L_0x84b1a0500; 1 drivers +v0x84b180e60_0 .net/s "product_ext", 31 0, L_0x84b1a05a0; 1 drivers +v0x84b180f00_0 .net/s "w", 7 0, L_0x84aee2080; 1 drivers +v0x84b180fa0_0 .net/s "x", 7 0, L_0x84aee1fe0; 1 drivers +L_0x84b1a03c0 .extend/s 16, L_0x84aee1fe0; +L_0x84b1a0460 .extend/s 16, L_0x84aee2080; +L_0x84b1a0500 .arith/mult 16, L_0x84b1a03c0, L_0x84b1a0460; +L_0x84aee1ea0 .part L_0x84b1a0500, 15, 1; +L_0x84aee1f40 .repeat 16, 16, L_0x84aee1ea0; +L_0x84b1a05a0 .concat [ 16 16 0 0], L_0x84b1a0500, L_0x84aee1f40; +L_0x84aed1d60 .arith/sum 32, L_0x84a879ac8, L_0x84b1a05a0; +S_0x84aea5080 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84aea4300; .timescale 0 0; -P_0x8d2c3b240 .param/l "n" 1 4 35, +C4<0110>; -S_0x8d3209b00 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d3209980; +P_0x84b1534c0 .param/l "i" 1 8 20, +C4<0100>; +S_0x84aea5200 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea5080; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a4c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a500 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a540 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b181040_0 .net/s *"_ivl_0", 15 0, L_0x84b1a0640; 1 drivers +v0x84b1810e0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a06e0; 1 drivers +v0x84b181180_0 .net *"_ivl_7", 0 0, L_0x84aee2120; 1 drivers +v0x84b181220_0 .net *"_ivl_9", 15 0, L_0x84aee21c0; 1 drivers +L_0x84a879b10 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1812c0_0 .net/s "acc_in", 31 0, L_0x84a879b10; 1 drivers +v0x84b181360_0 .net/s "acc_out", 31 0, L_0x84aed1e00; alias, 1 drivers +v0x84b181400_0 .net/s "product", 15 0, L_0x84b1a0780; 1 drivers +v0x84b1814a0_0 .net/s "product_ext", 31 0, L_0x84b1a0820; 1 drivers +v0x84b181540_0 .net/s "w", 7 0, L_0x84aee2300; 1 drivers +v0x84b1815e0_0 .net/s "x", 7 0, L_0x84aee2260; 1 drivers +L_0x84b1a0640 .extend/s 16, L_0x84aee2260; +L_0x84b1a06e0 .extend/s 16, L_0x84aee2300; +L_0x84b1a0780 .arith/mult 16, L_0x84b1a0640, L_0x84b1a06e0; +L_0x84aee2120 .part L_0x84b1a0780, 15, 1; +L_0x84aee21c0 .repeat 16, 16, L_0x84aee2120; +L_0x84b1a0820 .concat [ 16 16 0 0], L_0x84b1a0780, L_0x84aee21c0; +L_0x84aed1e00 .arith/sum 32, L_0x84a879b10, L_0x84b1a0820; +S_0x84aea5380 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153500 .param/l "i" 1 8 20, +C4<0101>; +S_0x84aea5500 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea5380; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a580 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a5c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a600 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b181680_0 .net/s *"_ivl_0", 15 0, L_0x84b1a08c0; 1 drivers +v0x84b181720_0 .net/s *"_ivl_2", 15 0, L_0x84b1a0960; 1 drivers +v0x84b1817c0_0 .net *"_ivl_7", 0 0, L_0x84aee23a0; 1 drivers +v0x84b181860_0 .net *"_ivl_9", 15 0, L_0x84aee2440; 1 drivers +L_0x84a879b58 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b181900_0 .net/s "acc_in", 31 0, L_0x84a879b58; 1 drivers +v0x84b1819a0_0 .net/s "acc_out", 31 0, L_0x84aed1ea0; alias, 1 drivers +v0x84b181a40_0 .net/s "product", 15 0, L_0x84b1a0a00; 1 drivers +v0x84b181ae0_0 .net/s "product_ext", 31 0, L_0x84b1a0aa0; 1 drivers +v0x84b181b80_0 .net/s "w", 7 0, L_0x84aee2580; 1 drivers +v0x84b181c20_0 .net/s "x", 7 0, L_0x84aee24e0; 1 drivers +L_0x84b1a08c0 .extend/s 16, L_0x84aee24e0; +L_0x84b1a0960 .extend/s 16, L_0x84aee2580; +L_0x84b1a0a00 .arith/mult 16, L_0x84b1a08c0, L_0x84b1a0960; +L_0x84aee23a0 .part L_0x84b1a0a00, 15, 1; +L_0x84aee2440 .repeat 16, 16, L_0x84aee23a0; +L_0x84b1a0aa0 .concat [ 16 16 0 0], L_0x84b1a0a00, L_0x84aee2440; +L_0x84aed1ea0 .arith/sum 32, L_0x84a879b58, L_0x84b1a0aa0; +S_0x84aea5680 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153540 .param/l "i" 1 8 20, +C4<0110>; +S_0x84aea5800 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea5680; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a640 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a680 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a6c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b181cc0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a0b40; 1 drivers +v0x84b181d60_0 .net/s *"_ivl_2", 15 0, L_0x84b1a0be0; 1 drivers +v0x84b181e00_0 .net *"_ivl_7", 0 0, L_0x84aee2620; 1 drivers +v0x84b181ea0_0 .net *"_ivl_9", 15 0, L_0x84aee26c0; 1 drivers +L_0x84a879ba0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b181f40_0 .net/s "acc_in", 31 0, L_0x84a879ba0; 1 drivers +v0x84b181fe0_0 .net/s "acc_out", 31 0, L_0x84aed1f40; alias, 1 drivers +v0x84b182080_0 .net/s "product", 15 0, L_0x84b1a0c80; 1 drivers +v0x84b182120_0 .net/s "product_ext", 31 0, L_0x84b1a0d20; 1 drivers +v0x84b1821c0_0 .net/s "w", 7 0, L_0x84aee2800; 1 drivers +v0x84b182260_0 .net/s "x", 7 0, L_0x84aee2760; 1 drivers +L_0x84b1a0b40 .extend/s 16, L_0x84aee2760; +L_0x84b1a0be0 .extend/s 16, L_0x84aee2800; +L_0x84b1a0c80 .arith/mult 16, L_0x84b1a0b40, L_0x84b1a0be0; +L_0x84aee2620 .part L_0x84b1a0c80, 15, 1; +L_0x84aee26c0 .repeat 16, 16, L_0x84aee2620; +L_0x84b1a0d20 .concat [ 16 16 0 0], L_0x84b1a0c80, L_0x84aee26c0; +L_0x84aed1f40 .arith/sum 32, L_0x84a879ba0, L_0x84b1a0d20; +S_0x84aea5980 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153580 .param/l "i" 1 8 20, +C4<0111>; +S_0x84aea5b00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea5980; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a700 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a740 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a780 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b182300_0 .net/s *"_ivl_0", 15 0, L_0x84b1a0dc0; 1 drivers +v0x84b1823a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a0e60; 1 drivers +v0x84b182440_0 .net *"_ivl_7", 0 0, L_0x84aee28a0; 1 drivers +v0x84b1824e0_0 .net *"_ivl_9", 15 0, L_0x84aee2940; 1 drivers +L_0x84a879be8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b182580_0 .net/s "acc_in", 31 0, L_0x84a879be8; 1 drivers +v0x84b182620_0 .net/s "acc_out", 31 0, L_0x84aed1fe0; alias, 1 drivers +v0x84b1826c0_0 .net/s "product", 15 0, L_0x84b1a0f00; 1 drivers +v0x84b182760_0 .net/s "product_ext", 31 0, L_0x84b1a0fa0; 1 drivers +v0x84b182800_0 .net/s "w", 7 0, L_0x84aee2a80; 1 drivers +v0x84b1828a0_0 .net/s "x", 7 0, L_0x84aee29e0; 1 drivers +L_0x84b1a0dc0 .extend/s 16, L_0x84aee29e0; +L_0x84b1a0e60 .extend/s 16, L_0x84aee2a80; +L_0x84b1a0f00 .arith/mult 16, L_0x84b1a0dc0, L_0x84b1a0e60; +L_0x84aee28a0 .part L_0x84b1a0f00, 15, 1; +L_0x84aee2940 .repeat 16, 16, L_0x84aee28a0; +L_0x84b1a0fa0 .concat [ 16 16 0 0], L_0x84b1a0f00, L_0x84aee2940; +L_0x84aed1fe0 .arith/sum 32, L_0x84a879be8, L_0x84b1a0fa0; +S_0x84aea5c80 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b1535c0 .param/l "i" 1 8 80, +C4<00>; +L_0x84aedc4d0 .functor BUFZ 32, L_0x84aed1b80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea5e00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153600 .param/l "i" 1 8 80, +C4<01>; +L_0x84aedc540 .functor BUFZ 32, L_0x84aed1c20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea5f80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153640 .param/l "i" 1 8 80, +C4<010>; +L_0x84aedc5b0 .functor BUFZ 32, L_0x84aed1cc0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6100 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153680 .param/l "i" 1 8 80, +C4<011>; +L_0x84aedc620 .functor BUFZ 32, L_0x84aed1d60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6280 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b1536c0 .param/l "i" 1 8 80, +C4<0100>; +L_0x84aedc690 .functor BUFZ 32, L_0x84aed1e00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6400 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153700 .param/l "i" 1 8 80, +C4<0101>; +L_0x84aedc700 .functor BUFZ 32, L_0x84aed1ea0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6580 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153740 .param/l "i" 1 8 80, +C4<0110>; +L_0x84aedc770 .functor BUFZ 32, L_0x84aed1f40, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6700 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153780 .param/l "i" 1 8 80, +C4<0111>; +L_0x84aedc7e0 .functor BUFZ 32, L_0x84aed1fe0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aea6880 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b1537c0 .param/l "level" 1 8 92, +C4<00>; +S_0x84aea6a00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea6880; + .timescale 0 0; +P_0x84b153800 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2080 .arith/sum 32, L_0x84aedc4d0, L_0x84aedc540; +S_0x84aea6b80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aea6880; + .timescale 0 0; +P_0x84b153840 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed2120 .arith/sum 32, L_0x84aedc5b0, L_0x84aedc620; +S_0x84aea6d00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84aea6880; + .timescale 0 0; +P_0x84b153880 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed21c0 .arith/sum 32, L_0x84aedc690, L_0x84aedc700; +S_0x84aea6e80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84aea6880; + .timescale 0 0; +P_0x84b1538c0 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed2260 .arith/sum 32, L_0x84aedc770, L_0x84aedc7e0; +S_0x84aea7000 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b153900 .param/l "level" 1 8 92, +C4<01>; +S_0x84aea7180 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea7000; + .timescale 0 0; +P_0x84b153940 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2300 .arith/sum 32, L_0x84aed2080, L_0x84aed2120; +S_0x84aea7300 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aea7000; + .timescale 0 0; +P_0x84b153980 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed23a0 .arith/sum 32, L_0x84aed21c0, L_0x84aed2260; +S_0x84aea7480 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84aea4300; + .timescale 0 0; +P_0x84b1539c0 .param/l "level" 1 8 92, +C4<010>; +S_0x84aea7600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aea7480; + .timescale 0 0; +P_0x84b153a00 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2440 .arith/sum 32, L_0x84aed2300, L_0x84aed23a0; +S_0x84aea7780 .scope generate, "GEN_NEURON[6]" "GEN_NEURON[6]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b153a40 .param/l "n" 1 12 34, +C4<0110>; +S_0x84aea7900 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84aea7780; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e673b0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e673f0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e67430 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e67470 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e674b0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e674f0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e67530 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c3f0 .functor BUFZ 16, L_0x8d322fa20, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2d103c0_0 .net *"_ivl_0", 31 0, L_0x8d322abc0; 1 drivers -v0x8d2d10460_0 .net *"_ivl_11", 31 0, L_0x8d2d20dc0; 1 drivers -v0x8d2d10500_0 .net *"_ivl_14", 31 0, L_0x8d322ac60; 1 drivers -L_0x8d2855a38 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d105a0_0 .net *"_ivl_17", 28 0, L_0x8d2855a38; 1 drivers -L_0x8d2855a80 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d10640_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855a80; 1 drivers -v0x8d2d106e0_0 .net *"_ivl_21", 31 0, L_0x8d2d20e60; 1 drivers -L_0x8d2855ac8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d10780_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855ac8; 1 drivers -v0x8d2d10820_0 .net *"_ivl_25", 31 0, L_0x8d2d20f00; 1 drivers -L_0x8d2855960 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d108c0_0 .net *"_ivl_3", 28 0, L_0x8d2855960; 1 drivers -v0x8d2d10960_0 .net *"_ivl_31", 0 0, L_0x8d322f7a0; 1 drivers -v0x8d2d10a00_0 .net *"_ivl_33", 23 0, L_0x8d2d223a0; 1 drivers -v0x8d2d10aa0_0 .net *"_ivl_36", 39 0, L_0x8d322bca0; 1 drivers -v0x8d2d10b40_0 .net *"_ivl_38", 31 0, L_0x8d322f840; 1 drivers -L_0x8d28559a8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d10be0_0 .net/2u *"_ivl_4", 31 0, L_0x8d28559a8; 1 drivers -L_0x8d2855d50 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d10c80_0 .net *"_ivl_40", 7 0, L_0x8d2855d50; 1 drivers -v0x8d2d10d20_0 .net *"_ivl_46", 31 0, L_0x8d322f8e0; 1 drivers -v0x8d2d10dc0_0 .net *"_ivl_7", 31 0, L_0x8d2d20d20; 1 drivers -L_0x8d28559f0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d10e60_0 .net/2u *"_ivl_8", 31 0, L_0x8d28559f0; 1 drivers -v0x8d2d10f00_0 .var/s "acc", 39 0; -v0x8d2d10fa0_0 .net/s "acc_next", 39 0, L_0x8d322bb60; 1 drivers -v0x8d2d11040_0 .net/s "bias", 15 0, L_0x8d322fa20; 1 drivers -v0x8d2d110e0_0 .net/s "bias_ext", 39 0, L_0x8d322bc00; 1 drivers -v0x8d2d11180_0 .net/s "bias_ext_small", 15 0, L_0x8d307c3f0; 1 drivers -v0x8d2d11220_0 .var "busy", 0 0; -v0x8d2d112c0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2d11360_0 .var "done", 0 0; -v0x8d2d11400_0 .net/s "final_acc", 39 0, L_0x8d322bd40; 1 drivers -v0x8d2d114a0_0 .net/s "final_value", 39 0, L_0x8d2d22440; 1 drivers -v0x8d2d11540_0 .var "group_index", 2 0; -v0x8d2d115e0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2d11680_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2d11720_0 .net/s "w_bus", 1023 0, L_0x8d322f980; 1 drivers -v0x8d2d117c0_0 .net/s "w_group", 127 0, L_0x8d322e800; 1 drivers -v0x8d2d11860_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2d11900_0 .net/s "x_group", 127 0, L_0x8d322e760; 1 drivers -v0x8d2d119a0_0 .var/s "y", 15 0; -L_0x8d322abc0 .concat [ 3 29 0 0], v0x8d2d11540_0, L_0x8d2855960; -L_0x8d2d20d20 .arith/mult 32, L_0x8d322abc0, L_0x8d28559a8; -L_0x8d2d20dc0 .arith/mult 32, L_0x8d2d20d20, L_0x8d28559f0; -L_0x8d322e760 .part/v v0x8d2d17ca0_0, L_0x8d2d20dc0, 128; -L_0x8d322ac60 .concat [ 3 29 0 0], v0x8d2d11540_0, L_0x8d2855a38; -L_0x8d2d20e60 .arith/mult 32, L_0x8d322ac60, L_0x8d2855a80; -L_0x8d2d20f00 .arith/mult 32, L_0x8d2d20e60, L_0x8d2855ac8; -L_0x8d322e800 .part/v L_0x8d322f980, L_0x8d2d20f00, 128; -L_0x8d322f7a0 .part L_0x8d307c3f0, 15, 1; -L_0x8d2d223a0 .repeat 24, 24, L_0x8d322f7a0; -L_0x8d322bc00 .concat [ 16 24 0 0], L_0x8d307c3f0, L_0x8d2d223a0; -L_0x8d322f840 .part L_0x8d322bc00, 0, 32; -L_0x8d322bca0 .concat [ 8 32 0 0], L_0x8d2855d50, L_0x8d322f840; -L_0x8d322bd40 .arith/sum 40, L_0x8d322bb60, L_0x8d322bca0; -L_0x8d322f8e0 .part L_0x8d322bd40, 8, 32; -L_0x8d2d22440 .extend/s 40, L_0x8d322f8e0; -S_0x8d3209c80 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d3209b00; +P_0x84aea7a80 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84aea7ac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84aea7b00 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84aea7b40 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84aea7b80 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84aea7bc0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b1875c0_0 .net *"_ivl_0", 31 0, L_0x84b1a1180; 1 drivers +v0x84b187660_0 .net *"_ivl_11", 31 0, L_0x84b1a12c0; 1 drivers +v0x84b187700_0 .net *"_ivl_14", 31 0, L_0x84b1a1360; 1 drivers +L_0x84a879d08 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1877a0_0 .net *"_ivl_17", 29 0, L_0x84a879d08; 1 drivers +L_0x84a879d50 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b187840_0 .net/2u *"_ivl_18", 31 0, L_0x84a879d50; 1 drivers +v0x84b1878e0_0 .net *"_ivl_21", 31 0, L_0x84b1a1400; 1 drivers +L_0x84a879d98 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b187980_0 .net/2u *"_ivl_22", 31 0, L_0x84a879d98; 1 drivers +v0x84b187a20_0 .net *"_ivl_25", 31 0, L_0x84b1a14a0; 1 drivers +v0x84b187ac0_0 .net *"_ivl_29", 0 0, L_0x84aee8320; 1 drivers +L_0x84a879c30 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b187b60_0 .net *"_ivl_3", 29 0, L_0x84a879c30; 1 drivers +v0x84b187c00_0 .net *"_ivl_31", 23 0, L_0x84aee83c0; 1 drivers +L_0x84a879c78 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b187ca0_0 .net/2u *"_ivl_4", 31 0, L_0x84a879c78; 1 drivers +v0x84b187d40_0 .net *"_ivl_7", 31 0, L_0x84b1a1220; 1 drivers +L_0x84a879cc0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b187de0_0 .net/2u *"_ivl_8", 31 0, L_0x84a879cc0; 1 drivers +v0x84b187e80_0 .var/s "acc", 31 0; +v0x84b187f20_0 .net/s "acc_next", 31 0, L_0x84aed2f80; 1 drivers +v0x84b18c000_0 .net/s "bias", 7 0, L_0x84aee8500; 1 drivers +v0x84b18c0a0_0 .net/s "bias_ext", 31 0, L_0x84b1a29e0; 1 drivers +v0x84b18c140_0 .var "busy", 0 0; +v0x84b18c1e0_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b18c280_0 .var "done", 0 0; +v0x84b18c320_0 .net/s "final_acc", 31 0, L_0x84aed3020; 1 drivers +v0x84b18c3c0_0 .var "group_index", 1 0; +v0x84b18c460_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b18c500_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b18c5a0_0 .net/s "w_bus", 255 0, L_0x84aee8460; 1 drivers +v0x84b18c640_0 .net/s "w_group", 63 0, L_0x84aee2e40; 1 drivers +v0x84b18c6e0_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b18c780_0 .net/s "x_group", 63 0, L_0x84aee2da0; 1 drivers +v0x84b18c820_0 .var/s "y", 7 0; +L_0x84b1a1180 .concat [ 2 30 0 0], v0x84b18c3c0_0, L_0x84a879c30; +L_0x84b1a1220 .arith/mult 32, L_0x84b1a1180, L_0x84a879c78; +L_0x84b1a12c0 .arith/mult 32, L_0x84b1a1220, L_0x84a879cc0; +L_0x84aee2da0 .part/v v0x84b191e00_0, L_0x84b1a12c0, 64; +L_0x84b1a1360 .concat [ 2 30 0 0], v0x84b18c3c0_0, L_0x84a879d08; +L_0x84b1a1400 .arith/mult 32, L_0x84b1a1360, L_0x84a879d50; +L_0x84b1a14a0 .arith/mult 32, L_0x84b1a1400, L_0x84a879d98; +L_0x84aee2e40 .part/v L_0x84aee8460, L_0x84b1a14a0, 64; +L_0x84aee8320 .part L_0x84aee8500, 7, 1; +L_0x84aee83c0 .repeat 24, 24, L_0x84aee8320; +L_0x84b1a29e0 .concat [ 8 24 0 0], L_0x84aee8500, L_0x84aee83c0; +L_0x84aed3020 .arith/sum 32, L_0x84aed2f80, L_0x84b1a29e0; +S_0x84aea7c00 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84aea7900; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a0940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2d0f7a0_0 .net/s "acc_in", 39 0, v0x8d2d10f00_0; 1 drivers -v0x8d2d0f840_0 .net/s "acc_out", 39 0, L_0x8d322bb60; alias, 1 drivers -v0x8d2d0f8e0_0 .net/s "m0", 39 0, L_0x8d322ada0; 1 drivers -v0x8d2d0f980_0 .net/s "m1", 39 0, L_0x8d322aee0; 1 drivers -v0x8d2d0fa20_0 .net/s "m2", 39 0, L_0x8d322b020; 1 drivers -v0x8d2d0fac0_0 .net/s "m3", 39 0, L_0x8d322b160; 1 drivers -v0x8d2d0fb60_0 .net/s "m4", 39 0, L_0x8d322b2a0; 1 drivers -v0x8d2d0fc00_0 .net/s "m5", 39 0, L_0x8d322b3e0; 1 drivers -v0x8d2d0fca0_0 .net/s "m6", 39 0, L_0x8d322b520; 1 drivers -v0x8d2d0fd40_0 .net/s "m7", 39 0, L_0x8d322b660; 1 drivers -v0x8d2d0fde0_0 .net/s "s0", 39 0, L_0x8d322b700; 1 drivers -v0x8d2d0fe80_0 .net/s "s1", 39 0, L_0x8d322b7a0; 1 drivers -v0x8d2d0ff20_0 .net/s "s2", 39 0, L_0x8d322b840; 1 drivers -v0x8d2d10000_0 .net/s "s3", 39 0, L_0x8d322b8e0; 1 drivers -v0x8d2d100a0_0 .net/s "s4", 39 0, L_0x8d322b980; 1 drivers -v0x8d2d10140_0 .net/s "s5", 39 0, L_0x8d322ba20; 1 drivers -v0x8d2d101e0_0 .net/s "sum", 39 0, L_0x8d322bac0; 1 drivers -v0x8d2d10280_0 .net/s "w_bus", 127 0, L_0x8d322e800; alias, 1 drivers -v0x8d2d10320_0 .net/s "x_bus", 127 0, L_0x8d322e760; alias, 1 drivers -L_0x8d322e940 .part L_0x8d322e760, 0, 16; -L_0x8d322e9e0 .part L_0x8d322e800, 0, 16; -L_0x8d322eb20 .part L_0x8d322e760, 16, 16; -L_0x8d322ebc0 .part L_0x8d322e800, 16, 16; -L_0x8d322ed00 .part L_0x8d322e760, 32, 16; -L_0x8d322eda0 .part L_0x8d322e800, 32, 16; -L_0x8d322eee0 .part L_0x8d322e760, 48, 16; -L_0x8d322ef80 .part L_0x8d322e800, 48, 16; -L_0x8d322f0c0 .part L_0x8d322e760, 64, 16; -L_0x8d322f160 .part L_0x8d322e800, 64, 16; -L_0x8d322f2a0 .part L_0x8d322e760, 80, 16; -L_0x8d322f340 .part L_0x8d322e800, 80, 16; -L_0x8d322f480 .part L_0x8d322e760, 96, 16; -L_0x8d322f520 .part L_0x8d322e800, 96, 16; -L_0x8d322f660 .part L_0x8d322e760, 112, 16; -L_0x8d322f700 .part L_0x8d322e800, 112, 16; -L_0x8d322b700 .arith/sum 40, L_0x8d322ada0, L_0x8d322aee0; -L_0x8d322b7a0 .arith/sum 40, L_0x8d322b020, L_0x8d322b160; -L_0x8d322b840 .arith/sum 40, L_0x8d322b2a0, L_0x8d322b3e0; -L_0x8d322b8e0 .arith/sum 40, L_0x8d322b520, L_0x8d322b660; -L_0x8d322b980 .arith/sum 40, L_0x8d322b700, L_0x8d322b7a0; -L_0x8d322ba20 .arith/sum 40, L_0x8d322b840, L_0x8d322b8e0; -L_0x8d322bac0 .arith/sum 40, L_0x8d322b980, L_0x8d322ba20; -L_0x8d322bb60 .arith/sum 40, v0x8d2d10f00_0, L_0x8d322bac0; -S_0x8d3209e00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d3209c80; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8900 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8940 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8980 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc89c0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b187200_0 .net/s "acc_in", 31 0, v0x84b187e80_0; 1 drivers +v0x84b1872a0_0 .net/s "acc_out", 31 0, L_0x84aed2f80; alias, 1 drivers +v0x84b187340 .array "products", 7 0; +v0x84b187340_0 .net/s v0x84b187340 0, 31 0, L_0x84aed2620; 1 drivers +v0x84b187340_1 .net/s v0x84b187340 1, 31 0, L_0x84aed26c0; 1 drivers +v0x84b187340_2 .net/s v0x84b187340 2, 31 0, L_0x84aed2760; 1 drivers +v0x84b187340_3 .net/s v0x84b187340 3, 31 0, L_0x84aed2800; 1 drivers +v0x84b187340_4 .net/s v0x84b187340 4, 31 0, L_0x84aed28a0; 1 drivers +v0x84b187340_5 .net/s v0x84b187340 5, 31 0, L_0x84aed2940; 1 drivers +v0x84b187340_6 .net/s v0x84b187340 6, 31 0, L_0x84aed29e0; 1 drivers +v0x84b187340_7 .net/s v0x84b187340 7, 31 0, L_0x84aed2a80; 1 drivers +v0x84b1873e0 .array "tree", 31 0; +v0x84b1873e0_0 .net/s v0x84b1873e0 0, 31 0, L_0x84aedc850; 1 drivers +v0x84b1873e0_1 .net/s v0x84b1873e0 1, 31 0, L_0x84aedc8c0; 1 drivers +v0x84b1873e0_2 .net/s v0x84b1873e0 2, 31 0, L_0x84aedc930; 1 drivers +v0x84b1873e0_3 .net/s v0x84b1873e0 3, 31 0, L_0x84aedc9a0; 1 drivers +v0x84b1873e0_4 .net/s v0x84b1873e0 4, 31 0, L_0x84aedca10; 1 drivers +v0x84b1873e0_5 .net/s v0x84b1873e0 5, 31 0, L_0x84aedca80; 1 drivers +v0x84b1873e0_6 .net/s v0x84b1873e0 6, 31 0, L_0x84aedcaf0; 1 drivers +v0x84b1873e0_7 .net/s v0x84b1873e0 7, 31 0, L_0x84aedcb60; 1 drivers +v0x84b1873e0_8 .net/s v0x84b1873e0 8, 31 0, L_0x84aed2b20; 1 drivers +v0x84b1873e0_9 .net/s v0x84b1873e0 9, 31 0, L_0x84aed2bc0; 1 drivers +v0x84b1873e0_10 .net/s v0x84b1873e0 10, 31 0, L_0x84aed2c60; 1 drivers +v0x84b1873e0_11 .net/s v0x84b1873e0 11, 31 0, L_0x84aed2d00; 1 drivers +o0x84a858170 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_12 .net/s v0x84b1873e0 12, 31 0, o0x84a858170; 0 drivers +o0x84a8581a0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_13 .net/s v0x84b1873e0 13, 31 0, o0x84a8581a0; 0 drivers +o0x84a8581d0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_14 .net/s v0x84b1873e0 14, 31 0, o0x84a8581d0; 0 drivers +o0x84a858200 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_15 .net/s v0x84b1873e0 15, 31 0, o0x84a858200; 0 drivers +v0x84b1873e0_16 .net/s v0x84b1873e0 16, 31 0, L_0x84aed2da0; 1 drivers +v0x84b1873e0_17 .net/s v0x84b1873e0 17, 31 0, L_0x84aed2e40; 1 drivers +o0x84a858290 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_18 .net/s v0x84b1873e0 18, 31 0, o0x84a858290; 0 drivers +o0x84a8582c0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_19 .net/s v0x84b1873e0 19, 31 0, o0x84a8582c0; 0 drivers +o0x84a8582f0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_20 .net/s v0x84b1873e0 20, 31 0, o0x84a8582f0; 0 drivers +o0x84a858320 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_21 .net/s v0x84b1873e0 21, 31 0, o0x84a858320; 0 drivers +o0x84a858350 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_22 .net/s v0x84b1873e0 22, 31 0, o0x84a858350; 0 drivers +o0x84a858380 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_23 .net/s v0x84b1873e0 23, 31 0, o0x84a858380; 0 drivers +v0x84b1873e0_24 .net/s v0x84b1873e0 24, 31 0, L_0x84aed2ee0; 1 drivers +o0x84a8583e0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_25 .net/s v0x84b1873e0 25, 31 0, o0x84a8583e0; 0 drivers +o0x84a858410 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_26 .net/s v0x84b1873e0 26, 31 0, o0x84a858410; 0 drivers +o0x84a858440 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_27 .net/s v0x84b1873e0 27, 31 0, o0x84a858440; 0 drivers +o0x84a858470 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_28 .net/s v0x84b1873e0 28, 31 0, o0x84a858470; 0 drivers +o0x84a8584a0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_29 .net/s v0x84b1873e0 29, 31 0, o0x84a8584a0; 0 drivers +o0x84a8584d0 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_30 .net/s v0x84b1873e0 30, 31 0, o0x84a8584d0; 0 drivers +o0x84a858500 .functor BUFZ 32, c4; HiZ drive +v0x84b1873e0_31 .net/s v0x84b1873e0 31, 31 0, o0x84a858500; 0 drivers +v0x84b187480_0 .net/s "w_bus", 63 0, L_0x84aee2e40; alias, 1 drivers +v0x84b187520_0 .net/s "x_bus", 63 0, L_0x84aee2da0; alias, 1 drivers +L_0x84aee3020 .part L_0x84aee2da0, 0, 8; +L_0x84aee30c0 .part L_0x84aee2e40, 0, 8; +L_0x84aee32a0 .part L_0x84aee2da0, 8, 8; +L_0x84aee3340 .part L_0x84aee2e40, 8, 8; +L_0x84aee3520 .part L_0x84aee2da0, 16, 8; +L_0x84aee35c0 .part L_0x84aee2e40, 16, 8; +L_0x84aee37a0 .part L_0x84aee2da0, 24, 8; +L_0x84aee3840 .part L_0x84aee2e40, 24, 8; +L_0x84aee3a20 .part L_0x84aee2da0, 32, 8; +L_0x84aee3ac0 .part L_0x84aee2e40, 32, 8; +L_0x84aee3ca0 .part L_0x84aee2da0, 40, 8; +L_0x84aee3d40 .part L_0x84aee2e40, 40, 8; +L_0x84aee3f20 .part L_0x84aee2da0, 48, 8; +L_0x84aee8000 .part L_0x84aee2e40, 48, 8; +L_0x84aee81e0 .part L_0x84aee2da0, 56, 8; +L_0x84aee8280 .part L_0x84aee2e40, 56, 8; +L_0x84aed2f80 .arith/sum 32, v0x84b187e80_0, L_0x84aed2ee0; +S_0x84aea7d80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84aea7c00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e4c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e500 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e540 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0c5a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20fa0; 1 drivers -v0x8d2d0c640_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21040; 1 drivers -v0x8d2d0c6e0_0 .net *"_ivl_7", 0 0, L_0x8d322e8a0; 1 drivers -v0x8d2d0c780_0 .net *"_ivl_9", 7 0, L_0x8d2d21180; 1 drivers -L_0x8d2855b10 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0c820_0 .net/s "acc_in", 39 0, L_0x8d2855b10; 1 drivers -v0x8d2d0c8c0_0 .net/s "acc_out", 39 0, L_0x8d322ada0; alias, 1 drivers -v0x8d2d0c960_0 .net/s "product", 31 0, L_0x8d2d210e0; 1 drivers -v0x8d2d0ca00_0 .net/s "product_ext", 39 0, L_0x8d322ad00; 1 drivers -v0x8d2d0caa0_0 .net/s "w", 15 0, L_0x8d322e9e0; 1 drivers -v0x8d2d0cb40_0 .net/s "x", 15 0, L_0x8d322e940; 1 drivers -L_0x8d2d20fa0 .extend/s 32, L_0x8d322e940; -L_0x8d2d21040 .extend/s 32, L_0x8d322e9e0; -L_0x8d2d210e0 .arith/mult 32, L_0x8d2d20fa0, L_0x8d2d21040; -L_0x8d322e8a0 .part L_0x8d2d210e0, 31, 1; -L_0x8d2d21180 .repeat 8, 8, L_0x8d322e8a0; -L_0x8d322ad00 .concat [ 32 8 0 0], L_0x8d2d210e0, L_0x8d2d21180; -L_0x8d322ada0 .arith/sum 40, L_0x8d2855b10, L_0x8d322ad00; -S_0x8d3209f80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d3209c80; +P_0x84b153a80 .param/l "i" 1 8 20, +C4<00>; +S_0x84aeb0000 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aea7d80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e580 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e5c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e600 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0cbe0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21220; 1 drivers -v0x8d2d0cc80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d212c0; 1 drivers -v0x8d2d0cd20_0 .net *"_ivl_7", 0 0, L_0x8d322ea80; 1 drivers -v0x8d2d0cdc0_0 .net *"_ivl_9", 7 0, L_0x8d2d21400; 1 drivers -L_0x8d2855b58 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0ce60_0 .net/s "acc_in", 39 0, L_0x8d2855b58; 1 drivers -v0x8d2d0cf00_0 .net/s "acc_out", 39 0, L_0x8d322aee0; alias, 1 drivers -v0x8d2d0cfa0_0 .net/s "product", 31 0, L_0x8d2d21360; 1 drivers -v0x8d2d0d040_0 .net/s "product_ext", 39 0, L_0x8d322ae40; 1 drivers -v0x8d2d0d0e0_0 .net/s "w", 15 0, L_0x8d322ebc0; 1 drivers -v0x8d2d0d180_0 .net/s "x", 15 0, L_0x8d322eb20; 1 drivers -L_0x8d2d21220 .extend/s 32, L_0x8d322eb20; -L_0x8d2d212c0 .extend/s 32, L_0x8d322ebc0; -L_0x8d2d21360 .arith/mult 32, L_0x8d2d21220, L_0x8d2d212c0; -L_0x8d322ea80 .part L_0x8d2d21360, 31, 1; -L_0x8d2d21400 .repeat 8, 8, L_0x8d322ea80; -L_0x8d322ae40 .concat [ 32 8 0 0], L_0x8d2d21360, L_0x8d2d21400; -L_0x8d322aee0 .arith/sum 40, L_0x8d2855b58, L_0x8d322ae40; -S_0x8d320a100 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d3209c80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a7c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a800 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a840 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b184000_0 .net/s *"_ivl_0", 15 0, L_0x84b1a1540; 1 drivers +v0x84b1840a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a15e0; 1 drivers +v0x84b184140_0 .net *"_ivl_7", 0 0, L_0x84aee2ee0; 1 drivers +v0x84b1841e0_0 .net *"_ivl_9", 15 0, L_0x84aee2f80; 1 drivers +L_0x84a879de0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b184280_0 .net/s "acc_in", 31 0, L_0x84a879de0; 1 drivers +v0x84b184320_0 .net/s "acc_out", 31 0, L_0x84aed2620; alias, 1 drivers +v0x84b1843c0_0 .net/s "product", 15 0, L_0x84b1a1680; 1 drivers +v0x84b184460_0 .net/s "product_ext", 31 0, L_0x84b1a1720; 1 drivers +v0x84b184500_0 .net/s "w", 7 0, L_0x84aee30c0; 1 drivers +v0x84b1845a0_0 .net/s "x", 7 0, L_0x84aee3020; 1 drivers +L_0x84b1a1540 .extend/s 16, L_0x84aee3020; +L_0x84b1a15e0 .extend/s 16, L_0x84aee30c0; +L_0x84b1a1680 .arith/mult 16, L_0x84b1a1540, L_0x84b1a15e0; +L_0x84aee2ee0 .part L_0x84b1a1680, 15, 1; +L_0x84aee2f80 .repeat 16, 16, L_0x84aee2ee0; +L_0x84b1a1720 .concat [ 16 16 0 0], L_0x84b1a1680, L_0x84aee2f80; +L_0x84aed2620 .arith/sum 32, L_0x84a879de0, L_0x84b1a1720; +S_0x84aeb0180 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84aea7c00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e640 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e680 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e6c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0d220_0 .net/s *"_ivl_0", 31 0, L_0x8d2d214a0; 1 drivers -v0x8d2d0d2c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21540; 1 drivers -v0x8d2d0d360_0 .net *"_ivl_7", 0 0, L_0x8d322ec60; 1 drivers -v0x8d2d0d400_0 .net *"_ivl_9", 7 0, L_0x8d2d21680; 1 drivers -L_0x8d2855ba0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0d4a0_0 .net/s "acc_in", 39 0, L_0x8d2855ba0; 1 drivers -v0x8d2d0d540_0 .net/s "acc_out", 39 0, L_0x8d322b020; alias, 1 drivers -v0x8d2d0d5e0_0 .net/s "product", 31 0, L_0x8d2d215e0; 1 drivers -v0x8d2d0d680_0 .net/s "product_ext", 39 0, L_0x8d322af80; 1 drivers -v0x8d2d0d720_0 .net/s "w", 15 0, L_0x8d322eda0; 1 drivers -v0x8d2d0d7c0_0 .net/s "x", 15 0, L_0x8d322ed00; 1 drivers -L_0x8d2d214a0 .extend/s 32, L_0x8d322ed00; -L_0x8d2d21540 .extend/s 32, L_0x8d322eda0; -L_0x8d2d215e0 .arith/mult 32, L_0x8d2d214a0, L_0x8d2d21540; -L_0x8d322ec60 .part L_0x8d2d215e0, 31, 1; -L_0x8d2d21680 .repeat 8, 8, L_0x8d322ec60; -L_0x8d322af80 .concat [ 32 8 0 0], L_0x8d2d215e0, L_0x8d2d21680; -L_0x8d322b020 .arith/sum 40, L_0x8d2855ba0, L_0x8d322af80; -S_0x8d320a280 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d3209c80; +P_0x84b153ac0 .param/l "i" 1 8 20, +C4<01>; +S_0x84aeb0300 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb0180; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e700 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e740 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e780 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0d860_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21720; 1 drivers -v0x8d2d0d900_0 .net/s *"_ivl_2", 31 0, L_0x8d2d217c0; 1 drivers -v0x8d2d0d9a0_0 .net *"_ivl_7", 0 0, L_0x8d322ee40; 1 drivers -v0x8d2d0da40_0 .net *"_ivl_9", 7 0, L_0x8d2d21900; 1 drivers -L_0x8d2855be8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0dae0_0 .net/s "acc_in", 39 0, L_0x8d2855be8; 1 drivers -v0x8d2d0db80_0 .net/s "acc_out", 39 0, L_0x8d322b160; alias, 1 drivers -v0x8d2d0dc20_0 .net/s "product", 31 0, L_0x8d2d21860; 1 drivers -v0x8d2d0dcc0_0 .net/s "product_ext", 39 0, L_0x8d322b0c0; 1 drivers -v0x8d2d0dd60_0 .net/s "w", 15 0, L_0x8d322ef80; 1 drivers -v0x8d2d0de00_0 .net/s "x", 15 0, L_0x8d322eee0; 1 drivers -L_0x8d2d21720 .extend/s 32, L_0x8d322eee0; -L_0x8d2d217c0 .extend/s 32, L_0x8d322ef80; -L_0x8d2d21860 .arith/mult 32, L_0x8d2d21720, L_0x8d2d217c0; -L_0x8d322ee40 .part L_0x8d2d21860, 31, 1; -L_0x8d2d21900 .repeat 8, 8, L_0x8d322ee40; -L_0x8d322b0c0 .concat [ 32 8 0 0], L_0x8d2d21860, L_0x8d2d21900; -L_0x8d322b160 .arith/sum 40, L_0x8d2855be8, L_0x8d322b0c0; -S_0x8d320a400 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d3209c80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a880 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a8c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a900 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b184640_0 .net/s *"_ivl_0", 15 0, L_0x84b1a17c0; 1 drivers +v0x84b1846e0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a1860; 1 drivers +v0x84b184780_0 .net *"_ivl_7", 0 0, L_0x84aee3160; 1 drivers +v0x84b184820_0 .net *"_ivl_9", 15 0, L_0x84aee3200; 1 drivers +L_0x84a879e28 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1848c0_0 .net/s "acc_in", 31 0, L_0x84a879e28; 1 drivers +v0x84b184960_0 .net/s "acc_out", 31 0, L_0x84aed26c0; alias, 1 drivers +v0x84b184a00_0 .net/s "product", 15 0, L_0x84b1a1900; 1 drivers +v0x84b184aa0_0 .net/s "product_ext", 31 0, L_0x84b1a19a0; 1 drivers +v0x84b184b40_0 .net/s "w", 7 0, L_0x84aee3340; 1 drivers +v0x84b184be0_0 .net/s "x", 7 0, L_0x84aee32a0; 1 drivers +L_0x84b1a17c0 .extend/s 16, L_0x84aee32a0; +L_0x84b1a1860 .extend/s 16, L_0x84aee3340; +L_0x84b1a1900 .arith/mult 16, L_0x84b1a17c0, L_0x84b1a1860; +L_0x84aee3160 .part L_0x84b1a1900, 15, 1; +L_0x84aee3200 .repeat 16, 16, L_0x84aee3160; +L_0x84b1a19a0 .concat [ 16 16 0 0], L_0x84b1a1900, L_0x84aee3200; +L_0x84aed26c0 .arith/sum 32, L_0x84a879e28, L_0x84b1a19a0; +S_0x84aeb0480 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84aea7c00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e7c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e800 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e840 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0dea0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d219a0; 1 drivers -v0x8d2d0df40_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21a40; 1 drivers -v0x8d2d0dfe0_0 .net *"_ivl_7", 0 0, L_0x8d322f020; 1 drivers -v0x8d2d0e080_0 .net *"_ivl_9", 7 0, L_0x8d2d21b80; 1 drivers -L_0x8d2855c30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0e120_0 .net/s "acc_in", 39 0, L_0x8d2855c30; 1 drivers -v0x8d2d0e1c0_0 .net/s "acc_out", 39 0, L_0x8d322b2a0; alias, 1 drivers -v0x8d2d0e260_0 .net/s "product", 31 0, L_0x8d2d21ae0; 1 drivers -v0x8d2d0e300_0 .net/s "product_ext", 39 0, L_0x8d322b200; 1 drivers -v0x8d2d0e3a0_0 .net/s "w", 15 0, L_0x8d322f160; 1 drivers -v0x8d2d0e440_0 .net/s "x", 15 0, L_0x8d322f0c0; 1 drivers -L_0x8d2d219a0 .extend/s 32, L_0x8d322f0c0; -L_0x8d2d21a40 .extend/s 32, L_0x8d322f160; -L_0x8d2d21ae0 .arith/mult 32, L_0x8d2d219a0, L_0x8d2d21a40; -L_0x8d322f020 .part L_0x8d2d21ae0, 31, 1; -L_0x8d2d21b80 .repeat 8, 8, L_0x8d322f020; -L_0x8d322b200 .concat [ 32 8 0 0], L_0x8d2d21ae0, L_0x8d2d21b80; -L_0x8d322b2a0 .arith/sum 40, L_0x8d2855c30, L_0x8d322b200; -S_0x8d320a580 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d3209c80; +P_0x84b153b00 .param/l "i" 1 8 20, +C4<010>; +S_0x84aeb0600 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb0480; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e880 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e8c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e900 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0e4e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21c20; 1 drivers -v0x8d2d0e580_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21cc0; 1 drivers -v0x8d2d0e620_0 .net *"_ivl_7", 0 0, L_0x8d322f200; 1 drivers -v0x8d2d0e6c0_0 .net *"_ivl_9", 7 0, L_0x8d2d21e00; 1 drivers -L_0x8d2855c78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0e760_0 .net/s "acc_in", 39 0, L_0x8d2855c78; 1 drivers -v0x8d2d0e800_0 .net/s "acc_out", 39 0, L_0x8d322b3e0; alias, 1 drivers -v0x8d2d0e8a0_0 .net/s "product", 31 0, L_0x8d2d21d60; 1 drivers -v0x8d2d0e940_0 .net/s "product_ext", 39 0, L_0x8d322b340; 1 drivers -v0x8d2d0e9e0_0 .net/s "w", 15 0, L_0x8d322f340; 1 drivers -v0x8d2d0ea80_0 .net/s "x", 15 0, L_0x8d322f2a0; 1 drivers -L_0x8d2d21c20 .extend/s 32, L_0x8d322f2a0; -L_0x8d2d21cc0 .extend/s 32, L_0x8d322f340; -L_0x8d2d21d60 .arith/mult 32, L_0x8d2d21c20, L_0x8d2d21cc0; -L_0x8d322f200 .part L_0x8d2d21d60, 31, 1; -L_0x8d2d21e00 .repeat 8, 8, L_0x8d322f200; -L_0x8d322b340 .concat [ 32 8 0 0], L_0x8d2d21d60, L_0x8d2d21e00; -L_0x8d322b3e0 .arith/sum 40, L_0x8d2855c78, L_0x8d322b340; -S_0x8d320a700 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d3209c80; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15a940 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15a980 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15a9c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b184c80_0 .net/s *"_ivl_0", 15 0, L_0x84b1a1a40; 1 drivers +v0x84b184d20_0 .net/s *"_ivl_2", 15 0, L_0x84b1a1ae0; 1 drivers +v0x84b184dc0_0 .net *"_ivl_7", 0 0, L_0x84aee33e0; 1 drivers +v0x84b184e60_0 .net *"_ivl_9", 15 0, L_0x84aee3480; 1 drivers +L_0x84a879e70 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b184f00_0 .net/s "acc_in", 31 0, L_0x84a879e70; 1 drivers +v0x84b184fa0_0 .net/s "acc_out", 31 0, L_0x84aed2760; alias, 1 drivers +v0x84b185040_0 .net/s "product", 15 0, L_0x84b1a1b80; 1 drivers +v0x84b1850e0_0 .net/s "product_ext", 31 0, L_0x84b1a1c20; 1 drivers +v0x84b185180_0 .net/s "w", 7 0, L_0x84aee35c0; 1 drivers +v0x84b185220_0 .net/s "x", 7 0, L_0x84aee3520; 1 drivers +L_0x84b1a1a40 .extend/s 16, L_0x84aee3520; +L_0x84b1a1ae0 .extend/s 16, L_0x84aee35c0; +L_0x84b1a1b80 .arith/mult 16, L_0x84b1a1a40, L_0x84b1a1ae0; +L_0x84aee33e0 .part L_0x84b1a1b80, 15, 1; +L_0x84aee3480 .repeat 16, 16, L_0x84aee33e0; +L_0x84b1a1c20 .concat [ 16 16 0 0], L_0x84b1a1b80, L_0x84aee3480; +L_0x84aed2760 .arith/sum 32, L_0x84a879e70, L_0x84b1a1c20; +S_0x84aeb0780 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84aea7c00; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306e940 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306e980 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306e9c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0eb20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21ea0; 1 drivers -v0x8d2d0ebc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21f40; 1 drivers -v0x8d2d0ec60_0 .net *"_ivl_7", 0 0, L_0x8d322f3e0; 1 drivers -v0x8d2d0ed00_0 .net *"_ivl_9", 7 0, L_0x8d2d22080; 1 drivers -L_0x8d2855cc0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0eda0_0 .net/s "acc_in", 39 0, L_0x8d2855cc0; 1 drivers -v0x8d2d0ee40_0 .net/s "acc_out", 39 0, L_0x8d322b520; alias, 1 drivers -v0x8d2d0eee0_0 .net/s "product", 31 0, L_0x8d2d21fe0; 1 drivers -v0x8d2d0ef80_0 .net/s "product_ext", 39 0, L_0x8d322b480; 1 drivers -v0x8d2d0f020_0 .net/s "w", 15 0, L_0x8d322f520; 1 drivers -v0x8d2d0f0c0_0 .net/s "x", 15 0, L_0x8d322f480; 1 drivers -L_0x8d2d21ea0 .extend/s 32, L_0x8d322f480; -L_0x8d2d21f40 .extend/s 32, L_0x8d322f520; -L_0x8d2d21fe0 .arith/mult 32, L_0x8d2d21ea0, L_0x8d2d21f40; -L_0x8d322f3e0 .part L_0x8d2d21fe0, 31, 1; -L_0x8d2d22080 .repeat 8, 8, L_0x8d322f3e0; -L_0x8d322b480 .concat [ 32 8 0 0], L_0x8d2d21fe0, L_0x8d2d22080; -L_0x8d322b520 .arith/sum 40, L_0x8d2855cc0, L_0x8d322b480; -S_0x8d320a880 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d3209c80; +P_0x84b153b40 .param/l "i" 1 8 20, +C4<011>; +S_0x84aeb0900 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb0780; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ea00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ea40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ea80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d0f160_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22120; 1 drivers -v0x8d2d0f200_0 .net/s *"_ivl_2", 31 0, L_0x8d2d221c0; 1 drivers -v0x8d2d0f2a0_0 .net *"_ivl_7", 0 0, L_0x8d322f5c0; 1 drivers -v0x8d2d0f340_0 .net *"_ivl_9", 7 0, L_0x8d2d22300; 1 drivers -L_0x8d2855d08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d0f3e0_0 .net/s "acc_in", 39 0, L_0x8d2855d08; 1 drivers -v0x8d2d0f480_0 .net/s "acc_out", 39 0, L_0x8d322b660; alias, 1 drivers -v0x8d2d0f520_0 .net/s "product", 31 0, L_0x8d2d22260; 1 drivers -v0x8d2d0f5c0_0 .net/s "product_ext", 39 0, L_0x8d322b5c0; 1 drivers -v0x8d2d0f660_0 .net/s "w", 15 0, L_0x8d322f700; 1 drivers -v0x8d2d0f700_0 .net/s "x", 15 0, L_0x8d322f660; 1 drivers -L_0x8d2d22120 .extend/s 32, L_0x8d322f660; -L_0x8d2d221c0 .extend/s 32, L_0x8d322f700; -L_0x8d2d22260 .arith/mult 32, L_0x8d2d22120, L_0x8d2d221c0; -L_0x8d322f5c0 .part L_0x8d2d22260, 31, 1; -L_0x8d2d22300 .repeat 8, 8, L_0x8d322f5c0; -L_0x8d322b5c0 .concat [ 32 8 0 0], L_0x8d2d22260, L_0x8d2d22300; -L_0x8d322b660 .arith/sum 40, L_0x8d2855d08, L_0x8d322b5c0; -S_0x8d320aa00 .scope generate, "GEN_NEURON[7]" "GEN_NEURON[7]" 4 35, 4 35 0, S_0x102e5b4b0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15aa00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15aa40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15aa80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b1852c0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a1cc0; 1 drivers +v0x84b185360_0 .net/s *"_ivl_2", 15 0, L_0x84b1a1d60; 1 drivers +v0x84b185400_0 .net *"_ivl_7", 0 0, L_0x84aee3660; 1 drivers +v0x84b1854a0_0 .net *"_ivl_9", 15 0, L_0x84aee3700; 1 drivers +L_0x84a879eb8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b185540_0 .net/s "acc_in", 31 0, L_0x84a879eb8; 1 drivers +v0x84b1855e0_0 .net/s "acc_out", 31 0, L_0x84aed2800; alias, 1 drivers +v0x84b185680_0 .net/s "product", 15 0, L_0x84b1a1e00; 1 drivers +v0x84b185720_0 .net/s "product_ext", 31 0, L_0x84b1a1ea0; 1 drivers +v0x84b1857c0_0 .net/s "w", 7 0, L_0x84aee3840; 1 drivers +v0x84b185860_0 .net/s "x", 7 0, L_0x84aee37a0; 1 drivers +L_0x84b1a1cc0 .extend/s 16, L_0x84aee37a0; +L_0x84b1a1d60 .extend/s 16, L_0x84aee3840; +L_0x84b1a1e00 .arith/mult 16, L_0x84b1a1cc0, L_0x84b1a1d60; +L_0x84aee3660 .part L_0x84b1a1e00, 15, 1; +L_0x84aee3700 .repeat 16, 16, L_0x84aee3660; +L_0x84b1a1ea0 .concat [ 16 16 0 0], L_0x84b1a1e00, L_0x84aee3700; +L_0x84aed2800 .arith/sum 32, L_0x84a879eb8, L_0x84b1a1ea0; +S_0x84aeb0a80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84aea7c00; .timescale 0 0; -P_0x8d2c3b280 .param/l "n" 1 4 35, +C4<0111>; -S_0x8d320ab80 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d320aa00; +P_0x84b153b80 .param/l "i" 1 8 20, +C4<0100>; +S_0x84aeb0c00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb0a80; .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15aac0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15ab00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15ab40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b185900_0 .net/s *"_ivl_0", 15 0, L_0x84b1a1f40; 1 drivers +v0x84b1859a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a1fe0; 1 drivers +v0x84b185a40_0 .net *"_ivl_7", 0 0, L_0x84aee38e0; 1 drivers +v0x84b185ae0_0 .net *"_ivl_9", 15 0, L_0x84aee3980; 1 drivers +L_0x84a879f00 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b185b80_0 .net/s "acc_in", 31 0, L_0x84a879f00; 1 drivers +v0x84b185c20_0 .net/s "acc_out", 31 0, L_0x84aed28a0; alias, 1 drivers +v0x84b185cc0_0 .net/s "product", 15 0, L_0x84b1a2080; 1 drivers +v0x84b185d60_0 .net/s "product_ext", 31 0, L_0x84b1a2120; 1 drivers +v0x84b185e00_0 .net/s "w", 7 0, L_0x84aee3ac0; 1 drivers +v0x84b185ea0_0 .net/s "x", 7 0, L_0x84aee3a20; 1 drivers +L_0x84b1a1f40 .extend/s 16, L_0x84aee3a20; +L_0x84b1a1fe0 .extend/s 16, L_0x84aee3ac0; +L_0x84b1a2080 .arith/mult 16, L_0x84b1a1f40, L_0x84b1a1fe0; +L_0x84aee38e0 .part L_0x84b1a2080, 15, 1; +L_0x84aee3980 .repeat 16, 16, L_0x84aee38e0; +L_0x84b1a2120 .concat [ 16 16 0 0], L_0x84b1a2080, L_0x84aee3980; +L_0x84aed28a0 .arith/sum 32, L_0x84a879f00, L_0x84b1a2120; +S_0x84aeb0d80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153bc0 .param/l "i" 1 8 20, +C4<0101>; +S_0x84aeb0f00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb0d80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15ab80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15abc0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15ac00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b185f40_0 .net/s *"_ivl_0", 15 0, L_0x84b1a21c0; 1 drivers +v0x84b185fe0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a2260; 1 drivers +v0x84b186080_0 .net *"_ivl_7", 0 0, L_0x84aee3b60; 1 drivers +v0x84b186120_0 .net *"_ivl_9", 15 0, L_0x84aee3c00; 1 drivers +L_0x84a879f48 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1861c0_0 .net/s "acc_in", 31 0, L_0x84a879f48; 1 drivers +v0x84b186260_0 .net/s "acc_out", 31 0, L_0x84aed2940; alias, 1 drivers +v0x84b186300_0 .net/s "product", 15 0, L_0x84b1a2300; 1 drivers +v0x84b1863a0_0 .net/s "product_ext", 31 0, L_0x84b1a23a0; 1 drivers +v0x84b186440_0 .net/s "w", 7 0, L_0x84aee3d40; 1 drivers +v0x84b1864e0_0 .net/s "x", 7 0, L_0x84aee3ca0; 1 drivers +L_0x84b1a21c0 .extend/s 16, L_0x84aee3ca0; +L_0x84b1a2260 .extend/s 16, L_0x84aee3d40; +L_0x84b1a2300 .arith/mult 16, L_0x84b1a21c0, L_0x84b1a2260; +L_0x84aee3b60 .part L_0x84b1a2300, 15, 1; +L_0x84aee3c00 .repeat 16, 16, L_0x84aee3b60; +L_0x84b1a23a0 .concat [ 16 16 0 0], L_0x84b1a2300, L_0x84aee3c00; +L_0x84aed2940 .arith/sum 32, L_0x84a879f48, L_0x84b1a23a0; +S_0x84aeb1080 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153c00 .param/l "i" 1 8 20, +C4<0110>; +S_0x84aeb1200 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb1080; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15ac40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15ac80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15acc0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b186580_0 .net/s *"_ivl_0", 15 0, L_0x84b1a2440; 1 drivers +v0x84b186620_0 .net/s *"_ivl_2", 15 0, L_0x84b1a24e0; 1 drivers +v0x84b1866c0_0 .net *"_ivl_7", 0 0, L_0x84aee3de0; 1 drivers +v0x84b186760_0 .net *"_ivl_9", 15 0, L_0x84aee3e80; 1 drivers +L_0x84a879f90 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b186800_0 .net/s "acc_in", 31 0, L_0x84a879f90; 1 drivers +v0x84b1868a0_0 .net/s "acc_out", 31 0, L_0x84aed29e0; alias, 1 drivers +v0x84b186940_0 .net/s "product", 15 0, L_0x84b1a2580; 1 drivers +v0x84b1869e0_0 .net/s "product_ext", 31 0, L_0x84b1a2620; 1 drivers +v0x84b186a80_0 .net/s "w", 7 0, L_0x84aee8000; 1 drivers +v0x84b186b20_0 .net/s "x", 7 0, L_0x84aee3f20; 1 drivers +L_0x84b1a2440 .extend/s 16, L_0x84aee3f20; +L_0x84b1a24e0 .extend/s 16, L_0x84aee8000; +L_0x84b1a2580 .arith/mult 16, L_0x84b1a2440, L_0x84b1a24e0; +L_0x84aee3de0 .part L_0x84b1a2580, 15, 1; +L_0x84aee3e80 .repeat 16, 16, L_0x84aee3de0; +L_0x84b1a2620 .concat [ 16 16 0 0], L_0x84b1a2580, L_0x84aee3e80; +L_0x84aed29e0 .arith/sum 32, L_0x84a879f90, L_0x84b1a2620; +S_0x84aeb1380 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153c40 .param/l "i" 1 8 20, +C4<0111>; +S_0x84aeb1500 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb1380; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15ad00 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15ad40 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15ad80 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b186bc0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a26c0; 1 drivers +v0x84b186c60_0 .net/s *"_ivl_2", 15 0, L_0x84b1a2760; 1 drivers +v0x84b186d00_0 .net *"_ivl_7", 0 0, L_0x84aee80a0; 1 drivers +v0x84b186da0_0 .net *"_ivl_9", 15 0, L_0x84aee8140; 1 drivers +L_0x84a879fd8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b186e40_0 .net/s "acc_in", 31 0, L_0x84a879fd8; 1 drivers +v0x84b186ee0_0 .net/s "acc_out", 31 0, L_0x84aed2a80; alias, 1 drivers +v0x84b186f80_0 .net/s "product", 15 0, L_0x84b1a2800; 1 drivers +v0x84b187020_0 .net/s "product_ext", 31 0, L_0x84b1a28a0; 1 drivers +v0x84b1870c0_0 .net/s "w", 7 0, L_0x84aee8280; 1 drivers +v0x84b187160_0 .net/s "x", 7 0, L_0x84aee81e0; 1 drivers +L_0x84b1a26c0 .extend/s 16, L_0x84aee81e0; +L_0x84b1a2760 .extend/s 16, L_0x84aee8280; +L_0x84b1a2800 .arith/mult 16, L_0x84b1a26c0, L_0x84b1a2760; +L_0x84aee80a0 .part L_0x84b1a2800, 15, 1; +L_0x84aee8140 .repeat 16, 16, L_0x84aee80a0; +L_0x84b1a28a0 .concat [ 16 16 0 0], L_0x84b1a2800, L_0x84aee8140; +L_0x84aed2a80 .arith/sum 32, L_0x84a879fd8, L_0x84b1a28a0; +S_0x84aeb1680 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153c80 .param/l "i" 1 8 80, +C4<00>; +L_0x84aedc850 .functor BUFZ 32, L_0x84aed2620, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1800 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153cc0 .param/l "i" 1 8 80, +C4<01>; +L_0x84aedc8c0 .functor BUFZ 32, L_0x84aed26c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1980 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153d00 .param/l "i" 1 8 80, +C4<010>; +L_0x84aedc930 .functor BUFZ 32, L_0x84aed2760, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1b00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153d40 .param/l "i" 1 8 80, +C4<011>; +L_0x84aedc9a0 .functor BUFZ 32, L_0x84aed2800, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1c80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153d80 .param/l "i" 1 8 80, +C4<0100>; +L_0x84aedca10 .functor BUFZ 32, L_0x84aed28a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1e00 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153dc0 .param/l "i" 1 8 80, +C4<0101>; +L_0x84aedca80 .functor BUFZ 32, L_0x84aed2940, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb1f80 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153e00 .param/l "i" 1 8 80, +C4<0110>; +L_0x84aedcaf0 .functor BUFZ 32, L_0x84aed29e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb2100 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153e40 .param/l "i" 1 8 80, +C4<0111>; +L_0x84aedcb60 .functor BUFZ 32, L_0x84aed2a80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb2280 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153e80 .param/l "level" 1 8 92, +C4<00>; +S_0x84aeb2400 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeb2280; + .timescale 0 0; +P_0x84b153ec0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2b20 .arith/sum 32, L_0x84aedc850, L_0x84aedc8c0; +S_0x84aeb2580 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aeb2280; + .timescale 0 0; +P_0x84b153f00 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed2bc0 .arith/sum 32, L_0x84aedc930, L_0x84aedc9a0; +S_0x84aeb2700 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84aeb2280; + .timescale 0 0; +P_0x84b153f40 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed2c60 .arith/sum 32, L_0x84aedca10, L_0x84aedca80; +S_0x84aeb2880 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84aeb2280; + .timescale 0 0; +P_0x84b153f80 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed2d00 .arith/sum 32, L_0x84aedcaf0, L_0x84aedcb60; +S_0x84aeb2a00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b153fc0 .param/l "level" 1 8 92, +C4<01>; +S_0x84aeb2b80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeb2a00; + .timescale 0 0; +P_0x84b188000 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2da0 .arith/sum 32, L_0x84aed2b20, L_0x84aed2bc0; +S_0x84aeb2d00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aeb2a00; + .timescale 0 0; +P_0x84b188040 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed2e40 .arith/sum 32, L_0x84aed2c60, L_0x84aed2d00; +S_0x84aeb2e80 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84aea7c00; + .timescale 0 0; +P_0x84b188080 .param/l "level" 1 8 92, +C4<010>; +S_0x84aeb3000 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeb2e80; + .timescale 0 0; +P_0x84b1880c0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed2ee0 .arith/sum 32, L_0x84aed2da0, L_0x84aed2e40; +S_0x84aeb3180 .scope generate, "GEN_NEURON[7]" "GEN_NEURON[7]" 12 34, 12 34 0, S_0x84ae85b00; + .timescale 0 0; +P_0x84b188100 .param/l "n" 1 12 34, +C4<0111>; +S_0x84aeb3300 .scope module, "u_neuron" "neuron_parallel" 12 41, 7 1 0, S_0x84aeb3180; + .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; - .port_info 3 /INPUT 1024 "x_bus"; - .port_info 4 /INPUT 1024 "w_bus"; - .port_info 5 /INPUT 16 "bias"; - .port_info 6 /OUTPUT 16 "y"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x102e67570 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; -P_0x102e675b0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -P_0x102e675f0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; -P_0x102e67630 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; -P_0x102e67670 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; -P_0x102e676b0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; -P_0x102e676f0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; -L_0x8d307c460 .functor BUFZ 16, L_0x8d323cdc0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x8d2d15860_0 .net *"_ivl_0", 31 0, L_0x8d322bde0; 1 drivers -v0x8d2d15900_0 .net *"_ivl_11", 31 0, L_0x8d2d22580; 1 drivers -v0x8d2d159a0_0 .net *"_ivl_14", 31 0, L_0x8d322be80; 1 drivers -L_0x8d2855e70 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d15a40_0 .net *"_ivl_17", 28 0, L_0x8d2855e70; 1 drivers -L_0x8d2855eb8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d15ae0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855eb8; 1 drivers -v0x8d2d15b80_0 .net *"_ivl_21", 31 0, L_0x8d2d22620; 1 drivers -L_0x8d2855f00 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d15c20_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855f00; 1 drivers -v0x8d2d15cc0_0 .net *"_ivl_25", 31 0, L_0x8d2d226c0; 1 drivers -L_0x8d2855d98 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d15d60_0 .net *"_ivl_3", 28 0, L_0x8d2855d98; 1 drivers -v0x8d2d15e00_0 .net *"_ivl_31", 0 0, L_0x8d323cb40; 1 drivers -v0x8d2d15ea0_0 .net *"_ivl_33", 23 0, L_0x8d2d23b60; 1 drivers -v0x8d2d15f40_0 .net *"_ivl_36", 39 0, L_0x8d3238f00; 1 drivers -v0x8d2d15fe0_0 .net *"_ivl_38", 31 0, L_0x8d323cbe0; 1 drivers -L_0x8d2855de0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x8d2d16080_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855de0; 1 drivers -L_0x8d2856188 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d16120_0 .net *"_ivl_40", 7 0, L_0x8d2856188; 1 drivers -v0x8d2d161c0_0 .net *"_ivl_46", 31 0, L_0x8d323cc80; 1 drivers -v0x8d2d16260_0 .net *"_ivl_7", 31 0, L_0x8d2d224e0; 1 drivers -L_0x8d2855e28 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x8d2d16300_0 .net/2u *"_ivl_8", 31 0, L_0x8d2855e28; 1 drivers -v0x8d2d163a0_0 .var/s "acc", 39 0; -v0x8d2d16440_0 .net/s "acc_next", 39 0, L_0x8d3238dc0; 1 drivers -v0x8d2d164e0_0 .net/s "bias", 15 0, L_0x8d323cdc0; 1 drivers -v0x8d2d16580_0 .net/s "bias_ext", 39 0, L_0x8d3238e60; 1 drivers -v0x8d2d16620_0 .net/s "bias_ext_small", 15 0, L_0x8d307c460; 1 drivers -v0x8d2d166c0_0 .var "busy", 0 0; -v0x8d2d16760_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers -v0x8d2d16800_0 .var "done", 0 0; -v0x8d2d168a0_0 .net/s "final_acc", 39 0, L_0x8d3238fa0; 1 drivers -v0x8d2d16940_0 .net/s "final_value", 39 0, L_0x8d2d23c00; 1 drivers -v0x8d2d169e0_0 .var "group_index", 2 0; -v0x8d2d16a80_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers -v0x8d2d16b20_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers -v0x8d2d16bc0_0 .net/s "w_bus", 1023 0, L_0x8d323cd20; 1 drivers -v0x8d2d16c60_0 .net/s "w_group", 127 0, L_0x8d322fb60; 1 drivers -v0x8d2d16d00_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers -v0x8d2d16da0_0 .net/s "x_group", 127 0, L_0x8d322fac0; 1 drivers -v0x8d2d16e40_0 .var/s "y", 15 0; -L_0x8d322bde0 .concat [ 3 29 0 0], v0x8d2d169e0_0, L_0x8d2855d98; -L_0x8d2d224e0 .arith/mult 32, L_0x8d322bde0, L_0x8d2855de0; -L_0x8d2d22580 .arith/mult 32, L_0x8d2d224e0, L_0x8d2855e28; -L_0x8d322fac0 .part/v v0x8d2d17ca0_0, L_0x8d2d22580, 128; -L_0x8d322be80 .concat [ 3 29 0 0], v0x8d2d169e0_0, L_0x8d2855e70; -L_0x8d2d22620 .arith/mult 32, L_0x8d322be80, L_0x8d2855eb8; -L_0x8d2d226c0 .arith/mult 32, L_0x8d2d22620, L_0x8d2855f00; -L_0x8d322fb60 .part/v L_0x8d323cd20, L_0x8d2d226c0, 128; -L_0x8d323cb40 .part L_0x8d307c460, 15, 1; -L_0x8d2d23b60 .repeat 24, 24, L_0x8d323cb40; -L_0x8d3238e60 .concat [ 16 24 0 0], L_0x8d307c460, L_0x8d2d23b60; -L_0x8d323cbe0 .part L_0x8d3238e60, 0, 32; -L_0x8d3238f00 .concat [ 8 32 0 0], L_0x8d2856188, L_0x8d323cbe0; -L_0x8d3238fa0 .arith/sum 40, L_0x8d3238dc0, L_0x8d3238f00; -L_0x8d323cc80 .part L_0x8d3238fa0, 8, 32; -L_0x8d2d23c00 .extend/s 40, L_0x8d323cc80; -S_0x8d320ad00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d320ab80; +P_0x84aeb3480 .param/l "ACC_WIDTH" 0 7 5, +C4<00000000000000000000000000100000>; +P_0x84aeb34c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>; +P_0x84aeb3500 .param/l "GROUPS" 1 7 20, +C4<00000000000000000000000000000100>; +P_0x84aeb3540 .param/l "GROUP_INDEX_WIDTH" 1 7 21, +C4<00000000000000000000000000000010>; +P_0x84aeb3580 .param/l "N_INPUTS" 0 7 3, +C4<00000000000000000000000000100000>; +P_0x84aeb35c0 .param/l "PARALLEL" 0 7 4, +C4<00000000000000000000000000001000>; +v0x84b18fe80_0 .net *"_ivl_0", 31 0, L_0x84b1a2a80; 1 drivers +v0x84b18ff20_0 .net *"_ivl_11", 31 0, L_0x84b1a2bc0; 1 drivers +v0x84b190000_0 .net *"_ivl_14", 31 0, L_0x84b1a2c60; 1 drivers +L_0x84a87a0f8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b1900a0_0 .net *"_ivl_17", 29 0, L_0x84a87a0f8; 1 drivers +L_0x84a87a140 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b190140_0 .net/2u *"_ivl_18", 31 0, L_0x84a87a140; 1 drivers +v0x84b1901e0_0 .net *"_ivl_21", 31 0, L_0x84b1a2d00; 1 drivers +L_0x84a87a188 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b190280_0 .net/2u *"_ivl_22", 31 0, L_0x84a87a188; 1 drivers +v0x84b190320_0 .net *"_ivl_25", 31 0, L_0x84b1a2da0; 1 drivers +v0x84b1903c0_0 .net *"_ivl_29", 0 0, L_0x84aee9ae0; 1 drivers +L_0x84a87a020 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b190460_0 .net *"_ivl_3", 29 0, L_0x84a87a020; 1 drivers +v0x84b190500_0 .net *"_ivl_31", 23 0, L_0x84aee9b80; 1 drivers +L_0x84a87a068 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1905a0_0 .net/2u *"_ivl_4", 31 0, L_0x84a87a068; 1 drivers +v0x84b190640_0 .net *"_ivl_7", 31 0, L_0x84b1a2b20; 1 drivers +L_0x84a87a0b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x84b1906e0_0 .net/2u *"_ivl_8", 31 0, L_0x84a87a0b0; 1 drivers +v0x84b190780_0 .var/s "acc", 31 0; +v0x84b190820_0 .net/s "acc_next", 31 0, L_0x84aed3a20; 1 drivers +v0x84b1908c0_0 .net/s "bias", 7 0, L_0x84aee9cc0; 1 drivers +v0x84b190960_0 .net/s "bias_ext", 31 0, L_0x84b1a4320; 1 drivers +v0x84b190a00_0 .var "busy", 0 0; +v0x84b190aa0_0 .net "clk", 0 0, v0x84b1919a0_0; alias, 1 drivers +v0x84b190b40_0 .var "done", 0 0; +v0x84b190be0_0 .net/s "final_acc", 31 0, L_0x84aed3ac0; 1 drivers +v0x84b190c80_0 .var "group_index", 1 0; +v0x84b190d20_0 .net "rst", 0 0, v0x84b191c20_0; alias, 1 drivers +v0x84b190dc0_0 .net "start", 0 0, v0x84b191cc0_0; alias, 1 drivers +v0x84b190e60_0 .net/s "w_bus", 255 0, L_0x84aee9c20; 1 drivers +v0x84b190f00_0 .net/s "w_group", 63 0, L_0x84aee8640; 1 drivers +v0x84b190fa0_0 .net/s "x_bus", 255 0, v0x84b191e00_0; alias, 1 drivers +v0x84b191040_0 .net/s "x_group", 63 0, L_0x84aee85a0; 1 drivers +v0x84b1910e0_0 .var/s "y", 7 0; +L_0x84b1a2a80 .concat [ 2 30 0 0], v0x84b190c80_0, L_0x84a87a020; +L_0x84b1a2b20 .arith/mult 32, L_0x84b1a2a80, L_0x84a87a068; +L_0x84b1a2bc0 .arith/mult 32, L_0x84b1a2b20, L_0x84a87a0b0; +L_0x84aee85a0 .part/v v0x84b191e00_0, L_0x84b1a2bc0, 64; +L_0x84b1a2c60 .concat [ 2 30 0 0], v0x84b190c80_0, L_0x84a87a0f8; +L_0x84b1a2d00 .arith/mult 32, L_0x84b1a2c60, L_0x84a87a140; +L_0x84b1a2da0 .arith/mult 32, L_0x84b1a2d00, L_0x84a87a188; +L_0x84aee8640 .part/v L_0x84aee9c20, L_0x84b1a2da0, 64; +L_0x84aee9ae0 .part L_0x84aee9cc0, 7, 1; +L_0x84aee9b80 .repeat 24, 24, L_0x84aee9ae0; +L_0x84b1a4320 .concat [ 8 24 0 0], L_0x84aee9cc0, L_0x84aee9b80; +L_0x84aed3ac0 .arith/sum 32, L_0x84aed3a20, L_0x84b1a4320; +S_0x84aeb3600 .scope module, "u_mac8" "mac8" 7 52, 8 1 0, S_0x84aeb3300; .timescale 0 0; - .port_info 0 /INPUT 128 "x_bus"; - .port_info 1 /INPUT 128 "w_bus"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d30a0980 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x8d30a09c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -v0x8d2d14c80_0 .net/s "acc_in", 39 0, v0x8d2d163a0_0; 1 drivers -v0x8d2d14d20_0 .net/s "acc_out", 39 0, L_0x8d3238dc0; alias, 1 drivers -v0x8d2d14dc0_0 .net/s "m0", 39 0, L_0x8d3238000; 1 drivers -v0x8d2d14e60_0 .net/s "m1", 39 0, L_0x8d3238140; 1 drivers -v0x8d2d14f00_0 .net/s "m2", 39 0, L_0x8d3238280; 1 drivers -v0x8d2d14fa0_0 .net/s "m3", 39 0, L_0x8d32383c0; 1 drivers -v0x8d2d15040_0 .net/s "m4", 39 0, L_0x8d3238500; 1 drivers -v0x8d2d150e0_0 .net/s "m5", 39 0, L_0x8d3238640; 1 drivers -v0x8d2d15180_0 .net/s "m6", 39 0, L_0x8d3238780; 1 drivers -v0x8d2d15220_0 .net/s "m7", 39 0, L_0x8d32388c0; 1 drivers -v0x8d2d152c0_0 .net/s "s0", 39 0, L_0x8d3238960; 1 drivers -v0x8d2d15360_0 .net/s "s1", 39 0, L_0x8d3238a00; 1 drivers -v0x8d2d15400_0 .net/s "s2", 39 0, L_0x8d3238aa0; 1 drivers -v0x8d2d154a0_0 .net/s "s3", 39 0, L_0x8d3238b40; 1 drivers -v0x8d2d15540_0 .net/s "s4", 39 0, L_0x8d3238be0; 1 drivers -v0x8d2d155e0_0 .net/s "s5", 39 0, L_0x8d3238c80; 1 drivers -v0x8d2d15680_0 .net/s "sum", 39 0, L_0x8d3238d20; 1 drivers -v0x8d2d15720_0 .net/s "w_bus", 127 0, L_0x8d322fb60; alias, 1 drivers -v0x8d2d157c0_0 .net/s "x_bus", 127 0, L_0x8d322fac0; alias, 1 drivers -L_0x8d322fca0 .part L_0x8d322fac0, 0, 16; -L_0x8d322fd40 .part L_0x8d322fb60, 0, 16; -L_0x8d322fe80 .part L_0x8d322fac0, 16, 16; -L_0x8d322ff20 .part L_0x8d322fb60, 16, 16; -L_0x8d323c0a0 .part L_0x8d322fac0, 32, 16; -L_0x8d323c140 .part L_0x8d322fb60, 32, 16; -L_0x8d323c280 .part L_0x8d322fac0, 48, 16; -L_0x8d323c320 .part L_0x8d322fb60, 48, 16; -L_0x8d323c460 .part L_0x8d322fac0, 64, 16; -L_0x8d323c500 .part L_0x8d322fb60, 64, 16; -L_0x8d323c640 .part L_0x8d322fac0, 80, 16; -L_0x8d323c6e0 .part L_0x8d322fb60, 80, 16; -L_0x8d323c820 .part L_0x8d322fac0, 96, 16; -L_0x8d323c8c0 .part L_0x8d322fb60, 96, 16; -L_0x8d323ca00 .part L_0x8d322fac0, 112, 16; -L_0x8d323caa0 .part L_0x8d322fb60, 112, 16; -L_0x8d3238960 .arith/sum 40, L_0x8d3238000, L_0x8d3238140; -L_0x8d3238a00 .arith/sum 40, L_0x8d3238280, L_0x8d32383c0; -L_0x8d3238aa0 .arith/sum 40, L_0x8d3238500, L_0x8d3238640; -L_0x8d3238b40 .arith/sum 40, L_0x8d3238780, L_0x8d32388c0; -L_0x8d3238be0 .arith/sum 40, L_0x8d3238960, L_0x8d3238a00; -L_0x8d3238c80 .arith/sum 40, L_0x8d3238aa0, L_0x8d3238b40; -L_0x8d3238d20 .arith/sum 40, L_0x8d3238be0, L_0x8d3238c80; -L_0x8d3238dc0 .arith/sum 40, v0x8d2d163a0_0, L_0x8d3238d20; -S_0x8d320ae80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d320ad00; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84acc8a00 .param/l "ACC_WIDTH" 0 8 3, +C4<00000000000000000000000000100000>; +P_0x84acc8a40 .param/l "DATA_WIDTH" 0 8 2, +C4<00000000000000000000000000001000>; +P_0x84acc8a80 .param/l "PARALLEL" 0 8 4, +C4<00000000000000000000000000001000>; +P_0x84acc8ac0 .param/l "TREE_LEVELS" 1 8 70, +C4<00000000000000000000000000000011>; +v0x84b18fac0_0 .net/s "acc_in", 31 0, v0x84b190780_0; 1 drivers +v0x84b18fb60_0 .net/s "acc_out", 31 0, L_0x84aed3a20; alias, 1 drivers +v0x84b18fc00 .array "products", 7 0; +v0x84b18fc00_0 .net/s v0x84b18fc00 0, 31 0, L_0x84aed30c0; 1 drivers +v0x84b18fc00_1 .net/s v0x84b18fc00 1, 31 0, L_0x84aed3160; 1 drivers +v0x84b18fc00_2 .net/s v0x84b18fc00 2, 31 0, L_0x84aed3200; 1 drivers +v0x84b18fc00_3 .net/s v0x84b18fc00 3, 31 0, L_0x84aed32a0; 1 drivers +v0x84b18fc00_4 .net/s v0x84b18fc00 4, 31 0, L_0x84aed3340; 1 drivers +v0x84b18fc00_5 .net/s v0x84b18fc00 5, 31 0, L_0x84aed33e0; 1 drivers +v0x84b18fc00_6 .net/s v0x84b18fc00 6, 31 0, L_0x84aed3480; 1 drivers +v0x84b18fc00_7 .net/s v0x84b18fc00 7, 31 0, L_0x84aed3520; 1 drivers +v0x84b18fca0 .array "tree", 31 0; +v0x84b18fca0_0 .net/s v0x84b18fca0 0, 31 0, L_0x84aedcbd0; 1 drivers +v0x84b18fca0_1 .net/s v0x84b18fca0 1, 31 0, L_0x84aedcc40; 1 drivers +v0x84b18fca0_2 .net/s v0x84b18fca0 2, 31 0, L_0x84aedccb0; 1 drivers +v0x84b18fca0_3 .net/s v0x84b18fca0 3, 31 0, L_0x84aedcd20; 1 drivers +v0x84b18fca0_4 .net/s v0x84b18fca0 4, 31 0, L_0x84aedcd90; 1 drivers +v0x84b18fca0_5 .net/s v0x84b18fca0 5, 31 0, L_0x84aedce00; 1 drivers +v0x84b18fca0_6 .net/s v0x84b18fca0 6, 31 0, L_0x84aedce70; 1 drivers +v0x84b18fca0_7 .net/s v0x84b18fca0 7, 31 0, L_0x84aedcee0; 1 drivers +v0x84b18fca0_8 .net/s v0x84b18fca0 8, 31 0, L_0x84aed35c0; 1 drivers +v0x84b18fca0_9 .net/s v0x84b18fca0 9, 31 0, L_0x84aed3660; 1 drivers +v0x84b18fca0_10 .net/s v0x84b18fca0 10, 31 0, L_0x84aed3700; 1 drivers +v0x84b18fca0_11 .net/s v0x84b18fca0 11, 31 0, L_0x84aed37a0; 1 drivers +o0x84a85a3c0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_12 .net/s v0x84b18fca0 12, 31 0, o0x84a85a3c0; 0 drivers +o0x84a85a3f0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_13 .net/s v0x84b18fca0 13, 31 0, o0x84a85a3f0; 0 drivers +o0x84a85a420 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_14 .net/s v0x84b18fca0 14, 31 0, o0x84a85a420; 0 drivers +o0x84a85a450 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_15 .net/s v0x84b18fca0 15, 31 0, o0x84a85a450; 0 drivers +v0x84b18fca0_16 .net/s v0x84b18fca0 16, 31 0, L_0x84aed3840; 1 drivers +v0x84b18fca0_17 .net/s v0x84b18fca0 17, 31 0, L_0x84aed38e0; 1 drivers +o0x84a85a4e0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_18 .net/s v0x84b18fca0 18, 31 0, o0x84a85a4e0; 0 drivers +o0x84a85a510 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_19 .net/s v0x84b18fca0 19, 31 0, o0x84a85a510; 0 drivers +o0x84a85a540 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_20 .net/s v0x84b18fca0 20, 31 0, o0x84a85a540; 0 drivers +o0x84a85a570 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_21 .net/s v0x84b18fca0 21, 31 0, o0x84a85a570; 0 drivers +o0x84a85a5a0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_22 .net/s v0x84b18fca0 22, 31 0, o0x84a85a5a0; 0 drivers +o0x84a85a5d0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_23 .net/s v0x84b18fca0 23, 31 0, o0x84a85a5d0; 0 drivers +v0x84b18fca0_24 .net/s v0x84b18fca0 24, 31 0, L_0x84aed3980; 1 drivers +o0x84a85a630 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_25 .net/s v0x84b18fca0 25, 31 0, o0x84a85a630; 0 drivers +o0x84a85a660 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_26 .net/s v0x84b18fca0 26, 31 0, o0x84a85a660; 0 drivers +o0x84a85a690 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_27 .net/s v0x84b18fca0 27, 31 0, o0x84a85a690; 0 drivers +o0x84a85a6c0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_28 .net/s v0x84b18fca0 28, 31 0, o0x84a85a6c0; 0 drivers +o0x84a85a6f0 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_29 .net/s v0x84b18fca0 29, 31 0, o0x84a85a6f0; 0 drivers +o0x84a85a720 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_30 .net/s v0x84b18fca0 30, 31 0, o0x84a85a720; 0 drivers +o0x84a85a750 .functor BUFZ 32, c4; HiZ drive +v0x84b18fca0_31 .net/s v0x84b18fca0 31, 31 0, o0x84a85a750; 0 drivers +v0x84b18fd40_0 .net/s "w_bus", 63 0, L_0x84aee8640; alias, 1 drivers +v0x84b18fde0_0 .net/s "x_bus", 63 0, L_0x84aee85a0; alias, 1 drivers +L_0x84aee8820 .part L_0x84aee85a0, 0, 8; +L_0x84aee88c0 .part L_0x84aee8640, 0, 8; +L_0x84aee8aa0 .part L_0x84aee85a0, 8, 8; +L_0x84aee8b40 .part L_0x84aee8640, 8, 8; +L_0x84aee8d20 .part L_0x84aee85a0, 16, 8; +L_0x84aee8dc0 .part L_0x84aee8640, 16, 8; +L_0x84aee8fa0 .part L_0x84aee85a0, 24, 8; +L_0x84aee9040 .part L_0x84aee8640, 24, 8; +L_0x84aee9220 .part L_0x84aee85a0, 32, 8; +L_0x84aee92c0 .part L_0x84aee8640, 32, 8; +L_0x84aee94a0 .part L_0x84aee85a0, 40, 8; +L_0x84aee9540 .part L_0x84aee8640, 40, 8; +L_0x84aee9720 .part L_0x84aee85a0, 48, 8; +L_0x84aee97c0 .part L_0x84aee8640, 48, 8; +L_0x84aee99a0 .part L_0x84aee85a0, 56, 8; +L_0x84aee9a40 .part L_0x84aee8640, 56, 8; +L_0x84aed3a20 .arith/sum 32, v0x84b190780_0, L_0x84aed3980; +S_0x84aeb3780 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 8 20, 8 20 0, S_0x84aeb3600; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306eac0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306eb00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306eb40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d11a40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22760; 1 drivers -v0x8d2d11ae0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22800; 1 drivers -v0x8d2d11b80_0 .net *"_ivl_7", 0 0, L_0x8d322fc00; 1 drivers -v0x8d2d11c20_0 .net *"_ivl_9", 7 0, L_0x8d2d22940; 1 drivers -L_0x8d2855f48 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d11cc0_0 .net/s "acc_in", 39 0, L_0x8d2855f48; 1 drivers -v0x8d2d11d60_0 .net/s "acc_out", 39 0, L_0x8d3238000; alias, 1 drivers -v0x8d2d11e00_0 .net/s "product", 31 0, L_0x8d2d228a0; 1 drivers -v0x8d2d11ea0_0 .net/s "product_ext", 39 0, L_0x8d322bf20; 1 drivers -v0x8d2d11f40_0 .net/s "w", 15 0, L_0x8d322fd40; 1 drivers -v0x8d2d11fe0_0 .net/s "x", 15 0, L_0x8d322fca0; 1 drivers -L_0x8d2d22760 .extend/s 32, L_0x8d322fca0; -L_0x8d2d22800 .extend/s 32, L_0x8d322fd40; -L_0x8d2d228a0 .arith/mult 32, L_0x8d2d22760, L_0x8d2d22800; -L_0x8d322fc00 .part L_0x8d2d228a0, 31, 1; -L_0x8d2d22940 .repeat 8, 8, L_0x8d322fc00; -L_0x8d322bf20 .concat [ 32 8 0 0], L_0x8d2d228a0, L_0x8d2d22940; -L_0x8d3238000 .arith/sum 40, L_0x8d2855f48, L_0x8d322bf20; -S_0x8d320b000 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d320ad00; +P_0x84b188140 .param/l "i" 1 8 20, +C4<00>; +S_0x84aeb3900 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb3780; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306eb80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ebc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ec00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d12080_0 .net/s *"_ivl_0", 31 0, L_0x8d2d229e0; 1 drivers -v0x8d2d12120_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22a80; 1 drivers -v0x8d2d121c0_0 .net *"_ivl_7", 0 0, L_0x8d322fde0; 1 drivers -v0x8d2d12260_0 .net *"_ivl_9", 7 0, L_0x8d2d22bc0; 1 drivers -L_0x8d2855f90 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d12300_0 .net/s "acc_in", 39 0, L_0x8d2855f90; 1 drivers -v0x8d2d123a0_0 .net/s "acc_out", 39 0, L_0x8d3238140; alias, 1 drivers -v0x8d2d12440_0 .net/s "product", 31 0, L_0x8d2d22b20; 1 drivers -v0x8d2d124e0_0 .net/s "product_ext", 39 0, L_0x8d32380a0; 1 drivers -v0x8d2d12580_0 .net/s "w", 15 0, L_0x8d322ff20; 1 drivers -v0x8d2d12620_0 .net/s "x", 15 0, L_0x8d322fe80; 1 drivers -L_0x8d2d229e0 .extend/s 32, L_0x8d322fe80; -L_0x8d2d22a80 .extend/s 32, L_0x8d322ff20; -L_0x8d2d22b20 .arith/mult 32, L_0x8d2d229e0, L_0x8d2d22a80; -L_0x8d322fde0 .part L_0x8d2d22b20, 31, 1; -L_0x8d2d22bc0 .repeat 8, 8, L_0x8d322fde0; -L_0x8d32380a0 .concat [ 32 8 0 0], L_0x8d2d22b20, L_0x8d2d22bc0; -L_0x8d3238140 .arith/sum 40, L_0x8d2855f90, L_0x8d32380a0; -S_0x8d320b180 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d320ad00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15adc0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15ae00 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15ae40 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18c8c0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a2e40; 1 drivers +v0x84b18c960_0 .net/s *"_ivl_2", 15 0, L_0x84b1a2ee0; 1 drivers +v0x84b18ca00_0 .net *"_ivl_7", 0 0, L_0x84aee86e0; 1 drivers +v0x84b18caa0_0 .net *"_ivl_9", 15 0, L_0x84aee8780; 1 drivers +L_0x84a87a1d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18cb40_0 .net/s "acc_in", 31 0, L_0x84a87a1d0; 1 drivers +v0x84b18cbe0_0 .net/s "acc_out", 31 0, L_0x84aed30c0; alias, 1 drivers +v0x84b18cc80_0 .net/s "product", 15 0, L_0x84b1a2f80; 1 drivers +v0x84b18cd20_0 .net/s "product_ext", 31 0, L_0x84b1a3020; 1 drivers +v0x84b18cdc0_0 .net/s "w", 7 0, L_0x84aee88c0; 1 drivers +v0x84b18ce60_0 .net/s "x", 7 0, L_0x84aee8820; 1 drivers +L_0x84b1a2e40 .extend/s 16, L_0x84aee8820; +L_0x84b1a2ee0 .extend/s 16, L_0x84aee88c0; +L_0x84b1a2f80 .arith/mult 16, L_0x84b1a2e40, L_0x84b1a2ee0; +L_0x84aee86e0 .part L_0x84b1a2f80, 15, 1; +L_0x84aee8780 .repeat 16, 16, L_0x84aee86e0; +L_0x84b1a3020 .concat [ 16 16 0 0], L_0x84b1a2f80, L_0x84aee8780; +L_0x84aed30c0 .arith/sum 32, L_0x84a87a1d0, L_0x84b1a3020; +S_0x84aeb3a80 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 8 20, 8 20 0, S_0x84aeb3600; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ec40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ec80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ecc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d126c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22c60; 1 drivers -v0x8d2d12760_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22d00; 1 drivers -v0x8d2d12800_0 .net *"_ivl_7", 0 0, L_0x8d323c000; 1 drivers -v0x8d2d128a0_0 .net *"_ivl_9", 7 0, L_0x8d2d22e40; 1 drivers -L_0x8d2855fd8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d12940_0 .net/s "acc_in", 39 0, L_0x8d2855fd8; 1 drivers -v0x8d2d129e0_0 .net/s "acc_out", 39 0, L_0x8d3238280; alias, 1 drivers -v0x8d2d12a80_0 .net/s "product", 31 0, L_0x8d2d22da0; 1 drivers -v0x8d2d12b20_0 .net/s "product_ext", 39 0, L_0x8d32381e0; 1 drivers -v0x8d2d12bc0_0 .net/s "w", 15 0, L_0x8d323c140; 1 drivers -v0x8d2d12c60_0 .net/s "x", 15 0, L_0x8d323c0a0; 1 drivers -L_0x8d2d22c60 .extend/s 32, L_0x8d323c0a0; -L_0x8d2d22d00 .extend/s 32, L_0x8d323c140; -L_0x8d2d22da0 .arith/mult 32, L_0x8d2d22c60, L_0x8d2d22d00; -L_0x8d323c000 .part L_0x8d2d22da0, 31, 1; -L_0x8d2d22e40 .repeat 8, 8, L_0x8d323c000; -L_0x8d32381e0 .concat [ 32 8 0 0], L_0x8d2d22da0, L_0x8d2d22e40; -L_0x8d3238280 .arith/sum 40, L_0x8d2855fd8, L_0x8d32381e0; -S_0x8d320b300 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d320ad00; +P_0x84b188180 .param/l "i" 1 8 20, +C4<01>; +S_0x84aeb3c00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb3a80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ed00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ed40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ed80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d12d00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22ee0; 1 drivers -v0x8d2d12da0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22f80; 1 drivers -v0x8d2d12e40_0 .net *"_ivl_7", 0 0, L_0x8d323c1e0; 1 drivers -v0x8d2d12ee0_0 .net *"_ivl_9", 7 0, L_0x8d2d230c0; 1 drivers -L_0x8d2856020 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d12f80_0 .net/s "acc_in", 39 0, L_0x8d2856020; 1 drivers -v0x8d2d13020_0 .net/s "acc_out", 39 0, L_0x8d32383c0; alias, 1 drivers -v0x8d2d130c0_0 .net/s "product", 31 0, L_0x8d2d23020; 1 drivers -v0x8d2d13160_0 .net/s "product_ext", 39 0, L_0x8d3238320; 1 drivers -v0x8d2d13200_0 .net/s "w", 15 0, L_0x8d323c320; 1 drivers -v0x8d2d132a0_0 .net/s "x", 15 0, L_0x8d323c280; 1 drivers -L_0x8d2d22ee0 .extend/s 32, L_0x8d323c280; -L_0x8d2d22f80 .extend/s 32, L_0x8d323c320; -L_0x8d2d23020 .arith/mult 32, L_0x8d2d22ee0, L_0x8d2d22f80; -L_0x8d323c1e0 .part L_0x8d2d23020, 31, 1; -L_0x8d2d230c0 .repeat 8, 8, L_0x8d323c1e0; -L_0x8d3238320 .concat [ 32 8 0 0], L_0x8d2d23020, L_0x8d2d230c0; -L_0x8d32383c0 .arith/sum 40, L_0x8d2856020, L_0x8d3238320; -S_0x8d320b480 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d320ad00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15ae80 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15aec0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15af00 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18cf00_0 .net/s *"_ivl_0", 15 0, L_0x84b1a30c0; 1 drivers +v0x84b18cfa0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a3160; 1 drivers +v0x84b18d040_0 .net *"_ivl_7", 0 0, L_0x84aee8960; 1 drivers +v0x84b18d0e0_0 .net *"_ivl_9", 15 0, L_0x84aee8a00; 1 drivers +L_0x84a87a218 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18d180_0 .net/s "acc_in", 31 0, L_0x84a87a218; 1 drivers +v0x84b18d220_0 .net/s "acc_out", 31 0, L_0x84aed3160; alias, 1 drivers +v0x84b18d2c0_0 .net/s "product", 15 0, L_0x84b1a3200; 1 drivers +v0x84b18d360_0 .net/s "product_ext", 31 0, L_0x84b1a32a0; 1 drivers +v0x84b18d400_0 .net/s "w", 7 0, L_0x84aee8b40; 1 drivers +v0x84b18d4a0_0 .net/s "x", 7 0, L_0x84aee8aa0; 1 drivers +L_0x84b1a30c0 .extend/s 16, L_0x84aee8aa0; +L_0x84b1a3160 .extend/s 16, L_0x84aee8b40; +L_0x84b1a3200 .arith/mult 16, L_0x84b1a30c0, L_0x84b1a3160; +L_0x84aee8960 .part L_0x84b1a3200, 15, 1; +L_0x84aee8a00 .repeat 16, 16, L_0x84aee8960; +L_0x84b1a32a0 .concat [ 16 16 0 0], L_0x84b1a3200, L_0x84aee8a00; +L_0x84aed3160 .arith/sum 32, L_0x84a87a218, L_0x84b1a32a0; +S_0x84aeb3d80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 8 20, 8 20 0, S_0x84aeb3600; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306edc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ee00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ee40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d13340_0 .net/s *"_ivl_0", 31 0, L_0x8d2d23160; 1 drivers -v0x8d2d133e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23200; 1 drivers -v0x8d2d13480_0 .net *"_ivl_7", 0 0, L_0x8d323c3c0; 1 drivers -v0x8d2d13520_0 .net *"_ivl_9", 7 0, L_0x8d2d23340; 1 drivers -L_0x8d2856068 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d135c0_0 .net/s "acc_in", 39 0, L_0x8d2856068; 1 drivers -v0x8d2d13660_0 .net/s "acc_out", 39 0, L_0x8d3238500; alias, 1 drivers -v0x8d2d13700_0 .net/s "product", 31 0, L_0x8d2d232a0; 1 drivers -v0x8d2d137a0_0 .net/s "product_ext", 39 0, L_0x8d3238460; 1 drivers -v0x8d2d13840_0 .net/s "w", 15 0, L_0x8d323c500; 1 drivers -v0x8d2d138e0_0 .net/s "x", 15 0, L_0x8d323c460; 1 drivers -L_0x8d2d23160 .extend/s 32, L_0x8d323c460; -L_0x8d2d23200 .extend/s 32, L_0x8d323c500; -L_0x8d2d232a0 .arith/mult 32, L_0x8d2d23160, L_0x8d2d23200; -L_0x8d323c3c0 .part L_0x8d2d232a0, 31, 1; -L_0x8d2d23340 .repeat 8, 8, L_0x8d323c3c0; -L_0x8d3238460 .concat [ 32 8 0 0], L_0x8d2d232a0, L_0x8d2d23340; -L_0x8d3238500 .arith/sum 40, L_0x8d2856068, L_0x8d3238460; -S_0x8d320b600 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d320ad00; +P_0x84b1881c0 .param/l "i" 1 8 20, +C4<010>; +S_0x84aeb8000 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb3d80; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ee80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306eec0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306ef00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d13980_0 .net/s *"_ivl_0", 31 0, L_0x8d2d233e0; 1 drivers -v0x8d2d13a20_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23480; 1 drivers -v0x8d2d13ac0_0 .net *"_ivl_7", 0 0, L_0x8d323c5a0; 1 drivers -v0x8d2d13b60_0 .net *"_ivl_9", 7 0, L_0x8d2d235c0; 1 drivers -L_0x8d28560b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d13c00_0 .net/s "acc_in", 39 0, L_0x8d28560b0; 1 drivers -v0x8d2d13ca0_0 .net/s "acc_out", 39 0, L_0x8d3238640; alias, 1 drivers -v0x8d2d13d40_0 .net/s "product", 31 0, L_0x8d2d23520; 1 drivers -v0x8d2d13de0_0 .net/s "product_ext", 39 0, L_0x8d32385a0; 1 drivers -v0x8d2d13e80_0 .net/s "w", 15 0, L_0x8d323c6e0; 1 drivers -v0x8d2d13f20_0 .net/s "x", 15 0, L_0x8d323c640; 1 drivers -L_0x8d2d233e0 .extend/s 32, L_0x8d323c640; -L_0x8d2d23480 .extend/s 32, L_0x8d323c6e0; -L_0x8d2d23520 .arith/mult 32, L_0x8d2d233e0, L_0x8d2d23480; -L_0x8d323c5a0 .part L_0x8d2d23520, 31, 1; -L_0x8d2d235c0 .repeat 8, 8, L_0x8d323c5a0; -L_0x8d32385a0 .concat [ 32 8 0 0], L_0x8d2d23520, L_0x8d2d235c0; -L_0x8d3238640 .arith/sum 40, L_0x8d28560b0, L_0x8d32385a0; -S_0x8d320b780 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d320ad00; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15af40 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15af80 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15afc0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18d540_0 .net/s *"_ivl_0", 15 0, L_0x84b1a3340; 1 drivers +v0x84b18d5e0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a33e0; 1 drivers +v0x84b18d680_0 .net *"_ivl_7", 0 0, L_0x84aee8be0; 1 drivers +v0x84b18d720_0 .net *"_ivl_9", 15 0, L_0x84aee8c80; 1 drivers +L_0x84a87a260 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18d7c0_0 .net/s "acc_in", 31 0, L_0x84a87a260; 1 drivers +v0x84b18d860_0 .net/s "acc_out", 31 0, L_0x84aed3200; alias, 1 drivers +v0x84b18d900_0 .net/s "product", 15 0, L_0x84b1a3480; 1 drivers +v0x84b18d9a0_0 .net/s "product_ext", 31 0, L_0x84b1a3520; 1 drivers +v0x84b18da40_0 .net/s "w", 7 0, L_0x84aee8dc0; 1 drivers +v0x84b18dae0_0 .net/s "x", 7 0, L_0x84aee8d20; 1 drivers +L_0x84b1a3340 .extend/s 16, L_0x84aee8d20; +L_0x84b1a33e0 .extend/s 16, L_0x84aee8dc0; +L_0x84b1a3480 .arith/mult 16, L_0x84b1a3340, L_0x84b1a33e0; +L_0x84aee8be0 .part L_0x84b1a3480, 15, 1; +L_0x84aee8c80 .repeat 16, 16, L_0x84aee8be0; +L_0x84b1a3520 .concat [ 16 16 0 0], L_0x84b1a3480, L_0x84aee8c80; +L_0x84aed3200 .arith/sum 32, L_0x84a87a260, L_0x84b1a3520; +S_0x84aeb8180 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 8 20, 8 20 0, S_0x84aeb3600; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306ef40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306ef80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306efc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d14000_0 .net/s *"_ivl_0", 31 0, L_0x8d2d23660; 1 drivers -v0x8d2d140a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23700; 1 drivers -v0x8d2d14140_0 .net *"_ivl_7", 0 0, L_0x8d323c780; 1 drivers -v0x8d2d141e0_0 .net *"_ivl_9", 7 0, L_0x8d2d23840; 1 drivers -L_0x8d28560f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d14280_0 .net/s "acc_in", 39 0, L_0x8d28560f8; 1 drivers -v0x8d2d14320_0 .net/s "acc_out", 39 0, L_0x8d3238780; alias, 1 drivers -v0x8d2d143c0_0 .net/s "product", 31 0, L_0x8d2d237a0; 1 drivers -v0x8d2d14460_0 .net/s "product_ext", 39 0, L_0x8d32386e0; 1 drivers -v0x8d2d14500_0 .net/s "w", 15 0, L_0x8d323c8c0; 1 drivers -v0x8d2d145a0_0 .net/s "x", 15 0, L_0x8d323c820; 1 drivers -L_0x8d2d23660 .extend/s 32, L_0x8d323c820; -L_0x8d2d23700 .extend/s 32, L_0x8d323c8c0; -L_0x8d2d237a0 .arith/mult 32, L_0x8d2d23660, L_0x8d2d23700; -L_0x8d323c780 .part L_0x8d2d237a0, 31, 1; -L_0x8d2d23840 .repeat 8, 8, L_0x8d323c780; -L_0x8d32386e0 .concat [ 32 8 0 0], L_0x8d2d237a0, L_0x8d2d23840; -L_0x8d3238780 .arith/sum 40, L_0x8d28560f8, L_0x8d32386e0; -S_0x8d320b900 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d320ad00; +P_0x84b188200 .param/l "i" 1 8 20, +C4<011>; +S_0x84aeb8300 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb8180; .timescale 0 0; - .port_info 0 /INPUT 16 "x"; - .port_info 1 /INPUT 16 "w"; - .port_info 2 /INPUT 40 "acc_in"; - .port_info 3 /OUTPUT 40 "acc_out"; -P_0x8d306f000 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; -P_0x8d306f040 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; -P_0x8d306f080 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x8d2d14640_0 .net/s *"_ivl_0", 31 0, L_0x8d2d238e0; 1 drivers -v0x8d2d146e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23980; 1 drivers -v0x8d2d14780_0 .net *"_ivl_7", 0 0, L_0x8d323c960; 1 drivers -v0x8d2d14820_0 .net *"_ivl_9", 7 0, L_0x8d2d23ac0; 1 drivers -L_0x8d2856140 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x8d2d148c0_0 .net/s "acc_in", 39 0, L_0x8d2856140; 1 drivers -v0x8d2d14960_0 .net/s "acc_out", 39 0, L_0x8d32388c0; alias, 1 drivers -v0x8d2d14a00_0 .net/s "product", 31 0, L_0x8d2d23a20; 1 drivers -v0x8d2d14aa0_0 .net/s "product_ext", 39 0, L_0x8d3238820; 1 drivers -v0x8d2d14b40_0 .net/s "w", 15 0, L_0x8d323caa0; 1 drivers -v0x8d2d14be0_0 .net/s "x", 15 0, L_0x8d323ca00; 1 drivers -L_0x8d2d238e0 .extend/s 32, L_0x8d323ca00; -L_0x8d2d23980 .extend/s 32, L_0x8d323caa0; -L_0x8d2d23a20 .arith/mult 32, L_0x8d2d238e0, L_0x8d2d23980; -L_0x8d323c960 .part L_0x8d2d23a20, 31, 1; -L_0x8d2d23ac0 .repeat 8, 8, L_0x8d323c960; -L_0x8d3238820 .concat [ 32 8 0 0], L_0x8d2d23a20, L_0x8d2d23ac0; -L_0x8d32388c0 .arith/sum 40, L_0x8d2856140, L_0x8d3238820; -S_0x8d320ba80 .scope function.vec4.u16, "q8_8" "q8_8" 3 56, 3 56 0, S_0x102e63dc0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15b000 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15b040 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15b080 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18db80_0 .net/s *"_ivl_0", 15 0, L_0x84b1a35c0; 1 drivers +v0x84b18dc20_0 .net/s *"_ivl_2", 15 0, L_0x84b1a3660; 1 drivers +v0x84b18dcc0_0 .net *"_ivl_7", 0 0, L_0x84aee8e60; 1 drivers +v0x84b18dd60_0 .net *"_ivl_9", 15 0, L_0x84aee8f00; 1 drivers +L_0x84a87a2a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18de00_0 .net/s "acc_in", 31 0, L_0x84a87a2a8; 1 drivers +v0x84b18dea0_0 .net/s "acc_out", 31 0, L_0x84aed32a0; alias, 1 drivers +v0x84b18df40_0 .net/s "product", 15 0, L_0x84b1a3700; 1 drivers +v0x84b18dfe0_0 .net/s "product_ext", 31 0, L_0x84b1a37a0; 1 drivers +v0x84b18e080_0 .net/s "w", 7 0, L_0x84aee9040; 1 drivers +v0x84b18e120_0 .net/s "x", 7 0, L_0x84aee8fa0; 1 drivers +L_0x84b1a35c0 .extend/s 16, L_0x84aee8fa0; +L_0x84b1a3660 .extend/s 16, L_0x84aee9040; +L_0x84b1a3700 .arith/mult 16, L_0x84b1a35c0, L_0x84b1a3660; +L_0x84aee8e60 .part L_0x84b1a3700, 15, 1; +L_0x84aee8f00 .repeat 16, 16, L_0x84aee8e60; +L_0x84b1a37a0 .concat [ 16 16 0 0], L_0x84b1a3700, L_0x84aee8f00; +L_0x84aed32a0 .arith/sum 32, L_0x84a87a2a8, L_0x84b1a37a0; +S_0x84aeb8480 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 8 20, 8 20 0, S_0x84aeb3600; .timescale 0 0; -; Variable q8_8 is vec4 return value of scope S_0x8d320ba80 -v0x8d2d17660_0 .var/real "value", 0 0; -TD_tb.q8_8 ; - %load/real v0x8d2d17660_0; - %pushi/real 1073741824, 4074; load=256.000 - %mul/wr; - %vpi_func 3 59 "$rtoi" 32, W<0,r> {0 1 0}; - %pad/s 16; - %ret/vec4 0, 0, 16; Assign to q8_8 (store_vec4_to_lval) - %end; -S_0x8d320bc00 .scope task, "run_layer" "run_layer" 3 63, 3 63 0, S_0x102e63dc0; +P_0x84b188240 .param/l "i" 1 8 20, +C4<0100>; +S_0x84aeb8600 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb8480; .timescale 0 0; -E_0x8d2ce4380 .event anyedge, v0x8d2d170c0_0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15b0c0 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15b100 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15b140 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18e1c0_0 .net/s *"_ivl_0", 15 0, L_0x84b1a3840; 1 drivers +v0x84b18e260_0 .net/s *"_ivl_2", 15 0, L_0x84b1a38e0; 1 drivers +v0x84b18e300_0 .net *"_ivl_7", 0 0, L_0x84aee90e0; 1 drivers +v0x84b18e3a0_0 .net *"_ivl_9", 15 0, L_0x84aee9180; 1 drivers +L_0x84a87a2f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18e440_0 .net/s "acc_in", 31 0, L_0x84a87a2f0; 1 drivers +v0x84b18e4e0_0 .net/s "acc_out", 31 0, L_0x84aed3340; alias, 1 drivers +v0x84b18e580_0 .net/s "product", 15 0, L_0x84b1a3980; 1 drivers +v0x84b18e620_0 .net/s "product_ext", 31 0, L_0x84b1a3a20; 1 drivers +v0x84b18e6c0_0 .net/s "w", 7 0, L_0x84aee92c0; 1 drivers +v0x84b18e760_0 .net/s "x", 7 0, L_0x84aee9220; 1 drivers +L_0x84b1a3840 .extend/s 16, L_0x84aee9220; +L_0x84b1a38e0 .extend/s 16, L_0x84aee92c0; +L_0x84b1a3980 .arith/mult 16, L_0x84b1a3840, L_0x84b1a38e0; +L_0x84aee90e0 .part L_0x84b1a3980, 15, 1; +L_0x84aee9180 .repeat 16, 16, L_0x84aee90e0; +L_0x84b1a3a20 .concat [ 16 16 0 0], L_0x84b1a3980, L_0x84aee9180; +L_0x84aed3340 .arith/sum 32, L_0x84a87a2f0, L_0x84b1a3a20; +S_0x84aeb8780 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 8 20, 8 20 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188280 .param/l "i" 1 8 20, +C4<0101>; +S_0x84aeb8900 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb8780; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15b180 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15b1c0 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15b200 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18e800_0 .net/s *"_ivl_0", 15 0, L_0x84b1a3ac0; 1 drivers +v0x84b18e8a0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a3b60; 1 drivers +v0x84b18e940_0 .net *"_ivl_7", 0 0, L_0x84aee9360; 1 drivers +v0x84b18e9e0_0 .net *"_ivl_9", 15 0, L_0x84aee9400; 1 drivers +L_0x84a87a338 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18ea80_0 .net/s "acc_in", 31 0, L_0x84a87a338; 1 drivers +v0x84b18eb20_0 .net/s "acc_out", 31 0, L_0x84aed33e0; alias, 1 drivers +v0x84b18ebc0_0 .net/s "product", 15 0, L_0x84b1a3c00; 1 drivers +v0x84b18ec60_0 .net/s "product_ext", 31 0, L_0x84b1a3ca0; 1 drivers +v0x84b18ed00_0 .net/s "w", 7 0, L_0x84aee9540; 1 drivers +v0x84b18eda0_0 .net/s "x", 7 0, L_0x84aee94a0; 1 drivers +L_0x84b1a3ac0 .extend/s 16, L_0x84aee94a0; +L_0x84b1a3b60 .extend/s 16, L_0x84aee9540; +L_0x84b1a3c00 .arith/mult 16, L_0x84b1a3ac0, L_0x84b1a3b60; +L_0x84aee9360 .part L_0x84b1a3c00, 15, 1; +L_0x84aee9400 .repeat 16, 16, L_0x84aee9360; +L_0x84b1a3ca0 .concat [ 16 16 0 0], L_0x84b1a3c00, L_0x84aee9400; +L_0x84aed33e0 .arith/sum 32, L_0x84a87a338, L_0x84b1a3ca0; +S_0x84aeb8a80 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 8 20, 8 20 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b1882c0 .param/l "i" 1 8 20, +C4<0110>; +S_0x84aeb8c00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb8a80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15b240 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15b280 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15b2c0 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18ee40_0 .net/s *"_ivl_0", 15 0, L_0x84b1a3d40; 1 drivers +v0x84b18eee0_0 .net/s *"_ivl_2", 15 0, L_0x84b1a3de0; 1 drivers +v0x84b18ef80_0 .net *"_ivl_7", 0 0, L_0x84aee95e0; 1 drivers +v0x84b18f020_0 .net *"_ivl_9", 15 0, L_0x84aee9680; 1 drivers +L_0x84a87a380 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18f0c0_0 .net/s "acc_in", 31 0, L_0x84a87a380; 1 drivers +v0x84b18f160_0 .net/s "acc_out", 31 0, L_0x84aed3480; alias, 1 drivers +v0x84b18f200_0 .net/s "product", 15 0, L_0x84b1a3e80; 1 drivers +v0x84b18f2a0_0 .net/s "product_ext", 31 0, L_0x84b1a3f20; 1 drivers +v0x84b18f340_0 .net/s "w", 7 0, L_0x84aee97c0; 1 drivers +v0x84b18f3e0_0 .net/s "x", 7 0, L_0x84aee9720; 1 drivers +L_0x84b1a3d40 .extend/s 16, L_0x84aee9720; +L_0x84b1a3de0 .extend/s 16, L_0x84aee97c0; +L_0x84b1a3e80 .arith/mult 16, L_0x84b1a3d40, L_0x84b1a3de0; +L_0x84aee95e0 .part L_0x84b1a3e80, 15, 1; +L_0x84aee9680 .repeat 16, 16, L_0x84aee95e0; +L_0x84b1a3f20 .concat [ 16 16 0 0], L_0x84b1a3e80, L_0x84aee9680; +L_0x84aed3480 .arith/sum 32, L_0x84a87a380, L_0x84b1a3f20; +S_0x84aeb8d80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 8 20, 8 20 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188300 .param/l "i" 1 8 20, +C4<0111>; +S_0x84aeb8f00 .scope module, "u_mac" "mac_unit" 8 25, 9 1 0, S_0x84aeb8d80; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0x84b15b300 .param/l "ACC_WIDTH" 0 9 3, +C4<00000000000000000000000000100000>; +P_0x84b15b340 .param/l "DATA_WIDTH" 0 9 2, +C4<00000000000000000000000000001000>; +P_0x84b15b380 .param/l "PROD_WIDTH" 1 9 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0x84b18f480_0 .net/s *"_ivl_0", 15 0, L_0x84b1a4000; 1 drivers +v0x84b18f520_0 .net/s *"_ivl_2", 15 0, L_0x84b1a40a0; 1 drivers +v0x84b18f5c0_0 .net *"_ivl_7", 0 0, L_0x84aee9860; 1 drivers +v0x84b18f660_0 .net *"_ivl_9", 15 0, L_0x84aee9900; 1 drivers +L_0x84a87a3c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x84b18f700_0 .net/s "acc_in", 31 0, L_0x84a87a3c8; 1 drivers +v0x84b18f7a0_0 .net/s "acc_out", 31 0, L_0x84aed3520; alias, 1 drivers +v0x84b18f840_0 .net/s "product", 15 0, L_0x84b1a4140; 1 drivers +v0x84b18f8e0_0 .net/s "product_ext", 31 0, L_0x84b1a41e0; 1 drivers +v0x84b18f980_0 .net/s "w", 7 0, L_0x84aee9a40; 1 drivers +v0x84b18fa20_0 .net/s "x", 7 0, L_0x84aee99a0; 1 drivers +L_0x84b1a4000 .extend/s 16, L_0x84aee99a0; +L_0x84b1a40a0 .extend/s 16, L_0x84aee9a40; +L_0x84b1a4140 .arith/mult 16, L_0x84b1a4000, L_0x84b1a40a0; +L_0x84aee9860 .part L_0x84b1a4140, 15, 1; +L_0x84aee9900 .repeat 16, 16, L_0x84aee9860; +L_0x84b1a41e0 .concat [ 16 16 0 0], L_0x84b1a4140, L_0x84aee9900; +L_0x84aed3520 .arith/sum 32, L_0x84a87a3c8, L_0x84b1a41e0; +S_0x84aeb9080 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188340 .param/l "i" 1 8 80, +C4<00>; +L_0x84aedcbd0 .functor BUFZ 32, L_0x84aed30c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9200 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188380 .param/l "i" 1 8 80, +C4<01>; +L_0x84aedcc40 .functor BUFZ 32, L_0x84aed3160, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9380 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b1883c0 .param/l "i" 1 8 80, +C4<010>; +L_0x84aedccb0 .functor BUFZ 32, L_0x84aed3200, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9500 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188400 .param/l "i" 1 8 80, +C4<011>; +L_0x84aedcd20 .functor BUFZ 32, L_0x84aed32a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9680 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188440 .param/l "i" 1 8 80, +C4<0100>; +L_0x84aedcd90 .functor BUFZ 32, L_0x84aed3340, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9800 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188480 .param/l "i" 1 8 80, +C4<0101>; +L_0x84aedce00 .functor BUFZ 32, L_0x84aed33e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9980 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b1884c0 .param/l "i" 1 8 80, +C4<0110>; +L_0x84aedce70 .functor BUFZ 32, L_0x84aed3480, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9b00 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 8 80, 8 80 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188500 .param/l "i" 1 8 80, +C4<0111>; +L_0x84aedcee0 .functor BUFZ 32, L_0x84aed3520, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0x84aeb9c80 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 8 92, 8 92 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188540 .param/l "level" 1 8 92, +C4<00>; +S_0x84aeb9e00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeb9c80; + .timescale 0 0; +P_0x84b188580 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed35c0 .arith/sum 32, L_0x84aedcbd0, L_0x84aedcc40; +S_0x84aeb9f80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aeb9c80; + .timescale 0 0; +P_0x84b1885c0 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed3660 .arith/sum 32, L_0x84aedccb0, L_0x84aedcd20; +S_0x84aeba100 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 8 94, 8 94 0, S_0x84aeb9c80; + .timescale 0 0; +P_0x84b188600 .param/l "node" 1 8 94, +C4<010>; +L_0x84aed3700 .arith/sum 32, L_0x84aedcd90, L_0x84aedce00; +S_0x84aeba280 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 8 94, 8 94 0, S_0x84aeb9c80; + .timescale 0 0; +P_0x84b188640 .param/l "node" 1 8 94, +C4<011>; +L_0x84aed37a0 .arith/sum 32, L_0x84aedce70, L_0x84aedcee0; +S_0x84aeba400 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 8 92, 8 92 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188680 .param/l "level" 1 8 92, +C4<01>; +S_0x84aeba580 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeba400; + .timescale 0 0; +P_0x84b1886c0 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed3840 .arith/sum 32, L_0x84aed35c0, L_0x84aed3660; +S_0x84aeba700 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 8 94, 8 94 0, S_0x84aeba400; + .timescale 0 0; +P_0x84b188700 .param/l "node" 1 8 94, +C4<01>; +L_0x84aed38e0 .arith/sum 32, L_0x84aed3700, L_0x84aed37a0; +S_0x84aeba880 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 8 92, 8 92 0, S_0x84aeb3600; + .timescale 0 0; +P_0x84b188740 .param/l "level" 1 8 92, +C4<010>; +S_0x84aebaa00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 8 94, 8 94 0, S_0x84aeba880; + .timescale 0 0; +P_0x84b188780 .param/l "node" 1 8 94, +C4<00>; +L_0x84aed3980 .arith/sum 32, L_0x84aed3840, L_0x84aed38e0; +S_0x84aebab80 .scope task, "run_layer" "run_layer" 11 55, 11 55 0, S_0x102e24df0; + .timescale -9 -12; +E_0x84ae47900 .event anyedge, v0x84b191360_0; TD_tb.run_layer ; - %wait E_0x8d2ce4340; + %wait E_0x84ae46680; %pushi/vec4 1, 0, 1; - %store/vec4 v0x8d2d17b60_0, 0, 1; - %wait E_0x8d2ce4340; + %store/vec4 v0x84b191cc0_0, 0, 1; + %wait E_0x84ae46680; %pushi/vec4 0, 0, 1; - %store/vec4 v0x8d2d17b60_0, 0, 1; -T_1.0 ; - %load/vec4 v0x8d2d178e0_0; + %store/vec4 v0x84b191cc0_0, 0, 1; +T_0.0 ; + %load/vec4 v0x84b191a40_0; %pad/u 32; %pushi/vec4 1, 0, 32; %cmp/e; %flag_get/vec4 4; %cmpi/ne 1, 0, 1; - %jmp/0xz T_1.1, 6; - %wait E_0x8d2ce4380; - %jmp T_1.0; -T_1.1 ; - %wait E_0x8d2ce4340; + %jmp/0xz T_0.1, 6; + %wait E_0x84ae47900; + %jmp T_0.0; +T_0.1 ; + %wait E_0x84ae46680; %end; - .scope S_0x102e579a0; + .scope S_0x102e26840; +T_1 ; + %wait E_0x84ae46340; + %load/vec4 v0x84b0c5540_0; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b0c55e0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b0c5360_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c5400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b0c4f00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b0c5180_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c50e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c52c0_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b0c4e60_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b0c5220_0, 0; + %jmp T_1.1; +T_1.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c5400_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c50e0_0, 0; + %load/vec4 v0x84b0c55e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_1.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_1.3, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b0c55e0_0, 0; + %jmp T_1.5; +T_1.2 ; + %load/vec4 v0x84b0c54a0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.6, 8; + %load/vec4 v0x84b0c57c0_0; + %assign/vec4 v0x84b0c52c0_0, 0; + %load/vec4 v0x84b0c4c80_0; + %assign/vec4 v0x84b0c4e60_0, 0; + %load/vec4 v0x84b0c5720_0; + %assign/vec4 v0x84b0c5220_0, 0; + %load/vec4 v0x84b0c4dc0_0; + %assign/vec4 v0x84b0c4f00_0, 0; + %load/vec4 v0x84b0c5680_0; + %assign/vec4 v0x84b0c5180_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b0c50e0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x84b0c55e0_0, 0; +T_1.6 ; + %jmp T_1.5; +T_1.3 ; + %load/vec4 v0x84b0c5040_0; + %flag_set/vec4 8; + %jmp/0xz T_1.8, 8; + %load/vec4 v0x84b0c52c0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.10, 8; + %load/vec4 v0x84b0c4fa0_0; + %assign/vec4 v0x84b0c5360_0, 0; +T_1.10 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b0c5400_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b0c55e0_0, 0; +T_1.8 ; + %jmp T_1.5; +T_1.5 ; + %pop/vec4 1; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x102e314f0; T_2 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2ced9a0_0; + %wait E_0x84ae46380; + %load/vec4 v0x84b0c5fe0_0; %flag_set/vec4 8; %jmp/0xz T_2.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2ced900_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2ced2c0_0, 0; %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cedd60_0, 0; + %assign/vec4 v0x84b0c5e00_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2ced5e0_0, 0; + %assign/vec4 v0x84b0c5ea0_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2ced720_0, 0; + %assign/vec4 v0x84b0c5900_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c5d60_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b0c5c20_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b0c5cc0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b0c5a40_0, 0; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x84b0c5ae0_0, 0, 32; +T_2.2 ; Top of for-loop + %load/vec4 v0x84b0c5ae0_0; + %cmpi/s 4096, 0, 32; + %jmp/0xz T_2.3, 5; + %pushi/vec4 0, 0, 16; + %ix/getv/s 3, v0x84b0c5ae0_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x84b0c5b80, 0, 4; +T_2.4 ; for-loop step statement + %load/vec4 v0x84b0c5ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x84b0c5ae0_0, 0, 32; + %jmp T_2.2; +T_2.3 ; for-loop exit label %jmp T_2.1; T_2.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2ced720_0, 0; - %load/vec4 v0x8d2ceda40_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_2.4, 9; - %load/vec4 v0x8d2ced5e0_0; + %assign/vec4 v0x84b0c5ea0_0, 0; + %load/vec4 v0x84b0c5900_0; %nor/r; - %and; -T_2.4; - %flag_set/vec4 8; - %jmp/0xz T_2.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2ced900_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2ced2c0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2ced5e0_0, 0; - %jmp T_2.3; -T_2.2 ; - %load/vec4 v0x8d2ced5e0_0; %flag_set/vec4 8; %jmp/0xz T_2.5, 8; - %load/vec4 v0x8d2ced900_0; - %pad/u 32; - %cmpi/e 7, 0, 32; - %jmp/0xz T_2.7, 4; - %load/vec4 v0x8d2ced7c0_0; - %assign/vec4 v0x8d2ced2c0_0, 0; - %load/vec4 v0x8d2ced860_0; - %cmpi/s 0, 0, 40; - %flag_or 5, 4; - %jmp/0xz T_2.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cedd60_0, 0; - %jmp T_2.10; -T_2.9 ; - %load/vec4 v0x8d2ced860_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0x84b0c5f40_0; + %flag_set/vec4 8; + %jmp/0xz T_2.7, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b0c5900_0, 0; + %load/vec4 v0x84b0c6120_0; + %assign/vec4 v0x84b0c5d60_0, 0; + %load/vec4 v0x84b0c5860_0; + %assign/vec4 v0x84b0c5c20_0, 0; + %load/vec4 v0x84b0c6080_0; + %assign/vec4 v0x84b0c5cc0_0, 0; + %pushi/vec4 2, 0, 32; + %assign/vec4 v0x84b0c5a40_0, 0; +T_2.7 ; + %jmp T_2.6; +T_2.5 ; + %load/vec4 v0x84b0c5a40_0; + %cmpi/s 0, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; - %jmp/0xz T_2.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2cedd60_0, 0; + %jmp/0xz T_2.9, 5; + %load/vec4 v0x84b0c5a40_0; + %subi 1, 0, 32; + %assign/vec4 v0x84b0c5a40_0, 0; + %jmp T_2.10; +T_2.9 ; + %load/vec4 v0x84b0c5d60_0; + %flag_set/vec4 8; + %jmp/0xz T_2.11, 8; + %load/vec4 v0x84b0c5c20_0; + %pad/u 32; + %cmpi/u 4096, 0, 32; + %jmp/0xz T_2.13, 5; + %load/vec4 v0x84b0c5cc0_0; + %ix/getv 3, v0x84b0c5c20_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x84b0c5b80, 0, 4; +T_2.13 ; %jmp T_2.12; T_2.11 ; - %load/vec4 v0x8d2ced860_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2cedd60_0, 0; + %load/vec4 v0x84b0c5c20_0; + %pad/u 32; + %cmpi/u 4096, 0, 32; + %jmp/0xz T_2.15, 5; + %ix/getv 4, v0x84b0c5c20_0; + %load/vec4a v0x84b0c5b80, 4; + %assign/vec4 v0x84b0c5e00_0, 0; + %jmp T_2.16; +T_2.15 ; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b0c5e00_0, 0; +T_2.16 ; T_2.12 ; -T_2.10 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2ced5e0_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2ced720_0, 0; - %jmp T_2.8; -T_2.7 ; - %load/vec4 v0x8d2ced360_0; - %assign/vec4 v0x8d2ced2c0_0, 0; - %load/vec4 v0x8d2ced900_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2ced900_0, 0; -T_2.8 ; -T_2.5 ; -T_2.3 ; + %assign/vec4 v0x84b0c5ea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b0c5900_0, 0; +T_2.10 ; +T_2.6 ; T_2.1 ; %jmp T_2; .thread T_2; - .scope S_0x8d31fc780; + .scope S_0x84ae7e100; T_3 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2cf2e40_0; + %wait E_0x84ae463c0; + %load/vec4 v0x84b1552c0_0; %flag_set/vec4 8; %jmp/0xz T_3.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2cf2da0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2cf2760_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b155360_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b154aa0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b1550e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b155180_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b154e60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b155040_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b154be0_0, 0; %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cf3200_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf2a80_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf2bc0_0, 0; + %assign/vec4 v0x84b154fa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154c80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154f00_0, 0; %jmp T_3.1; T_3.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf2bc0_0, 0; - %load/vec4 v0x8d2cf2ee0_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_3.4, 9; - %load/vec4 v0x8d2cf2a80_0; - %nor/r; - %and; -T_3.4; - %flag_set/vec4 8; - %jmp/0xz T_3.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2cf2da0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2cf2760_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2cf2a80_0, 0; - %jmp T_3.3; -T_3.2 ; - %load/vec4 v0x8d2cf2a80_0; - %flag_set/vec4 8; - %jmp/0xz T_3.5, 8; - %load/vec4 v0x8d2cf2da0_0; - %pad/u 32; - %cmpi/e 7, 0, 32; - %jmp/0xz T_3.7, 4; - %load/vec4 v0x8d2cf2c60_0; - %assign/vec4 v0x8d2cf2760_0, 0; - %load/vec4 v0x8d2cf2d00_0; - %cmpi/s 0, 0, 40; - %flag_or 5, 4; - %jmp/0xz T_3.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cf3200_0, 0; - %jmp T_3.10; -T_3.9 ; - %load/vec4 v0x8d2cf2d00_0; - %cmpi/s 32767, 0, 40; - %flag_or 5, 4; GT is !LE - %flag_inv 5; - %jmp/0xz T_3.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2cf3200_0, 0; - %jmp T_3.12; -T_3.11 ; - %load/vec4 v0x8d2cf2d00_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2cf3200_0, 0; -T_3.12 ; -T_3.10 ; + %assign/vec4 v0x84b155180_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf2a80_0, 0; + %assign/vec4 v0x84b154e60_0, 0; + %load/vec4 v0x84b155360_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_3.3, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b155360_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b154e60_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2cf2bc0_0, 0; - %jmp T_3.8; -T_3.7 ; - %load/vec4 v0x8d2cf2800_0; - %assign/vec4 v0x8d2cf2760_0, 0; - %load/vec4 v0x8d2cf2da0_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2cf2da0_0, 0; + %assign/vec4 v0x84b154c80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154f00_0, 0; + %jmp T_3.5; +T_3.2 ; + %load/vec4 v0x84b155220_0; + %flag_set/vec4 8; + %jmp/0xz T_3.6, 8; + %load/vec4 v0x84b154a00_0; + %assign/vec4 v0x84b154aa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154e60_0, 0; + %load/vec4 v0x84b1554a0_0; + %assign/vec4 v0x84b155040_0, 0; + %load/vec4 v0x84b154a00_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0x84b154be0_0, 0; + %load/vec4 v0x84b154a00_0; + %parti/s 1, 0, 2; + %cmpi/e 0, 0, 1; + %jmp/0xz T_3.8, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b154c80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154f00_0, 0; + %pushi/vec4 0, 0, 8; + %load/vec4 v0x84b155400_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x84b154fa0_0, 0; + %jmp T_3.9; T_3.8 ; -T_3.5 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b154c80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b154f00_0, 0; + %load/vec4 v0x84b155400_0; + %concati/vec4 0, 0, 8; + %assign/vec4 v0x84b154fa0_0, 0; +T_3.9 ; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x84b155360_0, 0; +T_3.6 ; + %jmp T_3.5; T_3.3 ; + %load/vec4 v0x84b154dc0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.10, 8; + %load/vec4 v0x84b154aa0_0; + %parti/s 1, 0, 2; + %cmpi/e 0, 0, 1; + %jmp/0xz T_3.12, 4; + %load/vec4 v0x84b154d20_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b1550e0_0, 0; + %jmp T_3.13; +T_3.12 ; + %load/vec4 v0x84b154d20_0; + %parti/s 8, 8, 5; + %assign/vec4 v0x84b1550e0_0, 0; +T_3.13 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b155180_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b155360_0, 0; +T_3.10 ; + %jmp T_3.5; +T_3.5 ; + %pop/vec4 1; T_3.1 ; %jmp T_3; .thread T_3; - .scope S_0x8d31fd800; + .scope S_0x84ae7e280; T_4 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2cfc320_0; + %wait E_0x84ae463c0; + %load/vec4 v0x84b15d9a0_0; %flag_set/vec4 8; %jmp/0xz T_4.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2cfc280_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2cf7c00_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cfc6e0_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b15d900_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b15d400_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b15dd60_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf7f20_0, 0; + %assign/vec4 v0x84b15d680_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cfc0a0_0, 0; + %assign/vec4 v0x84b15d7c0_0, 0; %jmp T_4.1; T_4.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cfc0a0_0, 0; - %load/vec4 v0x8d2cfc3c0_0; + %assign/vec4 v0x84b15d7c0_0, 0; + %load/vec4 v0x84b15da40_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_4.4, 9; - %load/vec4 v0x8d2cf7f20_0; + %load/vec4 v0x84b15d680_0; %nor/r; %and; T_4.4; %flag_set/vec4 8; %jmp/0xz T_4.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2cfc280_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2cf7c00_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b15d900_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b15d400_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2cf7f20_0, 0; + %assign/vec4 v0x84b15d680_0, 0; %jmp T_4.3; T_4.2 ; - %load/vec4 v0x8d2cf7f20_0; + %load/vec4 v0x84b15d680_0; %flag_set/vec4 8; %jmp/0xz T_4.5, 8; - %load/vec4 v0x8d2cfc280_0; + %load/vec4 v0x84b15d900_0; %pad/u 32; - %cmpi/e 7, 0, 32; + %cmpi/e 3, 0, 32; %jmp/0xz T_4.7, 4; - %load/vec4 v0x8d2cfc140_0; - %assign/vec4 v0x8d2cf7c00_0, 0; - %load/vec4 v0x8d2cfc1e0_0; - %cmpi/s 0, 0, 40; + %load/vec4 v0x84b15d860_0; + %assign/vec4 v0x84b15d400_0, 0; + %load/vec4 v0x84b15d860_0; + %cmpi/s 0, 0, 32; %flag_or 5, 4; %jmp/0xz T_4.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2cfc6e0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b15dd60_0, 0; %jmp T_4.10; T_4.9 ; - %load/vec4 v0x8d2cfc1e0_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0x84b15d860_0; + %cmpi/s 127, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_4.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2cfc6e0_0, 0; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b15dd60_0, 0; %jmp T_4.12; T_4.11 ; - %load/vec4 v0x8d2cfc1e0_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2cfc6e0_0, 0; + %load/vec4 v0x84b15d860_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b15dd60_0, 0; T_4.12 ; T_4.10 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2cf7f20_0, 0; + %assign/vec4 v0x84b15d680_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2cfc0a0_0, 0; + %assign/vec4 v0x84b15d7c0_0, 0; %jmp T_4.8; T_4.7 ; - %load/vec4 v0x8d2cf7ca0_0; - %assign/vec4 v0x8d2cf7c00_0, 0; - %load/vec4 v0x8d2cfc280_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2cfc280_0, 0; + %load/vec4 v0x84b15d4a0_0; + %assign/vec4 v0x84b15d400_0, 0; + %load/vec4 v0x84b15d900_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b15d900_0, 0; T_4.8 ; T_4.5 ; T_4.3 ; T_4.1 ; %jmp T_4; .thread T_4; - .scope S_0x8d31fe880; + .scope S_0x102e269c0; T_5 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2d017c0_0; + %wait E_0x84ae463c0; + %load/vec4 v0x84b15f340_0; %flag_set/vec4 8; %jmp/0xz T_5.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d01720_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d010e0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d01b80_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x84b15ec60_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b15e9e0_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d01400_0, 0; + %assign/vec4 v0x84b15e760_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d01540_0, 0; + %assign/vec4 v0x84b15e8a0_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b15e800_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15f200_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b15f8e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ea80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ebc0_0, 0; %jmp T_5.1; T_5.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d01540_0, 0; - %load/vec4 v0x8d2d01860_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_5.4, 9; - %load/vec4 v0x8d2d01400_0; - %nor/r; - %and; -T_5.4; - %flag_set/vec4 8; - %jmp/0xz T_5.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d01720_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d010e0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d01400_0, 0; - %jmp T_5.3; -T_5.2 ; - %load/vec4 v0x8d2d01400_0; - %flag_set/vec4 8; - %jmp/0xz T_5.5, 8; - %load/vec4 v0x8d2d01720_0; - %pad/u 32; - %cmpi/e 7, 0, 32; - %jmp/0xz T_5.7, 4; - %load/vec4 v0x8d2d015e0_0; - %assign/vec4 v0x8d2d010e0_0, 0; - %load/vec4 v0x8d2d01680_0; - %cmpi/s 0, 0, 40; - %flag_or 5, 4; - %jmp/0xz T_5.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d01b80_0, 0; - %jmp T_5.10; -T_5.9 ; - %load/vec4 v0x8d2d01680_0; - %cmpi/s 32767, 0, 40; - %flag_or 5, 4; GT is !LE - %flag_inv 5; - %jmp/0xz T_5.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2d01b80_0, 0; - %jmp T_5.12; -T_5.11 ; - %load/vec4 v0x8d2d01680_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2d01b80_0, 0; -T_5.12 ; -T_5.10 ; + %assign/vec4 v0x84b15e760_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d01400_0, 0; + %assign/vec4 v0x84b15f200_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ebc0_0, 0; + %load/vec4 v0x84b15f480_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_5.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_5.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_5.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_5.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_5.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_5.7, 6; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ea80_0, 0; + %jmp T_5.9; +T_5.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ea80_0, 0; + %load/vec4 v0x84b15f3e0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.10, 8; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d01540_0, 0; - %jmp T_5.8; -T_5.7 ; - %load/vec4 v0x8d2d01180_0; - %assign/vec4 v0x8d2d010e0_0, 0; - %load/vec4 v0x8d2d01720_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2d01720_0, 0; -T_5.8 ; -T_5.5 ; + %assign/vec4 v0x84b15ea80_0, 0; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x84b15ec60_0, 0; + %load/vec4 v0x84b15f700_0; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15e8a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15e760_0, 0; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; +T_5.10 ; + %jmp T_5.9; T_5.3 ; + %load/vec4 v0x84b15e6c0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.12, 8; + %load/vec4 v0x84b15e620_0; + %load/vec4 v0x84b15ec60_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x84b15f840, 0, 4; + %load/vec4 v0x84b15ec60_0; + %pad/u 32; + %cmpi/e 31, 0, 32; + %jmp/0xz T_5.14, 4; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x84b15ec60_0, 0; + %load/vec4 v0x84b15f520_0; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15e8a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15e760_0, 0; + %pushi/vec4 2, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; + %jmp T_5.15; +T_5.14 ; + %load/vec4 v0x84b15ec60_0; + %addi 1, 0, 6; + %assign/vec4 v0x84b15ec60_0, 0; + %load/vec4 v0x84b15f700_0; + %load/vec4 v0x84b15ec60_0; + %pad/u 22; + %add; + %addi 1, 0, 22; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15e760_0, 0; +T_5.15 ; +T_5.12 ; + %jmp T_5.9; +T_5.4 ; + %load/vec4 v0x84b15e6c0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.16, 8; + %load/vec4 v0x84b15e620_0; + %load/vec4 v0x84b15ec60_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x84b15f660, 0, 4; + %load/vec4 v0x84b15ec60_0; + %pad/u 32; + %cmpi/e 31, 0, 32; + %jmp/0xz T_5.18, 4; + %load/vec4 v0x84b15e940_0; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15e8a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15e760_0, 0; + %pushi/vec4 3, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; + %jmp T_5.19; +T_5.18 ; + %load/vec4 v0x84b15ec60_0; + %addi 1, 0, 6; + %assign/vec4 v0x84b15ec60_0, 0; + %load/vec4 v0x84b15f520_0; + %load/vec4 v0x84b15ec60_0; + %pad/u 22; + %add; + %addi 1, 0, 22; + %assign/vec4 v0x84b15e120_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15e760_0, 0; +T_5.19 ; +T_5.16 ; + %jmp T_5.9; +T_5.5 ; + %load/vec4 v0x84b15e6c0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.20, 8; + %load/vec4 v0x84b15e620_0; + %assign/vec4 v0x84b15e9e0_0, 0; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; +T_5.20 ; + %jmp T_5.9; +T_5.6 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15f200_0, 0; + %pushi/vec4 5, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; + %jmp T_5.9; +T_5.7 ; + %load/vec4 v0x84b15f160_0; + %flag_set/vec4 8; + %jmp/0xz T_5.22, 8; + %load/vec4 v0x84b15f2a0_0; + %assign/vec4 v0x84b15f8e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15ea80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15ebc0_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x84b15f480_0, 0; +T_5.22 ; + %jmp T_5.9; +T_5.9 ; + %pop/vec4 1; T_5.1 ; %jmp T_5; .thread T_5; - .scope S_0x8d31ff900; + .scope S_0x102e24c70; T_6 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2d06c60_0; + %wait E_0x84ae46640; + %load/vec4 v0x84b160820_0; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d06bc0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d06580_0, 0; + %assign/vec4 v0x84b1608c0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b15fa20_0, 0; %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d07020_0, 0; + %assign/vec4 v0x84b160a00_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d068a0_0, 0; + %assign/vec4 v0x84b160aa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15fd40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160960_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b15ff20_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d069e0_0, 0; + %assign/vec4 v0x84b160000_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x84b160320_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x84b15fca0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; %jmp T_6.1; T_6.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d069e0_0, 0; - %load/vec4 v0x8d2d06d00_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_6.4, 9; - %load/vec4 v0x8d2d068a0_0; - %nor/r; - %and; -T_6.4; - %flag_set/vec4 8; - %jmp/0xz T_6.2, 8; + %assign/vec4 v0x84b160000_0, 0; + %load/vec4 v0x84b1608c0_0; + %dup/vec4; %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d06bc0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d06580_0, 0; + %cmp/u; + %jmp/1 T_6.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_6.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_6.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_6.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_6.6, 6; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d068a0_0, 0; - %jmp T_6.3; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15fd40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160960_0, 0; + %jmp T_6.8; T_6.2 ; - %load/vec4 v0x8d2d068a0_0; - %flag_set/vec4 8; - %jmp/0xz T_6.5, 8; - %load/vec4 v0x8d2d06bc0_0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %load/vec4 v0x84b15fb60_0; %pad/u 32; - %cmpi/e 7, 0, 32; - %jmp/0xz T_6.7, 4; - %load/vec4 v0x8d2d06a80_0; - %assign/vec4 v0x8d2d06580_0, 0; - %load/vec4 v0x8d2d06b20_0; - %cmpi/s 0, 0, 40; - %flag_or 5, 4; - %jmp/0xz T_6.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d07020_0, 0; + %cmpi/e 11999, 0, 32; + %jmp/0xz T_6.9, 4; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; %jmp T_6.10; T_6.9 ; - %load/vec4 v0x8d2d06b20_0; - %cmpi/s 32767, 0, 40; - %flag_or 5, 4; GT is !LE - %flag_inv 5; - %jmp/0xz T_6.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2d07020_0, 0; - %jmp T_6.12; -T_6.11 ; - %load/vec4 v0x8d2d06b20_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2d07020_0, 0; -T_6.12 ; + %load/vec4 v0x84b15fb60_0; + %addi 1, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; T_6.10 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d068a0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d069e0_0, 0; %jmp T_6.8; -T_6.7 ; - %load/vec4 v0x8d2d06620_0; - %assign/vec4 v0x8d2d06580_0, 0; - %load/vec4 v0x8d2d06bc0_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2d06bc0_0, 0; -T_6.8 ; -T_6.5 ; T_6.3 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %load/vec4 v0x84b1600a0_0; + %flag_set/vec4 8; + %jmp/0xz T_6.11, 8; + %load/vec4 v0x84b15fde0_0; + %assign/vec4 v0x84b15fa20_0, 0; + %load/vec4 v0x84b1601e0_0; + %assign/vec4 v0x84b160a00_0, 0; + %load/vec4 v0x84b160280_0; + %assign/vec4 v0x84b160aa0_0, 0; + %load/vec4 v0x84b15fe80_0; + %assign/vec4 v0x84b15fd40_0, 0; + %load/vec4 v0x84b160140_0; + %assign/vec4 v0x84b160960_0, 0; + %load/vec4 v0x84b15fde0_0; + %assign/vec4 v0x84b160320_0, 0; + %load/vec4 v0x84b15fe80_0; + %assign/vec4 v0x84b160500_0, 0; + %load/vec4 v0x84b160140_0; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; + %load/vec4 v0x84b160280_0; + %flag_set/vec4 8; + %jmp/0xz T_6.13, 8; + %load/vec4 v0x84b1601e0_0; + %assign/vec4 v0x84b15fca0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; + %jmp T_6.14; +T_6.13 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; +T_6.14 ; +T_6.11 ; + %jmp T_6.8; +T_6.4 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %load/vec4 v0x84b15fd40_0; + %assign/vec4 v0x84b160500_0, 0; + %load/vec4 v0x84b160960_0; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %load/vec4 v0x84b15fb60_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_6.15, 4; + %load/vec4 v0x84b160460_0; + %assign/vec4 v0x84b15ff20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160000_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; + %jmp T_6.16; +T_6.15 ; + %load/vec4 v0x84b15fb60_0; + %addi 1, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; +T_6.16 ; + %jmp T_6.8; +T_6.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %load/vec4 v0x84b15fd40_0; + %assign/vec4 v0x84b160500_0, 0; + %load/vec4 v0x84b160960_0; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %load/vec4 v0x84b15fb60_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_6.17, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; + %jmp T_6.18; +T_6.17 ; + %load/vec4 v0x84b15fb60_0; + %addi 1, 0, 14; + %assign/vec4 v0x84b15fb60_0, 0; +T_6.18 ; + %jmp T_6.8; +T_6.6 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1605a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1606e0_0, 0; + %load/vec4 v0x84b15fd40_0; + %assign/vec4 v0x84b160500_0, 0; + %load/vec4 v0x84b160960_0; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b15fc00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1603c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160640_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b160000_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x84b1608c0_0, 0; + %jmp T_6.8; +T_6.8 ; + %pop/vec4 1; T_6.1 ; %jmp T_6; .thread T_6; - .scope S_0x8d3208a80; + .scope S_0x84ae85e00; T_7 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2d0c140_0; + %wait E_0x84ae46680; + %load/vec4 v0x84b168fa0_0; %flag_set/vec4 8; %jmp/0xz T_7.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d0c0a0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d0ba20_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d0c500_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b168f00_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b168a00_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b169360_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d0bd40_0, 0; + %assign/vec4 v0x84b168c80_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d0be80_0, 0; + %assign/vec4 v0x84b168dc0_0, 0; %jmp T_7.1; T_7.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d0be80_0, 0; - %load/vec4 v0x8d2d0c1e0_0; + %assign/vec4 v0x84b168dc0_0, 0; + %load/vec4 v0x84b169040_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_7.4, 9; - %load/vec4 v0x8d2d0bd40_0; + %load/vec4 v0x84b168c80_0; %nor/r; %and; T_7.4; %flag_set/vec4 8; %jmp/0xz T_7.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d0c0a0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d0ba20_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b168f00_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b168a00_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d0bd40_0, 0; + %assign/vec4 v0x84b168c80_0, 0; %jmp T_7.3; T_7.2 ; - %load/vec4 v0x8d2d0bd40_0; + %load/vec4 v0x84b168c80_0; %flag_set/vec4 8; %jmp/0xz T_7.5, 8; - %load/vec4 v0x8d2d0c0a0_0; + %load/vec4 v0x84b168f00_0; %pad/u 32; - %cmpi/e 7, 0, 32; + %cmpi/e 3, 0, 32; %jmp/0xz T_7.7, 4; - %load/vec4 v0x8d2d0bf20_0; - %assign/vec4 v0x8d2d0ba20_0, 0; - %load/vec4 v0x8d2d0c000_0; - %cmpi/s 0, 0, 40; + %load/vec4 v0x84b168e60_0; + %assign/vec4 v0x84b168a00_0, 0; + %load/vec4 v0x84b168e60_0; + %cmpi/s 0, 0, 32; %flag_or 5, 4; %jmp/0xz T_7.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d0c500_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b169360_0, 0; %jmp T_7.10; T_7.9 ; - %load/vec4 v0x8d2d0c000_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0x84b168e60_0; + %cmpi/s 127, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_7.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2d0c500_0, 0; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b169360_0, 0; %jmp T_7.12; T_7.11 ; - %load/vec4 v0x8d2d0c000_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2d0c500_0, 0; + %load/vec4 v0x84b168e60_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b169360_0, 0; T_7.12 ; T_7.10 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d0bd40_0, 0; + %assign/vec4 v0x84b168c80_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d0be80_0, 0; + %assign/vec4 v0x84b168dc0_0, 0; %jmp T_7.8; T_7.7 ; - %load/vec4 v0x8d2d0bac0_0; - %assign/vec4 v0x8d2d0ba20_0, 0; - %load/vec4 v0x8d2d0c0a0_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2d0c0a0_0, 0; + %load/vec4 v0x84b168aa0_0; + %assign/vec4 v0x84b168a00_0, 0; + %load/vec4 v0x84b168f00_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b168f00_0, 0; T_7.8 ; T_7.5 ; T_7.3 ; T_7.1 ; %jmp T_7; .thread T_7; - .scope S_0x8d3209b00; + .scope S_0x84ae89800; T_8 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2d115e0_0; + %wait E_0x84ae46680; + %load/vec4 v0x84b16d860_0; %flag_set/vec4 8; %jmp/0xz T_8.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d11540_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d10f00_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d119a0_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b16d7c0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b16d2c0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b16dc20_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d11220_0, 0; + %assign/vec4 v0x84b16d540_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d11360_0, 0; + %assign/vec4 v0x84b16d680_0, 0; %jmp T_8.1; T_8.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d11360_0, 0; - %load/vec4 v0x8d2d11680_0; + %assign/vec4 v0x84b16d680_0, 0; + %load/vec4 v0x84b16d900_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_8.4, 9; - %load/vec4 v0x8d2d11220_0; + %load/vec4 v0x84b16d540_0; %nor/r; %and; T_8.4; %flag_set/vec4 8; %jmp/0xz T_8.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d11540_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d10f00_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b16d7c0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b16d2c0_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d11220_0, 0; + %assign/vec4 v0x84b16d540_0, 0; %jmp T_8.3; T_8.2 ; - %load/vec4 v0x8d2d11220_0; + %load/vec4 v0x84b16d540_0; %flag_set/vec4 8; %jmp/0xz T_8.5, 8; - %load/vec4 v0x8d2d11540_0; + %load/vec4 v0x84b16d7c0_0; %pad/u 32; - %cmpi/e 7, 0, 32; + %cmpi/e 3, 0, 32; %jmp/0xz T_8.7, 4; - %load/vec4 v0x8d2d11400_0; - %assign/vec4 v0x8d2d10f00_0, 0; - %load/vec4 v0x8d2d114a0_0; - %cmpi/s 0, 0, 40; + %load/vec4 v0x84b16d720_0; + %assign/vec4 v0x84b16d2c0_0, 0; + %load/vec4 v0x84b16d720_0; + %cmpi/s 0, 0, 32; %flag_or 5, 4; %jmp/0xz T_8.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d119a0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b16dc20_0, 0; %jmp T_8.10; T_8.9 ; - %load/vec4 v0x8d2d114a0_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0x84b16d720_0; + %cmpi/s 127, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_8.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2d119a0_0, 0; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b16dc20_0, 0; %jmp T_8.12; T_8.11 ; - %load/vec4 v0x8d2d114a0_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2d119a0_0, 0; + %load/vec4 v0x84b16d720_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b16dc20_0, 0; T_8.12 ; T_8.10 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d11220_0, 0; + %assign/vec4 v0x84b16d540_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d11360_0, 0; + %assign/vec4 v0x84b16d680_0, 0; %jmp T_8.8; T_8.7 ; - %load/vec4 v0x8d2d10fa0_0; - %assign/vec4 v0x8d2d10f00_0, 0; - %load/vec4 v0x8d2d11540_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2d11540_0, 0; + %load/vec4 v0x84b16d360_0; + %assign/vec4 v0x84b16d2c0_0, 0; + %load/vec4 v0x84b16d7c0_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b16d7c0_0, 0; T_8.8 ; T_8.5 ; T_8.3 ; T_8.1 ; %jmp T_8; .thread T_8; - .scope S_0x8d320ab80; + .scope S_0x84ae95200; T_9 ; - %wait E_0x8d2ce4340; - %load/vec4 v0x8d2d16a80_0; + %wait E_0x84ae46680; + %load/vec4 v0x84b172120_0; %flag_set/vec4 8; %jmp/0xz T_9.0, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d169e0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d163a0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d16e40_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b172080_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b171b80_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b1724e0_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d166c0_0, 0; + %assign/vec4 v0x84b171e00_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d16800_0, 0; + %assign/vec4 v0x84b171f40_0, 0; %jmp T_9.1; T_9.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d16800_0, 0; - %load/vec4 v0x8d2d16b20_0; + %assign/vec4 v0x84b171f40_0, 0; + %load/vec4 v0x84b1721c0_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_9.4, 9; - %load/vec4 v0x8d2d166c0_0; + %load/vec4 v0x84b171e00_0; %nor/r; %and; T_9.4; %flag_set/vec4 8; %jmp/0xz T_9.2, 8; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x8d2d169e0_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x8d2d163a0_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b172080_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b171b80_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d166c0_0, 0; + %assign/vec4 v0x84b171e00_0, 0; %jmp T_9.3; T_9.2 ; - %load/vec4 v0x8d2d166c0_0; + %load/vec4 v0x84b171e00_0; %flag_set/vec4 8; %jmp/0xz T_9.5, 8; - %load/vec4 v0x8d2d169e0_0; + %load/vec4 v0x84b172080_0; %pad/u 32; - %cmpi/e 7, 0, 32; + %cmpi/e 3, 0, 32; %jmp/0xz T_9.7, 4; - %load/vec4 v0x8d2d168a0_0; - %assign/vec4 v0x8d2d163a0_0, 0; - %load/vec4 v0x8d2d16940_0; - %cmpi/s 0, 0, 40; + %load/vec4 v0x84b171fe0_0; + %assign/vec4 v0x84b171b80_0, 0; + %load/vec4 v0x84b171fe0_0; + %cmpi/s 0, 0, 32; %flag_or 5, 4; %jmp/0xz T_9.9, 5; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x8d2d16e40_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b1724e0_0, 0; %jmp T_9.10; T_9.9 ; - %load/vec4 v0x8d2d16940_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0x84b171fe0_0; + %cmpi/s 127, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_9.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x8d2d16e40_0, 0; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b1724e0_0, 0; %jmp T_9.12; T_9.11 ; - %load/vec4 v0x8d2d16940_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x8d2d16e40_0, 0; + %load/vec4 v0x84b171fe0_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b1724e0_0, 0; T_9.12 ; T_9.10 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x8d2d166c0_0, 0; + %assign/vec4 v0x84b171e00_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x8d2d16800_0, 0; + %assign/vec4 v0x84b171f40_0, 0; %jmp T_9.8; T_9.7 ; - %load/vec4 v0x8d2d16440_0; - %assign/vec4 v0x8d2d163a0_0, 0; - %load/vec4 v0x8d2d169e0_0; - %addi 1, 0, 3; - %assign/vec4 v0x8d2d169e0_0, 0; + %load/vec4 v0x84b171c20_0; + %assign/vec4 v0x84b171b80_0, 0; + %load/vec4 v0x84b172080_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b172080_0, 0; T_9.8 ; T_9.5 ; T_9.3 ; T_9.1 ; %jmp T_9; .thread T_9; - .scope S_0x102e63dc0; + .scope S_0x84ae9cc00; T_10 ; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x8d2d17840_0, 0, 1; -T_10.0 ; - %delay 5, 0; - %load/vec4 v0x8d2d17840_0; - %inv; - %store/vec4 v0x8d2d17840_0, 0, 1; - %jmp T_10.0; -T_10.1 ; - %end; - .thread T_10; - .scope S_0x102e63dc0; -T_11 ; - %vpi_call/w 3 79 "$dumpfile", "sim/layer.vcd" {0 0 0}; - %vpi_call/w 3 80 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x102e63dc0 {0 0 0}; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x8d2d17ac0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x8d2d17b60_0, 0, 1; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x8d2d17ca0_0, 0, 1024; - %pushi/vec4 0, 0, 8192; - %store/vec4 v0x8d2d17c00_0, 0, 8192; - %pushi/vec4 0, 0, 128; - %store/vec4 v0x8d2d17700_0, 0, 128; + %wait E_0x84ae46680; + %load/vec4 v0x84b1769e0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b176940_0, 0; %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; - %pushi/vec4 2, 0, 32; -T_11.0 %dup/vec4; + %assign/vec4 v0x84b176440_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b176da0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1766c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b176800_0, 0; + %jmp T_10.1; +T_10.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b176800_0, 0; + %load/vec4 v0x84b176a80_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.4, 9; + %load/vec4 v0x84b1766c0_0; + %nor/r; + %and; +T_10.4; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b176940_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b176440_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b1766c0_0, 0; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0x84b1766c0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.5, 8; + %load/vec4 v0x84b176940_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_10.7, 4; + %load/vec4 v0x84b1768a0_0; + %assign/vec4 v0x84b176440_0, 0; + %load/vec4 v0x84b1768a0_0; %cmpi/s 0, 0, 32; - %jmp/1xz T_11.1, 5; - %jmp/1 T_11.1, 4; - %subi 1, 0, 32; - %wait E_0x8d2ce4340; - %jmp T_11.0; + %flag_or 5, 4; + %jmp/0xz T_10.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b176da0_0, 0; + %jmp T_10.10; +T_10.9 ; + %load/vec4 v0x84b1768a0_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_10.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b176da0_0, 0; + %jmp T_10.12; +T_10.11 ; + %load/vec4 v0x84b1768a0_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b176da0_0, 0; +T_10.12 ; +T_10.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b1766c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b176800_0, 0; + %jmp T_10.8; +T_10.7 ; + %load/vec4 v0x84b1764e0_0; + %assign/vec4 v0x84b176440_0, 0; + %load/vec4 v0x84b176940_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b176940_0, 0; +T_10.8 ; +T_10.5 ; +T_10.3 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_0x84aea0600; +T_11 ; + %wait E_0x84ae46680; + %load/vec4 v0x84b17f2a0_0; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b17f200_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b17ed00_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b17f660_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b17ef80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b17f0c0_0, 0; + %jmp T_11.1; +T_11.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b17f0c0_0, 0; + %load/vec4 v0x84b17f340_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_11.4, 9; + %load/vec4 v0x84b17ef80_0; + %nor/r; + %and; +T_11.4; + %flag_set/vec4 8; + %jmp/0xz T_11.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b17f200_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b17ed00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b17ef80_0, 0; + %jmp T_11.3; +T_11.2 ; + %load/vec4 v0x84b17ef80_0; + %flag_set/vec4 8; + %jmp/0xz T_11.5, 8; + %load/vec4 v0x84b17f200_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_11.7, 4; + %load/vec4 v0x84b17f160_0; + %assign/vec4 v0x84b17ed00_0, 0; + %load/vec4 v0x84b17f160_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_11.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b17f660_0, 0; + %jmp T_11.10; +T_11.9 ; + %load/vec4 v0x84b17f160_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_11.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b17f660_0, 0; + %jmp T_11.12; +T_11.11 ; + %load/vec4 v0x84b17f160_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b17f660_0, 0; +T_11.12 ; +T_11.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b17ef80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b17f0c0_0, 0; + %jmp T_11.8; +T_11.7 ; + %load/vec4 v0x84b17eda0_0; + %assign/vec4 v0x84b17ed00_0, 0; + %load/vec4 v0x84b17f200_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b17f200_0, 0; +T_11.8 ; +T_11.5 ; +T_11.3 ; T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0x84aea4000; +T_12 ; + %wait E_0x84ae46680; + %load/vec4 v0x84b183b60_0; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b183ac0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b1835c0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b183f20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b183840_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b183980_0, 0; + %jmp T_12.1; +T_12.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b183980_0, 0; + %load/vec4 v0x84b183c00_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_12.4, 9; + %load/vec4 v0x84b183840_0; + %nor/r; + %and; +T_12.4; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b183ac0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b1835c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b183840_0, 0; + %jmp T_12.3; +T_12.2 ; + %load/vec4 v0x84b183840_0; + %flag_set/vec4 8; + %jmp/0xz T_12.5, 8; + %load/vec4 v0x84b183ac0_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_12.7, 4; + %load/vec4 v0x84b183a20_0; + %assign/vec4 v0x84b1835c0_0, 0; + %load/vec4 v0x84b183a20_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_12.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b183f20_0, 0; + %jmp T_12.10; +T_12.9 ; + %load/vec4 v0x84b183a20_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_12.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b183f20_0, 0; + %jmp T_12.12; +T_12.11 ; + %load/vec4 v0x84b183a20_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b183f20_0, 0; +T_12.12 ; +T_12.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b183840_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b183980_0, 0; + %jmp T_12.8; +T_12.7 ; + %load/vec4 v0x84b183660_0; + %assign/vec4 v0x84b1835c0_0, 0; + %load/vec4 v0x84b183ac0_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b183ac0_0, 0; +T_12.8 ; +T_12.5 ; +T_12.3 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x84aea7900; +T_13 ; + %wait E_0x84ae46680; + %load/vec4 v0x84b18c460_0; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b18c3c0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b187e80_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b18c820_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b18c140_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b18c280_0, 0; + %jmp T_13.1; +T_13.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b18c280_0, 0; + %load/vec4 v0x84b18c500_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_13.4, 9; + %load/vec4 v0x84b18c140_0; + %nor/r; + %and; +T_13.4; + %flag_set/vec4 8; + %jmp/0xz T_13.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b18c3c0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b187e80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b18c140_0, 0; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x84b18c140_0; + %flag_set/vec4 8; + %jmp/0xz T_13.5, 8; + %load/vec4 v0x84b18c3c0_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_13.7, 4; + %load/vec4 v0x84b18c320_0; + %assign/vec4 v0x84b187e80_0, 0; + %load/vec4 v0x84b18c320_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_13.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b18c820_0, 0; + %jmp T_13.10; +T_13.9 ; + %load/vec4 v0x84b18c320_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_13.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b18c820_0, 0; + %jmp T_13.12; +T_13.11 ; + %load/vec4 v0x84b18c320_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b18c820_0, 0; +T_13.12 ; +T_13.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b18c140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b18c280_0, 0; + %jmp T_13.8; +T_13.7 ; + %load/vec4 v0x84b187f20_0; + %assign/vec4 v0x84b187e80_0, 0; + %load/vec4 v0x84b18c3c0_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b18c3c0_0, 0; +T_13.8 ; +T_13.5 ; +T_13.3 ; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x84aeb3300; +T_14 ; + %wait E_0x84ae46680; + %load/vec4 v0x84b190d20_0; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b190c80_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b190780_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b1910e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b190a00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b190b40_0, 0; + %jmp T_14.1; +T_14.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b190b40_0, 0; + %load/vec4 v0x84b190dc0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_14.4, 9; + %load/vec4 v0x84b190a00_0; + %nor/r; + %and; +T_14.4; + %flag_set/vec4 8; + %jmp/0xz T_14.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x84b190c80_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x84b190780_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b190a00_0, 0; + %jmp T_14.3; +T_14.2 ; + %load/vec4 v0x84b190a00_0; + %flag_set/vec4 8; + %jmp/0xz T_14.5, 8; + %load/vec4 v0x84b190c80_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_14.7, 4; + %load/vec4 v0x84b190be0_0; + %assign/vec4 v0x84b190780_0, 0; + %load/vec4 v0x84b190be0_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_14.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x84b1910e0_0, 0; + %jmp T_14.10; +T_14.9 ; + %load/vec4 v0x84b190be0_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_14.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0x84b1910e0_0, 0; + %jmp T_14.12; +T_14.11 ; + %load/vec4 v0x84b190be0_0; + %parti/s 8, 0, 2; + %assign/vec4 v0x84b1910e0_0, 0; +T_14.12 ; +T_14.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x84b190a00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x84b190b40_0, 0; + %jmp T_14.8; +T_14.7 ; + %load/vec4 v0x84b190820_0; + %assign/vec4 v0x84b190780_0, 0; + %load/vec4 v0x84b190c80_0; + %addi 1, 0, 2; + %assign/vec4 v0x84b190c80_0, 0; +T_14.8 ; +T_14.5 ; +T_14.3 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x102e24df0; +T_15 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x84b1919a0_0, 0, 1; +T_15.0 ; + %delay 5000, 0; + %load/vec4 v0x84b1919a0_0; + %inv; + %store/vec4 v0x84b1919a0_0, 0, 1; + %jmp T_15.0; +T_15.1 ; + %end; + .thread T_15; + .scope S_0x102e24df0; +T_16 ; + %vpi_call/w 11 71 "$dumpfile", "sim/layer.vcd" {0 0 0}; + %vpi_call/w 11 72 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x102e24df0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x84b191c20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x84b191cc0_0, 0, 1; + %pushi/vec4 0, 0, 256; + %store/vec4 v0x84b191e00_0, 0, 256; + %pushi/vec4 0, 0, 2048; + %store/vec4 v0x84b191d60_0, 0, 2048; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x84b191860_0, 0, 64; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x84b191ae0_0, 0, 32; + %pushi/vec4 2, 0, 32; +T_16.0 %dup/vec4; + %cmpi/s 0, 0, 32; + %jmp/1xz T_16.1, 5; + %jmp/1 T_16.1, 4; + %subi 1, 0, 32; + %wait E_0x84ae46680; + %jmp T_16.0; +T_16.1 ; %pop/vec4 1; %pushi/vec4 0, 0, 1; - %store/vec4 v0x8d2d17ac0_0, 0, 1; + %store/vec4 v0x84b191c20_0, 0, 1; %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.2 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.3, 5; - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.2 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.3, 5; + %pushi/vec4 1, 0, 8; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x8d2d17ca0_0, 4, 16; -T_11.4 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191e00_0, 4, 8; +T_16.4 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.2; -T_11.3 ; for-loop exit label + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.2; +T_16.3 ; for-loop exit label %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.5 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.6, 5; - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.5 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.6, 5; + %pushi/vec4 1, 0, 8; %pushi/vec4 0, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.7 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.7 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.5; -T_11.6 ; for-loop exit label - %pushi/real 0, 4065; load=0.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.5; +T_16.6 ; for-loop exit label + %pushi/vec4 0, 0, 8; %ix/load 4, 0, 0; %flag_set/imm 4, 0; - %store/vec4 v0x8d2d17700_0, 4, 16; + %store/vec4 v0x84b191860_0, 4, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.8 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.9, 5; - %pushi/real 1073741824, 4065; load=0.500000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %pushi/vec4 1024, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.8 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.9, 5; + %pushi/vec4 3, 0, 8; + %pushi/vec4 256, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.10 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.10 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.8; -T_11.9 ; for-loop exit label + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.8; +T_16.9 ; for-loop exit label %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.11 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.12, 5; - %pushi/real 1073741824, 20449; load=-0.500000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %pushi/vec4 2048, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.11 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.12, 5; + %pushi/vec4 255, 0, 8; + %pushi/vec4 512, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.13 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.13 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.11; -T_11.12 ; for-loop exit label + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.11; +T_16.12 ; for-loop exit label %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.14 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.15, 5; - %pushi/real 1073741824, 4067; load=2.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %pushi/vec4 3072, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.14 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.15, 5; + %pushi/vec4 8, 0, 8; + %pushi/vec4 768, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.16 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.16 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.14; -T_11.15 ; for-loop exit label - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %ix/load 4, 64, 0; + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.14; +T_16.15 ; for-loop exit label + %pushi/vec4 5, 0, 8; + %ix/load 4, 32, 0; %flag_set/imm 4, 0; - %store/vec4 v0x8d2d17700_0, 4, 16; - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %ix/load 4, 80, 0; + %store/vec4 v0x84b191860_0, 4, 8; + %pushi/vec4 251, 0, 8; + %ix/load 4, 40, 0; %flag_set/imm 4, 0; - %store/vec4 v0x8d2d17700_0, 4, 16; + %store/vec4 v0x84b191860_0, 4, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.17 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.18, 5; - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %pushi/vec4 6144, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.17 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.18, 5; + %pushi/vec4 1, 0, 8; + %pushi/vec4 1536, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.19 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.19 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.17; -T_11.18 ; for-loop exit label - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %ix/load 4, 96, 0; + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.17; +T_16.18 ; for-loop exit label + %pushi/vec4 246, 0, 8; + %ix/load 4, 48, 0; %flag_set/imm 4, 0; - %store/vec4 v0x8d2d17700_0, 4, 16; + %store/vec4 v0x84b191860_0, 4, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; -T_11.20 ; Top of for-loop - %load/vec4 v0x8d2d17a20_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_11.21, 5; - %pushi/real 1073741824, 4064; load=0.250000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %pushi/vec4 7168, 0, 32; - %load/vec4 v0x8d2d17a20_0; - %muli 16, 0, 32; + %store/vec4 v0x84b191b80_0, 0, 32; +T_16.20 ; Top of for-loop + %load/vec4 v0x84b191b80_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_16.21, 5; + %load/vec4 v0x84b191b80_0; + %cmpi/s 16, 0, 32; + %flag_mov 8, 5; + %jmp/0 T_16.23, 8; + %pushi/vec4 1, 0, 8; + %jmp/1 T_16.24, 8; +T_16.23 ; End of true expr. + %pushi/vec4 0, 0, 8; + %jmp/0 T_16.24, 8; + ; End of false expr. + %blend; +T_16.24; + %pushi/vec4 1792, 0, 32; + %load/vec4 v0x84b191b80_0; + %muli 8, 0, 32; %add; %ix/vec4/s 4; - %store/vec4 v0x8d2d17c00_0, 4, 16; -T_11.22 ; for-loop step statement - %load/vec4 v0x8d2d17a20_0; + %store/vec4 v0x84b191d60_0, 4, 8; +T_16.22 ; for-loop step statement + %load/vec4 v0x84b191b80_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17a20_0, 0, 32; - %jmp T_11.20; -T_11.21 ; for-loop exit label - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x8d2d17660_0; - %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; - %ix/load 4, 112, 0; + %store/vec4 v0x84b191b80_0, 0, 32; + %jmp T_16.20; +T_16.21 ; for-loop exit label + %pushi/vec4 5, 0, 8; + %ix/load 4, 56, 0; %flag_set/imm 4, 0; - %store/vec4 v0x8d2d17700_0, 4, 16; - %vpi_call/w 3 197 "$display", "\000" {0 0 0}; - %vpi_call/w 3 198 "$display", "==============================" {0 0 0}; - %vpi_call/w 3 199 "$display", "LAYER TEST" {0 0 0}; - %vpi_call/w 3 200 "$display", "==============================" {0 0 0}; - %fork TD_tb.run_layer, S_0x8d320bc00; + %store/vec4 v0x84b191860_0, 4, 8; + %vpi_call/w 11 192 "$display", "\000" {0 0 0}; + %vpi_call/w 11 193 "$display", "==============================" {0 0 0}; + %vpi_call/w 11 194 "$display", "LAYER TEST (INT8)" {0 0 0}; + %vpi_call/w 11 195 "$display", "==============================" {0 0 0}; + %fork TD_tb.run_layer, S_0x84aebab80; %join; - %vpi_call/w 3 204 "$display", "Neuron 0 = %5d expected = 16384", &PV {0 0 0}; - %vpi_call/w 3 205 "$display", "Neuron 1 = %5d expected = 8192", &PV {0 0 0}; - %vpi_call/w 3 206 "$display", "Neuron 2 = %5d expected = 0", &PV {0 0 0}; - %vpi_call/w 3 207 "$display", "Neuron 3 = %5d expected = 32767", &PV {0 0 0}; - %vpi_call/w 3 208 "$display", "Neuron 4 = %5d expected = 256", &PV {0 0 0}; - %vpi_call/w 3 209 "$display", "Neuron 5 = %5d expected = 0", &PV {0 0 0}; - %vpi_call/w 3 210 "$display", "Neuron 6 = %5d expected = 16128", &PV {0 0 0}; - %vpi_call/w 3 211 "$display", "Neuron 7 = %5d expected = 4352", &PV {0 0 0}; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 0, 2; - %cmpi/ne 16384, 0, 16; - %jmp/0xz T_11.23, 6; - %load/vec4 v0x8d2d17980_0; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 0, 2; + %vpi_call/w 11 199 "$display", "Neuron 0 = %5d expected = 32", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 8, 5; + %vpi_call/w 11 200 "$display", "Neuron 1 = %5d expected = 96", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 16, 6; + %vpi_call/w 11 201 "$display", "Neuron 2 = %5d expected = 0", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 24, 6; + %vpi_call/w 11 202 "$display", "Neuron 3 = %5d expected = 127", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 32, 7; + %vpi_call/w 11 203 "$display", "Neuron 4 = %5d expected = 5", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 40, 7; + %vpi_call/w 11 204 "$display", "Neuron 5 = %5d expected = 0", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 48, 7; + %vpi_call/w 11 205 "$display", "Neuron 6 = %5d expected = 22", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 56, 7; + %vpi_call/w 11 206 "$display", "Neuron 7 = %5d expected = 21", S<0,vec4,s8> {1 0 0}; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 0, 2; + %cmpi/ne 32, 0, 8; + %jmp/0xz T_16.25, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.23 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 16, 6; - %cmpi/ne 8192, 0, 16; - %jmp/0xz T_11.25, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.25 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 8, 5; + %cmpi/ne 96, 0, 8; + %jmp/0xz T_16.27, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.25 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 32, 7; - %cmpi/ne 0, 0, 16; - %jmp/0xz T_11.27, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.27 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 16, 6; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_16.29, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.27 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 48, 7; - %cmpi/ne 32767, 0, 16; - %jmp/0xz T_11.29, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.29 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 24, 6; + %cmpi/ne 127, 0, 8; + %jmp/0xz T_16.31, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.29 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 64, 8; - %cmpi/ne 256, 0, 16; - %jmp/0xz T_11.31, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.31 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 32, 7; + %cmpi/ne 5, 0, 8; + %jmp/0xz T_16.33, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.31 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 80, 8; - %cmpi/ne 0, 0, 16; - %jmp/0xz T_11.33, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.33 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 40, 7; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_16.35, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.33 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 96, 8; - %cmpi/ne 16128, 0, 16; - %jmp/0xz T_11.35, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.35 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 48, 7; + %cmpi/ne 22, 0, 8; + %jmp/0xz T_16.37, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.35 ; - %load/vec4 v0x8d2d17d40_0; - %parti/s 16, 112, 8; - %cmpi/ne 4352, 0, 16; - %jmp/0xz T_11.37, 6; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.37 ; + %load/vec4 v0x84b191ea0_0; + %parti/s 8, 56, 7; + %cmpi/ne 21, 0, 8; + %jmp/0xz T_16.39, 6; + %load/vec4 v0x84b191ae0_0; %addi 1, 0, 32; - %store/vec4 v0x8d2d17980_0, 0, 32; -T_11.37 ; - %vpi_call/w 3 222 "$display", "busy = %0d", v0x8d2d177a0_0 {0 0 0}; - %vpi_call/w 3 223 "$display", "done = %0d", v0x8d2d178e0_0 {0 0 0}; - %vpi_call/w 3 225 "$display", "\000" {0 0 0}; - %vpi_call/w 3 226 "$display", "==============================" {0 0 0}; - %load/vec4 v0x8d2d17980_0; + %store/vec4 v0x84b191ae0_0, 0, 32; +T_16.39 ; + %vpi_call/w 11 217 "$display", "busy = %0d", v0x84b191900_0 {0 0 0}; + %vpi_call/w 11 218 "$display", "done = %0d", v0x84b191a40_0 {0 0 0}; + %vpi_call/w 11 220 "$display", "\000" {0 0 0}; + %vpi_call/w 11 221 "$display", "==============================" {0 0 0}; + %load/vec4 v0x84b191ae0_0; %cmpi/e 0, 0, 32; - %jmp/0xz T_11.39, 4; - %vpi_call/w 3 229 "$display", "PASS - ALL 8 NEURONS" {0 0 0}; - %jmp T_11.40; -T_11.39 ; - %vpi_call/w 3 231 "$display", "FAIL - %0d ERRORS", v0x8d2d17980_0 {0 0 0}; -T_11.40 ; - %vpi_call/w 3 233 "$display", "==============================" {0 0 0}; - %vpi_call/w 3 234 "$display", "LAYER TEST FINISHED" {0 0 0}; - %vpi_call/w 3 235 "$display", "\000" {0 0 0}; - %vpi_call/w 3 237 "$finish" {0 0 0}; + %jmp/0xz T_16.41, 4; + %vpi_call/w 11 224 "$display", "PASS - ALL 8 NEURONS" {0 0 0}; + %jmp T_16.42; +T_16.41 ; + %vpi_call/w 11 226 "$display", "FAIL - %0d ERRORS", v0x84b191ae0_0 {0 0 0}; +T_16.42 ; + %vpi_call/w 11 228 "$display", "==============================" {0 0 0}; + %vpi_call/w 11 229 "$display", "LAYER TEST FINISHED" {0 0 0}; + %vpi_call/w 11 230 "$display", "\000" {0 0 0}; + %vpi_call/w 11 232 "$finish" {0 0 0}; %end; - .thread T_11; + .thread T_16; # The file index is used to find the file name in the following table. -:file_names 8; +:file_names 13; "N/A"; ""; "-"; - "sim/layer_tb.v"; - "rtl/layer.v"; + "rtl/memory_interface.v"; + "rtl/memory_model.v"; + "rtl/neuron_memory.v"; + "rtl/int8_memory_access.v"; "rtl/neuron_parallel.v"; "rtl/mac8.v"; "rtl/mac_unit.v"; + "rtl/psram_controller.v"; + "sim/layer_tb.v"; + "rtl/layer.v"; diff --git a/sim/layer_tb.v b/sim/layer_tb.v index 9d33ad7..1c7ddfa 100644 --- a/sim/layer_tb.v +++ b/sim/layer_tb.v @@ -1,11 +1,12 @@ +`timescale 1ns/1ps + module tb; - parameter DATA_WIDTH = 16; - parameter FRAC_BITS = 8; - parameter N_INPUTS = 64; + parameter DATA_WIDTH = 8; + parameter N_INPUTS = 32; parameter N_NEURONS = 8; parameter PARALLEL = 8; - parameter ACC_WIDTH = 40; + parameter ACC_WIDTH = 32; reg clk; reg rst; @@ -26,12 +27,10 @@ module tb; wire done; integer i; - integer n; integer errors; layer #( .DATA_WIDTH(DATA_WIDTH), - .FRAC_BITS(FRAC_BITS), .N_INPUTS(N_INPUTS), .N_NEURONS(N_NEURONS), .PARALLEL(PARALLEL), @@ -53,13 +52,6 @@ module tb; forever #5 clk = ~clk; end - function signed [15:0] q8_8; - input real value; - begin - q8_8 = $rtoi(value * 256.0); - end - endfunction - task run_layer; begin @(posedge clk); @@ -92,41 +84,41 @@ module tb; /* * Input vector: - * all inputs = 1.0 + * all inputs = 1 */ for (i = 0; i < N_INPUTS; i = i + 1) - x_bus[i*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; /* * Neuron 0: - * weights = 1.0 + * weights = 1 * bias = 0 - * result = 64 + * result = 32 */ for (i = 0; i < N_INPUTS; i = i + 1) weights_bus[ 0*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(1.0); + ] = 8'sd1; - bias_bus[0*DATA_WIDTH +: DATA_WIDTH] = q8_8(0.0); + bias_bus[0*DATA_WIDTH +: DATA_WIDTH] = 8'sd0; /* * Neuron 1: - * weights = 0.5 - * result = 32 + * weights = 3 + * result = 96 */ for (i = 0; i < N_INPUTS; i = i + 1) weights_bus[ 1*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(0.5); + ] = 8'sd3; /* * Neuron 2: - * weights = -0.5 + * weights = -1 * result = -32 -> ReLU = 0 */ for (i = 0; i < N_INPUTS; i = i + 1) @@ -134,90 +126,93 @@ module tb; 2*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(-0.5); + ] = -8'sd1; /* * Neuron 3: - * weights = 2.0 - * result = 128 -> saturation = 127.996... + * weights = 8 + * result = 256 -> INT8 saturation = 127 */ for (i = 0; i < N_INPUTS; i = i + 1) weights_bus[ 3*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(2.0); + ] = 8'sd8; /* * Neuron 4: * weights = 0 - * bias = +1 - * result = 1 + * bias = +5 + * result = 5 */ - bias_bus[4*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + bias_bus[4*DATA_WIDTH +: DATA_WIDTH] = 8'sd5; /* * Neuron 5: * weights = 0 - * bias = -1 + * bias = -5 * ReLU = 0 */ - bias_bus[5*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + bias_bus[5*DATA_WIDTH +: DATA_WIDTH] = -8'sd5; /* * Neuron 6: - * weights = 1.0 - * bias = -1.0 - * result = 63 + * weights = 1 + * bias = -10 + * result = 32 - 10 = 22 */ for (i = 0; i < N_INPUTS; i = i + 1) weights_bus[ 6*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(1.0); + ] = 8'sd1; - bias_bus[6*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + bias_bus[6*DATA_WIDTH +: DATA_WIDTH] = -8'sd10; /* * Neuron 7: - * weights = 0.25 - * bias = +1 - * result = 16 + 1 = 17 + * first 16 weights = 1, remaining 16 = 0 + * bias = +5 + * result = 16 + 5 = 21 + * + * Exercises a sparse weight pattern across groups + * (PARALLEL = 8 -> GROUPS = 4). */ for (i = 0; i < N_INPUTS; i = i + 1) weights_bus[ 7*N_INPUTS*DATA_WIDTH + i*DATA_WIDTH +: DATA_WIDTH - ] = q8_8(0.25); + ] = (i < 16) ? 8'sd1 : 8'sd0; - bias_bus[7*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + bias_bus[7*DATA_WIDTH +: DATA_WIDTH] = 8'sd5; $display(""); $display("=============================="); - $display("LAYER TEST"); + $display("LAYER TEST (INT8)"); $display("=============================="); run_layer; - $display("Neuron 0 = %5d expected = 16384", y_bus[0*16 +: 16]); - $display("Neuron 1 = %5d expected = 8192", y_bus[1*16 +: 16]); - $display("Neuron 2 = %5d expected = 0", y_bus[2*16 +: 16]); - $display("Neuron 3 = %5d expected = 32767", y_bus[3*16 +: 16]); - $display("Neuron 4 = %5d expected = 256", y_bus[4*16 +: 16]); - $display("Neuron 5 = %5d expected = 0", y_bus[5*16 +: 16]); - $display("Neuron 6 = %5d expected = 16128", y_bus[6*16 +: 16]); - $display("Neuron 7 = %5d expected = 4352", y_bus[7*16 +: 16]); + $display("Neuron 0 = %5d expected = 32", $signed(y_bus[0*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 1 = %5d expected = 96", $signed(y_bus[1*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 2 = %5d expected = 0", $signed(y_bus[2*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 3 = %5d expected = 127", $signed(y_bus[3*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 4 = %5d expected = 5", $signed(y_bus[4*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 5 = %5d expected = 0", $signed(y_bus[5*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 6 = %5d expected = 22", $signed(y_bus[6*DATA_WIDTH +: DATA_WIDTH])); + $display("Neuron 7 = %5d expected = 21", $signed(y_bus[7*DATA_WIDTH +: DATA_WIDTH])); - if (y_bus[0*16 +: 16] !== 16'sd16384) errors = errors + 1; - if (y_bus[1*16 +: 16] !== 16'sd8192) errors = errors + 1; - if (y_bus[2*16 +: 16] !== 16'sd0) errors = errors + 1; - if (y_bus[3*16 +: 16] !== 16'sd32767) errors = errors + 1; - if (y_bus[4*16 +: 16] !== 16'sd256) errors = errors + 1; - if (y_bus[5*16 +: 16] !== 16'sd0) errors = errors + 1; - if (y_bus[6*16 +: 16] !== 16'sd16128) errors = errors + 1; - if (y_bus[7*16 +: 16] !== 16'sd4352) errors = errors + 1; + if ($signed(y_bus[0*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd32) errors = errors + 1; + if ($signed(y_bus[1*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd96) errors = errors + 1; + if ($signed(y_bus[2*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd0) errors = errors + 1; + if ($signed(y_bus[3*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd127) errors = errors + 1; + if ($signed(y_bus[4*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd5) errors = errors + 1; + if ($signed(y_bus[5*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd0) errors = errors + 1; + if ($signed(y_bus[6*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd22) errors = errors + 1; + if ($signed(y_bus[7*DATA_WIDTH +: DATA_WIDTH]) !== 8'sd21) errors = errors + 1; $display("busy = %0d", busy); $display("done = %0d", done); @@ -237,4 +232,4 @@ module tb; $finish; end -endmodule \ No newline at end of file +endmodule diff --git a/sim/neuron_parallel.vcd b/sim/neuron_parallel.vcd index 0ffe3f8..8d17eec 100644 --- a/sim/neuron_parallel.vcd +++ b/sim/neuron_parallel.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 08:54:48 2026 + Wed Sep 2 14:15:53 2026 $end $version Icarus Verilog @@ -8,160 +8,218 @@ $timescale 1ps $end $scope module tb $end -$var wire 16 ! y [15:0] $end +$var wire 8 ! y [7:0] $end $var wire 1 " done $end $var wire 1 # busy $end $var parameter 32 $ ACC_WIDTH $end $var parameter 32 % DATA_WIDTH $end -$var parameter 32 & FRAC_BITS $end -$var parameter 32 ' N_INPUTS $end -$var parameter 32 ( PARALLEL $end -$var reg 16 ) bias [15:0] $end -$var reg 1 * clk $end -$var reg 1 + rst $end -$var reg 1 , start $end -$var reg 1024 - w_bus [1023:0] $end -$var reg 1024 . x_bus [1023:0] $end -$var integer 32 / errors [31:0] $end -$var integer 32 0 i [31:0] $end -$scope function q8_8 $end -$var real 1 1 value $end -$upscope $end +$var parameter 32 & N_INPUTS $end +$var parameter 32 ' PARALLEL $end +$var reg 8 ( bias [7:0] $end +$var reg 1 ) clk $end +$var reg 1 * rst $end +$var reg 1 + start $end +$var reg 256 , w_bus [255:0] $end +$var reg 256 - x_bus [255:0] $end +$var integer 32 . errors [31:0] $end +$var integer 32 / i [31:0] $end $scope module dut $end -$var wire 16 2 bias [15:0] $end -$var wire 16 3 bias_ext_small [15:0] $end -$var wire 1 * clk $end -$var wire 1 + rst $end -$var wire 1 , start $end -$var wire 1024 4 w_bus [1023:0] $end -$var wire 1024 5 x_bus [1023:0] $end -$var wire 128 6 x_group [127:0] $end -$var wire 128 7 w_group [127:0] $end -$var wire 40 8 final_value [39:0] $end -$var wire 40 9 final_acc [39:0] $end -$var wire 40 : bias_ext [39:0] $end -$var wire 40 ; acc_next [39:0] $end -$var parameter 32 < ACC_WIDTH $end -$var parameter 32 = DATA_WIDTH $end -$var parameter 32 > FRAC_BITS $end -$var parameter 32 ? GROUPS $end -$var parameter 32 @ GROUP_INDEX_WIDTH $end -$var parameter 32 A N_INPUTS $end -$var parameter 32 B PARALLEL $end -$var reg 40 C acc [39:0] $end +$var wire 8 0 bias [7:0] $end +$var wire 1 ) clk $end +$var wire 1 * rst $end +$var wire 1 + start $end +$var wire 256 1 w_bus [255:0] $end +$var wire 256 2 x_bus [255:0] $end +$var wire 64 3 x_group [63:0] $end +$var wire 64 4 w_group [63:0] $end +$var wire 32 5 final_acc [31:0] $end +$var wire 32 6 bias_ext [31:0] $end +$var wire 32 7 acc_next [31:0] $end +$var parameter 32 8 ACC_WIDTH $end +$var parameter 32 9 DATA_WIDTH $end +$var parameter 32 : GROUPS $end +$var parameter 32 ; GROUP_INDEX_WIDTH $end +$var parameter 32 < N_INPUTS $end +$var parameter 32 = PARALLEL $end +$var reg 32 > acc [31:0] $end $var reg 1 # busy $end $var reg 1 " done $end -$var reg 3 D group_index [2:0] $end -$var reg 16 E y [15:0] $end +$var reg 2 ? group_index [1:0] $end +$var reg 8 @ y [7:0] $end $scope module u_mac8 $end -$var wire 40 F acc_in [39:0] $end -$var wire 128 G w_bus [127:0] $end -$var wire 128 H x_bus [127:0] $end -$var wire 40 I sum [39:0] $end -$var wire 40 J s5 [39:0] $end -$var wire 40 K s4 [39:0] $end -$var wire 40 L s3 [39:0] $end -$var wire 40 M s2 [39:0] $end -$var wire 40 N s1 [39:0] $end -$var wire 40 O s0 [39:0] $end -$var wire 40 P m7 [39:0] $end -$var wire 40 Q m6 [39:0] $end -$var wire 40 R m5 [39:0] $end -$var wire 40 S m4 [39:0] $end -$var wire 40 T m3 [39:0] $end -$var wire 40 U m2 [39:0] $end -$var wire 40 V m1 [39:0] $end -$var wire 40 W m0 [39:0] $end -$var wire 40 X acc_out [39:0] $end -$var parameter 32 Y ACC_WIDTH $end -$var parameter 32 Z DATA_WIDTH $end -$scope module mac0 $end -$var wire 40 [ acc_in [39:0] $end -$var wire 16 \ w [15:0] $end -$var wire 16 ] x [15:0] $end -$var wire 40 ^ product_ext [39:0] $end -$var wire 32 _ product [31:0] $end -$var wire 40 ` acc_out [39:0] $end -$var parameter 32 a ACC_WIDTH $end -$var parameter 32 b DATA_WIDTH $end -$var parameter 64 c PROD_WIDTH $end +$var wire 32 A acc_in [31:0] $end +$var wire 64 B w_bus [63:0] $end +$var wire 64 C x_bus [63:0] $end +$var wire 32 D acc_out [31:0] $end +$var parameter 32 E ACC_WIDTH $end +$var parameter 32 F DATA_WIDTH $end +$var parameter 32 G PARALLEL $end +$var parameter 32 H TREE_LEVELS $end +$scope begin GEN_MAC[0] $end +$var parameter 2 I i $end +$scope module u_mac $end +$var wire 32 J acc_in [31:0] $end +$var wire 8 K w [7:0] $end +$var wire 8 L x [7:0] $end +$var wire 32 M product_ext [31:0] $end +$var wire 16 N product [15:0] $end +$var wire 32 O acc_out [31:0] $end +$var parameter 32 P ACC_WIDTH $end +$var parameter 32 Q DATA_WIDTH $end +$var parameter 64 R PROD_WIDTH $end $upscope $end -$scope module mac1 $end -$var wire 40 d acc_in [39:0] $end -$var wire 16 e w [15:0] $end -$var wire 16 f x [15:0] $end -$var wire 40 g product_ext [39:0] $end -$var wire 32 h product [31:0] $end -$var wire 40 i acc_out [39:0] $end -$var parameter 32 j ACC_WIDTH $end -$var parameter 32 k DATA_WIDTH $end -$var parameter 64 l PROD_WIDTH $end $upscope $end -$scope module mac2 $end -$var wire 40 m acc_in [39:0] $end -$var wire 16 n w [15:0] $end -$var wire 16 o x [15:0] $end -$var wire 40 p product_ext [39:0] $end -$var wire 32 q product [31:0] $end -$var wire 40 r acc_out [39:0] $end -$var parameter 32 s ACC_WIDTH $end -$var parameter 32 t DATA_WIDTH $end -$var parameter 64 u PROD_WIDTH $end +$scope begin GEN_MAC[1] $end +$var parameter 2 S i $end +$scope module u_mac $end +$var wire 32 T acc_in [31:0] $end +$var wire 8 U w [7:0] $end +$var wire 8 V x [7:0] $end +$var wire 32 W product_ext [31:0] $end +$var wire 16 X product [15:0] $end +$var wire 32 Y acc_out [31:0] $end +$var parameter 32 Z ACC_WIDTH $end +$var parameter 32 [ DATA_WIDTH $end +$var parameter 64 \ PROD_WIDTH $end $upscope $end -$scope module mac3 $end -$var wire 40 v acc_in [39:0] $end -$var wire 16 w w [15:0] $end -$var wire 16 x x [15:0] $end -$var wire 40 y product_ext [39:0] $end -$var wire 32 z product [31:0] $end -$var wire 40 { acc_out [39:0] $end -$var parameter 32 | ACC_WIDTH $end -$var parameter 32 } DATA_WIDTH $end -$var parameter 64 ~ PROD_WIDTH $end $upscope $end -$scope module mac4 $end -$var wire 40 !" acc_in [39:0] $end -$var wire 16 "" w [15:0] $end -$var wire 16 #" x [15:0] $end -$var wire 40 $" product_ext [39:0] $end -$var wire 32 %" product [31:0] $end -$var wire 40 &" acc_out [39:0] $end -$var parameter 32 '" ACC_WIDTH $end -$var parameter 32 (" DATA_WIDTH $end -$var parameter 64 )" PROD_WIDTH $end +$scope begin GEN_MAC[2] $end +$var parameter 3 ] i $end +$scope module u_mac $end +$var wire 32 ^ acc_in [31:0] $end +$var wire 8 _ w [7:0] $end +$var wire 8 ` x [7:0] $end +$var wire 32 a product_ext [31:0] $end +$var wire 16 b product [15:0] $end +$var wire 32 c acc_out [31:0] $end +$var parameter 32 d ACC_WIDTH $end +$var parameter 32 e DATA_WIDTH $end +$var parameter 64 f PROD_WIDTH $end $upscope $end -$scope module mac5 $end -$var wire 40 *" acc_in [39:0] $end -$var wire 16 +" w [15:0] $end -$var wire 16 ," x [15:0] $end -$var wire 40 -" product_ext [39:0] $end -$var wire 32 ." product [31:0] $end -$var wire 40 /" acc_out [39:0] $end -$var parameter 32 0" ACC_WIDTH $end -$var parameter 32 1" DATA_WIDTH $end -$var parameter 64 2" PROD_WIDTH $end $upscope $end -$scope module mac6 $end -$var wire 40 3" acc_in [39:0] $end -$var wire 16 4" w [15:0] $end -$var wire 16 5" x [15:0] $end -$var wire 40 6" product_ext [39:0] $end -$var wire 32 7" product [31:0] $end -$var wire 40 8" acc_out [39:0] $end -$var parameter 32 9" ACC_WIDTH $end -$var parameter 32 :" DATA_WIDTH $end -$var parameter 64 ;" PROD_WIDTH $end +$scope begin GEN_MAC[3] $end +$var parameter 3 g i $end +$scope module u_mac $end +$var wire 32 h acc_in [31:0] $end +$var wire 8 i w [7:0] $end +$var wire 8 j x [7:0] $end +$var wire 32 k product_ext [31:0] $end +$var wire 16 l product [15:0] $end +$var wire 32 m acc_out [31:0] $end +$var parameter 32 n ACC_WIDTH $end +$var parameter 32 o DATA_WIDTH $end +$var parameter 64 p PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[4] $end +$var parameter 4 q i $end +$scope module u_mac $end +$var wire 32 r acc_in [31:0] $end +$var wire 8 s w [7:0] $end +$var wire 8 t x [7:0] $end +$var wire 32 u product_ext [31:0] $end +$var wire 16 v product [15:0] $end +$var wire 32 w acc_out [31:0] $end +$var parameter 32 x ACC_WIDTH $end +$var parameter 32 y DATA_WIDTH $end +$var parameter 64 z PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[5] $end +$var parameter 4 { i $end +$scope module u_mac $end +$var wire 32 | acc_in [31:0] $end +$var wire 8 } w [7:0] $end +$var wire 8 ~ x [7:0] $end +$var wire 32 !" product_ext [31:0] $end +$var wire 16 "" product [15:0] $end +$var wire 32 #" acc_out [31:0] $end +$var parameter 32 $" ACC_WIDTH $end +$var parameter 32 %" DATA_WIDTH $end +$var parameter 64 &" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[6] $end +$var parameter 4 '" i $end +$scope module u_mac $end +$var wire 32 (" acc_in [31:0] $end +$var wire 8 )" w [7:0] $end +$var wire 8 *" x [7:0] $end +$var wire 32 +" product_ext [31:0] $end +$var wire 16 ," product [15:0] $end +$var wire 32 -" acc_out [31:0] $end +$var parameter 32 ." ACC_WIDTH $end +$var parameter 32 /" DATA_WIDTH $end +$var parameter 64 0" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_MAC[7] $end +$var parameter 4 1" i $end +$scope module u_mac $end +$var wire 32 2" acc_in [31:0] $end +$var wire 8 3" w [7:0] $end +$var wire 8 4" x [7:0] $end +$var wire 32 5" product_ext [31:0] $end +$var wire 16 6" product [15:0] $end +$var wire 32 7" acc_out [31:0] $end +$var parameter 32 8" ACC_WIDTH $end +$var parameter 32 9" DATA_WIDTH $end +$var parameter 64 :" PROD_WIDTH $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_INPUT[0] $end +$var parameter 2 ;" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[1] $end +$var parameter 2 <" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[2] $end +$var parameter 3 =" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[3] $end +$var parameter 3 >" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[4] $end +$var parameter 4 ?" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[5] $end +$var parameter 4 @" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[6] $end +$var parameter 4 A" i $end +$upscope $end +$scope begin GEN_TREE_INPUT[7] $end +$var parameter 4 B" i $end +$upscope $end +$scope begin GEN_TREE_LEVEL[0] $end +$var parameter 2 C" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 D" node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 E" node $end +$upscope $end +$scope begin GEN_TREE_NODE[2] $end +$var parameter 3 F" node $end +$upscope $end +$scope begin GEN_TREE_NODE[3] $end +$var parameter 3 G" node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[1] $end +$var parameter 2 H" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 I" node $end +$upscope $end +$scope begin GEN_TREE_NODE[1] $end +$var parameter 2 J" node $end +$upscope $end +$upscope $end +$scope begin GEN_TREE_LEVEL[2] $end +$var parameter 3 K" level $end +$scope begin GEN_TREE_NODE[0] $end +$var parameter 2 L" node $end $upscope $end -$scope module mac7 $end -$var wire 40 <" acc_in [39:0] $end -$var wire 16 =" w [15:0] $end -$var wire 16 >" x [15:0] $end -$var wire 40 ?" product_ext [39:0] $end -$var wire 32 @" product [31:0] $end -$var wire 40 A" acc_out [39:0] $end -$var parameter 32 B" ACC_WIDTH $end -$var parameter 32 C" DATA_WIDTH $end -$var parameter 64 D" PROD_WIDTH $end $upscope $end $upscope $end $upscope $end @@ -179,849 +237,644 @@ $upscope $end $enddefinitions $end $comment Show the parameter values. $end $dumpall -b100000 D" -b10000 C" -b101000 B" -b100000 ;" +b0 L" +b10 K" +b1 J" +b0 I" +b1 H" +b11 G" +b10 F" +b1 E" +b0 D" +b0 C" +b111 B" +b110 A" +b101 @" +b100 ?" +b11 >" +b10 =" +b1 <" +b0 ;" b10000 :" -b101000 9" -b100000 2" -b10000 1" -b101000 0" -b100000 )" -b10000 (" -b101000 '" -b100000 ~ -b10000 } -b101000 | -b100000 u -b10000 t -b101000 s -b100000 l -b10000 k -b101000 j -b100000 c -b10000 b -b101000 a -b10000 Z -b101000 Y -b1000 B -b1000000 A -b11 @ -b1000 ? -b1000 > -b10000 = -b101000 < -b1000 ( -b1000000 ' -b1000 & -b10000 % -b101000 $ +b1000 9" +b100000 8" +b111 1" +b10000 0" +b1000 /" +b100000 ." +b110 '" +b10000 &" +b1000 %" +b100000 $" +b101 { +b10000 z +b1000 y +b100000 x +b100 q +b10000 p +b1000 o +b100000 n +b11 g +b10000 f +b1000 e +b100000 d +b10 ] +b10000 \ +b1000 [ +b100000 Z +b1 S +b10000 R +b1000 Q +b100000 P +b0 I +b11 H +b1000 G +b1000 F +b100000 E +b1000 = +b100000 < +b10 ; +b100 : +b1000 9 +b100000 8 +b1000 ' +b100000 & +b1000 % +b100000 $ $end #0 $dumpvars -bx A" -bx @" -bx ?" -bx >" -bx =" -b0 <" -bx 8" bx 7" bx 6" bx 5" bx 4" -b0 3" -bx /" -bx ." +bx 3" +b0 2" bx -" bx ," bx +" -b0 *" -bx &" -bx %" -bx $" +bx *" +bx )" +b0 (" bx #" bx "" -b0 !" -bx { -bx z -bx y -bx x +bx !" +bx ~ +bx } +b0 | bx w -b0 v -bx r -bx q -bx p -bx o -bx n -b0 m +bx v +bx u +bx t +bx s +b0 r +bx m +bx l +bx k +bx j bx i -bx h -bx g -bx f -bx e -b0 d +b0 h +bx c +bx b +bx a bx ` bx _ -bx ^ -bx ] -bx \ -b0 [ +b0 ^ +bx Y bx X bx W bx V bx U -bx T -bx S -bx R -bx Q -bx P +b0 T bx O bx N bx M bx L bx K -bx J -bx I -bx H -bx G -bx F -bx E +b0 J bx D bx C -bx ; -b0 : -bx 9 -bx 8 +bx B +bx A +bx @ +bx ? +bx > bx 7 -bx 6 -b0 5 -b0 4 -b0 3 +b0 6 +bx 5 +bx 4 +bx 3 b0 2 -r0 1 -bx 0 -b0 / +b0 1 +b0 0 +bx / b0 . b0 - -0, -1+ -0* -b0 ) +b0 , +0+ +1* +0) +b0 ( x# x" bx ! $end #5000 -b0 8 -b0 9 -b0 ; -b0 X -b0 I -b0 K -b0 O -b0 W -b0 ` -b0 V -b0 i -b0 N -b0 U -b0 r -b0 T -b0 { -b0 J -b0 M -b0 S -b0 &" -b0 R -b0 /" -b0 L -b0 Q -b0 8" -b0 P -b0 A" -b0 ^ -b0 g -b0 p -b0 y -b0 $" -b0 -" -b0 6" -b0 ?" -b0 _ -b0 ] -b0 h -b0 f -b0 q -b0 o -b0 z -b0 x -b0 %" -b0 #" -b0 ." -b0 ," -b0 7" -b0 5" -b0 @" -b0 >" -b0 \ -b0 e -b0 n -b0 w -b0 "" -b0 +" -b0 4" -b0 =" -b0 6 -b0 H +b0 5 b0 7 -b0 G +b0 D +b0 O +b0 Y +b0 c +b0 m +b0 w +b0 #" +b0 -" +b0 7" +b0 M +b0 W +b0 a +b0 k +b0 u +b0 !" +b0 +" +b0 5" +b0 N +b0 L +b0 X +b0 V +b0 b +b0 ` +b0 l +b0 j +b0 v +b0 t +b0 "" +b0 ~ +b0 ," +b0 *" +b0 6" +b0 4" +b0 K +b0 U +b0 _ +b0 i +b0 s +b0 } +b0 )" +b0 3" +b0 3 +b0 C +b0 4 +b0 B 0" 0# b0 ! -b0 E -b0 C -b0 F -b0 D -1* +b0 @ +b0 > +b0 A +b0 ? +1) #10000 -0* +0) #15000 -b110111100 8 -b10000000000000 N -b10000000000000 U -b10000000000000 r -b10000000000000 p -b1111111111111111111111100000000000000000 V -b1111111111111111111111100000000000000000 i -b1111111111111111111111100000000000000000 g -b11011110000000000 9 -b10010000000000000 ; -b10010000000000000 X -b10010000000000000 I -b10010000000000000 K -b10000000000000000 O -b110000000000000000 W -b110000000000000000 ` -b110000000000000000 ^ -b10000000000000 q -b1000000 n -b10000000 o -b11111111111111100000000000000000 h -b1111111100000000 e -b1000000000 f -b110000000000000000 _ -b1000000000 \ -b110000000 ] -b10011100 : -b100000011111111000000000000001000000000 7 -b100000011111111000000000000001000000000 G -b100000011111111000000000000001000000000 - -b100000011111111000000000000001000000000 4 -b1000000000000010000000000000000110000000 6 -b1000000000000010000000000000000110000000 H -b1000000000000010000000000000000110000000 . -b1000000000000010000000000000000110000000 5 -b10011100 3 -b10011100 ) -b10011100 2 -r0.25 1 -0+ -1* -#20000 +b10 c +b10 a +b11111111111111111111111111111100 Y +b11111111111111111111111111111100 W +b100 7 +b100 D +b110 O +b110 M +b10 b +b1 _ +b10 ` +b1111111111111100 X +b11111111 U +b100 V +b110 N +b10 K +b11 L +b101 5 +b1 6 +b11111111100000010 4 +b11111111100000010 B +b11111111100000010 , +b11111111100000010 1 +b100000010000000011 3 +b100000010000000011 C +b100000010000000011 - +b100000010000000011 2 +b1 ( +b1 0 0* +1) +#20000 +0) #25000 1# -1, -1* +1+ +1) #30000 -0* +0) #35000 -b0 W -b0 ` -b0 ^ b0 O -b0 V -b0 i -b0 g -b0 I -b0 K -b0 N -b0 U -b0 r -b0 p -b0 ] -b0 f -b0 o -b0 _ -b0 \ -b0 h -b0 e -b0 q -b0 n -b0 6 -b0 H -b0 7 -b0 G -b110111100 8 -b1 D -b11011110000000000 9 -b10010000000000000 ; -b10010000000000000 X -b10010000000000000 C -b10010000000000000 F -0, -1* -#40000 -0* -#45000 -b10 D -1* -#50000 -0* -#55000 -b11 D -1* -#60000 -0* -#65000 -b100 D -1* -#70000 -0* -#75000 -b101 D -1* -#80000 -0* -#85000 -b110 D -1* -#90000 -0* -#95000 -b111 D -1* -#100000 -0* -#105000 -b1001011000 8 -1" -0# -b110111100 ! -b110111100 E -b100101100000000000 9 -b11011110000000000 ; -b11011110000000000 X -b11011110000000000 C -b11011110000000000 F -1* -#110000 -0* -#115000 -0" -b1111111111111111111111111111100110111100 8 -b1111111111111111111111110000000000000000 P -b1111111111111111111111110000000000000000 A" -b1111111111111111111111110000000000000000 ?" -b1111111111111111111111100000000000000000 L -b1111111111111111111111110000000000000000 Q -b1111111111111111111111110000000000000000 8" -b1111111111111111111111110000000000000000 6" -b1111111111111111111111110000000000000000 R -b1111111111111111111111110000000000000000 /" -b1111111111111111111111110000000000000000 -" -b1111111111111111111111000000000000000000 J -b1111111111111111111111100000000000000000 M -b1111111111111111111111110000000000000000 S -b1111111111111111111111110000000000000000 &" -b1111111111111111111111110000000000000000 $" -b1111111111111111111111110000000000000000 T -b1111111111111111111111110000000000000000 { -b1111111111111111111111110000000000000000 y -b1111111111111111111111100000000000000000 N -b1111111111111111111111110000000000000000 U -b1111111111111111111111110000000000000000 r -b1111111111111111111111110000000000000000 p -b1111111111111111111111110000000000000000 V -b1111111111111111111111110000000000000000 i -b1111111111111111111111110000000000000000 g -b1111111111111111111110011011110000000000 9 -b1111111111111111111110011011110000000000 ; -b1111111111111111111110011011110000000000 X -b1111111111111111111110000000000000000000 I -b1111111111111111111111000000000000000000 K -b1111111111111111111111100000000000000000 O -b1111111111111111111111110000000000000000 W -b1111111111111111111111110000000000000000 ` -b1111111111111111111111110000000000000000 ^ -b11111111111111110000000000000000 @" -b1111111100000000 =" -b100000000 >" -b11111111111111110000000000000000 7" -b1111111100000000 4" -b100000000 5" -b11111111111111110000000000000000 ." -b1111111100000000 +" -b100000000 ," -b11111111111111110000000000000000 %" -b1111111100000000 "" -b100000000 #" -b11111111111111110000000000000000 z -b1111111100000000 w -b100000000 x -b11111111111111110000000000000000 q -b1111111100000000 n -b100000000 o -b11111111111111110000000000000000 h -b1111111100000000 e -b100000000 f -b11111111111111110000000000000000 _ -b1111111100000000 \ -b100000000 ] -b0 : -b11111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000 7 -b11111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000 G -b1000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000 6 -b1000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000 H -r-1 1 -b1000000 0 -b0 3 -b0 ) -b0 2 -b1111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000 - -b1111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000 4 -b100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000 . -b100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000000000100000000 5 -1* -#120000 -0* -#125000 -b1111111111111111111111111111100000000000 8 -1# -b1111111111111111111110000000000000000000 9 -b1111111111111111111110000000000000000000 ; -b1111111111111111111110000000000000000000 X -b0 C -b0 F -b0 D -1, -1* -#130000 -0* -#135000 -b1111111111111111111111111111000000000000 8 -b1 D -b1111111111111111111100000000000000000000 9 -b1111111111111111111100000000000000000000 ; -b1111111111111111111100000000000000000000 X -b1111111111111111111110000000000000000000 C -b1111111111111111111110000000000000000000 F -0, -1* -#140000 -0* -#145000 -b1111111111111111111111111110100000000000 8 -b10 D -b1111111111111111111010000000000000000000 9 -b1111111111111111111010000000000000000000 ; -b1111111111111111111010000000000000000000 X -b1111111111111111111100000000000000000000 C -b1111111111111111111100000000000000000000 F -1* -#150000 -0* -#155000 -b1111111111111111111111111110000000000000 8 -b11 D -b1111111111111111111000000000000000000000 9 -b1111111111111111111000000000000000000000 ; -b1111111111111111111000000000000000000000 X -b1111111111111111111010000000000000000000 C -b1111111111111111111010000000000000000000 F -1* -#160000 -0* -#165000 -b1111111111111111111111111101100000000000 8 -b100 D -b1111111111111111110110000000000000000000 9 -b1111111111111111110110000000000000000000 ; -b1111111111111111110110000000000000000000 X -b1111111111111111111000000000000000000000 C -b1111111111111111111000000000000000000000 F -1* -#170000 -0* -#175000 -b1111111111111111111111111101000000000000 8 -b101 D -b1111111111111111110100000000000000000000 9 -b1111111111111111110100000000000000000000 ; -b1111111111111111110100000000000000000000 X -b1111111111111111110110000000000000000000 C -b1111111111111111110110000000000000000000 F -1* -#180000 -0* -#185000 -b1111111111111111111111111100100000000000 8 -b110 D -b1111111111111111110010000000000000000000 9 -b1111111111111111110010000000000000000000 ; -b1111111111111111110010000000000000000000 X -b1111111111111111110100000000000000000000 C -b1111111111111111110100000000000000000000 F -1* -#190000 -0* -#195000 -b1111111111111111111111111100000000000000 8 -b111 D -b1111111111111111110000000000000000000000 9 -b1111111111111111110000000000000000000000 ; -b1111111111111111110000000000000000000000 X -b1111111111111111110010000000000000000000 C -b1111111111111111110010000000000000000000 F -1* -#200000 -0* -#205000 -b1111111111111111111111111011100000000000 8 -1" -0# -b0 ! -b0 E -b1111111111111111101110000000000000000000 9 -b1111111111111111101110000000000000000000 ; -b1111111111111111101110000000000000000000 X -b1111111111111111110000000000000000000000 C -b1111111111111111110000000000000000000000 F -1* -#210000 -0* -#215000 -0" -b1111011000000000000 8 -b111111100000000000000000 W -b111111100000000000000000 ` -b111111100000000000000000 ^ -b1111111000000000000000000 O -b111111100000000000000000 V -b111111100000000000000000 i -b111111100000000000000000 g -b111111100000000000000000 U -b111111100000000000000000 r -b111111100000000000000000 p -b11111110000000000000000000 K -b1111111000000000000000000 N -b111111100000000000000000 T -b111111100000000000000000 { -b111111100000000000000000 y -b111111100000000000000000 S -b111111100000000000000000 &" -b111111100000000000000000 $" -b1111111000000000000000000 M -b111111100000000000000000 R -b111111100000000000000000 /" -b111111100000000000000000 -" -b111111100000000000000000 Q -b111111100000000000000000 8" -b111111100000000000000000 6" -b111101100000000000000000000 9 -b111101100000000000000000000 ; -b111101100000000000000000000 X -b111111100000000000000000000 I -b11111110000000000000000000 J -b1111111000000000000000000 L -b111111100000000000000000 P -b111111100000000000000000 A" -b111111100000000000000000 ?" -b1000000000 \ -b1000000000 e -b1000000000 n -b1000000000 w -b1000000000 "" -b1000000000 +" -b1000000000 4" -b1000000000 =" -b111111100000000000000000 _ -b111111100000000 ] -b111111100000000000000000 h -b111111100000000 f -b111111100000000000000000 q -b111111100000000 o -b111111100000000000000000 z -b111111100000000 x -b111111100000000000000000 %" -b111111100000000 #" -b111111100000000000000000 ." -b111111100000000 ," -b111111100000000000000000 7" -b111111100000000 5" -b111111100000000000000000 @" -b111111100000000 >" -r2 1 -b1000000 0 -b10000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000 7 -b10000000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000000000000001000000000 G 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+b1111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010 2 +1) +#200000 +0) +#205000 +1# +b11111111111111111111111111110100 5 +b100 7 +b100 D +b0 > +b0 A +b0 ? +1+ +1) +#210000 +0) +#215000 +b1 ? +b11111111111111111111111111111000 5 +b1000 7 +b1000 D +b100 > +b100 A +0+ +1) +#220000 +0) +#225000 +b10 ? +b11111111111111111111111111111100 5 +b1100 7 +b1100 D +b1000 > +b1000 A +1) +#230000 +0) +#235000 +b11 ? +b0 5 +b10000 7 +b10000 D +b1100 > +b1100 A +1) +#240000 +0) +#245000 +1" +0# +b0 ! +b0 @ +b11111111111111111111111111110100 5 +b100 7 +b100 D +b0 > +b0 A +1) +#250000 +0) +#255000 +0" +1) diff --git a/sim/neuron_parallel_tb.v b/sim/neuron_parallel_tb.v index 6863b29..cd85b6a 100644 --- a/sim/neuron_parallel_tb.v +++ b/sim/neuron_parallel_tb.v @@ -2,11 +2,10 @@ module tb; - parameter DATA_WIDTH = 16; - parameter FRAC_BITS = 8; - parameter N_INPUTS = 64; + parameter DATA_WIDTH = 8; + parameter N_INPUTS = 32; parameter PARALLEL = 8; - parameter ACC_WIDTH = 40; + parameter ACC_WIDTH = 32; reg clk; reg rst; @@ -25,7 +24,6 @@ module tb; neuron_parallel #( .DATA_WIDTH(DATA_WIDTH), - .FRAC_BITS(FRAC_BITS), .N_INPUTS(N_INPUTS), .PARALLEL(PARALLEL), .ACC_WIDTH(ACC_WIDTH) @@ -47,16 +45,6 @@ module tb; forever #5 clk = ~clk; end - // ------------------------------------------------------------ - // Helper: convert real value to Q8.8 - // ------------------------------------------------------------ - function signed [15:0] q8_8; - input real value; - begin - q8_8 = $rtoi(value * 256.0); - end - endfunction - // ------------------------------------------------------------ // Start neuron and wait for completion // ------------------------------------------------------------ @@ -79,14 +67,13 @@ module tb; // // Diverse vector: // - // x0 = 1.5 w0 = 2.0 -> 3.0 - // x1 = 2.0 w1 = -1.0 -> -2.0 - // x2 = 0.5 w2 = 0.25 -> 0.125 + // x0 = 3 w0 = 2 -> 6 + // x1 = 4 w1 = -1 -> -4 + // x2 = 2 w2 = 1 -> 2 // - // bias = 0.609375 + // bias = 1 // - // total = 1.734375 - // Q8.8 = 444 + // total = 6 - 4 + 2 + 1 = 5 // ------------------------------------------------------------ task test_1; begin @@ -95,23 +82,23 @@ module tb; x_bus = 0; w_bus = 0; - bias = q8_8(0.609375); + bias = 8'sd1; - x_bus[0*16 +: 16] = q8_8(1.5); - w_bus[0*16 +: 16] = q8_8(2.0); + x_bus[0*DATA_WIDTH +: DATA_WIDTH] = 8'sd3; + w_bus[0*DATA_WIDTH +: DATA_WIDTH] = 8'sd2; - x_bus[1*16 +: 16] = q8_8(2.0); - w_bus[1*16 +: 16] = q8_8(-1.0); + x_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd4; + w_bus[1*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; - x_bus[2*16 +: 16] = q8_8(0.5); - w_bus[2*16 +: 16] = q8_8(0.25); + x_bus[2*DATA_WIDTH +: DATA_WIDTH] = 8'sd2; + w_bus[2*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; run_neuron; $display("RTL = %0d", y); - $display("EXPECTED = 444"); + $display("EXPECTED = 5"); - if (y !== 16'sd444) begin + if (y !== 8'sd5) begin $display("FAIL - TEST 1"); errors = errors + 1; end @@ -137,8 +124,8 @@ module tb; bias = 0; for (i = 0; i < N_INPUTS; i = i + 1) begin - x_bus[i*16 +: 16] = q8_8(1.0); - w_bus[i*16 +: 16] = q8_8(-1.0); + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; + w_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; end run_neuron; @@ -146,7 +133,7 @@ module tb; $display("RTL = %0d", y); $display("EXPECTED = 0"); - if (y !== 16'sd0) begin + if (y !== 8'sd0) begin $display("FAIL - TEST 2"); errors = errors + 1; end @@ -160,7 +147,7 @@ module tb; // TEST 3 // // Large positive result. - // Must saturate to +32767. + // Must saturate to +127 (INT8). // ------------------------------------------------------------ task test_3; begin @@ -172,16 +159,16 @@ module tb; bias = 0; for (i = 0; i < N_INPUTS; i = i + 1) begin - x_bus[i*16 +: 16] = q8_8(127.0); - w_bus[i*16 +: 16] = q8_8(2.0); + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd100; + w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd2; end run_neuron; $display("RTL = %0d", y); - $display("EXPECTED = 32767"); + $display("EXPECTED = 127"); - if (y !== 16'sd32767) begin + if (y !== 8'sd127) begin $display("FAIL - TEST 3"); errors = errors + 1; end @@ -196,12 +183,12 @@ module tb; // // Mixed positive/negative products. // - // 32 x (+1) - // 32 x (-1) - // sum = 0 - // bias = -1 + // 16 x (2 * 1) = 32 + // 16 x (-1 * 1) = -16 + // sum = 16 + // bias = -16 // - // ReLU -> 0 + // total = 0 -> ReLU boundary -> 0 // ------------------------------------------------------------ task test_4; begin @@ -210,16 +197,16 @@ module tb; x_bus = 0; w_bus = 0; - bias = q8_8(-1.0); + bias = -8'sd16; for (i = 0; i < N_INPUTS; i = i + 1) begin if ((i % 2) == 0) begin - x_bus[i*16 +: 16] = q8_8(2.0); - w_bus[i*16 +: 16] = q8_8(0.5); + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd2; + w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; end else begin - x_bus[i*16 +: 16] = q8_8(-1.0); - w_bus[i*16 +: 16] = q8_8(1.0); + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; + w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; end end @@ -228,7 +215,7 @@ module tb; $display("RTL = %0d", y); $display("EXPECTED = 0"); - if (y !== 16'sd0) begin + if (y !== 8'sd0) begin $display("FAIL - TEST 4"); errors = errors + 1; end @@ -259,7 +246,7 @@ module tb; $display(""); $display("=============================="); - $display("NEURON_PARALLEL TESTBENCH"); + $display("NEURON_PARALLEL TESTBENCH (INT8)"); $display("=============================="); test_1; @@ -283,4 +270,4 @@ module tb; $finish; end -endmodule \ No newline at end of file +endmodule diff --git a/sim/neuron_sim b/sim/neuron_sim index 2424e25..7c0facc 100755 --- a/sim/neuron_sim +++ b/sim/neuron_sim @@ -8,28 +8,73 @@ :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi"; :vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi"; -S_0x1012719d0 .scope package, "$unit" "$unit" 2 1; +S_0x102e30ba0 .scope package, "$unit" "$unit" 2 1; .timescale 0 0; -S_0x1012716f0 .scope module, "tb" "tb" 3 3; +S_0x102e308c0 .scope module, "layer" "layer" 3 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 8192 "weights_bus"; + .port_info 5 /INPUT 128 "bias_bus"; + .port_info 6 /OUTPUT 128 "y_bus"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbaad1c000 .param/l "ACC_WIDTH" 0 3 6, +C4<00000000000000000000000000101000>; +P_0xbaad1c040 .param/l "DATA_WIDTH" 0 3 2, +C4<00000000000000000000000000010000>; +P_0xbaad1c080 .param/l "N_INPUTS" 0 3 3, +C4<00000000000000000000000001000000>; +P_0xbaad1c0c0 .param/l "N_NEURONS" 0 3 4, +C4<00000000000000000000000000001000>; +P_0xbaad1c100 .param/l "PARALLEL" 0 3 5, +C4<00000000000000000000000000001000>; +o0xbaa855350 .functor BUFZ 128, c4; HiZ drive +v0xbab3012c0_0 .net/s "bias_bus", 127 0, o0xbaa855350; 0 drivers +v0xbab301360_0 .net "busy", 0 0, L_0xbab346760; 1 drivers +o0xbaa845fc0 .functor BUFZ 1, c4; HiZ drive +v0xbab301400_0 .net "clk", 0 0, o0xbaa845fc0; 0 drivers +v0xbab3014a0_0 .net "done", 0 0, L_0xbab346800; 1 drivers +v0xbab301540_0 .net "neuron_busy", 7 0, L_0xbab34c5a0; 1 drivers +v0xbab3015e0_0 .net "neuron_done", 7 0, L_0xbab34c640; 1 drivers +o0xbaa846080 .functor BUFZ 1, c4; HiZ drive +v0xbab301680_0 .net "rst", 0 0, o0xbaa846080; 0 drivers +o0xbaa8460b0 .functor BUFZ 1, c4; HiZ drive +v0xbab301720_0 .net "start", 0 0, o0xbaa8460b0; 0 drivers +o0xbaa855440 .functor BUFZ 8192, c4; HiZ drive +v0xbab3017c0_0 .net/s "weights_bus", 8191 0, o0xbaa855440; 0 drivers +o0xbaa846110 .functor BUFZ 1024, c4; HiZ drive +v0xbab301860_0 .net/s "x_bus", 1023 0, o0xbaa846110; 0 drivers +v0xbab301900_0 .net/s "y_bus", 127 0, L_0xbab34c500; 1 drivers +L_0xbab27aee0 .part o0xbaa855440, 0, 1024; +L_0xbab27af80 .part o0xbaa855350, 0, 16; +L_0xbab22f660 .part o0xbaa855440, 1024, 1024; +L_0xbab22d400 .part o0xbaa855350, 16, 16; +L_0xbab330b40 .part o0xbaa855440, 2048, 1024; +L_0xbab330be0 .part o0xbaa855350, 32, 16; +L_0xbab331d60 .part o0xbaa855440, 3072, 1024; +L_0xbab331e00 .part o0xbaa855350, 48, 16; +L_0xbab332f80 .part o0xbaa855440, 4096, 1024; +L_0xbab333020 .part o0xbaa855350, 64, 16; +L_0xbab3441e0 .part o0xbaa855440, 5120, 1024; +L_0xbab344280 .part o0xbaa855350, 80, 16; +L_0xbab345400 .part o0xbaa855440, 6144, 1024; +L_0xbab3454a0 .part o0xbaa855350, 96, 16; +L_0xbab346620 .part o0xbaa855440, 7168, 1024; +L_0xbab3466c0 .part o0xbaa855350, 112, 16; +LS_0xbab34c500_0_0 .concat8 [ 16 16 16 16], v0xbab2a94a0_0, v0xbab2b9d60_0, v0xbab2c2620_0, v0xbab2d2ee0_0; +LS_0xbab34c500_0_4 .concat8 [ 16 16 16 16], v0xbab2db7a0_0, v0xbab2e80a0_0, v0xbab2f8960_0, v0xbab301220_0; +L_0xbab34c500 .concat8 [ 64 64 0 0], LS_0xbab34c500_0_0, LS_0xbab34c500_0_4; +LS_0xbab34c5a0_0_0 .concat8 [ 1 1 1 1], v0xbab2a8dc0_0, v0xbab2b9680_0, v0xbab2c1f40_0, v0xbab2d2800_0; +LS_0xbab34c5a0_0_4 .concat8 [ 1 1 1 1], v0xbab2db0c0_0, v0xbab2e3980_0, v0xbab2f8280_0, v0xbab300b40_0; +L_0xbab34c5a0 .concat8 [ 4 4 0 0], LS_0xbab34c5a0_0_0, LS_0xbab34c5a0_0_4; +LS_0xbab34c640_0_0 .concat8 [ 1 1 1 1], v0xbab2a8f00_0, v0xbab2b97c0_0, v0xbab2c2080_0, v0xbab2d2940_0; +LS_0xbab34c640_0_4 .concat8 [ 1 1 1 1], v0xbab2db200_0, v0xbab2e3ac0_0, v0xbab2f83c0_0, v0xbab300c80_0; +L_0xbab34c640 .concat8 [ 4 4 0 0], LS_0xbab34c640_0_0, LS_0xbab34c640_0_4; +L_0xbab346760 .reduce/or L_0xbab34c5a0; +L_0xbab346800 .reduce/and L_0xbab34c640; +S_0x102e22cb0 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad29c00 .param/l "n" 1 3 34, +C4<00>; +S_0x102e22e30 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0x102e22cb0; .timescale -9 -12; -P_0x7e30a43c0 .param/l "ACC_WIDTH" 0 3 9, +C4<00000000000000000000000000101000>; -P_0x7e30a4400 .param/l "DATA_WIDTH" 0 3 5, +C4<00000000000000000000000000010000>; -P_0x7e30a4440 .param/l "FRAC_BITS" 0 3 6, +C4<00000000000000000000000000001000>; -P_0x7e30a4480 .param/l "N_INPUTS" 0 3 7, +C4<00000000000000000000000001000000>; -P_0x7e30a44c0 .param/l "PARALLEL" 0 3 8, +C4<00000000000000000000000000001000>; -v0x7e30b9040_0 .var/s "bias", 15 0; -v0x7e30b90e0_0 .net "busy", 0 0, v0x7e30b86e0_0; 1 drivers -v0x7e30b9180_0 .var "clk", 0 0; -v0x7e30b9220_0 .net "done", 0 0, v0x7e30b8820_0; 1 drivers -v0x7e30b92c0_0 .var/i "errors", 31 0; -v0x7e30b9360_0 .var/i "i", 31 0; -v0x7e30b9400_0 .var "rst", 0 0; -v0x7e30b94a0_0 .var "start", 0 0; -v0x7e30b9540_0 .var/s "w_bus", 1023 0; -v0x7e30b95e0_0 .var/s "x_bus", 1023 0; -v0x7e30b9680_0 .net/s "y", 15 0, v0x7e30b8e60_0; 1 drivers -S_0x1012679f0 .scope module, "dut" "neuron_parallel" 3 32, 4 1 0, S_0x1012716f0; - .timescale 0 0; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rst"; .port_info 2 /INPUT 1 "start"; @@ -39,784 +84,7187 @@ S_0x1012679f0 .scope module, "dut" "neuron_parallel" 3 32, 4 1 0, S_0x1012716f0; .port_info 6 /OUTPUT 16 "y"; .port_info 7 /OUTPUT 1 "busy"; .port_info 8 /OUTPUT 1 "done"; -P_0x101267b70 .param/l "ACC_WIDTH" 0 4 6, +C4<00000000000000000000000000101000>; -P_0x101267bb0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; -P_0x101267bf0 .param/l "FRAC_BITS" 0 4 3, +C4<00000000000000000000000000001000>; -P_0x101267c30 .param/l "GROUPS" 1 4 21, +C4<00000000000000000000000000001000>; -P_0x101267c70 .param/l "GROUP_INDEX_WIDTH" 1 4 22, +C4<00000000000000000000000000000011>; -P_0x101267cb0 .param/l "N_INPUTS" 0 4 4, +C4<00000000000000000000000001000000>; -P_0x101267cf0 .param/l "PARALLEL" 0 4 5, +C4<00000000000000000000000000001000>; -L_0x7e2c2c2a0 .functor BUFZ 16, v0x7e30b9040_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; -v0x7e30b7840_0 .net *"_ivl_0", 31 0, L_0x7e30b9720; 1 drivers -v0x7e30b78e0_0 .net *"_ivl_11", 31 0, L_0x7e30b9860; 1 drivers -v0x7e30b7980_0 .net *"_ivl_14", 31 0, L_0x7e30b9900; 1 drivers -L_0x7e28540e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b7a20_0 .net *"_ivl_17", 28 0, L_0x7e28540e8; 1 drivers -L_0x7e2854130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x7e30b7ac0_0 .net/2u *"_ivl_18", 31 0, L_0x7e2854130; 1 drivers -v0x7e30b7b60_0 .net *"_ivl_21", 31 0, L_0x7e30b99a0; 1 drivers -L_0x7e2854178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x7e30b7c00_0 .net/2u *"_ivl_22", 31 0, L_0x7e2854178; 1 drivers -v0x7e30b7ca0_0 .net *"_ivl_25", 31 0, L_0x7e30b9a40; 1 drivers -L_0x7e2854010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b7d40_0 .net *"_ivl_3", 28 0, L_0x7e2854010; 1 drivers -v0x7e30b7de0_0 .net *"_ivl_31", 0 0, L_0x7e2c857c0; 1 drivers -v0x7e30b7e80_0 .net *"_ivl_33", 23 0, L_0x7e2c85860; 1 drivers -v0x7e30b7f20_0 .net *"_ivl_36", 39 0, L_0x7e30baf80; 1 drivers -v0x7e30b8000_0 .net *"_ivl_38", 31 0, L_0x7e2c85900; 1 drivers -L_0x7e2854058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; -v0x7e30b80a0_0 .net/2u *"_ivl_4", 31 0, L_0x7e2854058; 1 drivers -L_0x7e2854400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b8140_0 .net *"_ivl_40", 7 0, L_0x7e2854400; 1 drivers -v0x7e30b81e0_0 .net *"_ivl_46", 31 0, L_0x7e2c859a0; 1 drivers -v0x7e30b8280_0 .net *"_ivl_7", 31 0, L_0x7e30b97c0; 1 drivers -L_0x7e28540a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; -v0x7e30b8320_0 .net/2u *"_ivl_8", 31 0, L_0x7e28540a0; 1 drivers -v0x7e30b83c0_0 .var/s "acc", 39 0; -v0x7e30b8460_0 .net/s "acc_next", 39 0, L_0x7e2c590e0; 1 drivers -v0x7e30b8500_0 .net/s "bias", 15 0, v0x7e30b9040_0; 1 drivers -v0x7e30b85a0_0 .net/s "bias_ext", 39 0, L_0x7e30baee0; 1 drivers -v0x7e30b8640_0 .net/s "bias_ext_small", 15 0, L_0x7e2c2c2a0; 1 drivers -v0x7e30b86e0_0 .var "busy", 0 0; -v0x7e30b8780_0 .net "clk", 0 0, v0x7e30b9180_0; 1 drivers -v0x7e30b8820_0 .var "done", 0 0; -v0x7e30b88c0_0 .net/s "final_acc", 39 0, L_0x7e2c59180; 1 drivers -v0x7e30b8960_0 .net/s "final_value", 39 0, L_0x7e30bb020; 1 drivers -v0x7e30b8a00_0 .var "group_index", 2 0; -v0x7e30b8aa0_0 .net "rst", 0 0, v0x7e30b9400_0; 1 drivers -v0x7e30b8b40_0 .net "start", 0 0, v0x7e30b94a0_0; 1 drivers -v0x7e30b8be0_0 .net/s "w_bus", 1023 0, v0x7e30b9540_0; 1 drivers -v0x7e30b8c80_0 .net/s "w_group", 127 0, L_0x7e2c84320; 1 drivers -v0x7e30b8d20_0 .net/s "x_bus", 1023 0, v0x7e30b95e0_0; 1 drivers -v0x7e30b8dc0_0 .net/s "x_group", 127 0, L_0x7e2c84280; 1 drivers -v0x7e30b8e60_0 .var/s "y", 15 0; -E_0x7e2c81380 .event posedge, v0x7e30b8780_0; -L_0x7e30b9720 .concat [ 3 29 0 0], v0x7e30b8a00_0, L_0x7e2854010; -L_0x7e30b97c0 .arith/mult 32, L_0x7e30b9720, L_0x7e2854058; -L_0x7e30b9860 .arith/mult 32, L_0x7e30b97c0, L_0x7e28540a0; -L_0x7e2c84280 .part/v v0x7e30b95e0_0, L_0x7e30b9860, 128; -L_0x7e30b9900 .concat [ 3 29 0 0], v0x7e30b8a00_0, L_0x7e28540e8; -L_0x7e30b99a0 .arith/mult 32, L_0x7e30b9900, L_0x7e2854130; -L_0x7e30b9a40 .arith/mult 32, L_0x7e30b99a0, L_0x7e2854178; -L_0x7e2c84320 .part/v v0x7e30b9540_0, L_0x7e30b9a40, 128; -L_0x7e2c857c0 .part L_0x7e2c2c2a0, 15, 1; -L_0x7e2c85860 .repeat 24, 24, L_0x7e2c857c0; -L_0x7e30baee0 .concat [ 16 24 0 0], L_0x7e2c2c2a0, L_0x7e2c85860; -L_0x7e2c85900 .part L_0x7e30baee0, 0, 32; -L_0x7e30baf80 .concat [ 8 32 0 0], L_0x7e2854400, L_0x7e2c85900; -L_0x7e2c59180 .arith/sum 40, L_0x7e2c590e0, L_0x7e30baf80; -L_0x7e2c859a0 .part L_0x7e2c59180, 8, 32; -L_0x7e30bb020 .extend/s 40, L_0x7e2c859a0; -S_0x101263710 .scope module, "u_mac8" "mac8" 4 51, 5 1 0, S_0x1012679f0; +P_0x102e203c0 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0x102e20400 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0x102e20440 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0x102e20480 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0x102e204c0 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0x102e20500 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2a8280_0 .net *"_ivl_0", 31 0, L_0xbab322800; 1 drivers +v0xbab2a8320_0 .net *"_ivl_11", 31 0, L_0xbaad169e0; 1 drivers +v0xbab2a83c0_0 .net *"_ivl_14", 31 0, L_0xbab3228a0; 1 drivers +L_0xbaa8780e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8460_0 .net *"_ivl_17", 28 0, L_0xbaa8780e8; 1 drivers +L_0xbaa878130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8500_0 .net/2u *"_ivl_18", 31 0, L_0xbaa878130; 1 drivers +v0xbab2a85a0_0 .net *"_ivl_21", 31 0, L_0xbaad16b20; 1 drivers +L_0xbaa878178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8640_0 .net/2u *"_ivl_22", 31 0, L_0xbaa878178; 1 drivers +v0xbab2a86e0_0 .net *"_ivl_25", 31 0, L_0xbaad16bc0; 1 drivers +v0xbab2a8780_0 .net *"_ivl_29", 0 0, L_0xbab27ae40; 1 drivers +L_0xbaa878010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8820_0 .net *"_ivl_3", 28 0, L_0xbaa878010; 1 drivers +v0xbab2a88c0_0 .net *"_ivl_31", 23 0, L_0xbaad17700; 1 drivers +L_0xbaa878058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8960_0 .net/2u *"_ivl_4", 31 0, L_0xbaa878058; 1 drivers +v0xbab2a8a00_0 .net *"_ivl_7", 31 0, L_0xbaad16a80; 1 drivers +L_0xbaa8780a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2a8aa0_0 .net/2u *"_ivl_8", 31 0, L_0xbaa8780a0; 1 drivers +v0xbab2a8b40_0 .var/s "acc", 39 0; +v0xbab2a8be0_0 .net/s "acc_next", 39 0, L_0xbab32c1e0; 1 drivers +v0xbab2a8c80_0 .net/s "bias", 15 0, L_0xbab27af80; 1 drivers +v0xbab2a8d20_0 .net/s "bias_ext", 39 0, L_0xbab32c280; 1 drivers +v0xbab2a8dc0_0 .var "busy", 0 0; +v0xbab2a8e60_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2a8f00_0 .var "done", 0 0; +v0xbab2a8fa0_0 .net/s "final_acc", 39 0, L_0xbab32c320; 1 drivers +v0xbab2a9040_0 .var "group_index", 2 0; +v0xbab2a90e0_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2a9180_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2a9220_0 .net/s "w_bus", 1023 0, L_0xbab27aee0; 1 drivers +v0xbab2a92c0_0 .net/s "w_group", 127 0, L_0xbab279ea0; 1 drivers +v0xbab2a9360_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2a9400_0 .net/s "x_group", 127 0, L_0xbab279e00; 1 drivers +v0xbab2a94a0_0 .var/s "y", 15 0; +E_0xbaad38ec0 .event posedge, v0xbab2a8e60_0; +L_0xbab322800 .concat [ 3 29 0 0], v0xbab2a9040_0, L_0xbaa878010; +L_0xbaad16a80 .arith/mult 32, L_0xbab322800, L_0xbaa878058; +L_0xbaad169e0 .arith/mult 32, L_0xbaad16a80, L_0xbaa8780a0; +L_0xbab279e00 .part/v o0xbaa846110, L_0xbaad169e0, 128; +L_0xbab3228a0 .concat [ 3 29 0 0], v0xbab2a9040_0, L_0xbaa8780e8; +L_0xbaad16b20 .arith/mult 32, L_0xbab3228a0, L_0xbaa878130; +L_0xbaad16bc0 .arith/mult 32, L_0xbaad16b20, L_0xbaa878178; +L_0xbab279ea0 .part/v L_0xbab27aee0, L_0xbaad16bc0, 128; +L_0xbab27ae40 .part L_0xbab27af80, 15, 1; +L_0xbaad17700 .repeat 24, 24, L_0xbab27ae40; +L_0xbab32c280 .concat [ 16 24 0 0], L_0xbab27af80, L_0xbaad17700; +L_0xbab32c320 .arith/sum 40, L_0xbab32c1e0, L_0xbab32c280; +S_0x102e20540 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0x102e22e30; .timescale 0 0; .port_info 0 /INPUT 128 "x_bus"; .port_info 1 /INPUT 128 "w_bus"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e3070b00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; -P_0x7e3070b40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; -v0x7e30b6c60_0 .net/s "acc_in", 39 0, v0x7e30b83c0_0; 1 drivers -v0x7e30b6d00_0 .net/s "acc_out", 39 0, L_0x7e2c590e0; alias, 1 drivers -v0x7e30b6da0_0 .net/s "m0", 39 0, L_0x7e2c58780; 1 drivers -v0x7e30b6e40_0 .net/s "m1", 39 0, L_0x7e2c58820; 1 drivers -v0x7e30b6ee0_0 .net/s "m2", 39 0, L_0x7e2c588c0; 1 drivers -v0x7e30b6f80_0 .net/s "m3", 39 0, L_0x7e2c58960; 1 drivers -v0x7e30b7020_0 .net/s "m4", 39 0, L_0x7e2c58a00; 1 drivers -v0x7e30b70c0_0 .net/s "m5", 39 0, L_0x7e2c58aa0; 1 drivers -v0x7e30b7160_0 .net/s "m6", 39 0, L_0x7e2c58b40; 1 drivers -v0x7e30b7200_0 .net/s "m7", 39 0, L_0x7e2c58be0; 1 drivers -v0x7e30b72a0_0 .net/s "s0", 39 0, L_0x7e2c58c80; 1 drivers -v0x7e30b7340_0 .net/s "s1", 39 0, L_0x7e2c58d20; 1 drivers -v0x7e30b73e0_0 .net/s "s2", 39 0, L_0x7e2c58dc0; 1 drivers -v0x7e30b7480_0 .net/s "s3", 39 0, L_0x7e2c58e60; 1 drivers -v0x7e30b7520_0 .net/s "s4", 39 0, L_0x7e2c58f00; 1 drivers -v0x7e30b75c0_0 .net/s "s5", 39 0, L_0x7e2c58fa0; 1 drivers -v0x7e30b7660_0 .net/s "sum", 39 0, L_0x7e2c59040; 1 drivers -v0x7e30b7700_0 .net/s "w_bus", 127 0, L_0x7e2c84320; alias, 1 drivers -v0x7e30b77a0_0 .net/s "x_bus", 127 0, L_0x7e2c84280; alias, 1 drivers -L_0x7e2c84500 .part L_0x7e2c84280, 0, 16; -L_0x7e2c845a0 .part L_0x7e2c84320, 0, 16; -L_0x7e2c84780 .part L_0x7e2c84280, 16, 16; -L_0x7e2c84820 .part L_0x7e2c84320, 16, 16; -L_0x7e2c84a00 .part L_0x7e2c84280, 32, 16; -L_0x7e2c84aa0 .part L_0x7e2c84320, 32, 16; -L_0x7e2c84c80 .part L_0x7e2c84280, 48, 16; -L_0x7e2c84d20 .part L_0x7e2c84320, 48, 16; -L_0x7e2c84f00 .part L_0x7e2c84280, 64, 16; -L_0x7e2c84fa0 .part L_0x7e2c84320, 64, 16; -L_0x7e2c85180 .part L_0x7e2c84280, 80, 16; -L_0x7e2c85220 .part L_0x7e2c84320, 80, 16; -L_0x7e2c85400 .part L_0x7e2c84280, 96, 16; -L_0x7e2c854a0 .part L_0x7e2c84320, 96, 16; -L_0x7e2c85680 .part L_0x7e2c84280, 112, 16; -L_0x7e2c85720 .part L_0x7e2c84320, 112, 16; -L_0x7e2c58c80 .arith/sum 40, L_0x7e2c58780, L_0x7e2c58820; -L_0x7e2c58d20 .arith/sum 40, L_0x7e2c588c0, L_0x7e2c58960; -L_0x7e2c58dc0 .arith/sum 40, L_0x7e2c58a00, L_0x7e2c58aa0; -L_0x7e2c58e60 .arith/sum 40, L_0x7e2c58b40, L_0x7e2c58be0; -L_0x7e2c58f00 .arith/sum 40, L_0x7e2c58c80, L_0x7e2c58d20; -L_0x7e2c58fa0 .arith/sum 40, L_0x7e2c58dc0, L_0x7e2c58e60; -L_0x7e2c59040 .arith/sum 40, L_0x7e2c58f00, L_0x7e2c58fa0; -L_0x7e2c590e0 .arith/sum 40, v0x7e30b83c0_0, L_0x7e2c59040; -S_0x101263890 .scope module, "mac0" "mac_unit" 5 33, 6 1 0, S_0x101263710; +P_0xbab294100 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab294140 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab294180 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2941c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab0b3e80_0 .net/s "acc_in", 39 0, v0xbab2a8b40_0; 1 drivers +v0xbab0b3f20_0 .net/s "acc_out", 39 0, L_0xbab32c1e0; alias, 1 drivers +v0xbab2a8000 .array "products", 7 0; +v0xbab2a8000_0 .net/s v0xbab2a8000 0, 39 0, L_0xbab322b20; 1 drivers +v0xbab2a8000_1 .net/s v0xbab2a8000 1, 39 0, L_0xbab322da0; 1 drivers +v0xbab2a8000_2 .net/s v0xbab2a8000 2, 39 0, L_0xbab323020; 1 drivers +v0xbab2a8000_3 .net/s v0xbab2a8000 3, 39 0, L_0xbab3232a0; 1 drivers +v0xbab2a8000_4 .net/s v0xbab2a8000 4, 39 0, L_0xbab323520; 1 drivers +v0xbab2a8000_5 .net/s v0xbab2a8000 5, 39 0, L_0xbab3237a0; 1 drivers +v0xbab2a8000_6 .net/s v0xbab2a8000 6, 39 0, L_0xbab323a20; 1 drivers +v0xbab2a8000_7 .net/s v0xbab2a8000 7, 39 0, L_0xbab323ca0; 1 drivers +v0xbab2a80a0 .array "tree", 31 0; +v0xbab2a80a0_0 .net/s v0xbab2a80a0 0, 39 0, L_0xbab068380; 1 drivers +v0xbab2a80a0_1 .net/s v0xbab2a80a0 1, 39 0, L_0xbab0683f0; 1 drivers +v0xbab2a80a0_2 .net/s v0xbab2a80a0 2, 39 0, L_0xbab068460; 1 drivers +v0xbab2a80a0_3 .net/s v0xbab2a80a0 3, 39 0, L_0xbab0684d0; 1 drivers +v0xbab2a80a0_4 .net/s v0xbab2a80a0 4, 39 0, L_0xbab068540; 1 drivers +v0xbab2a80a0_5 .net/s v0xbab2a80a0 5, 39 0, L_0xbab0685b0; 1 drivers +v0xbab2a80a0_6 .net/s v0xbab2a80a0 6, 39 0, L_0xbab068620; 1 drivers +v0xbab2a80a0_7 .net/s v0xbab2a80a0 7, 39 0, L_0xbab068690; 1 drivers +v0xbab2a80a0_8 .net/s v0xbab2a80a0 8, 39 0, L_0xbab323d40; 1 drivers +v0xbab2a80a0_9 .net/s v0xbab2a80a0 9, 39 0, L_0xbab323de0; 1 drivers +v0xbab2a80a0_10 .net/s v0xbab2a80a0 10, 39 0, L_0xbab323e80; 1 drivers +v0xbab2a80a0_11 .net/s v0xbab2a80a0 11, 39 0, L_0xbab323f20; 1 drivers +o0xbaa8457b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_12 .net/s v0xbab2a80a0 12, 39 0, o0xbaa8457b0; 0 drivers +o0xbaa8457e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_13 .net/s v0xbab2a80a0 13, 39 0, o0xbaa8457e0; 0 drivers +o0xbaa845810 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_14 .net/s v0xbab2a80a0 14, 39 0, o0xbaa845810; 0 drivers +o0xbaa845840 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_15 .net/s v0xbab2a80a0 15, 39 0, o0xbaa845840; 0 drivers +v0xbab2a80a0_16 .net/s v0xbab2a80a0 16, 39 0, L_0xbab32c000; 1 drivers +v0xbab2a80a0_17 .net/s v0xbab2a80a0 17, 39 0, L_0xbab32c0a0; 1 drivers +o0xbaa8458d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_18 .net/s v0xbab2a80a0 18, 39 0, o0xbaa8458d0; 0 drivers +o0xbaa845900 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_19 .net/s v0xbab2a80a0 19, 39 0, o0xbaa845900; 0 drivers +o0xbaa845930 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_20 .net/s v0xbab2a80a0 20, 39 0, o0xbaa845930; 0 drivers +o0xbaa845960 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_21 .net/s v0xbab2a80a0 21, 39 0, o0xbaa845960; 0 drivers +o0xbaa845990 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_22 .net/s v0xbab2a80a0 22, 39 0, o0xbaa845990; 0 drivers +o0xbaa8459c0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_23 .net/s v0xbab2a80a0 23, 39 0, o0xbaa8459c0; 0 drivers +v0xbab2a80a0_24 .net/s v0xbab2a80a0 24, 39 0, L_0xbab32c140; 1 drivers +o0xbaa845a20 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_25 .net/s v0xbab2a80a0 25, 39 0, o0xbaa845a20; 0 drivers +o0xbaa845a50 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_26 .net/s v0xbab2a80a0 26, 39 0, o0xbaa845a50; 0 drivers +o0xbaa845a80 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_27 .net/s v0xbab2a80a0 27, 39 0, o0xbaa845a80; 0 drivers +o0xbaa845ab0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_28 .net/s v0xbab2a80a0 28, 39 0, o0xbaa845ab0; 0 drivers +o0xbaa845ae0 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_29 .net/s v0xbab2a80a0 29, 39 0, o0xbaa845ae0; 0 drivers +o0xbaa845b10 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_30 .net/s v0xbab2a80a0 30, 39 0, o0xbaa845b10; 0 drivers +o0xbaa845b40 .functor BUFZ 40, c4; HiZ drive +v0xbab2a80a0_31 .net/s v0xbab2a80a0 31, 39 0, o0xbaa845b40; 0 drivers +v0xbab2a8140_0 .net/s "w_bus", 127 0, L_0xbab279ea0; alias, 1 drivers +v0xbab2a81e0_0 .net/s "x_bus", 127 0, L_0xbab279e00; alias, 1 drivers +L_0xbab279fe0 .part L_0xbab279e00, 0, 16; +L_0xbab27a080 .part L_0xbab279ea0, 0, 16; +L_0xbab27a1c0 .part L_0xbab279e00, 16, 16; +L_0xbab27a260 .part L_0xbab279ea0, 16, 16; +L_0xbab27a3a0 .part L_0xbab279e00, 32, 16; +L_0xbab27a440 .part L_0xbab279ea0, 32, 16; +L_0xbab27a580 .part L_0xbab279e00, 48, 16; +L_0xbab27a620 .part L_0xbab279ea0, 48, 16; +L_0xbab27a760 .part L_0xbab279e00, 64, 16; +L_0xbab27a800 .part L_0xbab279ea0, 64, 16; +L_0xbab27a940 .part L_0xbab279e00, 80, 16; +L_0xbab27a9e0 .part L_0xbab279ea0, 80, 16; +L_0xbab27ab20 .part L_0xbab279e00, 96, 16; +L_0xbab27abc0 .part L_0xbab279ea0, 96, 16; +L_0xbab27ad00 .part L_0xbab279e00, 112, 16; +L_0xbab27ada0 .part L_0xbab279ea0, 112, 16; +L_0xbab32c1e0 .arith/sum 40, v0xbab2a8b40_0, L_0xbab32c140; +S_0x102e20e70 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29c40 .param/l "i" 1 5 20, +C4<00>; +S_0x102e20ff0 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102e20e70; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x101271870_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9ae0; 1 drivers -v0x101271b50_0 .net/s *"_ivl_2", 31 0, L_0x7e30b9b80; 1 drivers -v0x10126f830_0 .net *"_ivl_7", 0 0, L_0x7e2c843c0; 1 drivers -v0x101271ff0_0 .net *"_ivl_9", 7 0, L_0x7e2c84460; 1 drivers -L_0x7e28541c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x101271e50_0 .net/s "acc_in", 39 0, L_0x7e28541c0; 1 drivers -v0x101271cb0_0 .net/s "acc_out", 39 0, L_0x7e2c58780; alias, 1 drivers -v0x1012714b0_0 .net/s "product", 31 0, L_0x7e30b9c20; 1 drivers -v0x1012712d0_0 .net/s "product_ext", 39 0, L_0x7e30b9cc0; 1 drivers -v0x101271090_0 .net/s "w", 15 0, L_0x7e2c845a0; 1 drivers -v0x7e30b4000_0 .net/s "x", 15 0, L_0x7e2c84500; 1 drivers -L_0x7e30b9ae0 .extend/s 32, L_0x7e2c84500; -L_0x7e30b9b80 .extend/s 32, L_0x7e2c845a0; -L_0x7e30b9c20 .arith/mult 32, L_0x7e30b9ae0, L_0x7e30b9b80; -L_0x7e2c843c0 .part L_0x7e30b9c20, 31, 1; -L_0x7e2c84460 .repeat 8, 8, L_0x7e2c843c0; -L_0x7e30b9cc0 .concat [ 32 8 0 0], L_0x7e30b9c20, L_0x7e2c84460; -L_0x7e2c58780 .arith/sum 40, L_0x7e28541c0, L_0x7e30b9cc0; -S_0x10125c9b0 .scope module, "mac1" "mac_unit" 5 43, 6 1 0, S_0x101263710; +P_0x102e24610 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x102e24650 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x102e24690 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b0c80_0 .net/s *"_ivl_0", 31 0, L_0xbab322940; 1 drivers +v0xbab0b0d20_0 .net/s *"_ivl_2", 31 0, L_0xbab3229e0; 1 drivers +v0xbab0b0dc0_0 .net *"_ivl_7", 0 0, L_0xbab279f40; 1 drivers +v0xbab0b0e60_0 .net *"_ivl_9", 7 0, L_0xbaad16d00; 1 drivers +L_0xbaa8781c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b0f00_0 .net/s "acc_in", 39 0, L_0xbaa8781c0; 1 drivers +v0xbab0b0fa0_0 .net/s "acc_out", 39 0, L_0xbab322b20; alias, 1 drivers +v0xbab0b1040_0 .net/s "product", 31 0, L_0xbaad16c60; 1 drivers +v0xbab0b10e0_0 .net/s "product_ext", 39 0, L_0xbab322a80; 1 drivers +v0xbab0b1180_0 .net/s "w", 15 0, L_0xbab27a080; 1 drivers +v0xbab0b1220_0 .net/s "x", 15 0, L_0xbab279fe0; 1 drivers +L_0xbab322940 .extend/s 32, L_0xbab279fe0; +L_0xbab3229e0 .extend/s 32, L_0xbab27a080; +L_0xbaad16c60 .arith/mult 32, L_0xbab322940, L_0xbab3229e0; +L_0xbab279f40 .part L_0xbaad16c60, 31, 1; +L_0xbaad16d00 .repeat 8, 8, L_0xbab279f40; +L_0xbab322a80 .concat [ 32 8 0 0], L_0xbaad16c60, L_0xbaad16d00; +L_0xbab322b20 .arith/sum 40, L_0xbaa8781c0, L_0xbab322a80; +S_0x102e1e940 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29c80 .param/l "i" 1 5 20, +C4<01>; +S_0x102e1eac0 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102e1e940; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b00c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b40a0_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9d60; 1 drivers -v0x7e30b4140_0 .net/s *"_ivl_2", 31 0, L_0x7e30b9e00; 1 drivers -v0x7e30b41e0_0 .net *"_ivl_7", 0 0, L_0x7e2c84640; 1 drivers -v0x7e30b4280_0 .net *"_ivl_9", 7 0, L_0x7e2c846e0; 1 drivers -L_0x7e2854208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b4320_0 .net/s "acc_in", 39 0, L_0x7e2854208; 1 drivers -v0x7e30b43c0_0 .net/s "acc_out", 39 0, L_0x7e2c58820; alias, 1 drivers -v0x7e30b4460_0 .net/s "product", 31 0, L_0x7e30b9ea0; 1 drivers -v0x7e30b4500_0 .net/s "product_ext", 39 0, L_0x7e30b9f40; 1 drivers -v0x7e30b45a0_0 .net/s "w", 15 0, L_0x7e2c84820; 1 drivers -v0x7e30b4640_0 .net/s "x", 15 0, L_0x7e2c84780; 1 drivers -L_0x7e30b9d60 .extend/s 32, L_0x7e2c84780; -L_0x7e30b9e00 .extend/s 32, L_0x7e2c84820; -L_0x7e30b9ea0 .arith/mult 32, L_0x7e30b9d60, L_0x7e30b9e00; -L_0x7e2c84640 .part L_0x7e30b9ea0, 31, 1; -L_0x7e2c846e0 .repeat 8, 8, L_0x7e2c84640; -L_0x7e30b9f40 .concat [ 32 8 0 0], L_0x7e30b9ea0, L_0x7e2c846e0; -L_0x7e2c58820 .arith/sum 40, L_0x7e2854208, L_0x7e30b9f40; -S_0x10125cb30 .scope module, "mac2" "mac_unit" 5 53, 6 1 0, S_0x101263710; +P_0x102e30d20 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x102e30d60 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x102e30da0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b12c0_0 .net/s *"_ivl_0", 31 0, L_0xbab322bc0; 1 drivers +v0xbab0b1360_0 .net/s *"_ivl_2", 31 0, L_0xbab322c60; 1 drivers +v0xbab0b1400_0 .net *"_ivl_7", 0 0, L_0xbab27a120; 1 drivers +v0xbab0b14a0_0 .net *"_ivl_9", 7 0, L_0xbaad16e40; 1 drivers +L_0xbaa878208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b1540_0 .net/s "acc_in", 39 0, L_0xbaa878208; 1 drivers +v0xbab0b15e0_0 .net/s "acc_out", 39 0, L_0xbab322da0; alias, 1 drivers +v0xbab0b1680_0 .net/s "product", 31 0, L_0xbaad16da0; 1 drivers +v0xbab0b1720_0 .net/s "product_ext", 39 0, L_0xbab322d00; 1 drivers +v0xbab0b17c0_0 .net/s "w", 15 0, L_0xbab27a260; 1 drivers +v0xbab0b1860_0 .net/s "x", 15 0, L_0xbab27a1c0; 1 drivers +L_0xbab322bc0 .extend/s 32, L_0xbab27a1c0; +L_0xbab322c60 .extend/s 32, L_0xbab27a260; +L_0xbaad16da0 .arith/mult 32, L_0xbab322bc0, L_0xbab322c60; +L_0xbab27a120 .part L_0xbaad16da0, 31, 1; +L_0xbaad16e40 .repeat 8, 8, L_0xbab27a120; +L_0xbab322d00 .concat [ 32 8 0 0], L_0xbaad16da0, L_0xbaad16e40; +L_0xbab322da0 .arith/sum 40, L_0xbaa878208, L_0xbab322d00; +S_0x102e169a0 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29cc0 .param/l "i" 1 5 20, +C4<010>; +S_0x102e16b20 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102e169a0; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b01c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b46e0_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9fe0; 1 drivers -v0x7e30b4780_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba080; 1 drivers -v0x7e30b4820_0 .net *"_ivl_7", 0 0, L_0x7e2c848c0; 1 drivers -v0x7e30b48c0_0 .net *"_ivl_9", 7 0, L_0x7e2c84960; 1 drivers -L_0x7e2854250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b4960_0 .net/s "acc_in", 39 0, L_0x7e2854250; 1 drivers -v0x7e30b4a00_0 .net/s "acc_out", 39 0, L_0x7e2c588c0; alias, 1 drivers -v0x7e30b4aa0_0 .net/s "product", 31 0, L_0x7e30ba120; 1 drivers -v0x7e30b4b40_0 .net/s "product_ext", 39 0, L_0x7e30ba1c0; 1 drivers -v0x7e30b4be0_0 .net/s "w", 15 0, L_0x7e2c84aa0; 1 drivers -v0x7e30b4c80_0 .net/s "x", 15 0, L_0x7e2c84a00; 1 drivers -L_0x7e30b9fe0 .extend/s 32, L_0x7e2c84a00; -L_0x7e30ba080 .extend/s 32, L_0x7e2c84aa0; -L_0x7e30ba120 .arith/mult 32, L_0x7e30b9fe0, L_0x7e30ba080; -L_0x7e2c848c0 .part L_0x7e30ba120, 31, 1; -L_0x7e2c84960 .repeat 8, 8, L_0x7e2c848c0; -L_0x7e30ba1c0 .concat [ 32 8 0 0], L_0x7e30ba120, L_0x7e2c84960; -L_0x7e2c588c0 .arith/sum 40, L_0x7e2854250, L_0x7e30ba1c0; -S_0x10125f110 .scope module, "mac3" "mac_unit" 5 63, 6 1 0, S_0x101263710; +P_0x102e2fbc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x102e2fc00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x102e2fc40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b1900_0 .net/s *"_ivl_0", 31 0, L_0xbab322e40; 1 drivers +v0xbab0b19a0_0 .net/s *"_ivl_2", 31 0, L_0xbab322ee0; 1 drivers +v0xbab0b1a40_0 .net *"_ivl_7", 0 0, L_0xbab27a300; 1 drivers +v0xbab0b1ae0_0 .net *"_ivl_9", 7 0, L_0xbaad16f80; 1 drivers +L_0xbaa878250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b1b80_0 .net/s "acc_in", 39 0, L_0xbaa878250; 1 drivers +v0xbab0b1c20_0 .net/s "acc_out", 39 0, L_0xbab323020; alias, 1 drivers +v0xbab0b1cc0_0 .net/s "product", 31 0, L_0xbaad16ee0; 1 drivers +v0xbab0b1d60_0 .net/s "product_ext", 39 0, L_0xbab322f80; 1 drivers +v0xbab0b1e00_0 .net/s "w", 15 0, L_0xbab27a440; 1 drivers +v0xbab0b1ea0_0 .net/s "x", 15 0, L_0xbab27a3a0; 1 drivers +L_0xbab322e40 .extend/s 32, L_0xbab27a3a0; +L_0xbab322ee0 .extend/s 32, L_0xbab27a440; +L_0xbaad16ee0 .arith/mult 32, L_0xbab322e40, L_0xbab322ee0; +L_0xbab27a300 .part L_0xbaad16ee0, 31, 1; +L_0xbaad16f80 .repeat 8, 8, L_0xbab27a300; +L_0xbab322f80 .concat [ 32 8 0 0], L_0xbaad16ee0, L_0xbaad16f80; +L_0xbab323020 .arith/sum 40, L_0xbaa878250, L_0xbab322f80; +S_0xbab2a4000 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29d00 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2a4180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a4000; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b02c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b4d20_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba260; 1 drivers -v0x7e30b4dc0_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba300; 1 drivers -v0x7e30b4e60_0 .net *"_ivl_7", 0 0, L_0x7e2c84b40; 1 drivers -v0x7e30b4f00_0 .net *"_ivl_9", 7 0, L_0x7e2c84be0; 1 drivers -L_0x7e2854298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b4fa0_0 .net/s "acc_in", 39 0, L_0x7e2854298; 1 drivers -v0x7e30b5040_0 .net/s "acc_out", 39 0, L_0x7e2c58960; alias, 1 drivers -v0x7e30b50e0_0 .net/s "product", 31 0, L_0x7e30ba3a0; 1 drivers -v0x7e30b5180_0 .net/s "product_ext", 39 0, L_0x7e30ba440; 1 drivers -v0x7e30b5220_0 .net/s "w", 15 0, L_0x7e2c84d20; 1 drivers -v0x7e30b52c0_0 .net/s "x", 15 0, L_0x7e2c84c80; 1 drivers -L_0x7e30ba260 .extend/s 32, L_0x7e2c84c80; -L_0x7e30ba300 .extend/s 32, L_0x7e2c84d20; -L_0x7e30ba3a0 .arith/mult 32, L_0x7e30ba260, L_0x7e30ba300; -L_0x7e2c84b40 .part L_0x7e30ba3a0, 31, 1; -L_0x7e2c84be0 .repeat 8, 8, L_0x7e2c84b40; -L_0x7e30ba440 .concat [ 32 8 0 0], L_0x7e30ba3a0, L_0x7e2c84be0; -L_0x7e2c58960 .arith/sum 40, L_0x7e2854298, L_0x7e30ba440; -S_0x10125f290 .scope module, "mac4" "mac_unit" 5 73, 6 1 0, S_0x101263710; +P_0xbaad4c000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b1f40_0 .net/s *"_ivl_0", 31 0, L_0xbab3230c0; 1 drivers +v0xbab0b1fe0_0 .net/s *"_ivl_2", 31 0, L_0xbab323160; 1 drivers +v0xbab0b2080_0 .net *"_ivl_7", 0 0, L_0xbab27a4e0; 1 drivers +v0xbab0b2120_0 .net *"_ivl_9", 7 0, L_0xbaad170c0; 1 drivers +L_0xbaa878298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b21c0_0 .net/s "acc_in", 39 0, L_0xbaa878298; 1 drivers +v0xbab0b2260_0 .net/s "acc_out", 39 0, L_0xbab3232a0; alias, 1 drivers +v0xbab0b2300_0 .net/s "product", 31 0, L_0xbaad17020; 1 drivers +v0xbab0b23a0_0 .net/s "product_ext", 39 0, L_0xbab323200; 1 drivers +v0xbab0b2440_0 .net/s "w", 15 0, L_0xbab27a620; 1 drivers +v0xbab0b24e0_0 .net/s "x", 15 0, L_0xbab27a580; 1 drivers +L_0xbab3230c0 .extend/s 32, L_0xbab27a580; +L_0xbab323160 .extend/s 32, L_0xbab27a620; +L_0xbaad17020 .arith/mult 32, L_0xbab3230c0, L_0xbab323160; +L_0xbab27a4e0 .part L_0xbaad17020, 31, 1; +L_0xbaad170c0 .repeat 8, 8, L_0xbab27a4e0; +L_0xbab323200 .concat [ 32 8 0 0], L_0xbaad17020, L_0xbaad170c0; +L_0xbab3232a0 .arith/sum 40, L_0xbaa878298, L_0xbab323200; +S_0xbab2a4300 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29d80 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2a4480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a4300; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b5360_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba4e0; 1 drivers -v0x7e30b5400_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba580; 1 drivers -v0x7e30b54a0_0 .net *"_ivl_7", 0 0, L_0x7e2c84dc0; 1 drivers -v0x7e30b5540_0 .net *"_ivl_9", 7 0, L_0x7e2c84e60; 1 drivers -L_0x7e28542e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b55e0_0 .net/s "acc_in", 39 0, L_0x7e28542e0; 1 drivers -v0x7e30b5680_0 .net/s "acc_out", 39 0, L_0x7e2c58a00; alias, 1 drivers -v0x7e30b5720_0 .net/s "product", 31 0, L_0x7e30ba620; 1 drivers -v0x7e30b57c0_0 .net/s "product_ext", 39 0, L_0x7e30ba6c0; 1 drivers -v0x7e30b5860_0 .net/s "w", 15 0, L_0x7e2c84fa0; 1 drivers -v0x7e30b5900_0 .net/s "x", 15 0, L_0x7e2c84f00; 1 drivers -L_0x7e30ba4e0 .extend/s 32, L_0x7e2c84f00; -L_0x7e30ba580 .extend/s 32, L_0x7e2c84fa0; -L_0x7e30ba620 .arith/mult 32, L_0x7e30ba4e0, L_0x7e30ba580; -L_0x7e2c84dc0 .part L_0x7e30ba620, 31, 1; -L_0x7e2c84e60 .repeat 8, 8, L_0x7e2c84dc0; -L_0x7e30ba6c0 .concat [ 32 8 0 0], L_0x7e30ba620, L_0x7e2c84e60; -L_0x7e2c58a00 .arith/sum 40, L_0x7e28542e0, L_0x7e30ba6c0; -S_0x101272590 .scope module, "mac5" "mac_unit" 5 83, 6 1 0, S_0x101263710; +P_0xbaad4c0c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b2580_0 .net/s *"_ivl_0", 31 0, L_0xbab323340; 1 drivers +v0xbab0b2620_0 .net/s *"_ivl_2", 31 0, L_0xbab3233e0; 1 drivers +v0xbab0b26c0_0 .net *"_ivl_7", 0 0, L_0xbab27a6c0; 1 drivers +v0xbab0b2760_0 .net *"_ivl_9", 7 0, L_0xbaad17200; 1 drivers +L_0xbaa8782e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b2800_0 .net/s "acc_in", 39 0, L_0xbaa8782e0; 1 drivers +v0xbab0b28a0_0 .net/s "acc_out", 39 0, L_0xbab323520; alias, 1 drivers +v0xbab0b2940_0 .net/s "product", 31 0, L_0xbaad17160; 1 drivers +v0xbab0b29e0_0 .net/s "product_ext", 39 0, L_0xbab323480; 1 drivers +v0xbab0b2a80_0 .net/s "w", 15 0, L_0xbab27a800; 1 drivers +v0xbab0b2b20_0 .net/s "x", 15 0, L_0xbab27a760; 1 drivers +L_0xbab323340 .extend/s 32, L_0xbab27a760; +L_0xbab3233e0 .extend/s 32, L_0xbab27a800; +L_0xbaad17160 .arith/mult 32, L_0xbab323340, L_0xbab3233e0; +L_0xbab27a6c0 .part L_0xbaad17160, 31, 1; +L_0xbaad17200 .repeat 8, 8, L_0xbab27a6c0; +L_0xbab323480 .concat [ 32 8 0 0], L_0xbaad17160, L_0xbaad17200; +L_0xbab323520 .arith/sum 40, L_0xbaa8782e0, L_0xbab323480; +S_0xbab2a4600 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29dc0 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2a4780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a4600; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b03c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b59a0_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba760; 1 drivers -v0x7e30b5a40_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba800; 1 drivers -v0x7e30b5ae0_0 .net *"_ivl_7", 0 0, L_0x7e2c85040; 1 drivers -v0x7e30b5b80_0 .net *"_ivl_9", 7 0, L_0x7e2c850e0; 1 drivers -L_0x7e2854328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b5c20_0 .net/s "acc_in", 39 0, L_0x7e2854328; 1 drivers -v0x7e30b5cc0_0 .net/s "acc_out", 39 0, L_0x7e2c58aa0; alias, 1 drivers -v0x7e30b5d60_0 .net/s "product", 31 0, L_0x7e30ba8a0; 1 drivers -v0x7e30b5e00_0 .net/s "product_ext", 39 0, L_0x7e30ba940; 1 drivers -v0x7e30b5ea0_0 .net/s "w", 15 0, L_0x7e2c85220; 1 drivers -v0x7e30b5f40_0 .net/s "x", 15 0, L_0x7e2c85180; 1 drivers -L_0x7e30ba760 .extend/s 32, L_0x7e2c85180; -L_0x7e30ba800 .extend/s 32, L_0x7e2c85220; -L_0x7e30ba8a0 .arith/mult 32, L_0x7e30ba760, L_0x7e30ba800; -L_0x7e2c85040 .part L_0x7e30ba8a0, 31, 1; -L_0x7e2c850e0 .repeat 8, 8, L_0x7e2c85040; -L_0x7e30ba940 .concat [ 32 8 0 0], L_0x7e30ba8a0, L_0x7e2c850e0; -L_0x7e2c58aa0 .arith/sum 40, L_0x7e2854328, L_0x7e30ba940; -S_0x1012700f0 .scope module, "mac6" "mac_unit" 5 93, 6 1 0, S_0x101263710; +P_0xbaad4c180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c1c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b2bc0_0 .net/s *"_ivl_0", 31 0, L_0xbab3235c0; 1 drivers +v0xbab0b2c60_0 .net/s *"_ivl_2", 31 0, L_0xbab323660; 1 drivers +v0xbab0b2d00_0 .net *"_ivl_7", 0 0, L_0xbab27a8a0; 1 drivers +v0xbab0b2da0_0 .net *"_ivl_9", 7 0, L_0xbaad17340; 1 drivers +L_0xbaa878328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b2e40_0 .net/s "acc_in", 39 0, L_0xbaa878328; 1 drivers +v0xbab0b2ee0_0 .net/s "acc_out", 39 0, L_0xbab3237a0; alias, 1 drivers +v0xbab0b2f80_0 .net/s "product", 31 0, L_0xbaad172a0; 1 drivers +v0xbab0b3020_0 .net/s "product_ext", 39 0, L_0xbab323700; 1 drivers +v0xbab0b30c0_0 .net/s "w", 15 0, L_0xbab27a9e0; 1 drivers +v0xbab0b3160_0 .net/s "x", 15 0, L_0xbab27a940; 1 drivers +L_0xbab3235c0 .extend/s 32, L_0xbab27a940; +L_0xbab323660 .extend/s 32, L_0xbab27a9e0; +L_0xbaad172a0 .arith/mult 32, L_0xbab3235c0, L_0xbab323660; +L_0xbab27a8a0 .part L_0xbaad172a0, 31, 1; +L_0xbaad17340 .repeat 8, 8, L_0xbab27a8a0; +L_0xbab323700 .concat [ 32 8 0 0], L_0xbaad172a0, L_0xbaad17340; +L_0xbab3237a0 .arith/sum 40, L_0xbaa878328, L_0xbab323700; +S_0xbab2a4900 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29e00 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2a4a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a4900; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b04c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b0500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b5fe0_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba9e0; 1 drivers -v0x7e30b6080_0 .net/s *"_ivl_2", 31 0, L_0x7e30baa80; 1 drivers -v0x7e30b6120_0 .net *"_ivl_7", 0 0, L_0x7e2c852c0; 1 drivers -v0x7e30b61c0_0 .net *"_ivl_9", 7 0, L_0x7e2c85360; 1 drivers -L_0x7e2854370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b6260_0 .net/s "acc_in", 39 0, L_0x7e2854370; 1 drivers -v0x7e30b6300_0 .net/s "acc_out", 39 0, L_0x7e2c58b40; alias, 1 drivers -v0x7e30b63a0_0 .net/s "product", 31 0, L_0x7e30bab20; 1 drivers -v0x7e30b6440_0 .net/s "product_ext", 39 0, L_0x7e30babc0; 1 drivers -v0x7e30b64e0_0 .net/s "w", 15 0, L_0x7e2c854a0; 1 drivers -v0x7e30b6580_0 .net/s "x", 15 0, L_0x7e2c85400; 1 drivers -L_0x7e30ba9e0 .extend/s 32, L_0x7e2c85400; -L_0x7e30baa80 .extend/s 32, L_0x7e2c854a0; -L_0x7e30bab20 .arith/mult 32, L_0x7e30ba9e0, L_0x7e30baa80; -L_0x7e2c852c0 .part L_0x7e30bab20, 31, 1; -L_0x7e2c85360 .repeat 8, 8, L_0x7e2c852c0; -L_0x7e30babc0 .concat [ 32 8 0 0], L_0x7e30bab20, L_0x7e2c85360; -L_0x7e2c58b40 .arith/sum 40, L_0x7e2854370, L_0x7e30babc0; -S_0x101270270 .scope module, "mac7" "mac_unit" 5 103, 6 1 0, S_0x101263710; +P_0xbaad4c240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c2c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b3200_0 .net/s *"_ivl_0", 31 0, L_0xbab323840; 1 drivers +v0xbab0b32a0_0 .net/s *"_ivl_2", 31 0, L_0xbab3238e0; 1 drivers +v0xbab0b3340_0 .net *"_ivl_7", 0 0, L_0xbab27aa80; 1 drivers +v0xbab0b33e0_0 .net *"_ivl_9", 7 0, L_0xbaad17480; 1 drivers +L_0xbaa878370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b3480_0 .net/s "acc_in", 39 0, L_0xbaa878370; 1 drivers +v0xbab0b3520_0 .net/s "acc_out", 39 0, L_0xbab323a20; alias, 1 drivers +v0xbab0b35c0_0 .net/s "product", 31 0, L_0xbaad173e0; 1 drivers +v0xbab0b3660_0 .net/s "product_ext", 39 0, L_0xbab323980; 1 drivers +v0xbab0b3700_0 .net/s "w", 15 0, L_0xbab27abc0; 1 drivers +v0xbab0b37a0_0 .net/s "x", 15 0, L_0xbab27ab20; 1 drivers +L_0xbab323840 .extend/s 32, L_0xbab27ab20; +L_0xbab3238e0 .extend/s 32, L_0xbab27abc0; +L_0xbaad173e0 .arith/mult 32, L_0xbab323840, L_0xbab3238e0; +L_0xbab27aa80 .part L_0xbaad173e0, 31, 1; +L_0xbaad17480 .repeat 8, 8, L_0xbab27aa80; +L_0xbab323980 .concat [ 32 8 0 0], L_0xbaad173e0, L_0xbaad17480; +L_0xbab323a20 .arith/sum 40, L_0xbaa878370, L_0xbab323980; +S_0xbab2a4c00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29e40 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2a4d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a4c00; .timescale 0 0; .port_info 0 /INPUT 16 "x"; .port_info 1 /INPUT 16 "w"; .port_info 2 /INPUT 40 "acc_in"; .port_info 3 /OUTPUT 40 "acc_out"; -P_0x7e30b0540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; -P_0x7e30b0580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; -P_0x7e30b05c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; -v0x7e30b6620_0 .net/s *"_ivl_0", 31 0, L_0x7e30bac60; 1 drivers -v0x7e30b66c0_0 .net/s *"_ivl_2", 31 0, L_0x7e30bad00; 1 drivers -v0x7e30b6760_0 .net *"_ivl_7", 0 0, L_0x7e2c85540; 1 drivers -v0x7e30b6800_0 .net *"_ivl_9", 7 0, L_0x7e2c855e0; 1 drivers -L_0x7e28543b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x7e30b68a0_0 .net/s "acc_in", 39 0, L_0x7e28543b8; 1 drivers -v0x7e30b6940_0 .net/s "acc_out", 39 0, L_0x7e2c58be0; alias, 1 drivers -v0x7e30b69e0_0 .net/s "product", 31 0, L_0x7e30bada0; 1 drivers -v0x7e30b6a80_0 .net/s "product_ext", 39 0, L_0x7e30bae40; 1 drivers -v0x7e30b6b20_0 .net/s "w", 15 0, L_0x7e2c85720; 1 drivers -v0x7e30b6bc0_0 .net/s "x", 15 0, L_0x7e2c85680; 1 drivers -L_0x7e30bac60 .extend/s 32, L_0x7e2c85680; -L_0x7e30bad00 .extend/s 32, L_0x7e2c85720; -L_0x7e30bada0 .arith/mult 32, L_0x7e30bac60, L_0x7e30bad00; -L_0x7e2c85540 .part L_0x7e30bada0, 31, 1; -L_0x7e2c855e0 .repeat 8, 8, L_0x7e2c85540; -L_0x7e30bae40 .concat [ 32 8 0 0], L_0x7e30bada0, L_0x7e2c855e0; -L_0x7e2c58be0 .arith/sum 40, L_0x7e28543b8, L_0x7e30bae40; -S_0x7e2ca0000 .scope function.vec4.u16, "q8_8" "q8_8" 3 53, 3 53 0, S_0x1012716f0; +P_0xbaad4c300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab0b3840_0 .net/s *"_ivl_0", 31 0, L_0xbab323ac0; 1 drivers +v0xbab0b38e0_0 .net/s *"_ivl_2", 31 0, L_0xbab323b60; 1 drivers +v0xbab0b3980_0 .net *"_ivl_7", 0 0, L_0xbab27ac60; 1 drivers +v0xbab0b3a20_0 .net *"_ivl_9", 7 0, L_0xbaad175c0; 1 drivers +L_0xbaa8783b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab0b3ac0_0 .net/s "acc_in", 39 0, L_0xbaa8783b8; 1 drivers +v0xbab0b3b60_0 .net/s "acc_out", 39 0, L_0xbab323ca0; alias, 1 drivers +v0xbab0b3c00_0 .net/s "product", 31 0, L_0xbaad17520; 1 drivers +v0xbab0b3ca0_0 .net/s "product_ext", 39 0, L_0xbab323c00; 1 drivers +v0xbab0b3d40_0 .net/s "w", 15 0, L_0xbab27ada0; 1 drivers +v0xbab0b3de0_0 .net/s "x", 15 0, L_0xbab27ad00; 1 drivers +L_0xbab323ac0 .extend/s 32, L_0xbab27ad00; +L_0xbab323b60 .extend/s 32, L_0xbab27ada0; +L_0xbaad17520 .arith/mult 32, L_0xbab323ac0, L_0xbab323b60; +L_0xbab27ac60 .part L_0xbaad17520, 31, 1; +L_0xbaad175c0 .repeat 8, 8, L_0xbab27ac60; +L_0xbab323c00 .concat [ 32 8 0 0], L_0xbaad17520, L_0xbaad175c0; +L_0xbab323ca0 .arith/sum 40, L_0xbaa8783b8, L_0xbab323c00; +S_0xbab2a4f00 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29d40 .param/l "i" 1 5 80, +C4<00>; +L_0xbab068380 .functor BUFZ 40, L_0xbab322b20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5080 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29e80 .param/l "i" 1 5 80, +C4<01>; +L_0xbab0683f0 .functor BUFZ 40, L_0xbab322da0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5200 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29ec0 .param/l "i" 1 5 80, +C4<010>; +L_0xbab068460 .functor BUFZ 40, L_0xbab323020, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5380 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29f00 .param/l "i" 1 5 80, +C4<011>; +L_0xbab0684d0 .functor BUFZ 40, L_0xbab3232a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5500 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29f40 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab068540 .functor BUFZ 40, L_0xbab323520, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5680 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29f80 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab0685b0 .functor BUFZ 40, L_0xbab3237a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5800 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad29fc0 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab068620 .functor BUFZ 40, L_0xbab323a20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5980 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad2a000 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab068690 .functor BUFZ 40, L_0xbab323ca0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2a5b00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad2a040 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2a5c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2a5b00; + .timescale 0 0; +P_0xbaad2a080 .param/l "node" 1 5 94, +C4<00>; +L_0xbab323d40 .arith/sum 40, L_0xbab068380, L_0xbab0683f0; +S_0xbab2a5e00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2a5b00; + .timescale 0 0; +P_0xbaad2a0c0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab323de0 .arith/sum 40, L_0xbab068460, L_0xbab0684d0; +S_0xbab2a5f80 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2a5b00; + .timescale 0 0; +P_0xbaad2a100 .param/l "node" 1 5 94, +C4<010>; +L_0xbab323e80 .arith/sum 40, L_0xbab068540, L_0xbab0685b0; +S_0xbab2a6100 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2a5b00; + .timescale 0 0; +P_0xbaad2a140 .param/l "node" 1 5 94, +C4<011>; +L_0xbab323f20 .arith/sum 40, L_0xbab068620, L_0xbab068690; +S_0xbab2a6280 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad2a180 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2a6400 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2a6280; + .timescale 0 0; +P_0xbaad2a1c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32c000 .arith/sum 40, L_0xbab323d40, L_0xbab323de0; +S_0xbab2a6580 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2a6280; + .timescale 0 0; +P_0xbaad2a200 .param/l "node" 1 5 94, +C4<01>; +L_0xbab32c0a0 .arith/sum 40, L_0xbab323e80, L_0xbab323f20; +S_0xbab2a6700 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0x102e20540; + .timescale 0 0; +P_0xbaad2a240 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2a6880 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2a6700; + .timescale 0 0; +P_0xbaad2a280 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32c140 .arith/sum 40, L_0xbab32c000, L_0xbab32c0a0; +S_0xbab2a6a00 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad2a300 .param/l "n" 1 3 34, +C4<01>; +S_0xbab2a6b80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2a6a00; .timescale -9 -12; -; Variable q8_8 is vec4 return value of scope S_0x7e2ca0000 -v0x7e30b8fa0_0 .var/real "value", 0 0; -TD_tb.q8_8 ; - %load/real v0x7e30b8fa0_0; - %pushi/real 1073741824, 4074; load=256.000 - %mul/wr; - %vpi_func 3 56 "$rtoi" 32, W<0,r> {0 1 0}; - %pad/s 16; - %ret/vec4 0, 0, 16; Assign to q8_8 (store_vec4_to_lval) - %end; -S_0x7e2ca0180 .scope task, "run_neuron" "run_neuron" 3 63, 3 63 0, S_0x1012716f0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e35800 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0x102e35840 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0x102e35880 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0x102e358c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0x102e35900 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0x102e35940 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2b8b40_0 .net *"_ivl_0", 31 0, L_0xbab32c3c0; 1 drivers +v0xbab2b8be0_0 .net *"_ivl_11", 31 0, L_0xbaad17840; 1 drivers +v0xbab2b8c80_0 .net *"_ivl_14", 31 0, L_0xbab32c460; 1 drivers +L_0xbaa8784d8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2b8d20_0 .net *"_ivl_17", 28 0, L_0xbaa8784d8; 1 drivers +L_0xbaa878520 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2b8dc0_0 .net/2u *"_ivl_18", 31 0, L_0xbaa878520; 1 drivers +v0xbab2b8e60_0 .net *"_ivl_21", 31 0, L_0xbaad178e0; 1 drivers +L_0xbaa878568 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2b8f00_0 .net/2u *"_ivl_22", 31 0, L_0xbaa878568; 1 drivers +v0xbab2b8fa0_0 .net *"_ivl_25", 31 0, L_0xbaad17980; 1 drivers +v0xbab2b9040_0 .net *"_ivl_29", 0 0, L_0xbab22fb60; 1 drivers +L_0xbaa878400 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2b90e0_0 .net *"_ivl_3", 28 0, L_0xbaa878400; 1 drivers +v0xbab2b9180_0 .net *"_ivl_31", 23 0, L_0xbaad54500; 1 drivers +L_0xbaa878448 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2b9220_0 .net/2u *"_ivl_4", 31 0, L_0xbaa878448; 1 drivers +v0xbab2b92c0_0 .net *"_ivl_7", 31 0, L_0xbaad177a0; 1 drivers +L_0xbaa878490 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2b9360_0 .net/2u *"_ivl_8", 31 0, L_0xbaa878490; 1 drivers +v0xbab2b9400_0 .var/s "acc", 39 0; +v0xbab2b94a0_0 .net/s "acc_next", 39 0, L_0xbab32dd60; 1 drivers +v0xbab2b9540_0 .net/s "bias", 15 0, L_0xbab22d400; 1 drivers +v0xbab2b95e0_0 .net/s "bias_ext", 39 0, L_0xbab32de00; 1 drivers +v0xbab2b9680_0 .var "busy", 0 0; +v0xbab2b9720_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2b97c0_0 .var "done", 0 0; +v0xbab2b9860_0 .net/s "final_acc", 39 0, L_0xbab32dea0; 1 drivers +v0xbab2b9900_0 .var "group_index", 2 0; +v0xbab2b99a0_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2b9a40_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2b9ae0_0 .net/s "w_bus", 1023 0, L_0xbab22f660; 1 drivers +v0xbab2b9b80_0 .net/s "w_group", 127 0, L_0xbab27b0c0; 1 drivers +v0xbab2b9c20_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2b9cc0_0 .net/s "x_group", 127 0, L_0xbab27b020; 1 drivers +v0xbab2b9d60_0 .var/s "y", 15 0; +L_0xbab32c3c0 .concat [ 3 29 0 0], v0xbab2b9900_0, L_0xbaa878400; +L_0xbaad177a0 .arith/mult 32, L_0xbab32c3c0, L_0xbaa878448; +L_0xbaad17840 .arith/mult 32, L_0xbaad177a0, L_0xbaa878490; +L_0xbab27b020 .part/v o0xbaa846110, L_0xbaad17840, 128; +L_0xbab32c460 .concat [ 3 29 0 0], v0xbab2b9900_0, L_0xbaa8784d8; +L_0xbaad178e0 .arith/mult 32, L_0xbab32c460, L_0xbaa878520; +L_0xbaad17980 .arith/mult 32, L_0xbaad178e0, L_0xbaa878568; +L_0xbab27b0c0 .part/v L_0xbab22f660, L_0xbaad17980, 128; +L_0xbab22fb60 .part L_0xbab22d400, 15, 1; +L_0xbaad54500 .repeat 24, 24, L_0xbab22fb60; +L_0xbab32de00 .concat [ 16 24 0 0], L_0xbab22d400, L_0xbaad54500; +L_0xbab32dea0 .arith/sum 40, L_0xbab32dd60, L_0xbab32de00; +S_0xbab2a6d00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2a6b80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab294400 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab294440 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab294480 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2944c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2b8780_0 .net/s "acc_in", 39 0, v0xbab2b9400_0; 1 drivers +v0xbab2b8820_0 .net/s "acc_out", 39 0, L_0xbab32dd60; alias, 1 drivers +v0xbab2b88c0 .array "products", 7 0; +v0xbab2b88c0_0 .net/s v0xbab2b88c0 0, 39 0, L_0xbab32c6e0; 1 drivers +v0xbab2b88c0_1 .net/s v0xbab2b88c0 1, 39 0, L_0xbab32c960; 1 drivers +v0xbab2b88c0_2 .net/s v0xbab2b88c0 2, 39 0, L_0xbab32cbe0; 1 drivers +v0xbab2b88c0_3 .net/s v0xbab2b88c0 3, 39 0, L_0xbab32ce60; 1 drivers +v0xbab2b88c0_4 .net/s v0xbab2b88c0 4, 39 0, L_0xbab32d0e0; 1 drivers +v0xbab2b88c0_5 .net/s v0xbab2b88c0 5, 39 0, L_0xbab32d360; 1 drivers +v0xbab2b88c0_6 .net/s v0xbab2b88c0 6, 39 0, L_0xbab32d5e0; 1 drivers +v0xbab2b88c0_7 .net/s v0xbab2b88c0 7, 39 0, L_0xbab32d860; 1 drivers +v0xbab2b8960 .array "tree", 31 0; +v0xbab2b8960_0 .net/s v0xbab2b8960 0, 39 0, L_0xbab068700; 1 drivers +v0xbab2b8960_1 .net/s v0xbab2b8960 1, 39 0, L_0xbab068770; 1 drivers +v0xbab2b8960_2 .net/s v0xbab2b8960 2, 39 0, L_0xbab0687e0; 1 drivers +v0xbab2b8960_3 .net/s v0xbab2b8960 3, 39 0, L_0xbab068850; 1 drivers +v0xbab2b8960_4 .net/s v0xbab2b8960 4, 39 0, L_0xbab0688c0; 1 drivers +v0xbab2b8960_5 .net/s v0xbab2b8960 5, 39 0, L_0xbab068930; 1 drivers +v0xbab2b8960_6 .net/s v0xbab2b8960 6, 39 0, L_0xbab0689a0; 1 drivers +v0xbab2b8960_7 .net/s v0xbab2b8960 7, 39 0, L_0xbab068a10; 1 drivers +v0xbab2b8960_8 .net/s v0xbab2b8960 8, 39 0, L_0xbab32d900; 1 drivers +v0xbab2b8960_9 .net/s v0xbab2b8960 9, 39 0, L_0xbab32d9a0; 1 drivers +v0xbab2b8960_10 .net/s v0xbab2b8960 10, 39 0, L_0xbab32da40; 1 drivers +v0xbab2b8960_11 .net/s v0xbab2b8960 11, 39 0, L_0xbab32dae0; 1 drivers +o0xbaa847ac0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_12 .net/s v0xbab2b8960 12, 39 0, o0xbaa847ac0; 0 drivers +o0xbaa847af0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_13 .net/s v0xbab2b8960 13, 39 0, o0xbaa847af0; 0 drivers +o0xbaa847b20 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_14 .net/s v0xbab2b8960 14, 39 0, o0xbaa847b20; 0 drivers +o0xbaa847b50 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_15 .net/s v0xbab2b8960 15, 39 0, o0xbaa847b50; 0 drivers +v0xbab2b8960_16 .net/s v0xbab2b8960 16, 39 0, L_0xbab32db80; 1 drivers +v0xbab2b8960_17 .net/s v0xbab2b8960 17, 39 0, L_0xbab32dc20; 1 drivers +o0xbaa847be0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_18 .net/s v0xbab2b8960 18, 39 0, o0xbaa847be0; 0 drivers +o0xbaa847c10 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_19 .net/s v0xbab2b8960 19, 39 0, o0xbaa847c10; 0 drivers +o0xbaa847c40 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_20 .net/s v0xbab2b8960 20, 39 0, o0xbaa847c40; 0 drivers +o0xbaa847c70 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_21 .net/s v0xbab2b8960 21, 39 0, o0xbaa847c70; 0 drivers +o0xbaa847ca0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_22 .net/s v0xbab2b8960 22, 39 0, o0xbaa847ca0; 0 drivers +o0xbaa847cd0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_23 .net/s v0xbab2b8960 23, 39 0, o0xbaa847cd0; 0 drivers +v0xbab2b8960_24 .net/s v0xbab2b8960 24, 39 0, L_0xbab32dcc0; 1 drivers +o0xbaa847d30 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_25 .net/s v0xbab2b8960 25, 39 0, o0xbaa847d30; 0 drivers +o0xbaa847d60 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_26 .net/s v0xbab2b8960 26, 39 0, o0xbaa847d60; 0 drivers +o0xbaa847d90 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_27 .net/s v0xbab2b8960 27, 39 0, o0xbaa847d90; 0 drivers +o0xbaa847dc0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_28 .net/s v0xbab2b8960 28, 39 0, o0xbaa847dc0; 0 drivers +o0xbaa847df0 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_29 .net/s v0xbab2b8960 29, 39 0, o0xbaa847df0; 0 drivers +o0xbaa847e20 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_30 .net/s v0xbab2b8960 30, 39 0, o0xbaa847e20; 0 drivers +o0xbaa847e50 .functor BUFZ 40, c4; HiZ drive +v0xbab2b8960_31 .net/s v0xbab2b8960 31, 39 0, o0xbaa847e50; 0 drivers +v0xbab2b8a00_0 .net/s "w_bus", 127 0, L_0xbab27b0c0; alias, 1 drivers +v0xbab2b8aa0_0 .net/s "x_bus", 127 0, L_0xbab27b020; alias, 1 drivers +L_0xbab27b200 .part L_0xbab27b020, 0, 16; +L_0xbab27b2a0 .part L_0xbab27b0c0, 0, 16; +L_0xbab27b3e0 .part L_0xbab27b020, 16, 16; +L_0xbab27b480 .part L_0xbab27b0c0, 16, 16; +L_0xbab27b5c0 .part L_0xbab27b020, 32, 16; +L_0xbab27b660 .part L_0xbab27b0c0, 32, 16; +L_0xbab27b7a0 .part L_0xbab27b020, 48, 16; +L_0xbab27b840 .part L_0xbab27b0c0, 48, 16; +L_0xbab27b980 .part L_0xbab27b020, 64, 16; +L_0xbab27ba20 .part L_0xbab27b0c0, 64, 16; +L_0xbab27bb60 .part L_0xbab27b020, 80, 16; +L_0xbab27bc00 .part L_0xbab27b0c0, 80, 16; +L_0xbab27bd40 .part L_0xbab27b020, 96, 16; +L_0xbab27bde0 .part L_0xbab27b0c0, 96, 16; +L_0xbab27bf20 .part L_0xbab27b020, 112, 16; +L_0xbab22fde0 .part L_0xbab27b0c0, 112, 16; +L_0xbab32dd60 .arith/sum 40, v0xbab2b9400_0, L_0xbab32dcc0; +S_0xbab2a6e80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a340 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2a7000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a6e80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c3c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2a9540_0 .net/s *"_ivl_0", 31 0, L_0xbab32c500; 1 drivers +v0xbab2a95e0_0 .net/s *"_ivl_2", 31 0, L_0xbab32c5a0; 1 drivers +v0xbab2a9680_0 .net *"_ivl_7", 0 0, L_0xbab27b160; 1 drivers +v0xbab2a9720_0 .net *"_ivl_9", 7 0, L_0xbaad17ac0; 1 drivers +L_0xbaa8785b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2a97c0_0 .net/s "acc_in", 39 0, L_0xbaa8785b0; 1 drivers +v0xbab2a9860_0 .net/s "acc_out", 39 0, L_0xbab32c6e0; alias, 1 drivers +v0xbab2a9900_0 .net/s "product", 31 0, L_0xbaad17a20; 1 drivers +v0xbab2a99a0_0 .net/s "product_ext", 39 0, L_0xbab32c640; 1 drivers +v0xbab2a9a40_0 .net/s "w", 15 0, L_0xbab27b2a0; 1 drivers +v0xbab2a9ae0_0 .net/s "x", 15 0, L_0xbab27b200; 1 drivers +L_0xbab32c500 .extend/s 32, L_0xbab27b200; +L_0xbab32c5a0 .extend/s 32, L_0xbab27b2a0; +L_0xbaad17a20 .arith/mult 32, L_0xbab32c500, L_0xbab32c5a0; +L_0xbab27b160 .part L_0xbaad17a20, 31, 1; +L_0xbaad17ac0 .repeat 8, 8, L_0xbab27b160; +L_0xbab32c640 .concat [ 32 8 0 0], L_0xbaad17a20, L_0xbaad17ac0; +L_0xbab32c6e0 .arith/sum 40, L_0xbaa8785b0, L_0xbab32c640; +S_0xbab2a7180 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a380 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2a7300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a7180; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c4c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2a9b80_0 .net/s *"_ivl_0", 31 0, L_0xbab32c780; 1 drivers +v0xbab2a9c20_0 .net/s *"_ivl_2", 31 0, L_0xbab32c820; 1 drivers +v0xbab2a9cc0_0 .net *"_ivl_7", 0 0, L_0xbab27b340; 1 drivers +v0xbab2a9d60_0 .net *"_ivl_9", 7 0, L_0xbaad17c00; 1 drivers +L_0xbaa8785f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2a9e00_0 .net/s "acc_in", 39 0, L_0xbaa8785f8; 1 drivers +v0xbab2a9ea0_0 .net/s "acc_out", 39 0, L_0xbab32c960; alias, 1 drivers +v0xbab2a9f40_0 .net/s "product", 31 0, L_0xbaad17b60; 1 drivers +v0xbab2a9fe0_0 .net/s "product_ext", 39 0, L_0xbab32c8c0; 1 drivers +v0xbab2aa080_0 .net/s "w", 15 0, L_0xbab27b480; 1 drivers +v0xbab2aa120_0 .net/s "x", 15 0, L_0xbab27b3e0; 1 drivers +L_0xbab32c780 .extend/s 32, L_0xbab27b3e0; +L_0xbab32c820 .extend/s 32, L_0xbab27b480; +L_0xbaad17b60 .arith/mult 32, L_0xbab32c780, L_0xbab32c820; +L_0xbab27b340 .part L_0xbaad17b60, 31, 1; +L_0xbaad17c00 .repeat 8, 8, L_0xbab27b340; +L_0xbab32c8c0 .concat [ 32 8 0 0], L_0xbaad17b60, L_0xbaad17c00; +L_0xbab32c960 .arith/sum 40, L_0xbaa8785f8, L_0xbab32c8c0; +S_0xbab2a7480 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a3c0 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2a7600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a7480; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c5c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2aa1c0_0 .net/s *"_ivl_0", 31 0, L_0xbab32ca00; 1 drivers +v0xbab2aa260_0 .net/s *"_ivl_2", 31 0, L_0xbab32caa0; 1 drivers +v0xbab2aa300_0 .net *"_ivl_7", 0 0, L_0xbab27b520; 1 drivers +v0xbab2aa3a0_0 .net *"_ivl_9", 7 0, L_0xbaad17d40; 1 drivers +L_0xbaa878640 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2aa440_0 .net/s "acc_in", 39 0, L_0xbaa878640; 1 drivers +v0xbab2aa4e0_0 .net/s "acc_out", 39 0, L_0xbab32cbe0; alias, 1 drivers +v0xbab2aa580_0 .net/s "product", 31 0, L_0xbaad17ca0; 1 drivers +v0xbab2aa620_0 .net/s "product_ext", 39 0, L_0xbab32cb40; 1 drivers +v0xbab2aa6c0_0 .net/s "w", 15 0, L_0xbab27b660; 1 drivers +v0xbab2aa760_0 .net/s "x", 15 0, L_0xbab27b5c0; 1 drivers +L_0xbab32ca00 .extend/s 32, L_0xbab27b5c0; +L_0xbab32caa0 .extend/s 32, L_0xbab27b660; +L_0xbaad17ca0 .arith/mult 32, L_0xbab32ca00, L_0xbab32caa0; +L_0xbab27b520 .part L_0xbaad17ca0, 31, 1; +L_0xbaad17d40 .repeat 8, 8, L_0xbab27b520; +L_0xbab32cb40 .concat [ 32 8 0 0], L_0xbaad17ca0, L_0xbaad17d40; +L_0xbab32cbe0 .arith/sum 40, L_0xbaa878640, L_0xbab32cb40; +S_0xbab2a7780 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a400 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2a7900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a7780; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c680 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2aa800_0 .net/s *"_ivl_0", 31 0, L_0xbab32cc80; 1 drivers +v0xbab2aa8a0_0 .net/s *"_ivl_2", 31 0, L_0xbab32cd20; 1 drivers +v0xbab2aa940_0 .net *"_ivl_7", 0 0, L_0xbab27b700; 1 drivers +v0xbab2aa9e0_0 .net *"_ivl_9", 7 0, L_0xbaad17e80; 1 drivers +L_0xbaa878688 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2aaa80_0 .net/s "acc_in", 39 0, L_0xbaa878688; 1 drivers +v0xbab2aab20_0 .net/s "acc_out", 39 0, L_0xbab32ce60; alias, 1 drivers +v0xbab2aabc0_0 .net/s "product", 31 0, L_0xbaad17de0; 1 drivers +v0xbab2aac60_0 .net/s "product_ext", 39 0, L_0xbab32cdc0; 1 drivers +v0xbab2aad00_0 .net/s "w", 15 0, L_0xbab27b840; 1 drivers +v0xbab2aada0_0 .net/s "x", 15 0, L_0xbab27b7a0; 1 drivers +L_0xbab32cc80 .extend/s 32, L_0xbab27b7a0; +L_0xbab32cd20 .extend/s 32, L_0xbab27b840; +L_0xbaad17de0 .arith/mult 32, L_0xbab32cc80, L_0xbab32cd20; +L_0xbab27b700 .part L_0xbaad17de0, 31, 1; +L_0xbaad17e80 .repeat 8, 8, L_0xbab27b700; +L_0xbab32cdc0 .concat [ 32 8 0 0], L_0xbaad17de0, L_0xbaad17e80; +L_0xbab32ce60 .arith/sum 40, L_0xbaa878688, L_0xbab32cdc0; +S_0xbab2a7a80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a480 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2a7c00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a7a80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c6c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c700 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c740 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2aae40_0 .net/s *"_ivl_0", 31 0, L_0xbab32cf00; 1 drivers +v0xbab2aaee0_0 .net/s *"_ivl_2", 31 0, L_0xbab32cfa0; 1 drivers +v0xbab2aaf80_0 .net *"_ivl_7", 0 0, L_0xbab27b8e0; 1 drivers +v0xbab2ab020_0 .net *"_ivl_9", 7 0, L_0xbaad54000; 1 drivers +L_0xbaa8786d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ab0c0_0 .net/s "acc_in", 39 0, L_0xbaa8786d0; 1 drivers +v0xbab2ab160_0 .net/s "acc_out", 39 0, L_0xbab32d0e0; alias, 1 drivers +v0xbab2ab200_0 .net/s "product", 31 0, L_0xbaad17f20; 1 drivers +v0xbab2ab2a0_0 .net/s "product_ext", 39 0, L_0xbab32d040; 1 drivers +v0xbab2ab340_0 .net/s "w", 15 0, L_0xbab27ba20; 1 drivers +v0xbab2ab3e0_0 .net/s "x", 15 0, L_0xbab27b980; 1 drivers +L_0xbab32cf00 .extend/s 32, L_0xbab27b980; +L_0xbab32cfa0 .extend/s 32, L_0xbab27ba20; +L_0xbaad17f20 .arith/mult 32, L_0xbab32cf00, L_0xbab32cfa0; +L_0xbab27b8e0 .part L_0xbaad17f20, 31, 1; +L_0xbaad54000 .repeat 8, 8, L_0xbab27b8e0; +L_0xbab32d040 .concat [ 32 8 0 0], L_0xbaad17f20, L_0xbaad54000; +L_0xbab32d0e0 .arith/sum 40, L_0xbaa8786d0, L_0xbab32d040; +S_0xbab2a7d80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a4c0 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2b0000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2a7d80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c7c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c800 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2ab480_0 .net/s *"_ivl_0", 31 0, L_0xbab32d180; 1 drivers +v0xbab2ab520_0 .net/s *"_ivl_2", 31 0, L_0xbab32d220; 1 drivers +v0xbab2ab5c0_0 .net *"_ivl_7", 0 0, L_0xbab27bac0; 1 drivers +v0xbab2ab660_0 .net *"_ivl_9", 7 0, L_0xbaad54140; 1 drivers +L_0xbaa878718 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ab700_0 .net/s "acc_in", 39 0, L_0xbaa878718; 1 drivers +v0xbab2ab7a0_0 .net/s "acc_out", 39 0, L_0xbab32d360; alias, 1 drivers +v0xbab2ab840_0 .net/s "product", 31 0, L_0xbaad540a0; 1 drivers +v0xbab2ab8e0_0 .net/s "product_ext", 39 0, L_0xbab32d2c0; 1 drivers +v0xbab2ab980_0 .net/s "w", 15 0, L_0xbab27bc00; 1 drivers +v0xbab2aba20_0 .net/s "x", 15 0, L_0xbab27bb60; 1 drivers +L_0xbab32d180 .extend/s 32, L_0xbab27bb60; +L_0xbab32d220 .extend/s 32, L_0xbab27bc00; +L_0xbaad540a0 .arith/mult 32, L_0xbab32d180, L_0xbab32d220; +L_0xbab27bac0 .part L_0xbaad540a0, 31, 1; +L_0xbaad54140 .repeat 8, 8, L_0xbab27bac0; +L_0xbab32d2c0 .concat [ 32 8 0 0], L_0xbaad540a0, L_0xbaad54140; +L_0xbab32d360 .arith/sum 40, L_0xbaa878718, L_0xbab32d2c0; +S_0xbab2b0180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a500 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2b0300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b0180; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c840 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c880 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c8c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2abac0_0 .net/s *"_ivl_0", 31 0, L_0xbab32d400; 1 drivers +v0xbab2abb60_0 .net/s *"_ivl_2", 31 0, L_0xbab32d4a0; 1 drivers +v0xbab2abc00_0 .net *"_ivl_7", 0 0, L_0xbab27bca0; 1 drivers +v0xbab2abca0_0 .net *"_ivl_9", 7 0, L_0xbaad54280; 1 drivers +L_0xbaa878760 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2abd40_0 .net/s "acc_in", 39 0, L_0xbaa878760; 1 drivers +v0xbab2abde0_0 .net/s "acc_out", 39 0, L_0xbab32d5e0; alias, 1 drivers +v0xbab2abe80_0 .net/s "product", 31 0, L_0xbaad541e0; 1 drivers +v0xbab2abf20_0 .net/s "product_ext", 39 0, L_0xbab32d540; 1 drivers +v0xbab2b8000_0 .net/s "w", 15 0, L_0xbab27bde0; 1 drivers +v0xbab2b80a0_0 .net/s "x", 15 0, L_0xbab27bd40; 1 drivers +L_0xbab32d400 .extend/s 32, L_0xbab27bd40; +L_0xbab32d4a0 .extend/s 32, L_0xbab27bde0; +L_0xbaad541e0 .arith/mult 32, L_0xbab32d400, L_0xbab32d4a0; +L_0xbab27bca0 .part L_0xbaad541e0, 31, 1; +L_0xbaad54280 .repeat 8, 8, L_0xbab27bca0; +L_0xbab32d540 .concat [ 32 8 0 0], L_0xbaad541e0, L_0xbaad54280; +L_0xbab32d5e0 .arith/sum 40, L_0xbaa878760, L_0xbab32d540; +S_0xbab2b0480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a540 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2b0600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b0480; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4c940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4c980 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2b8140_0 .net/s *"_ivl_0", 31 0, L_0xbab32d680; 1 drivers +v0xbab2b81e0_0 .net/s *"_ivl_2", 31 0, L_0xbab32d720; 1 drivers +v0xbab2b8280_0 .net *"_ivl_7", 0 0, L_0xbab27be80; 1 drivers +v0xbab2b8320_0 .net *"_ivl_9", 7 0, L_0xbaad543c0; 1 drivers +L_0xbaa8787a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2b83c0_0 .net/s "acc_in", 39 0, L_0xbaa8787a8; 1 drivers +v0xbab2b8460_0 .net/s "acc_out", 39 0, L_0xbab32d860; alias, 1 drivers +v0xbab2b8500_0 .net/s "product", 31 0, L_0xbaad54320; 1 drivers +v0xbab2b85a0_0 .net/s "product_ext", 39 0, L_0xbab32d7c0; 1 drivers +v0xbab2b8640_0 .net/s "w", 15 0, L_0xbab22fde0; 1 drivers +v0xbab2b86e0_0 .net/s "x", 15 0, L_0xbab27bf20; 1 drivers +L_0xbab32d680 .extend/s 32, L_0xbab27bf20; +L_0xbab32d720 .extend/s 32, L_0xbab22fde0; +L_0xbaad54320 .arith/mult 32, L_0xbab32d680, L_0xbab32d720; +L_0xbab27be80 .part L_0xbaad54320, 31, 1; +L_0xbaad543c0 .repeat 8, 8, L_0xbab27be80; +L_0xbab32d7c0 .concat [ 32 8 0 0], L_0xbaad54320, L_0xbaad543c0; +L_0xbab32d860 .arith/sum 40, L_0xbaa8787a8, L_0xbab32d7c0; +S_0xbab2b0780 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a440 .param/l "i" 1 5 80, +C4<00>; +L_0xbab068700 .functor BUFZ 40, L_0xbab32c6e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b0900 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a580 .param/l "i" 1 5 80, +C4<01>; +L_0xbab068770 .functor BUFZ 40, L_0xbab32c960, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b0a80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a5c0 .param/l "i" 1 5 80, +C4<010>; +L_0xbab0687e0 .functor BUFZ 40, L_0xbab32cbe0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b0c00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a600 .param/l "i" 1 5 80, +C4<011>; +L_0xbab068850 .functor BUFZ 40, L_0xbab32ce60, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b0d80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a640 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab0688c0 .functor BUFZ 40, L_0xbab32d0e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b0f00 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a680 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab068930 .functor BUFZ 40, L_0xbab32d360, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b1080 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a6c0 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab0689a0 .functor BUFZ 40, L_0xbab32d5e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b1200 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a700 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab068a10 .functor BUFZ 40, L_0xbab32d860, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2b1380 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a740 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2b1500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2b1380; + .timescale 0 0; +P_0xbaad2a780 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32d900 .arith/sum 40, L_0xbab068700, L_0xbab068770; +S_0xbab2b1680 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2b1380; + .timescale 0 0; +P_0xbaad2a7c0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab32d9a0 .arith/sum 40, L_0xbab0687e0, L_0xbab068850; +S_0xbab2b1800 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2b1380; + .timescale 0 0; +P_0xbaad2a800 .param/l "node" 1 5 94, +C4<010>; +L_0xbab32da40 .arith/sum 40, L_0xbab0688c0, L_0xbab068930; +S_0xbab2b1980 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2b1380; + .timescale 0 0; +P_0xbaad2a840 .param/l "node" 1 5 94, +C4<011>; +L_0xbab32dae0 .arith/sum 40, L_0xbab0689a0, L_0xbab068a10; +S_0xbab2b1b00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a880 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2b1c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2b1b00; + .timescale 0 0; +P_0xbaad2a8c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32db80 .arith/sum 40, L_0xbab32d900, L_0xbab32d9a0; +S_0xbab2b1e00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2b1b00; + .timescale 0 0; +P_0xbaad2a900 .param/l "node" 1 5 94, +C4<01>; +L_0xbab32dc20 .arith/sum 40, L_0xbab32da40, L_0xbab32dae0; +S_0xbab2b1f80 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2a6d00; + .timescale 0 0; +P_0xbaad2a940 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2b2100 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2b1f80; + .timescale 0 0; +P_0xbaad2a980 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32dcc0 .arith/sum 40, L_0xbab32db80, L_0xbab32dc20; +S_0xbab2b2280 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad2aa00 .param/l "n" 1 3 34, +C4<010>; +S_0xbab2b2400 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2b2280; .timescale -9 -12; -E_0x7e2c81600 .event anyedge, v0x7e30b8820_0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc000 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc040 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc080 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc0c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc100 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc140 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2c1400_0 .net *"_ivl_0", 31 0, L_0xbab32df40; 1 drivers +v0xbab2c14a0_0 .net *"_ivl_11", 31 0, L_0xbaad54640; 1 drivers +v0xbab2c1540_0 .net *"_ivl_14", 31 0, L_0xbab32dfe0; 1 drivers +L_0xbaa8788c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c15e0_0 .net *"_ivl_17", 28 0, L_0xbaa8788c8; 1 drivers +L_0xbaa878910 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2c1680_0 .net/2u *"_ivl_18", 31 0, L_0xbaa878910; 1 drivers +v0xbab2c1720_0 .net *"_ivl_21", 31 0, L_0xbaad546e0; 1 drivers +L_0xbaa878958 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2c17c0_0 .net/2u *"_ivl_22", 31 0, L_0xbaa878958; 1 drivers +v0xbab2c1860_0 .net *"_ivl_25", 31 0, L_0xbaad54780; 1 drivers +v0xbab2c1900_0 .net *"_ivl_29", 0 0, L_0xbab330aa0; 1 drivers +L_0xbaa8787f0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c19a0_0 .net *"_ivl_3", 28 0, L_0xbaa8787f0; 1 drivers +v0xbab2c1a40_0 .net *"_ivl_31", 23 0, L_0xbaad552c0; 1 drivers +L_0xbaa878838 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2c1ae0_0 .net/2u *"_ivl_4", 31 0, L_0xbaa878838; 1 drivers +v0xbab2c1b80_0 .net *"_ivl_7", 31 0, L_0xbaad545a0; 1 drivers +L_0xbaa878880 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2c1c20_0 .net/2u *"_ivl_8", 31 0, L_0xbaa878880; 1 drivers +v0xbab2c1cc0_0 .var/s "acc", 39 0; +v0xbab2c1d60_0 .net/s "acc_next", 39 0, L_0xbab32f8e0; 1 drivers +v0xbab2c1e00_0 .net/s "bias", 15 0, L_0xbab330be0; 1 drivers +v0xbab2c1ea0_0 .net/s "bias_ext", 39 0, L_0xbab32f980; 1 drivers +v0xbab2c1f40_0 .var "busy", 0 0; +v0xbab2c1fe0_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2c2080_0 .var "done", 0 0; +v0xbab2c2120_0 .net/s "final_acc", 39 0, L_0xbab32fa20; 1 drivers +v0xbab2c21c0_0 .var "group_index", 2 0; +v0xbab2c2260_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2c2300_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2c23a0_0 .net/s "w_bus", 1023 0, L_0xbab330b40; 1 drivers +v0xbab2c2440_0 .net/s "w_group", 127 0, L_0xbab1faf80; 1 drivers +v0xbab2c24e0_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2c2580_0 .net/s "x_group", 127 0, L_0xbab2121c0; 1 drivers +v0xbab2c2620_0 .var/s "y", 15 0; +L_0xbab32df40 .concat [ 3 29 0 0], v0xbab2c21c0_0, L_0xbaa8787f0; +L_0xbaad545a0 .arith/mult 32, L_0xbab32df40, L_0xbaa878838; +L_0xbaad54640 .arith/mult 32, L_0xbaad545a0, L_0xbaa878880; +L_0xbab2121c0 .part/v o0xbaa846110, L_0xbaad54640, 128; +L_0xbab32dfe0 .concat [ 3 29 0 0], v0xbab2c21c0_0, L_0xbaa8788c8; +L_0xbaad546e0 .arith/mult 32, L_0xbab32dfe0, L_0xbaa878910; +L_0xbaad54780 .arith/mult 32, L_0xbaad546e0, L_0xbaa878958; +L_0xbab1faf80 .part/v L_0xbab330b40, L_0xbaad54780, 128; +L_0xbab330aa0 .part L_0xbab330be0, 15, 1; +L_0xbaad552c0 .repeat 24, 24, L_0xbab330aa0; +L_0xbab32f980 .concat [ 16 24 0 0], L_0xbab330be0, L_0xbaad552c0; +L_0xbab32fa20 .arith/sum 40, L_0xbab32f8e0, L_0xbab32f980; +S_0xbab2b2580 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2b2400; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab294700 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab294740 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab294780 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2947c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2c1040_0 .net/s "acc_in", 39 0, v0xbab2c1cc0_0; 1 drivers +v0xbab2c10e0_0 .net/s "acc_out", 39 0, L_0xbab32f8e0; alias, 1 drivers +v0xbab2c1180 .array "products", 7 0; +v0xbab2c1180_0 .net/s v0xbab2c1180 0, 39 0, L_0xbab32e260; 1 drivers +v0xbab2c1180_1 .net/s v0xbab2c1180 1, 39 0, L_0xbab32e4e0; 1 drivers +v0xbab2c1180_2 .net/s v0xbab2c1180 2, 39 0, L_0xbab32e760; 1 drivers +v0xbab2c1180_3 .net/s v0xbab2c1180 3, 39 0, L_0xbab32e9e0; 1 drivers +v0xbab2c1180_4 .net/s v0xbab2c1180 4, 39 0, L_0xbab32ec60; 1 drivers +v0xbab2c1180_5 .net/s v0xbab2c1180 5, 39 0, L_0xbab32eee0; 1 drivers +v0xbab2c1180_6 .net/s v0xbab2c1180 6, 39 0, L_0xbab32f160; 1 drivers +v0xbab2c1180_7 .net/s v0xbab2c1180 7, 39 0, L_0xbab32f3e0; 1 drivers +v0xbab2c1220 .array "tree", 31 0; +v0xbab2c1220_0 .net/s v0xbab2c1220 0, 39 0, L_0xbab068a80; 1 drivers +v0xbab2c1220_1 .net/s v0xbab2c1220 1, 39 0, L_0xbab068af0; 1 drivers +v0xbab2c1220_2 .net/s v0xbab2c1220 2, 39 0, L_0xbab068b60; 1 drivers +v0xbab2c1220_3 .net/s v0xbab2c1220 3, 39 0, L_0xbab068bd0; 1 drivers +v0xbab2c1220_4 .net/s v0xbab2c1220 4, 39 0, L_0xbab068c40; 1 drivers +v0xbab2c1220_5 .net/s v0xbab2c1220 5, 39 0, L_0xbab068cb0; 1 drivers +v0xbab2c1220_6 .net/s v0xbab2c1220 6, 39 0, L_0xbab068d20; 1 drivers +v0xbab2c1220_7 .net/s v0xbab2c1220 7, 39 0, L_0xbab068d90; 1 drivers +v0xbab2c1220_8 .net/s v0xbab2c1220 8, 39 0, L_0xbab32f480; 1 drivers +v0xbab2c1220_9 .net/s v0xbab2c1220 9, 39 0, L_0xbab32f520; 1 drivers +v0xbab2c1220_10 .net/s v0xbab2c1220 10, 39 0, L_0xbab32f5c0; 1 drivers +v0xbab2c1220_11 .net/s v0xbab2c1220 11, 39 0, L_0xbab32f660; 1 drivers +o0xbaa849d10 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_12 .net/s v0xbab2c1220 12, 39 0, o0xbaa849d10; 0 drivers +o0xbaa849d40 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_13 .net/s v0xbab2c1220 13, 39 0, o0xbaa849d40; 0 drivers +o0xbaa849d70 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_14 .net/s v0xbab2c1220 14, 39 0, o0xbaa849d70; 0 drivers +o0xbaa849da0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_15 .net/s v0xbab2c1220 15, 39 0, o0xbaa849da0; 0 drivers +v0xbab2c1220_16 .net/s v0xbab2c1220 16, 39 0, L_0xbab32f700; 1 drivers +v0xbab2c1220_17 .net/s v0xbab2c1220 17, 39 0, L_0xbab32f7a0; 1 drivers +o0xbaa849e30 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_18 .net/s v0xbab2c1220 18, 39 0, o0xbaa849e30; 0 drivers +o0xbaa849e60 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_19 .net/s v0xbab2c1220 19, 39 0, o0xbaa849e60; 0 drivers +o0xbaa849e90 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_20 .net/s v0xbab2c1220 20, 39 0, o0xbaa849e90; 0 drivers +o0xbaa849ec0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_21 .net/s v0xbab2c1220 21, 39 0, o0xbaa849ec0; 0 drivers +o0xbaa849ef0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_22 .net/s v0xbab2c1220 22, 39 0, o0xbaa849ef0; 0 drivers +o0xbaa849f20 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_23 .net/s v0xbab2c1220 23, 39 0, o0xbaa849f20; 0 drivers +v0xbab2c1220_24 .net/s v0xbab2c1220 24, 39 0, L_0xbab32f840; 1 drivers +o0xbaa849f80 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_25 .net/s v0xbab2c1220 25, 39 0, o0xbaa849f80; 0 drivers +o0xbaa849fb0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_26 .net/s v0xbab2c1220 26, 39 0, o0xbaa849fb0; 0 drivers +o0xbaa849fe0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_27 .net/s v0xbab2c1220 27, 39 0, o0xbaa849fe0; 0 drivers +o0xbaa84a010 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_28 .net/s v0xbab2c1220 28, 39 0, o0xbaa84a010; 0 drivers +o0xbaa84a040 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_29 .net/s v0xbab2c1220 29, 39 0, o0xbaa84a040; 0 drivers +o0xbaa84a070 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_30 .net/s v0xbab2c1220 30, 39 0, o0xbaa84a070; 0 drivers +o0xbaa84a0a0 .functor BUFZ 40, c4; HiZ drive +v0xbab2c1220_31 .net/s v0xbab2c1220 31, 39 0, o0xbaa84a0a0; 0 drivers +v0xbab2c12c0_0 .net/s "w_bus", 127 0, L_0xbab1faf80; alias, 1 drivers +v0xbab2c1360_0 .net/s "x_bus", 127 0, L_0xbab2121c0; alias, 1 drivers +L_0xbab19a6c0 .part L_0xbab2121c0, 0, 16; +L_0xbab1d4be0 .part L_0xbab1faf80, 0, 16; +L_0xbab1d7d40 .part L_0xbab2121c0, 16, 16; +L_0xbab1d4b40 .part L_0xbab1faf80, 16, 16; +L_0xbab330000 .part L_0xbab2121c0, 32, 16; +L_0xbab3300a0 .part L_0xbab1faf80, 32, 16; +L_0xbab3301e0 .part L_0xbab2121c0, 48, 16; +L_0xbab330280 .part L_0xbab1faf80, 48, 16; +L_0xbab3303c0 .part L_0xbab2121c0, 64, 16; +L_0xbab330460 .part L_0xbab1faf80, 64, 16; +L_0xbab3305a0 .part L_0xbab2121c0, 80, 16; +L_0xbab330640 .part L_0xbab1faf80, 80, 16; +L_0xbab330780 .part L_0xbab2121c0, 96, 16; +L_0xbab330820 .part L_0xbab1faf80, 96, 16; +L_0xbab330960 .part L_0xbab2121c0, 112, 16; +L_0xbab330a00 .part L_0xbab1faf80, 112, 16; +L_0xbab32f8e0 .arith/sum 40, v0xbab2c1cc0_0, L_0xbab32f840; +S_0xbab2b2700 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2aa40 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2b2880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b2700; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4c9c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ca00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ca40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2b9e00_0 .net/s *"_ivl_0", 31 0, L_0xbab32e080; 1 drivers +v0xbab2b9ea0_0 .net/s *"_ivl_2", 31 0, L_0xbab32e120; 1 drivers +v0xbab2b9f40_0 .net *"_ivl_7", 0 0, L_0xbab1b9900; 1 drivers +v0xbab2b9fe0_0 .net *"_ivl_9", 7 0, L_0xbaad548c0; 1 drivers +L_0xbaa8789a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ba080_0 .net/s "acc_in", 39 0, L_0xbaa8789a0; 1 drivers +v0xbab2ba120_0 .net/s "acc_out", 39 0, L_0xbab32e260; alias, 1 drivers +v0xbab2ba1c0_0 .net/s "product", 31 0, L_0xbaad54820; 1 drivers +v0xbab2ba260_0 .net/s "product_ext", 39 0, L_0xbab32e1c0; 1 drivers +v0xbab2ba300_0 .net/s "w", 15 0, L_0xbab1d4be0; 1 drivers +v0xbab2ba3a0_0 .net/s "x", 15 0, L_0xbab19a6c0; 1 drivers +L_0xbab32e080 .extend/s 32, L_0xbab19a6c0; +L_0xbab32e120 .extend/s 32, L_0xbab1d4be0; +L_0xbaad54820 .arith/mult 32, L_0xbab32e080, L_0xbab32e120; +L_0xbab1b9900 .part L_0xbaad54820, 31, 1; +L_0xbaad548c0 .repeat 8, 8, L_0xbab1b9900; +L_0xbab32e1c0 .concat [ 32 8 0 0], L_0xbaad54820, L_0xbaad548c0; +L_0xbab32e260 .arith/sum 40, L_0xbaa8789a0, L_0xbab32e1c0; +S_0xbab2b2a00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2aa80 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2b2b80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b2a00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ca80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cac0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cb00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2ba440_0 .net/s *"_ivl_0", 31 0, L_0xbab32e300; 1 drivers +v0xbab2ba4e0_0 .net/s *"_ivl_2", 31 0, L_0xbab32e3a0; 1 drivers +v0xbab2ba580_0 .net *"_ivl_7", 0 0, L_0xbab1d4c80; 1 drivers +v0xbab2ba620_0 .net *"_ivl_9", 7 0, L_0xbaad54a00; 1 drivers +L_0xbaa8789e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ba6c0_0 .net/s "acc_in", 39 0, L_0xbaa8789e8; 1 drivers +v0xbab2ba760_0 .net/s "acc_out", 39 0, L_0xbab32e4e0; alias, 1 drivers +v0xbab2ba800_0 .net/s "product", 31 0, L_0xbaad54960; 1 drivers +v0xbab2ba8a0_0 .net/s "product_ext", 39 0, L_0xbab32e440; 1 drivers +v0xbab2ba940_0 .net/s "w", 15 0, L_0xbab1d4b40; 1 drivers +v0xbab2ba9e0_0 .net/s "x", 15 0, L_0xbab1d7d40; 1 drivers +L_0xbab32e300 .extend/s 32, L_0xbab1d7d40; +L_0xbab32e3a0 .extend/s 32, L_0xbab1d4b40; +L_0xbaad54960 .arith/mult 32, L_0xbab32e300, L_0xbab32e3a0; +L_0xbab1d4c80 .part L_0xbaad54960, 31, 1; +L_0xbaad54a00 .repeat 8, 8, L_0xbab1d4c80; +L_0xbab32e440 .concat [ 32 8 0 0], L_0xbaad54960, L_0xbaad54a00; +L_0xbab32e4e0 .arith/sum 40, L_0xbaa8789e8, L_0xbab32e440; +S_0xbab2b2d00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2aac0 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2b2e80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b2d00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4cb40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cb80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cbc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2baa80_0 .net/s *"_ivl_0", 31 0, L_0xbab32e580; 1 drivers +v0xbab2bab20_0 .net/s *"_ivl_2", 31 0, L_0xbab32e620; 1 drivers +v0xbab2babc0_0 .net *"_ivl_7", 0 0, L_0xbab1d4d20; 1 drivers +v0xbab2bac60_0 .net *"_ivl_9", 7 0, L_0xbaad54b40; 1 drivers +L_0xbaa878a30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2bad00_0 .net/s "acc_in", 39 0, L_0xbaa878a30; 1 drivers +v0xbab2bada0_0 .net/s "acc_out", 39 0, L_0xbab32e760; alias, 1 drivers +v0xbab2bae40_0 .net/s "product", 31 0, L_0xbaad54aa0; 1 drivers +v0xbab2baee0_0 .net/s "product_ext", 39 0, L_0xbab32e6c0; 1 drivers +v0xbab2baf80_0 .net/s "w", 15 0, L_0xbab3300a0; 1 drivers +v0xbab2bb020_0 .net/s "x", 15 0, L_0xbab330000; 1 drivers +L_0xbab32e580 .extend/s 32, L_0xbab330000; +L_0xbab32e620 .extend/s 32, L_0xbab3300a0; +L_0xbaad54aa0 .arith/mult 32, L_0xbab32e580, L_0xbab32e620; +L_0xbab1d4d20 .part L_0xbaad54aa0, 31, 1; +L_0xbaad54b40 .repeat 8, 8, L_0xbab1d4d20; +L_0xbab32e6c0 .concat [ 32 8 0 0], L_0xbaad54aa0, L_0xbaad54b40; +L_0xbab32e760 .arith/sum 40, L_0xbaa878a30, L_0xbab32e6c0; +S_0xbab2b3000 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ab00 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2b3180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b3000; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4cc00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cc40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cc80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2bb0c0_0 .net/s *"_ivl_0", 31 0, L_0xbab32e800; 1 drivers +v0xbab2bb160_0 .net/s *"_ivl_2", 31 0, L_0xbab32e8a0; 1 drivers +v0xbab2bb200_0 .net *"_ivl_7", 0 0, L_0xbab330140; 1 drivers +v0xbab2bb2a0_0 .net *"_ivl_9", 7 0, L_0xbaad54c80; 1 drivers +L_0xbaa878a78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2bb340_0 .net/s "acc_in", 39 0, L_0xbaa878a78; 1 drivers +v0xbab2bb3e0_0 .net/s "acc_out", 39 0, L_0xbab32e9e0; alias, 1 drivers +v0xbab2bb480_0 .net/s "product", 31 0, L_0xbaad54be0; 1 drivers +v0xbab2bb520_0 .net/s "product_ext", 39 0, L_0xbab32e940; 1 drivers +v0xbab2bb5c0_0 .net/s "w", 15 0, L_0xbab330280; 1 drivers +v0xbab2bb660_0 .net/s "x", 15 0, L_0xbab3301e0; 1 drivers +L_0xbab32e800 .extend/s 32, L_0xbab3301e0; +L_0xbab32e8a0 .extend/s 32, L_0xbab330280; +L_0xbaad54be0 .arith/mult 32, L_0xbab32e800, L_0xbab32e8a0; +L_0xbab330140 .part L_0xbaad54be0, 31, 1; +L_0xbaad54c80 .repeat 8, 8, L_0xbab330140; +L_0xbab32e940 .concat [ 32 8 0 0], L_0xbaad54be0, L_0xbaad54c80; +L_0xbab32e9e0 .arith/sum 40, L_0xbaa878a78, L_0xbab32e940; +S_0xbab2b3300 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ab80 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2b3480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b3300; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ccc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cd00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cd40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2bb700_0 .net/s *"_ivl_0", 31 0, L_0xbab32ea80; 1 drivers +v0xbab2bb7a0_0 .net/s *"_ivl_2", 31 0, L_0xbab32eb20; 1 drivers +v0xbab2bb840_0 .net *"_ivl_7", 0 0, L_0xbab330320; 1 drivers +v0xbab2bb8e0_0 .net *"_ivl_9", 7 0, L_0xbaad54dc0; 1 drivers +L_0xbaa878ac0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2bb980_0 .net/s "acc_in", 39 0, L_0xbaa878ac0; 1 drivers +v0xbab2bba20_0 .net/s "acc_out", 39 0, L_0xbab32ec60; alias, 1 drivers +v0xbab2bbac0_0 .net/s "product", 31 0, L_0xbaad54d20; 1 drivers +v0xbab2bbb60_0 .net/s "product_ext", 39 0, L_0xbab32ebc0; 1 drivers +v0xbab2bbc00_0 .net/s "w", 15 0, L_0xbab330460; 1 drivers +v0xbab2bbca0_0 .net/s "x", 15 0, L_0xbab3303c0; 1 drivers +L_0xbab32ea80 .extend/s 32, L_0xbab3303c0; +L_0xbab32eb20 .extend/s 32, L_0xbab330460; +L_0xbaad54d20 .arith/mult 32, L_0xbab32ea80, L_0xbab32eb20; +L_0xbab330320 .part L_0xbaad54d20, 31, 1; +L_0xbaad54dc0 .repeat 8, 8, L_0xbab330320; +L_0xbab32ebc0 .concat [ 32 8 0 0], L_0xbaad54d20, L_0xbaad54dc0; +L_0xbab32ec60 .arith/sum 40, L_0xbaa878ac0, L_0xbab32ebc0; +S_0xbab2b3600 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2abc0 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2b3780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b3600; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4cd80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cdc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ce00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2bbd40_0 .net/s *"_ivl_0", 31 0, L_0xbab32ed00; 1 drivers +v0xbab2bbde0_0 .net/s *"_ivl_2", 31 0, L_0xbab32eda0; 1 drivers +v0xbab2bbe80_0 .net *"_ivl_7", 0 0, L_0xbab330500; 1 drivers +v0xbab2bbf20_0 .net *"_ivl_9", 7 0, L_0xbaad54f00; 1 drivers +L_0xbaa878b08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c0000_0 .net/s "acc_in", 39 0, L_0xbaa878b08; 1 drivers +v0xbab2c00a0_0 .net/s "acc_out", 39 0, L_0xbab32eee0; alias, 1 drivers +v0xbab2c0140_0 .net/s "product", 31 0, L_0xbaad54e60; 1 drivers +v0xbab2c01e0_0 .net/s "product_ext", 39 0, L_0xbab32ee40; 1 drivers +v0xbab2c0280_0 .net/s "w", 15 0, L_0xbab330640; 1 drivers +v0xbab2c0320_0 .net/s "x", 15 0, L_0xbab3305a0; 1 drivers +L_0xbab32ed00 .extend/s 32, L_0xbab3305a0; +L_0xbab32eda0 .extend/s 32, L_0xbab330640; +L_0xbaad54e60 .arith/mult 32, L_0xbab32ed00, L_0xbab32eda0; +L_0xbab330500 .part L_0xbaad54e60, 31, 1; +L_0xbaad54f00 .repeat 8, 8, L_0xbab330500; +L_0xbab32ee40 .concat [ 32 8 0 0], L_0xbaad54e60, L_0xbaad54f00; +L_0xbab32eee0 .arith/sum 40, L_0xbaa878b08, L_0xbab32ee40; +S_0xbab2b3900 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ac00 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2b3a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b3900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ce40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ce80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cec0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c03c0_0 .net/s *"_ivl_0", 31 0, L_0xbab32ef80; 1 drivers +v0xbab2c0460_0 .net/s *"_ivl_2", 31 0, L_0xbab32f020; 1 drivers +v0xbab2c0500_0 .net *"_ivl_7", 0 0, L_0xbab3306e0; 1 drivers +v0xbab2c05a0_0 .net *"_ivl_9", 7 0, L_0xbaad55040; 1 drivers +L_0xbaa878b50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c0640_0 .net/s "acc_in", 39 0, L_0xbaa878b50; 1 drivers +v0xbab2c06e0_0 .net/s "acc_out", 39 0, L_0xbab32f160; alias, 1 drivers +v0xbab2c0780_0 .net/s "product", 31 0, L_0xbaad54fa0; 1 drivers +v0xbab2c0820_0 .net/s "product_ext", 39 0, L_0xbab32f0c0; 1 drivers +v0xbab2c08c0_0 .net/s "w", 15 0, L_0xbab330820; 1 drivers +v0xbab2c0960_0 .net/s "x", 15 0, L_0xbab330780; 1 drivers +L_0xbab32ef80 .extend/s 32, L_0xbab330780; +L_0xbab32f020 .extend/s 32, L_0xbab330820; +L_0xbaad54fa0 .arith/mult 32, L_0xbab32ef80, L_0xbab32f020; +L_0xbab3306e0 .part L_0xbaad54fa0, 31, 1; +L_0xbaad55040 .repeat 8, 8, L_0xbab3306e0; +L_0xbab32f0c0 .concat [ 32 8 0 0], L_0xbaad54fa0, L_0xbaad55040; +L_0xbab32f160 .arith/sum 40, L_0xbaa878b50, L_0xbab32f0c0; +S_0xbab2b3c00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ac40 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2b3d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2b3c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4cf00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4cf40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4cf80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c0a00_0 .net/s *"_ivl_0", 31 0, L_0xbab32f200; 1 drivers +v0xbab2c0aa0_0 .net/s *"_ivl_2", 31 0, L_0xbab32f2a0; 1 drivers +v0xbab2c0b40_0 .net *"_ivl_7", 0 0, L_0xbab3308c0; 1 drivers +v0xbab2c0be0_0 .net *"_ivl_9", 7 0, L_0xbaad55180; 1 drivers +L_0xbaa878b98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c0c80_0 .net/s "acc_in", 39 0, L_0xbaa878b98; 1 drivers +v0xbab2c0d20_0 .net/s "acc_out", 39 0, L_0xbab32f3e0; alias, 1 drivers +v0xbab2c0dc0_0 .net/s "product", 31 0, L_0xbaad550e0; 1 drivers +v0xbab2c0e60_0 .net/s "product_ext", 39 0, L_0xbab32f340; 1 drivers +v0xbab2c0f00_0 .net/s "w", 15 0, L_0xbab330a00; 1 drivers +v0xbab2c0fa0_0 .net/s "x", 15 0, L_0xbab330960; 1 drivers +L_0xbab32f200 .extend/s 32, L_0xbab330960; +L_0xbab32f2a0 .extend/s 32, L_0xbab330a00; +L_0xbaad550e0 .arith/mult 32, L_0xbab32f200, L_0xbab32f2a0; +L_0xbab3308c0 .part L_0xbaad550e0, 31, 1; +L_0xbaad55180 .repeat 8, 8, L_0xbab3308c0; +L_0xbab32f340 .concat [ 32 8 0 0], L_0xbaad550e0, L_0xbaad55180; +L_0xbab32f3e0 .arith/sum 40, L_0xbaa878b98, L_0xbab32f340; +S_0xbab2c4000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ab40 .param/l "i" 1 5 80, +C4<00>; +L_0xbab068a80 .functor BUFZ 40, L_0xbab32e260, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ac80 .param/l "i" 1 5 80, +C4<01>; +L_0xbab068af0 .functor BUFZ 40, L_0xbab32e4e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2acc0 .param/l "i" 1 5 80, +C4<010>; +L_0xbab068b60 .functor BUFZ 40, L_0xbab32e760, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ad00 .param/l "i" 1 5 80, +C4<011>; +L_0xbab068bd0 .functor BUFZ 40, L_0xbab32e9e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ad40 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab068c40 .functor BUFZ 40, L_0xbab32ec60, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ad80 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab068cb0 .functor BUFZ 40, L_0xbab32eee0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2adc0 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab068d20 .functor BUFZ 40, L_0xbab32f160, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4a80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ae00 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab068d90 .functor BUFZ 40, L_0xbab32f3e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c4c00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2ae40 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2c4d80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2c4c00; + .timescale 0 0; +P_0xbaad2ae80 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32f480 .arith/sum 40, L_0xbab068a80, L_0xbab068af0; +S_0xbab2c4f00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2c4c00; + .timescale 0 0; +P_0xbaad2aec0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab32f520 .arith/sum 40, L_0xbab068b60, L_0xbab068bd0; +S_0xbab2c5080 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2c4c00; + .timescale 0 0; +P_0xbaad2af00 .param/l "node" 1 5 94, +C4<010>; +L_0xbab32f5c0 .arith/sum 40, L_0xbab068c40, L_0xbab068cb0; +S_0xbab2c5200 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2c4c00; + .timescale 0 0; +P_0xbaad2af40 .param/l "node" 1 5 94, +C4<011>; +L_0xbab32f660 .arith/sum 40, L_0xbab068d20, L_0xbab068d90; +S_0xbab2c5380 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2af80 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2c5500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2c5380; + .timescale 0 0; +P_0xbaad2afc0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32f700 .arith/sum 40, L_0xbab32f480, L_0xbab32f520; +S_0xbab2c5680 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2c5380; + .timescale 0 0; +P_0xbaad2b000 .param/l "node" 1 5 94, +C4<01>; +L_0xbab32f7a0 .arith/sum 40, L_0xbab32f5c0, L_0xbab32f660; +S_0xbab2c5800 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2b2580; + .timescale 0 0; +P_0xbaad2b040 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2c5980 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2c5800; + .timescale 0 0; +P_0xbaad2b080 .param/l "node" 1 5 94, +C4<00>; +L_0xbab32f840 .arith/sum 40, L_0xbab32f700, L_0xbab32f7a0; +S_0xbab2c5b00 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad2b100 .param/l "n" 1 3 34, +C4<011>; +S_0xbab2c5c80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2c5b00; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc180 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc1c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc200 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc240 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc280 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc2c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2d1cc0_0 .net *"_ivl_0", 31 0, L_0xbab32fac0; 1 drivers +v0xbab2d1d60_0 .net *"_ivl_11", 31 0, L_0xbaad55400; 1 drivers +v0xbab2d1e00_0 .net *"_ivl_14", 31 0, L_0xbab32fb60; 1 drivers +L_0xbaa878cb8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d1ea0_0 .net *"_ivl_17", 28 0, L_0xbaa878cb8; 1 drivers +L_0xbaa878d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2d1f40_0 .net/2u *"_ivl_18", 31 0, L_0xbaa878d00; 1 drivers +v0xbab2d1fe0_0 .net *"_ivl_21", 31 0, L_0xbaad554a0; 1 drivers +L_0xbaa878d48 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2d2080_0 .net/2u *"_ivl_22", 31 0, L_0xbaa878d48; 1 drivers +v0xbab2d2120_0 .net *"_ivl_25", 31 0, L_0xbaad55540; 1 drivers +v0xbab2d21c0_0 .net *"_ivl_29", 0 0, L_0xbab331cc0; 1 drivers +L_0xbaa878be0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d2260_0 .net *"_ivl_3", 28 0, L_0xbaa878be0; 1 drivers +v0xbab2d2300_0 .net *"_ivl_31", 23 0, L_0xbaad56080; 1 drivers +L_0xbaa878c28 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2d23a0_0 .net/2u *"_ivl_4", 31 0, L_0xbaa878c28; 1 drivers +v0xbab2d2440_0 .net *"_ivl_7", 31 0, L_0xbaad55360; 1 drivers +L_0xbaa878c70 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2d24e0_0 .net/2u *"_ivl_8", 31 0, L_0xbaa878c70; 1 drivers +v0xbab2d2580_0 .var/s "acc", 39 0; +v0xbab2d2620_0 .net/s "acc_next", 39 0, L_0xbab3394a0; 1 drivers +v0xbab2d26c0_0 .net/s "bias", 15 0, L_0xbab331e00; 1 drivers +v0xbab2d2760_0 .net/s "bias_ext", 39 0, L_0xbab339540; 1 drivers +v0xbab2d2800_0 .var "busy", 0 0; +v0xbab2d28a0_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2d2940_0 .var "done", 0 0; +v0xbab2d29e0_0 .net/s "final_acc", 39 0, L_0xbab3395e0; 1 drivers +v0xbab2d2a80_0 .var "group_index", 2 0; +v0xbab2d2b20_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2d2bc0_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2d2c60_0 .net/s "w_bus", 1023 0, L_0xbab331d60; 1 drivers +v0xbab2d2d00_0 .net/s "w_group", 127 0, L_0xbab330d20; 1 drivers +v0xbab2d2da0_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2d2e40_0 .net/s "x_group", 127 0, L_0xbab330c80; 1 drivers +v0xbab2d2ee0_0 .var/s "y", 15 0; +L_0xbab32fac0 .concat [ 3 29 0 0], v0xbab2d2a80_0, L_0xbaa878be0; +L_0xbaad55360 .arith/mult 32, L_0xbab32fac0, L_0xbaa878c28; +L_0xbaad55400 .arith/mult 32, L_0xbaad55360, L_0xbaa878c70; +L_0xbab330c80 .part/v o0xbaa846110, L_0xbaad55400, 128; +L_0xbab32fb60 .concat [ 3 29 0 0], v0xbab2d2a80_0, L_0xbaa878cb8; +L_0xbaad554a0 .arith/mult 32, L_0xbab32fb60, L_0xbaa878d00; +L_0xbaad55540 .arith/mult 32, L_0xbaad554a0, L_0xbaa878d48; +L_0xbab330d20 .part/v L_0xbab331d60, L_0xbaad55540, 128; +L_0xbab331cc0 .part L_0xbab331e00, 15, 1; +L_0xbaad56080 .repeat 24, 24, L_0xbab331cc0; +L_0xbab339540 .concat [ 16 24 0 0], L_0xbab331e00, L_0xbaad56080; +L_0xbab3395e0 .arith/sum 40, L_0xbab3394a0, L_0xbab339540; +S_0xbab2c5e00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2c5c80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab294a00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab294a40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab294a80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab294ac0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2d1900_0 .net/s "acc_in", 39 0, v0xbab2d2580_0; 1 drivers +v0xbab2d19a0_0 .net/s "acc_out", 39 0, L_0xbab3394a0; alias, 1 drivers +v0xbab2d1a40 .array "products", 7 0; +v0xbab2d1a40_0 .net/s v0xbab2d1a40 0, 39 0, L_0xbab32fde0; 1 drivers +v0xbab2d1a40_1 .net/s v0xbab2d1a40 1, 39 0, L_0xbab3380a0; 1 drivers +v0xbab2d1a40_2 .net/s v0xbab2d1a40 2, 39 0, L_0xbab338320; 1 drivers +v0xbab2d1a40_3 .net/s v0xbab2d1a40 3, 39 0, L_0xbab3385a0; 1 drivers +v0xbab2d1a40_4 .net/s v0xbab2d1a40 4, 39 0, L_0xbab338820; 1 drivers +v0xbab2d1a40_5 .net/s v0xbab2d1a40 5, 39 0, L_0xbab338aa0; 1 drivers +v0xbab2d1a40_6 .net/s v0xbab2d1a40 6, 39 0, L_0xbab338d20; 1 drivers +v0xbab2d1a40_7 .net/s v0xbab2d1a40 7, 39 0, L_0xbab338fa0; 1 drivers +v0xbab2d1ae0 .array "tree", 31 0; +v0xbab2d1ae0_0 .net/s v0xbab2d1ae0 0, 39 0, L_0xbab068e00; 1 drivers +v0xbab2d1ae0_1 .net/s v0xbab2d1ae0 1, 39 0, L_0xbab068e70; 1 drivers +v0xbab2d1ae0_2 .net/s v0xbab2d1ae0 2, 39 0, L_0xbab068ee0; 1 drivers +v0xbab2d1ae0_3 .net/s v0xbab2d1ae0 3, 39 0, L_0xbab068f50; 1 drivers +v0xbab2d1ae0_4 .net/s v0xbab2d1ae0 4, 39 0, L_0xbab068fc0; 1 drivers +v0xbab2d1ae0_5 .net/s v0xbab2d1ae0 5, 39 0, L_0xbab069030; 1 drivers +v0xbab2d1ae0_6 .net/s v0xbab2d1ae0 6, 39 0, L_0xbab0690a0; 1 drivers +v0xbab2d1ae0_7 .net/s v0xbab2d1ae0 7, 39 0, L_0xbab069110; 1 drivers +v0xbab2d1ae0_8 .net/s v0xbab2d1ae0 8, 39 0, L_0xbab339040; 1 drivers +v0xbab2d1ae0_9 .net/s v0xbab2d1ae0 9, 39 0, L_0xbab3390e0; 1 drivers +v0xbab2d1ae0_10 .net/s v0xbab2d1ae0 10, 39 0, L_0xbab339180; 1 drivers +v0xbab2d1ae0_11 .net/s v0xbab2d1ae0 11, 39 0, L_0xbab339220; 1 drivers +o0xbaa84bf60 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_12 .net/s v0xbab2d1ae0 12, 39 0, o0xbaa84bf60; 0 drivers +o0xbaa84bf90 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_13 .net/s v0xbab2d1ae0 13, 39 0, o0xbaa84bf90; 0 drivers +o0xbaa84bfc0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_14 .net/s v0xbab2d1ae0 14, 39 0, o0xbaa84bfc0; 0 drivers +o0xbaa84bff0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_15 .net/s v0xbab2d1ae0 15, 39 0, o0xbaa84bff0; 0 drivers +v0xbab2d1ae0_16 .net/s v0xbab2d1ae0 16, 39 0, L_0xbab3392c0; 1 drivers +v0xbab2d1ae0_17 .net/s v0xbab2d1ae0 17, 39 0, L_0xbab339360; 1 drivers +o0xbaa84c080 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_18 .net/s v0xbab2d1ae0 18, 39 0, o0xbaa84c080; 0 drivers +o0xbaa84c0b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_19 .net/s v0xbab2d1ae0 19, 39 0, o0xbaa84c0b0; 0 drivers +o0xbaa84c0e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_20 .net/s v0xbab2d1ae0 20, 39 0, o0xbaa84c0e0; 0 drivers +o0xbaa84c110 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_21 .net/s v0xbab2d1ae0 21, 39 0, o0xbaa84c110; 0 drivers +o0xbaa84c140 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_22 .net/s v0xbab2d1ae0 22, 39 0, o0xbaa84c140; 0 drivers +o0xbaa84c170 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_23 .net/s v0xbab2d1ae0 23, 39 0, o0xbaa84c170; 0 drivers +v0xbab2d1ae0_24 .net/s v0xbab2d1ae0 24, 39 0, L_0xbab339400; 1 drivers +o0xbaa84c1d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_25 .net/s v0xbab2d1ae0 25, 39 0, o0xbaa84c1d0; 0 drivers +o0xbaa84c200 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_26 .net/s v0xbab2d1ae0 26, 39 0, o0xbaa84c200; 0 drivers +o0xbaa84c230 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_27 .net/s v0xbab2d1ae0 27, 39 0, o0xbaa84c230; 0 drivers +o0xbaa84c260 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_28 .net/s v0xbab2d1ae0 28, 39 0, o0xbaa84c260; 0 drivers +o0xbaa84c290 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_29 .net/s v0xbab2d1ae0 29, 39 0, o0xbaa84c290; 0 drivers +o0xbaa84c2c0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_30 .net/s v0xbab2d1ae0 30, 39 0, o0xbaa84c2c0; 0 drivers +o0xbaa84c2f0 .functor BUFZ 40, c4; HiZ drive +v0xbab2d1ae0_31 .net/s v0xbab2d1ae0 31, 39 0, o0xbaa84c2f0; 0 drivers +v0xbab2d1b80_0 .net/s "w_bus", 127 0, L_0xbab330d20; alias, 1 drivers +v0xbab2d1c20_0 .net/s "x_bus", 127 0, L_0xbab330c80; alias, 1 drivers +L_0xbab330e60 .part L_0xbab330c80, 0, 16; +L_0xbab330f00 .part L_0xbab330d20, 0, 16; +L_0xbab331040 .part L_0xbab330c80, 16, 16; +L_0xbab3310e0 .part L_0xbab330d20, 16, 16; +L_0xbab331220 .part L_0xbab330c80, 32, 16; +L_0xbab3312c0 .part L_0xbab330d20, 32, 16; +L_0xbab331400 .part L_0xbab330c80, 48, 16; +L_0xbab3314a0 .part L_0xbab330d20, 48, 16; +L_0xbab3315e0 .part L_0xbab330c80, 64, 16; +L_0xbab331680 .part L_0xbab330d20, 64, 16; +L_0xbab3317c0 .part L_0xbab330c80, 80, 16; +L_0xbab331860 .part L_0xbab330d20, 80, 16; +L_0xbab3319a0 .part L_0xbab330c80, 96, 16; +L_0xbab331a40 .part L_0xbab330d20, 96, 16; +L_0xbab331b80 .part L_0xbab330c80, 112, 16; +L_0xbab331c20 .part L_0xbab330d20, 112, 16; +L_0xbab3394a0 .arith/sum 40, v0xbab2d2580_0, L_0xbab339400; +S_0xbab2c5f80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b140 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2c6100 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c5f80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4cfc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d000 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d040 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c26c0_0 .net/s *"_ivl_0", 31 0, L_0xbab32fc00; 1 drivers +v0xbab2c2760_0 .net/s *"_ivl_2", 31 0, L_0xbab32fca0; 1 drivers +v0xbab2c2800_0 .net *"_ivl_7", 0 0, L_0xbab330dc0; 1 drivers +v0xbab2c28a0_0 .net *"_ivl_9", 7 0, L_0xbaad55680; 1 drivers +L_0xbaa878d90 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c2940_0 .net/s "acc_in", 39 0, L_0xbaa878d90; 1 drivers +v0xbab2c29e0_0 .net/s "acc_out", 39 0, L_0xbab32fde0; alias, 1 drivers +v0xbab2c2a80_0 .net/s "product", 31 0, L_0xbaad555e0; 1 drivers +v0xbab2c2b20_0 .net/s "product_ext", 39 0, L_0xbab32fd40; 1 drivers +v0xbab2c2bc0_0 .net/s "w", 15 0, L_0xbab330f00; 1 drivers +v0xbab2c2c60_0 .net/s "x", 15 0, L_0xbab330e60; 1 drivers +L_0xbab32fc00 .extend/s 32, L_0xbab330e60; +L_0xbab32fca0 .extend/s 32, L_0xbab330f00; +L_0xbaad555e0 .arith/mult 32, L_0xbab32fc00, L_0xbab32fca0; +L_0xbab330dc0 .part L_0xbaad555e0, 31, 1; +L_0xbaad55680 .repeat 8, 8, L_0xbab330dc0; +L_0xbab32fd40 .concat [ 32 8 0 0], L_0xbaad555e0, L_0xbaad55680; +L_0xbab32fde0 .arith/sum 40, L_0xbaa878d90, L_0xbab32fd40; +S_0xbab2c6280 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b180 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2c6400 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c6280; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d080 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d0c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d100 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c2d00_0 .net/s *"_ivl_0", 31 0, L_0xbab32fe80; 1 drivers +v0xbab2c2da0_0 .net/s *"_ivl_2", 31 0, L_0xbab32ff20; 1 drivers +v0xbab2c2e40_0 .net *"_ivl_7", 0 0, L_0xbab330fa0; 1 drivers +v0xbab2c2ee0_0 .net *"_ivl_9", 7 0, L_0xbaad557c0; 1 drivers +L_0xbaa878dd8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c2f80_0 .net/s "acc_in", 39 0, L_0xbaa878dd8; 1 drivers +v0xbab2c3020_0 .net/s "acc_out", 39 0, L_0xbab3380a0; alias, 1 drivers +v0xbab2c30c0_0 .net/s "product", 31 0, L_0xbaad55720; 1 drivers +v0xbab2c3160_0 .net/s "product_ext", 39 0, L_0xbab338000; 1 drivers +v0xbab2c3200_0 .net/s "w", 15 0, L_0xbab3310e0; 1 drivers +v0xbab2c32a0_0 .net/s "x", 15 0, L_0xbab331040; 1 drivers +L_0xbab32fe80 .extend/s 32, L_0xbab331040; +L_0xbab32ff20 .extend/s 32, L_0xbab3310e0; +L_0xbaad55720 .arith/mult 32, L_0xbab32fe80, L_0xbab32ff20; +L_0xbab330fa0 .part L_0xbaad55720, 31, 1; +L_0xbaad557c0 .repeat 8, 8, L_0xbab330fa0; +L_0xbab338000 .concat [ 32 8 0 0], L_0xbaad55720, L_0xbaad557c0; +L_0xbab3380a0 .arith/sum 40, L_0xbaa878dd8, L_0xbab338000; +S_0xbab2c6580 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b1c0 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2c6700 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c6580; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d140 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d180 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d1c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c3340_0 .net/s *"_ivl_0", 31 0, L_0xbab338140; 1 drivers +v0xbab2c33e0_0 .net/s *"_ivl_2", 31 0, L_0xbab3381e0; 1 drivers +v0xbab2c3480_0 .net *"_ivl_7", 0 0, L_0xbab331180; 1 drivers +v0xbab2c3520_0 .net *"_ivl_9", 7 0, L_0xbaad55900; 1 drivers +L_0xbaa878e20 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c35c0_0 .net/s "acc_in", 39 0, L_0xbaa878e20; 1 drivers +v0xbab2c3660_0 .net/s "acc_out", 39 0, L_0xbab338320; alias, 1 drivers +v0xbab2c3700_0 .net/s "product", 31 0, L_0xbaad55860; 1 drivers +v0xbab2c37a0_0 .net/s "product_ext", 39 0, L_0xbab338280; 1 drivers +v0xbab2c3840_0 .net/s "w", 15 0, L_0xbab3312c0; 1 drivers +v0xbab2c38e0_0 .net/s "x", 15 0, L_0xbab331220; 1 drivers +L_0xbab338140 .extend/s 32, L_0xbab331220; +L_0xbab3381e0 .extend/s 32, L_0xbab3312c0; +L_0xbaad55860 .arith/mult 32, L_0xbab338140, L_0xbab3381e0; +L_0xbab331180 .part L_0xbaad55860, 31, 1; +L_0xbaad55900 .repeat 8, 8, L_0xbab331180; +L_0xbab338280 .concat [ 32 8 0 0], L_0xbaad55860, L_0xbaad55900; +L_0xbab338320 .arith/sum 40, L_0xbaa878e20, L_0xbab338280; +S_0xbab2c6880 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b200 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2c6a00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c6880; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d200 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d240 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d280 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2c3980_0 .net/s *"_ivl_0", 31 0, L_0xbab3383c0; 1 drivers +v0xbab2c3a20_0 .net/s *"_ivl_2", 31 0, L_0xbab338460; 1 drivers +v0xbab2c3ac0_0 .net *"_ivl_7", 0 0, L_0xbab331360; 1 drivers +v0xbab2c3b60_0 .net *"_ivl_9", 7 0, L_0xbaad55a40; 1 drivers +L_0xbaa878e68 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2c3c00_0 .net/s "acc_in", 39 0, L_0xbaa878e68; 1 drivers +v0xbab2c3ca0_0 .net/s "acc_out", 39 0, L_0xbab3385a0; alias, 1 drivers +v0xbab2c3d40_0 .net/s "product", 31 0, L_0xbaad559a0; 1 drivers +v0xbab2c3de0_0 .net/s "product_ext", 39 0, L_0xbab338500; 1 drivers +v0xbab2c3e80_0 .net/s "w", 15 0, L_0xbab3314a0; 1 drivers +v0xbab2c3f20_0 .net/s "x", 15 0, L_0xbab331400; 1 drivers +L_0xbab3383c0 .extend/s 32, L_0xbab331400; +L_0xbab338460 .extend/s 32, L_0xbab3314a0; +L_0xbaad559a0 .arith/mult 32, L_0xbab3383c0, L_0xbab338460; +L_0xbab331360 .part L_0xbaad559a0, 31, 1; +L_0xbaad55a40 .repeat 8, 8, L_0xbab331360; +L_0xbab338500 .concat [ 32 8 0 0], L_0xbaad559a0, L_0xbaad55a40; +L_0xbab3385a0 .arith/sum 40, L_0xbaa878e68, L_0xbab338500; +S_0xbab2c6b80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b280 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2c6d00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c6b80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d2c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d300 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d340 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d0000_0 .net/s *"_ivl_0", 31 0, L_0xbab338640; 1 drivers +v0xbab2d00a0_0 .net/s *"_ivl_2", 31 0, L_0xbab3386e0; 1 drivers +v0xbab2d0140_0 .net *"_ivl_7", 0 0, L_0xbab331540; 1 drivers +v0xbab2d01e0_0 .net *"_ivl_9", 7 0, L_0xbaad55b80; 1 drivers +L_0xbaa878eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d0280_0 .net/s "acc_in", 39 0, L_0xbaa878eb0; 1 drivers +v0xbab2d0320_0 .net/s "acc_out", 39 0, L_0xbab338820; alias, 1 drivers +v0xbab2d03c0_0 .net/s "product", 31 0, L_0xbaad55ae0; 1 drivers +v0xbab2d0460_0 .net/s "product_ext", 39 0, L_0xbab338780; 1 drivers +v0xbab2d0500_0 .net/s "w", 15 0, L_0xbab331680; 1 drivers +v0xbab2d05a0_0 .net/s "x", 15 0, L_0xbab3315e0; 1 drivers +L_0xbab338640 .extend/s 32, L_0xbab3315e0; +L_0xbab3386e0 .extend/s 32, L_0xbab331680; +L_0xbaad55ae0 .arith/mult 32, L_0xbab338640, L_0xbab3386e0; +L_0xbab331540 .part L_0xbaad55ae0, 31, 1; +L_0xbaad55b80 .repeat 8, 8, L_0xbab331540; +L_0xbab338780 .concat [ 32 8 0 0], L_0xbaad55ae0, L_0xbaad55b80; +L_0xbab338820 .arith/sum 40, L_0xbaa878eb0, L_0xbab338780; +S_0xbab2c6e80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b2c0 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2c7000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c6e80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d380 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d3c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d400 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d0640_0 .net/s *"_ivl_0", 31 0, L_0xbab3388c0; 1 drivers +v0xbab2d06e0_0 .net/s *"_ivl_2", 31 0, L_0xbab338960; 1 drivers +v0xbab2d0780_0 .net *"_ivl_7", 0 0, L_0xbab331720; 1 drivers +v0xbab2d0820_0 .net *"_ivl_9", 7 0, L_0xbaad55cc0; 1 drivers +L_0xbaa878ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d08c0_0 .net/s "acc_in", 39 0, L_0xbaa878ef8; 1 drivers +v0xbab2d0960_0 .net/s "acc_out", 39 0, L_0xbab338aa0; alias, 1 drivers +v0xbab2d0a00_0 .net/s "product", 31 0, L_0xbaad55c20; 1 drivers +v0xbab2d0aa0_0 .net/s "product_ext", 39 0, L_0xbab338a00; 1 drivers +v0xbab2d0b40_0 .net/s "w", 15 0, L_0xbab331860; 1 drivers +v0xbab2d0be0_0 .net/s "x", 15 0, L_0xbab3317c0; 1 drivers +L_0xbab3388c0 .extend/s 32, L_0xbab3317c0; +L_0xbab338960 .extend/s 32, L_0xbab331860; +L_0xbaad55c20 .arith/mult 32, L_0xbab3388c0, L_0xbab338960; +L_0xbab331720 .part L_0xbaad55c20, 31, 1; +L_0xbaad55cc0 .repeat 8, 8, L_0xbab331720; +L_0xbab338a00 .concat [ 32 8 0 0], L_0xbaad55c20, L_0xbaad55cc0; +L_0xbab338aa0 .arith/sum 40, L_0xbaa878ef8, L_0xbab338a00; +S_0xbab2c7180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b300 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2c7300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c7180; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d440 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d480 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d4c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d0c80_0 .net/s *"_ivl_0", 31 0, L_0xbab338b40; 1 drivers +v0xbab2d0d20_0 .net/s *"_ivl_2", 31 0, L_0xbab338be0; 1 drivers +v0xbab2d0dc0_0 .net *"_ivl_7", 0 0, L_0xbab331900; 1 drivers +v0xbab2d0e60_0 .net *"_ivl_9", 7 0, L_0xbaad55e00; 1 drivers +L_0xbaa878f40 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d0f00_0 .net/s "acc_in", 39 0, L_0xbaa878f40; 1 drivers +v0xbab2d0fa0_0 .net/s "acc_out", 39 0, L_0xbab338d20; alias, 1 drivers +v0xbab2d1040_0 .net/s "product", 31 0, L_0xbaad55d60; 1 drivers +v0xbab2d10e0_0 .net/s "product_ext", 39 0, L_0xbab338c80; 1 drivers +v0xbab2d1180_0 .net/s "w", 15 0, L_0xbab331a40; 1 drivers +v0xbab2d1220_0 .net/s "x", 15 0, L_0xbab3319a0; 1 drivers +L_0xbab338b40 .extend/s 32, L_0xbab3319a0; +L_0xbab338be0 .extend/s 32, L_0xbab331a40; +L_0xbaad55d60 .arith/mult 32, L_0xbab338b40, L_0xbab338be0; +L_0xbab331900 .part L_0xbaad55d60, 31, 1; +L_0xbaad55e00 .repeat 8, 8, L_0xbab331900; +L_0xbab338c80 .concat [ 32 8 0 0], L_0xbaad55d60, L_0xbaad55e00; +L_0xbab338d20 .arith/sum 40, L_0xbaa878f40, L_0xbab338c80; +S_0xbab2c7480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b340 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2c7600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2c7480; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d500 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d540 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d580 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d12c0_0 .net/s *"_ivl_0", 31 0, L_0xbab338dc0; 1 drivers +v0xbab2d1360_0 .net/s *"_ivl_2", 31 0, L_0xbab338e60; 1 drivers +v0xbab2d1400_0 .net *"_ivl_7", 0 0, L_0xbab331ae0; 1 drivers +v0xbab2d14a0_0 .net *"_ivl_9", 7 0, L_0xbaad55f40; 1 drivers +L_0xbaa878f88 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d1540_0 .net/s "acc_in", 39 0, L_0xbaa878f88; 1 drivers +v0xbab2d15e0_0 .net/s "acc_out", 39 0, L_0xbab338fa0; alias, 1 drivers +v0xbab2d1680_0 .net/s "product", 31 0, L_0xbaad55ea0; 1 drivers +v0xbab2d1720_0 .net/s "product_ext", 39 0, L_0xbab338f00; 1 drivers +v0xbab2d17c0_0 .net/s "w", 15 0, L_0xbab331c20; 1 drivers +v0xbab2d1860_0 .net/s "x", 15 0, L_0xbab331b80; 1 drivers +L_0xbab338dc0 .extend/s 32, L_0xbab331b80; +L_0xbab338e60 .extend/s 32, L_0xbab331c20; +L_0xbaad55ea0 .arith/mult 32, L_0xbab338dc0, L_0xbab338e60; +L_0xbab331ae0 .part L_0xbaad55ea0, 31, 1; +L_0xbaad55f40 .repeat 8, 8, L_0xbab331ae0; +L_0xbab338f00 .concat [ 32 8 0 0], L_0xbaad55ea0, L_0xbaad55f40; +L_0xbab338fa0 .arith/sum 40, L_0xbaa878f88, L_0xbab338f00; +S_0xbab2c7780 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b240 .param/l "i" 1 5 80, +C4<00>; +L_0xbab068e00 .functor BUFZ 40, L_0xbab32fde0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c7900 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b380 .param/l "i" 1 5 80, +C4<01>; +L_0xbab068e70 .functor BUFZ 40, L_0xbab3380a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c7a80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b3c0 .param/l "i" 1 5 80, +C4<010>; +L_0xbab068ee0 .functor BUFZ 40, L_0xbab338320, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c7c00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b400 .param/l "i" 1 5 80, +C4<011>; +L_0xbab068f50 .functor BUFZ 40, L_0xbab3385a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2c7d80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b440 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab068fc0 .functor BUFZ 40, L_0xbab338820, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d4000 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b480 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab069030 .functor BUFZ 40, L_0xbab338aa0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d4180 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b4c0 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab0690a0 .functor BUFZ 40, L_0xbab338d20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d4300 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b500 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab069110 .functor BUFZ 40, L_0xbab338fa0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d4480 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b540 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2d4600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2d4480; + .timescale 0 0; +P_0xbaad2b580 .param/l "node" 1 5 94, +C4<00>; +L_0xbab339040 .arith/sum 40, L_0xbab068e00, L_0xbab068e70; +S_0xbab2d4780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2d4480; + .timescale 0 0; +P_0xbaad2b5c0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab3390e0 .arith/sum 40, L_0xbab068ee0, L_0xbab068f50; +S_0xbab2d4900 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2d4480; + .timescale 0 0; +P_0xbaad2b600 .param/l "node" 1 5 94, +C4<010>; +L_0xbab339180 .arith/sum 40, L_0xbab068fc0, L_0xbab069030; +S_0xbab2d4a80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2d4480; + .timescale 0 0; +P_0xbaad2b640 .param/l "node" 1 5 94, +C4<011>; +L_0xbab339220 .arith/sum 40, L_0xbab0690a0, L_0xbab069110; +S_0xbab2d4c00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b680 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2d4d80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2d4c00; + .timescale 0 0; +P_0xbaad2b6c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab3392c0 .arith/sum 40, L_0xbab339040, L_0xbab3390e0; +S_0xbab2d4f00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2d4c00; + .timescale 0 0; +P_0xbaad2b700 .param/l "node" 1 5 94, +C4<01>; +L_0xbab339360 .arith/sum 40, L_0xbab339180, L_0xbab339220; +S_0xbab2d5080 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2c5e00; + .timescale 0 0; +P_0xbaad2b740 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2d5200 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2d5080; + .timescale 0 0; +P_0xbaad2b780 .param/l "node" 1 5 94, +C4<00>; +L_0xbab339400 .arith/sum 40, L_0xbab3392c0, L_0xbab339360; +S_0xbab2d5380 .scope generate, "GEN_NEURON[4]" "GEN_NEURON[4]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad2b840 .param/l "n" 1 3 34, +C4<0100>; +S_0xbab2d5500 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2d5380; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc300 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc340 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc380 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc3c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc400 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc440 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2da580_0 .net *"_ivl_0", 31 0, L_0xbab339680; 1 drivers +v0xbab2da620_0 .net *"_ivl_11", 31 0, L_0xbaad561c0; 1 drivers +v0xbab2da6c0_0 .net *"_ivl_14", 31 0, L_0xbab339720; 1 drivers +L_0xbaa8790a8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2da760_0 .net *"_ivl_17", 28 0, L_0xbaa8790a8; 1 drivers +L_0xbaa8790f0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2da800_0 .net/2u *"_ivl_18", 31 0, L_0xbaa8790f0; 1 drivers +v0xbab2da8a0_0 .net *"_ivl_21", 31 0, L_0xbaad56260; 1 drivers +L_0xbaa879138 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2da940_0 .net/2u *"_ivl_22", 31 0, L_0xbaa879138; 1 drivers +v0xbab2da9e0_0 .net *"_ivl_25", 31 0, L_0xbaad56300; 1 drivers +v0xbab2daa80_0 .net *"_ivl_29", 0 0, L_0xbab332ee0; 1 drivers +L_0xbaa878fd0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2dab20_0 .net *"_ivl_3", 28 0, L_0xbaa878fd0; 1 drivers +v0xbab2dabc0_0 .net *"_ivl_31", 23 0, L_0xbaad56e40; 1 drivers +L_0xbaa879018 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2dac60_0 .net/2u *"_ivl_4", 31 0, L_0xbaa879018; 1 drivers +v0xbab2dad00_0 .net *"_ivl_7", 31 0, L_0xbaad56120; 1 drivers +L_0xbaa879060 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2dada0_0 .net/2u *"_ivl_8", 31 0, L_0xbaa879060; 1 drivers +v0xbab2dae40_0 .var/s "acc", 39 0; +v0xbab2daee0_0 .net/s "acc_next", 39 0, L_0xbab33b020; 1 drivers +v0xbab2daf80_0 .net/s "bias", 15 0, L_0xbab333020; 1 drivers +v0xbab2db020_0 .net/s "bias_ext", 39 0, L_0xbab33b0c0; 1 drivers +v0xbab2db0c0_0 .var "busy", 0 0; +v0xbab2db160_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2db200_0 .var "done", 0 0; +v0xbab2db2a0_0 .net/s "final_acc", 39 0, L_0xbab33b160; 1 drivers +v0xbab2db340_0 .var "group_index", 2 0; +v0xbab2db3e0_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2db480_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2db520_0 .net/s "w_bus", 1023 0, L_0xbab332f80; 1 drivers +v0xbab2db5c0_0 .net/s "w_group", 127 0, L_0xbab331f40; 1 drivers +v0xbab2db660_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2db700_0 .net/s "x_group", 127 0, L_0xbab331ea0; 1 drivers +v0xbab2db7a0_0 .var/s "y", 15 0; +L_0xbab339680 .concat [ 3 29 0 0], v0xbab2db340_0, L_0xbaa878fd0; +L_0xbaad56120 .arith/mult 32, L_0xbab339680, L_0xbaa879018; +L_0xbaad561c0 .arith/mult 32, L_0xbaad56120, L_0xbaa879060; +L_0xbab331ea0 .part/v o0xbaa846110, L_0xbaad561c0, 128; +L_0xbab339720 .concat [ 3 29 0 0], v0xbab2db340_0, L_0xbaa8790a8; +L_0xbaad56260 .arith/mult 32, L_0xbab339720, L_0xbaa8790f0; +L_0xbaad56300 .arith/mult 32, L_0xbaad56260, L_0xbaa879138; +L_0xbab331f40 .part/v L_0xbab332f80, L_0xbaad56300, 128; +L_0xbab332ee0 .part L_0xbab333020, 15, 1; +L_0xbaad56e40 .repeat 24, 24, L_0xbab332ee0; +L_0xbab33b0c0 .concat [ 16 24 0 0], L_0xbab333020, L_0xbaad56e40; +L_0xbab33b160 .arith/sum 40, L_0xbab33b020, L_0xbab33b0c0; +S_0xbab2d5680 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2d5500; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab294d00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab294d40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab294d80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab294dc0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2da1c0_0 .net/s "acc_in", 39 0, v0xbab2dae40_0; 1 drivers +v0xbab2da260_0 .net/s "acc_out", 39 0, L_0xbab33b020; alias, 1 drivers +v0xbab2da300 .array "products", 7 0; +v0xbab2da300_0 .net/s v0xbab2da300 0, 39 0, L_0xbab3399a0; 1 drivers +v0xbab2da300_1 .net/s v0xbab2da300 1, 39 0, L_0xbab339c20; 1 drivers +v0xbab2da300_2 .net/s v0xbab2da300 2, 39 0, L_0xbab339ea0; 1 drivers +v0xbab2da300_3 .net/s v0xbab2da300 3, 39 0, L_0xbab33a120; 1 drivers +v0xbab2da300_4 .net/s v0xbab2da300 4, 39 0, L_0xbab33a3a0; 1 drivers +v0xbab2da300_5 .net/s v0xbab2da300 5, 39 0, L_0xbab33a620; 1 drivers +v0xbab2da300_6 .net/s v0xbab2da300 6, 39 0, L_0xbab33a8a0; 1 drivers +v0xbab2da300_7 .net/s v0xbab2da300 7, 39 0, L_0xbab33ab20; 1 drivers +v0xbab2da3a0 .array "tree", 31 0; +v0xbab2da3a0_0 .net/s v0xbab2da3a0 0, 39 0, L_0xbab069180; 1 drivers +v0xbab2da3a0_1 .net/s v0xbab2da3a0 1, 39 0, L_0xbab0691f0; 1 drivers +v0xbab2da3a0_2 .net/s v0xbab2da3a0 2, 39 0, L_0xbab069260; 1 drivers +v0xbab2da3a0_3 .net/s v0xbab2da3a0 3, 39 0, L_0xbab0692d0; 1 drivers +v0xbab2da3a0_4 .net/s v0xbab2da3a0 4, 39 0, L_0xbab069340; 1 drivers +v0xbab2da3a0_5 .net/s v0xbab2da3a0 5, 39 0, L_0xbab0693b0; 1 drivers +v0xbab2da3a0_6 .net/s v0xbab2da3a0 6, 39 0, L_0xbab069420; 1 drivers +v0xbab2da3a0_7 .net/s v0xbab2da3a0 7, 39 0, L_0xbab069490; 1 drivers +v0xbab2da3a0_8 .net/s v0xbab2da3a0 8, 39 0, L_0xbab33abc0; 1 drivers +v0xbab2da3a0_9 .net/s v0xbab2da3a0 9, 39 0, L_0xbab33ac60; 1 drivers +v0xbab2da3a0_10 .net/s v0xbab2da3a0 10, 39 0, L_0xbab33ad00; 1 drivers +v0xbab2da3a0_11 .net/s v0xbab2da3a0 11, 39 0, L_0xbab33ada0; 1 drivers +o0xbaa84e1b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_12 .net/s v0xbab2da3a0 12, 39 0, o0xbaa84e1b0; 0 drivers +o0xbaa84e1e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_13 .net/s v0xbab2da3a0 13, 39 0, o0xbaa84e1e0; 0 drivers +o0xbaa84e210 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_14 .net/s v0xbab2da3a0 14, 39 0, o0xbaa84e210; 0 drivers +o0xbaa84e240 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_15 .net/s v0xbab2da3a0 15, 39 0, o0xbaa84e240; 0 drivers +v0xbab2da3a0_16 .net/s v0xbab2da3a0 16, 39 0, L_0xbab33ae40; 1 drivers +v0xbab2da3a0_17 .net/s v0xbab2da3a0 17, 39 0, L_0xbab33aee0; 1 drivers +o0xbaa84e2d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_18 .net/s v0xbab2da3a0 18, 39 0, o0xbaa84e2d0; 0 drivers +o0xbaa84e300 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_19 .net/s v0xbab2da3a0 19, 39 0, o0xbaa84e300; 0 drivers +o0xbaa84e330 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_20 .net/s v0xbab2da3a0 20, 39 0, o0xbaa84e330; 0 drivers +o0xbaa84e360 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_21 .net/s v0xbab2da3a0 21, 39 0, o0xbaa84e360; 0 drivers +o0xbaa84e390 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_22 .net/s v0xbab2da3a0 22, 39 0, o0xbaa84e390; 0 drivers +o0xbaa84e3c0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_23 .net/s v0xbab2da3a0 23, 39 0, o0xbaa84e3c0; 0 drivers +v0xbab2da3a0_24 .net/s v0xbab2da3a0 24, 39 0, L_0xbab33af80; 1 drivers +o0xbaa84e420 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_25 .net/s v0xbab2da3a0 25, 39 0, o0xbaa84e420; 0 drivers +o0xbaa84e450 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_26 .net/s v0xbab2da3a0 26, 39 0, o0xbaa84e450; 0 drivers +o0xbaa84e480 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_27 .net/s v0xbab2da3a0 27, 39 0, o0xbaa84e480; 0 drivers +o0xbaa84e4b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_28 .net/s v0xbab2da3a0 28, 39 0, o0xbaa84e4b0; 0 drivers +o0xbaa84e4e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_29 .net/s v0xbab2da3a0 29, 39 0, o0xbaa84e4e0; 0 drivers +o0xbaa84e510 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_30 .net/s v0xbab2da3a0 30, 39 0, o0xbaa84e510; 0 drivers +o0xbaa84e540 .functor BUFZ 40, c4; HiZ drive +v0xbab2da3a0_31 .net/s v0xbab2da3a0 31, 39 0, o0xbaa84e540; 0 drivers +v0xbab2da440_0 .net/s "w_bus", 127 0, L_0xbab331f40; alias, 1 drivers +v0xbab2da4e0_0 .net/s "x_bus", 127 0, L_0xbab331ea0; alias, 1 drivers +L_0xbab332080 .part L_0xbab331ea0, 0, 16; +L_0xbab332120 .part L_0xbab331f40, 0, 16; +L_0xbab332260 .part L_0xbab331ea0, 16, 16; +L_0xbab332300 .part L_0xbab331f40, 16, 16; +L_0xbab332440 .part L_0xbab331ea0, 32, 16; +L_0xbab3324e0 .part L_0xbab331f40, 32, 16; +L_0xbab332620 .part L_0xbab331ea0, 48, 16; +L_0xbab3326c0 .part L_0xbab331f40, 48, 16; +L_0xbab332800 .part L_0xbab331ea0, 64, 16; +L_0xbab3328a0 .part L_0xbab331f40, 64, 16; +L_0xbab3329e0 .part L_0xbab331ea0, 80, 16; +L_0xbab332a80 .part L_0xbab331f40, 80, 16; +L_0xbab332bc0 .part L_0xbab331ea0, 96, 16; +L_0xbab332c60 .part L_0xbab331f40, 96, 16; +L_0xbab332da0 .part L_0xbab331ea0, 112, 16; +L_0xbab332e40 .part L_0xbab331f40, 112, 16; +L_0xbab33b020 .arith/sum 40, v0xbab2dae40_0, L_0xbab33af80; +S_0xbab2d5800 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b880 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2d5980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d5800; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d5c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d600 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d640 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d2f80_0 .net/s *"_ivl_0", 31 0, L_0xbab3397c0; 1 drivers +v0xbab2d3020_0 .net/s *"_ivl_2", 31 0, L_0xbab339860; 1 drivers +v0xbab2d30c0_0 .net *"_ivl_7", 0 0, L_0xbab331fe0; 1 drivers +v0xbab2d3160_0 .net *"_ivl_9", 7 0, L_0xbaad56440; 1 drivers +L_0xbaa879180 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d3200_0 .net/s "acc_in", 39 0, L_0xbaa879180; 1 drivers +v0xbab2d32a0_0 .net/s "acc_out", 39 0, L_0xbab3399a0; alias, 1 drivers +v0xbab2d3340_0 .net/s "product", 31 0, L_0xbaad563a0; 1 drivers +v0xbab2d33e0_0 .net/s "product_ext", 39 0, L_0xbab339900; 1 drivers +v0xbab2d3480_0 .net/s "w", 15 0, L_0xbab332120; 1 drivers +v0xbab2d3520_0 .net/s "x", 15 0, L_0xbab332080; 1 drivers +L_0xbab3397c0 .extend/s 32, L_0xbab332080; +L_0xbab339860 .extend/s 32, L_0xbab332120; +L_0xbaad563a0 .arith/mult 32, L_0xbab3397c0, L_0xbab339860; +L_0xbab331fe0 .part L_0xbaad563a0, 31, 1; +L_0xbaad56440 .repeat 8, 8, L_0xbab331fe0; +L_0xbab339900 .concat [ 32 8 0 0], L_0xbaad563a0, L_0xbaad56440; +L_0xbab3399a0 .arith/sum 40, L_0xbaa879180, L_0xbab339900; +S_0xbab2d5b00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b8c0 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2d5c80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d5b00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d680 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d6c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d700 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d35c0_0 .net/s *"_ivl_0", 31 0, L_0xbab339a40; 1 drivers +v0xbab2d3660_0 .net/s *"_ivl_2", 31 0, L_0xbab339ae0; 1 drivers +v0xbab2d3700_0 .net *"_ivl_7", 0 0, L_0xbab3321c0; 1 drivers +v0xbab2d37a0_0 .net *"_ivl_9", 7 0, L_0xbaad56580; 1 drivers +L_0xbaa8791c8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d3840_0 .net/s "acc_in", 39 0, L_0xbaa8791c8; 1 drivers +v0xbab2d38e0_0 .net/s "acc_out", 39 0, L_0xbab339c20; alias, 1 drivers +v0xbab2d3980_0 .net/s "product", 31 0, L_0xbaad564e0; 1 drivers +v0xbab2d3a20_0 .net/s "product_ext", 39 0, L_0xbab339b80; 1 drivers +v0xbab2d3ac0_0 .net/s "w", 15 0, L_0xbab332300; 1 drivers +v0xbab2d3b60_0 .net/s "x", 15 0, L_0xbab332260; 1 drivers +L_0xbab339a40 .extend/s 32, L_0xbab332260; +L_0xbab339ae0 .extend/s 32, L_0xbab332300; +L_0xbaad564e0 .arith/mult 32, L_0xbab339a40, L_0xbab339ae0; +L_0xbab3321c0 .part L_0xbaad564e0, 31, 1; +L_0xbaad56580 .repeat 8, 8, L_0xbab3321c0; +L_0xbab339b80 .concat [ 32 8 0 0], L_0xbaad564e0, L_0xbaad56580; +L_0xbab339c20 .arith/sum 40, L_0xbaa8791c8, L_0xbab339b80; +S_0xbab2d5e00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b900 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2d5f80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d5e00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d740 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d780 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d7c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d3c00_0 .net/s *"_ivl_0", 31 0, L_0xbab339cc0; 1 drivers +v0xbab2d3ca0_0 .net/s *"_ivl_2", 31 0, L_0xbab339d60; 1 drivers +v0xbab2d3d40_0 .net *"_ivl_7", 0 0, L_0xbab3323a0; 1 drivers +v0xbab2d3de0_0 .net *"_ivl_9", 7 0, L_0xbaad566c0; 1 drivers +L_0xbaa879210 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d3e80_0 .net/s "acc_in", 39 0, L_0xbaa879210; 1 drivers +v0xbab2d3f20_0 .net/s "acc_out", 39 0, L_0xbab339ea0; alias, 1 drivers +v0xbab2d8000_0 .net/s "product", 31 0, L_0xbaad56620; 1 drivers +v0xbab2d80a0_0 .net/s "product_ext", 39 0, L_0xbab339e00; 1 drivers +v0xbab2d8140_0 .net/s "w", 15 0, L_0xbab3324e0; 1 drivers +v0xbab2d81e0_0 .net/s "x", 15 0, L_0xbab332440; 1 drivers +L_0xbab339cc0 .extend/s 32, L_0xbab332440; +L_0xbab339d60 .extend/s 32, L_0xbab3324e0; +L_0xbaad56620 .arith/mult 32, L_0xbab339cc0, L_0xbab339d60; +L_0xbab3323a0 .part L_0xbaad56620, 31, 1; +L_0xbaad566c0 .repeat 8, 8, L_0xbab3323a0; +L_0xbab339e00 .concat [ 32 8 0 0], L_0xbaad56620, L_0xbaad566c0; +L_0xbab339ea0 .arith/sum 40, L_0xbaa879210, L_0xbab339e00; +S_0xbab2d6100 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b940 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2d6280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d6100; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d800 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d840 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d880 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d8280_0 .net/s *"_ivl_0", 31 0, L_0xbab339f40; 1 drivers +v0xbab2d8320_0 .net/s *"_ivl_2", 31 0, L_0xbab339fe0; 1 drivers +v0xbab2d83c0_0 .net *"_ivl_7", 0 0, L_0xbab332580; 1 drivers +v0xbab2d8460_0 .net *"_ivl_9", 7 0, L_0xbaad56800; 1 drivers +L_0xbaa879258 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d8500_0 .net/s "acc_in", 39 0, L_0xbaa879258; 1 drivers +v0xbab2d85a0_0 .net/s "acc_out", 39 0, L_0xbab33a120; alias, 1 drivers +v0xbab2d8640_0 .net/s "product", 31 0, L_0xbaad56760; 1 drivers +v0xbab2d86e0_0 .net/s "product_ext", 39 0, L_0xbab33a080; 1 drivers +v0xbab2d8780_0 .net/s "w", 15 0, L_0xbab3326c0; 1 drivers +v0xbab2d8820_0 .net/s "x", 15 0, L_0xbab332620; 1 drivers +L_0xbab339f40 .extend/s 32, L_0xbab332620; +L_0xbab339fe0 .extend/s 32, L_0xbab3326c0; +L_0xbaad56760 .arith/mult 32, L_0xbab339f40, L_0xbab339fe0; +L_0xbab332580 .part L_0xbaad56760, 31, 1; +L_0xbaad56800 .repeat 8, 8, L_0xbab332580; +L_0xbab33a080 .concat [ 32 8 0 0], L_0xbaad56760, L_0xbaad56800; +L_0xbab33a120 .arith/sum 40, L_0xbaa879258, L_0xbab33a080; +S_0xbab2d6400 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b9c0 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2d6580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d6400; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d8c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d900 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4d940 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d88c0_0 .net/s *"_ivl_0", 31 0, L_0xbab33a1c0; 1 drivers +v0xbab2d8960_0 .net/s *"_ivl_2", 31 0, L_0xbab33a260; 1 drivers +v0xbab2d8a00_0 .net *"_ivl_7", 0 0, L_0xbab332760; 1 drivers +v0xbab2d8aa0_0 .net *"_ivl_9", 7 0, L_0xbaad56940; 1 drivers +L_0xbaa8792a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d8b40_0 .net/s "acc_in", 39 0, L_0xbaa8792a0; 1 drivers +v0xbab2d8be0_0 .net/s "acc_out", 39 0, L_0xbab33a3a0; alias, 1 drivers +v0xbab2d8c80_0 .net/s "product", 31 0, L_0xbaad568a0; 1 drivers +v0xbab2d8d20_0 .net/s "product_ext", 39 0, L_0xbab33a300; 1 drivers +v0xbab2d8dc0_0 .net/s "w", 15 0, L_0xbab3328a0; 1 drivers +v0xbab2d8e60_0 .net/s "x", 15 0, L_0xbab332800; 1 drivers +L_0xbab33a1c0 .extend/s 32, L_0xbab332800; +L_0xbab33a260 .extend/s 32, L_0xbab3328a0; +L_0xbaad568a0 .arith/mult 32, L_0xbab33a1c0, L_0xbab33a260; +L_0xbab332760 .part L_0xbaad568a0, 31, 1; +L_0xbaad56940 .repeat 8, 8, L_0xbab332760; +L_0xbab33a300 .concat [ 32 8 0 0], L_0xbaad568a0, L_0xbaad56940; +L_0xbab33a3a0 .arith/sum 40, L_0xbaa8792a0, L_0xbab33a300; +S_0xbab2d6700 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2ba00 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2d6880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d6700; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4d980 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4d9c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4da00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d8f00_0 .net/s *"_ivl_0", 31 0, L_0xbab33a440; 1 drivers +v0xbab2d8fa0_0 .net/s *"_ivl_2", 31 0, L_0xbab33a4e0; 1 drivers +v0xbab2d9040_0 .net *"_ivl_7", 0 0, L_0xbab332940; 1 drivers +v0xbab2d90e0_0 .net *"_ivl_9", 7 0, L_0xbaad56a80; 1 drivers +L_0xbaa8792e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d9180_0 .net/s "acc_in", 39 0, L_0xbaa8792e8; 1 drivers +v0xbab2d9220_0 .net/s "acc_out", 39 0, L_0xbab33a620; alias, 1 drivers +v0xbab2d92c0_0 .net/s "product", 31 0, L_0xbaad569e0; 1 drivers +v0xbab2d9360_0 .net/s "product_ext", 39 0, L_0xbab33a580; 1 drivers +v0xbab2d9400_0 .net/s "w", 15 0, L_0xbab332a80; 1 drivers +v0xbab2d94a0_0 .net/s "x", 15 0, L_0xbab3329e0; 1 drivers +L_0xbab33a440 .extend/s 32, L_0xbab3329e0; +L_0xbab33a4e0 .extend/s 32, L_0xbab332a80; +L_0xbaad569e0 .arith/mult 32, L_0xbab33a440, L_0xbab33a4e0; +L_0xbab332940 .part L_0xbaad569e0, 31, 1; +L_0xbaad56a80 .repeat 8, 8, L_0xbab332940; +L_0xbab33a580 .concat [ 32 8 0 0], L_0xbaad569e0, L_0xbaad56a80; +L_0xbab33a620 .arith/sum 40, L_0xbaa8792e8, L_0xbab33a580; +S_0xbab2d6a00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2ba40 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2d6b80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d6a00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4da40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4da80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4dac0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d9540_0 .net/s *"_ivl_0", 31 0, L_0xbab33a6c0; 1 drivers +v0xbab2d95e0_0 .net/s *"_ivl_2", 31 0, L_0xbab33a760; 1 drivers +v0xbab2d9680_0 .net *"_ivl_7", 0 0, L_0xbab332b20; 1 drivers +v0xbab2d9720_0 .net *"_ivl_9", 7 0, L_0xbaad56bc0; 1 drivers +L_0xbaa879330 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d97c0_0 .net/s "acc_in", 39 0, L_0xbaa879330; 1 drivers +v0xbab2d9860_0 .net/s "acc_out", 39 0, L_0xbab33a8a0; alias, 1 drivers +v0xbab2d9900_0 .net/s "product", 31 0, L_0xbaad56b20; 1 drivers +v0xbab2d99a0_0 .net/s "product_ext", 39 0, L_0xbab33a800; 1 drivers +v0xbab2d9a40_0 .net/s "w", 15 0, L_0xbab332c60; 1 drivers +v0xbab2d9ae0_0 .net/s "x", 15 0, L_0xbab332bc0; 1 drivers +L_0xbab33a6c0 .extend/s 32, L_0xbab332bc0; +L_0xbab33a760 .extend/s 32, L_0xbab332c60; +L_0xbaad56b20 .arith/mult 32, L_0xbab33a6c0, L_0xbab33a760; +L_0xbab332b20 .part L_0xbaad56b20, 31, 1; +L_0xbaad56bc0 .repeat 8, 8, L_0xbab332b20; +L_0xbab33a800 .concat [ 32 8 0 0], L_0xbaad56b20, L_0xbaad56bc0; +L_0xbab33a8a0 .arith/sum 40, L_0xbaa879330, L_0xbab33a800; +S_0xbab2d6d00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2ba80 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2d6e80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2d6d00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4db00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4db40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4db80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2d9b80_0 .net/s *"_ivl_0", 31 0, L_0xbab33a940; 1 drivers +v0xbab2d9c20_0 .net/s *"_ivl_2", 31 0, L_0xbab33a9e0; 1 drivers +v0xbab2d9cc0_0 .net *"_ivl_7", 0 0, L_0xbab332d00; 1 drivers +v0xbab2d9d60_0 .net *"_ivl_9", 7 0, L_0xbaad56d00; 1 drivers +L_0xbaa879378 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2d9e00_0 .net/s "acc_in", 39 0, L_0xbaa879378; 1 drivers +v0xbab2d9ea0_0 .net/s "acc_out", 39 0, L_0xbab33ab20; alias, 1 drivers +v0xbab2d9f40_0 .net/s "product", 31 0, L_0xbaad56c60; 1 drivers +v0xbab2d9fe0_0 .net/s "product_ext", 39 0, L_0xbab33aa80; 1 drivers +v0xbab2da080_0 .net/s "w", 15 0, L_0xbab332e40; 1 drivers +v0xbab2da120_0 .net/s "x", 15 0, L_0xbab332da0; 1 drivers +L_0xbab33a940 .extend/s 32, L_0xbab332da0; +L_0xbab33a9e0 .extend/s 32, L_0xbab332e40; +L_0xbaad56c60 .arith/mult 32, L_0xbab33a940, L_0xbab33a9e0; +L_0xbab332d00 .part L_0xbaad56c60, 31, 1; +L_0xbaad56d00 .repeat 8, 8, L_0xbab332d00; +L_0xbab33aa80 .concat [ 32 8 0 0], L_0xbaad56c60, L_0xbaad56d00; +L_0xbab33ab20 .arith/sum 40, L_0xbaa879378, L_0xbab33aa80; +S_0xbab2d7000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2b980 .param/l "i" 1 5 80, +C4<00>; +L_0xbab069180 .functor BUFZ 40, L_0xbab3399a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bac0 .param/l "i" 1 5 80, +C4<01>; +L_0xbab0691f0 .functor BUFZ 40, L_0xbab339c20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bb00 .param/l "i" 1 5 80, +C4<010>; +L_0xbab069260 .functor BUFZ 40, L_0xbab339ea0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bb40 .param/l "i" 1 5 80, +C4<011>; +L_0xbab0692d0 .functor BUFZ 40, L_0xbab33a120, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bb80 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab069340 .functor BUFZ 40, L_0xbab33a3a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bbc0 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab0693b0 .functor BUFZ 40, L_0xbab33a620, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bc00 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab069420 .functor BUFZ 40, L_0xbab33a8a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7a80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bc40 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab069490 .functor BUFZ 40, L_0xbab33ab20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2d7c00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bc80 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2d7d80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2d7c00; + .timescale 0 0; +P_0xbaad2bcc0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab33abc0 .arith/sum 40, L_0xbab069180, L_0xbab0691f0; +S_0xbab2dc000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2d7c00; + .timescale 0 0; +P_0xbaad2bd00 .param/l "node" 1 5 94, +C4<01>; +L_0xbab33ac60 .arith/sum 40, L_0xbab069260, L_0xbab0692d0; +S_0xbab2dc180 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2d7c00; + .timescale 0 0; +P_0xbaad2bd40 .param/l "node" 1 5 94, +C4<010>; +L_0xbab33ad00 .arith/sum 40, L_0xbab069340, L_0xbab0693b0; +S_0xbab2dc300 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2d7c00; + .timescale 0 0; +P_0xbaad2bd80 .param/l "node" 1 5 94, +C4<011>; +L_0xbab33ada0 .arith/sum 40, L_0xbab069420, L_0xbab069490; +S_0xbab2dc480 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2bdc0 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2dc600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2dc480; + .timescale 0 0; +P_0xbaad2be00 .param/l "node" 1 5 94, +C4<00>; +L_0xbab33ae40 .arith/sum 40, L_0xbab33abc0, L_0xbab33ac60; +S_0xbab2dc780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2dc480; + .timescale 0 0; +P_0xbaad2be40 .param/l "node" 1 5 94, +C4<01>; +L_0xbab33aee0 .arith/sum 40, L_0xbab33ad00, L_0xbab33ada0; +S_0xbab2dc900 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2d5680; + .timescale 0 0; +P_0xbaad2be80 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2dca80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2dc900; + .timescale 0 0; +P_0xbaad2bec0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab33af80 .arith/sum 40, L_0xbab33ae40, L_0xbab33aee0; +S_0xbab2dcc00 .scope generate, "GEN_NEURON[5]" "GEN_NEURON[5]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad2bf40 .param/l "n" 1 3 34, +C4<0101>; +S_0xbab2dcd80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2dcc00; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc480 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc4c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc500 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc540 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc580 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc5c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2e2e40_0 .net *"_ivl_0", 31 0, L_0xbab33b200; 1 drivers +v0xbab2e2ee0_0 .net *"_ivl_11", 31 0, L_0xbaad56f80; 1 drivers +v0xbab2e2f80_0 .net *"_ivl_14", 31 0, L_0xbab33b2a0; 1 drivers +L_0xbaa879498 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e3020_0 .net *"_ivl_17", 28 0, L_0xbaa879498; 1 drivers +L_0xbaa8794e0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2e30c0_0 .net/2u *"_ivl_18", 31 0, L_0xbaa8794e0; 1 drivers +v0xbab2e3160_0 .net *"_ivl_21", 31 0, L_0xbaad57020; 1 drivers +L_0xbaa879528 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2e3200_0 .net/2u *"_ivl_22", 31 0, L_0xbaa879528; 1 drivers +v0xbab2e32a0_0 .net *"_ivl_25", 31 0, L_0xbaad570c0; 1 drivers +v0xbab2e3340_0 .net *"_ivl_29", 0 0, L_0xbab344140; 1 drivers +L_0xbaa8793c0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e33e0_0 .net *"_ivl_3", 28 0, L_0xbaa8793c0; 1 drivers +v0xbab2e3480_0 .net *"_ivl_31", 23 0, L_0xbaad57c00; 1 drivers +L_0xbaa879408 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2e3520_0 .net/2u *"_ivl_4", 31 0, L_0xbaa879408; 1 drivers +v0xbab2e35c0_0 .net *"_ivl_7", 31 0, L_0xbaad56ee0; 1 drivers +L_0xbaa879450 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2e3660_0 .net/2u *"_ivl_8", 31 0, L_0xbaa879450; 1 drivers +v0xbab2e3700_0 .var/s "acc", 39 0; +v0xbab2e37a0_0 .net/s "acc_next", 39 0, L_0xbab340be0; 1 drivers +v0xbab2e3840_0 .net/s "bias", 15 0, L_0xbab344280; 1 drivers +v0xbab2e38e0_0 .net/s "bias_ext", 39 0, L_0xbab340c80; 1 drivers +v0xbab2e3980_0 .var "busy", 0 0; +v0xbab2e3a20_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2e3ac0_0 .var "done", 0 0; +v0xbab2e3b60_0 .net/s "final_acc", 39 0, L_0xbab340d20; 1 drivers +v0xbab2e3c00_0 .var "group_index", 2 0; +v0xbab2e3ca0_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2e3d40_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2e3de0_0 .net/s "w_bus", 1023 0, L_0xbab3441e0; 1 drivers +v0xbab2e3e80_0 .net/s "w_group", 127 0, L_0xbab333160; 1 drivers +v0xbab2e3f20_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2e8000_0 .net/s "x_group", 127 0, L_0xbab3330c0; 1 drivers +v0xbab2e80a0_0 .var/s "y", 15 0; +L_0xbab33b200 .concat [ 3 29 0 0], v0xbab2e3c00_0, L_0xbaa8793c0; +L_0xbaad56ee0 .arith/mult 32, L_0xbab33b200, L_0xbaa879408; +L_0xbaad56f80 .arith/mult 32, L_0xbaad56ee0, L_0xbaa879450; +L_0xbab3330c0 .part/v o0xbaa846110, L_0xbaad56f80, 128; +L_0xbab33b2a0 .concat [ 3 29 0 0], v0xbab2e3c00_0, L_0xbaa879498; +L_0xbaad57020 .arith/mult 32, L_0xbab33b2a0, L_0xbaa8794e0; +L_0xbaad570c0 .arith/mult 32, L_0xbaad57020, L_0xbaa879528; +L_0xbab333160 .part/v L_0xbab3441e0, L_0xbaad570c0, 128; +L_0xbab344140 .part L_0xbab344280, 15, 1; +L_0xbaad57c00 .repeat 24, 24, L_0xbab344140; +L_0xbab340c80 .concat [ 16 24 0 0], L_0xbab344280, L_0xbaad57c00; +L_0xbab340d20 .arith/sum 40, L_0xbab340be0, L_0xbab340c80; +S_0xbab2dcf00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2dcd80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab295000 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab295040 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab295080 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2950c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2e2a80_0 .net/s "acc_in", 39 0, v0xbab2e3700_0; 1 drivers +v0xbab2e2b20_0 .net/s "acc_out", 39 0, L_0xbab340be0; alias, 1 drivers +v0xbab2e2bc0 .array "products", 7 0; +v0xbab2e2bc0_0 .net/s v0xbab2e2bc0 0, 39 0, L_0xbab33b520; 1 drivers +v0xbab2e2bc0_1 .net/s v0xbab2e2bc0 1, 39 0, L_0xbab33b7a0; 1 drivers +v0xbab2e2bc0_2 .net/s v0xbab2e2bc0 2, 39 0, L_0xbab33ba20; 1 drivers +v0xbab2e2bc0_3 .net/s v0xbab2e2bc0 3, 39 0, L_0xbab33bca0; 1 drivers +v0xbab2e2bc0_4 .net/s v0xbab2e2bc0 4, 39 0, L_0xbab33bf20; 1 drivers +v0xbab2e2bc0_5 .net/s v0xbab2e2bc0 5, 39 0, L_0xbab3401e0; 1 drivers +v0xbab2e2bc0_6 .net/s v0xbab2e2bc0 6, 39 0, L_0xbab340460; 1 drivers +v0xbab2e2bc0_7 .net/s v0xbab2e2bc0 7, 39 0, L_0xbab3406e0; 1 drivers +v0xbab2e2c60 .array "tree", 31 0; +v0xbab2e2c60_0 .net/s v0xbab2e2c60 0, 39 0, L_0xbab069500; 1 drivers +v0xbab2e2c60_1 .net/s v0xbab2e2c60 1, 39 0, L_0xbab069570; 1 drivers +v0xbab2e2c60_2 .net/s v0xbab2e2c60 2, 39 0, L_0xbab0695e0; 1 drivers +v0xbab2e2c60_3 .net/s v0xbab2e2c60 3, 39 0, L_0xbab069650; 1 drivers +v0xbab2e2c60_4 .net/s v0xbab2e2c60 4, 39 0, L_0xbab0696c0; 1 drivers +v0xbab2e2c60_5 .net/s v0xbab2e2c60 5, 39 0, L_0xbab069730; 1 drivers +v0xbab2e2c60_6 .net/s v0xbab2e2c60 6, 39 0, L_0xbab0697a0; 1 drivers +v0xbab2e2c60_7 .net/s v0xbab2e2c60 7, 39 0, L_0xbab069810; 1 drivers +v0xbab2e2c60_8 .net/s v0xbab2e2c60 8, 39 0, L_0xbab340780; 1 drivers +v0xbab2e2c60_9 .net/s v0xbab2e2c60 9, 39 0, L_0xbab340820; 1 drivers +v0xbab2e2c60_10 .net/s v0xbab2e2c60 10, 39 0, L_0xbab3408c0; 1 drivers +v0xbab2e2c60_11 .net/s v0xbab2e2c60 11, 39 0, L_0xbab340960; 1 drivers +o0xbaa850400 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_12 .net/s v0xbab2e2c60 12, 39 0, o0xbaa850400; 0 drivers +o0xbaa850430 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_13 .net/s v0xbab2e2c60 13, 39 0, o0xbaa850430; 0 drivers +o0xbaa850460 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_14 .net/s v0xbab2e2c60 14, 39 0, o0xbaa850460; 0 drivers +o0xbaa850490 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_15 .net/s v0xbab2e2c60 15, 39 0, o0xbaa850490; 0 drivers +v0xbab2e2c60_16 .net/s v0xbab2e2c60 16, 39 0, L_0xbab340a00; 1 drivers +v0xbab2e2c60_17 .net/s v0xbab2e2c60 17, 39 0, L_0xbab340aa0; 1 drivers +o0xbaa850520 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_18 .net/s v0xbab2e2c60 18, 39 0, o0xbaa850520; 0 drivers +o0xbaa850550 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_19 .net/s v0xbab2e2c60 19, 39 0, o0xbaa850550; 0 drivers +o0xbaa850580 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_20 .net/s v0xbab2e2c60 20, 39 0, o0xbaa850580; 0 drivers +o0xbaa8505b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_21 .net/s v0xbab2e2c60 21, 39 0, o0xbaa8505b0; 0 drivers +o0xbaa8505e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_22 .net/s v0xbab2e2c60 22, 39 0, o0xbaa8505e0; 0 drivers +o0xbaa850610 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_23 .net/s v0xbab2e2c60 23, 39 0, o0xbaa850610; 0 drivers +v0xbab2e2c60_24 .net/s v0xbab2e2c60 24, 39 0, L_0xbab340b40; 1 drivers +o0xbaa850670 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_25 .net/s v0xbab2e2c60 25, 39 0, o0xbaa850670; 0 drivers +o0xbaa8506a0 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_26 .net/s v0xbab2e2c60 26, 39 0, o0xbaa8506a0; 0 drivers +o0xbaa8506d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_27 .net/s v0xbab2e2c60 27, 39 0, o0xbaa8506d0; 0 drivers +o0xbaa850700 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_28 .net/s v0xbab2e2c60 28, 39 0, o0xbaa850700; 0 drivers +o0xbaa850730 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_29 .net/s v0xbab2e2c60 29, 39 0, o0xbaa850730; 0 drivers +o0xbaa850760 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_30 .net/s v0xbab2e2c60 30, 39 0, o0xbaa850760; 0 drivers +o0xbaa850790 .functor BUFZ 40, c4; HiZ drive +v0xbab2e2c60_31 .net/s v0xbab2e2c60 31, 39 0, o0xbaa850790; 0 drivers +v0xbab2e2d00_0 .net/s "w_bus", 127 0, L_0xbab333160; alias, 1 drivers +v0xbab2e2da0_0 .net/s "x_bus", 127 0, L_0xbab3330c0; alias, 1 drivers +L_0xbab3332a0 .part L_0xbab3330c0, 0, 16; +L_0xbab333340 .part L_0xbab333160, 0, 16; +L_0xbab333480 .part L_0xbab3330c0, 16, 16; +L_0xbab333520 .part L_0xbab333160, 16, 16; +L_0xbab333660 .part L_0xbab3330c0, 32, 16; +L_0xbab333700 .part L_0xbab333160, 32, 16; +L_0xbab333840 .part L_0xbab3330c0, 48, 16; +L_0xbab3338e0 .part L_0xbab333160, 48, 16; +L_0xbab333a20 .part L_0xbab3330c0, 64, 16; +L_0xbab333ac0 .part L_0xbab333160, 64, 16; +L_0xbab333c00 .part L_0xbab3330c0, 80, 16; +L_0xbab333ca0 .part L_0xbab333160, 80, 16; +L_0xbab333de0 .part L_0xbab3330c0, 96, 16; +L_0xbab333e80 .part L_0xbab333160, 96, 16; +L_0xbab344000 .part L_0xbab3330c0, 112, 16; +L_0xbab3440a0 .part L_0xbab333160, 112, 16; +L_0xbab340be0 .arith/sum 40, v0xbab2e3700_0, L_0xbab340b40; +S_0xbab2dd080 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad2bf80 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2dd200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2dd080; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4dbc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4dc00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4dc40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2db840_0 .net/s *"_ivl_0", 31 0, L_0xbab33b340; 1 drivers +v0xbab2db8e0_0 .net/s *"_ivl_2", 31 0, L_0xbab33b3e0; 1 drivers +v0xbab2db980_0 .net *"_ivl_7", 0 0, L_0xbab333200; 1 drivers +v0xbab2dba20_0 .net *"_ivl_9", 7 0, L_0xbaad57200; 1 drivers +L_0xbaa879570 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2dbac0_0 .net/s "acc_in", 39 0, L_0xbaa879570; 1 drivers +v0xbab2dbb60_0 .net/s "acc_out", 39 0, L_0xbab33b520; alias, 1 drivers +v0xbab2dbc00_0 .net/s "product", 31 0, L_0xbaad57160; 1 drivers +v0xbab2dbca0_0 .net/s "product_ext", 39 0, L_0xbab33b480; 1 drivers +v0xbab2dbd40_0 .net/s "w", 15 0, L_0xbab333340; 1 drivers +v0xbab2dbde0_0 .net/s "x", 15 0, L_0xbab3332a0; 1 drivers +L_0xbab33b340 .extend/s 32, L_0xbab3332a0; +L_0xbab33b3e0 .extend/s 32, L_0xbab333340; +L_0xbaad57160 .arith/mult 32, L_0xbab33b340, L_0xbab33b3e0; +L_0xbab333200 .part L_0xbaad57160, 31, 1; +L_0xbaad57200 .repeat 8, 8, L_0xbab333200; +L_0xbab33b480 .concat [ 32 8 0 0], L_0xbaad57160, L_0xbaad57200; +L_0xbab33b520 .arith/sum 40, L_0xbaa879570, L_0xbab33b480; +S_0xbab2dd380 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad2bfc0 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2dd500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2dd380; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4dc80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4dcc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4dd00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2dbe80_0 .net/s *"_ivl_0", 31 0, L_0xbab33b5c0; 1 drivers +v0xbab2dbf20_0 .net/s *"_ivl_2", 31 0, L_0xbab33b660; 1 drivers +v0xbab2e0000_0 .net *"_ivl_7", 0 0, L_0xbab3333e0; 1 drivers +v0xbab2e00a0_0 .net *"_ivl_9", 7 0, L_0xbaad57340; 1 drivers +L_0xbaa8795b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e0140_0 .net/s "acc_in", 39 0, L_0xbaa8795b8; 1 drivers +v0xbab2e01e0_0 .net/s "acc_out", 39 0, L_0xbab33b7a0; alias, 1 drivers +v0xbab2e0280_0 .net/s "product", 31 0, L_0xbaad572a0; 1 drivers +v0xbab2e0320_0 .net/s "product_ext", 39 0, L_0xbab33b700; 1 drivers +v0xbab2e03c0_0 .net/s "w", 15 0, L_0xbab333520; 1 drivers +v0xbab2e0460_0 .net/s "x", 15 0, L_0xbab333480; 1 drivers +L_0xbab33b5c0 .extend/s 32, L_0xbab333480; +L_0xbab33b660 .extend/s 32, L_0xbab333520; +L_0xbaad572a0 .arith/mult 32, L_0xbab33b5c0, L_0xbab33b660; +L_0xbab3333e0 .part L_0xbaad572a0, 31, 1; +L_0xbaad57340 .repeat 8, 8, L_0xbab3333e0; +L_0xbab33b700 .concat [ 32 8 0 0], L_0xbaad572a0, L_0xbaad57340; +L_0xbab33b7a0 .arith/sum 40, L_0xbaa8795b8, L_0xbab33b700; +S_0xbab2dd680 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50000 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2dd800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2dd680; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4dd40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4dd80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ddc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e0500_0 .net/s *"_ivl_0", 31 0, L_0xbab33b840; 1 drivers +v0xbab2e05a0_0 .net/s *"_ivl_2", 31 0, L_0xbab33b8e0; 1 drivers +v0xbab2e0640_0 .net *"_ivl_7", 0 0, L_0xbab3335c0; 1 drivers +v0xbab2e06e0_0 .net *"_ivl_9", 7 0, L_0xbaad57480; 1 drivers +L_0xbaa879600 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e0780_0 .net/s "acc_in", 39 0, L_0xbaa879600; 1 drivers +v0xbab2e0820_0 .net/s "acc_out", 39 0, L_0xbab33ba20; alias, 1 drivers +v0xbab2e08c0_0 .net/s "product", 31 0, L_0xbaad573e0; 1 drivers +v0xbab2e0960_0 .net/s "product_ext", 39 0, L_0xbab33b980; 1 drivers +v0xbab2e0a00_0 .net/s "w", 15 0, L_0xbab333700; 1 drivers +v0xbab2e0aa0_0 .net/s "x", 15 0, L_0xbab333660; 1 drivers +L_0xbab33b840 .extend/s 32, L_0xbab333660; +L_0xbab33b8e0 .extend/s 32, L_0xbab333700; +L_0xbaad573e0 .arith/mult 32, L_0xbab33b840, L_0xbab33b8e0; +L_0xbab3335c0 .part L_0xbaad573e0, 31, 1; +L_0xbaad57480 .repeat 8, 8, L_0xbab3335c0; +L_0xbab33b980 .concat [ 32 8 0 0], L_0xbaad573e0, L_0xbaad57480; +L_0xbab33ba20 .arith/sum 40, L_0xbaa879600, L_0xbab33b980; +S_0xbab2dd980 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50040 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2ddb00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2dd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4de00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4de40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4de80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e0b40_0 .net/s *"_ivl_0", 31 0, L_0xbab33bac0; 1 drivers +v0xbab2e0be0_0 .net/s *"_ivl_2", 31 0, L_0xbab33bb60; 1 drivers +v0xbab2e0c80_0 .net *"_ivl_7", 0 0, L_0xbab3337a0; 1 drivers +v0xbab2e0d20_0 .net *"_ivl_9", 7 0, L_0xbaad575c0; 1 drivers +L_0xbaa879648 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e0dc0_0 .net/s "acc_in", 39 0, L_0xbaa879648; 1 drivers +v0xbab2e0e60_0 .net/s "acc_out", 39 0, L_0xbab33bca0; alias, 1 drivers +v0xbab2e0f00_0 .net/s "product", 31 0, L_0xbaad57520; 1 drivers +v0xbab2e0fa0_0 .net/s "product_ext", 39 0, L_0xbab33bc00; 1 drivers +v0xbab2e1040_0 .net/s "w", 15 0, L_0xbab3338e0; 1 drivers +v0xbab2e10e0_0 .net/s "x", 15 0, L_0xbab333840; 1 drivers +L_0xbab33bac0 .extend/s 32, L_0xbab333840; +L_0xbab33bb60 .extend/s 32, L_0xbab3338e0; +L_0xbaad57520 .arith/mult 32, L_0xbab33bac0, L_0xbab33bb60; +L_0xbab3337a0 .part L_0xbaad57520, 31, 1; +L_0xbaad575c0 .repeat 8, 8, L_0xbab3337a0; +L_0xbab33bc00 .concat [ 32 8 0 0], L_0xbaad57520, L_0xbaad575c0; +L_0xbab33bca0 .arith/sum 40, L_0xbaa879648, L_0xbab33bc00; +S_0xbab2ddc80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad500c0 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2dde00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2ddc80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4dec0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4df00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4df40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e1180_0 .net/s *"_ivl_0", 31 0, L_0xbab33bd40; 1 drivers +v0xbab2e1220_0 .net/s *"_ivl_2", 31 0, L_0xbab33bde0; 1 drivers +v0xbab2e12c0_0 .net *"_ivl_7", 0 0, L_0xbab333980; 1 drivers +v0xbab2e1360_0 .net *"_ivl_9", 7 0, L_0xbaad57700; 1 drivers +L_0xbaa879690 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e1400_0 .net/s "acc_in", 39 0, L_0xbaa879690; 1 drivers +v0xbab2e14a0_0 .net/s "acc_out", 39 0, L_0xbab33bf20; alias, 1 drivers +v0xbab2e1540_0 .net/s "product", 31 0, L_0xbaad57660; 1 drivers +v0xbab2e15e0_0 .net/s "product_ext", 39 0, L_0xbab33be80; 1 drivers +v0xbab2e1680_0 .net/s "w", 15 0, L_0xbab333ac0; 1 drivers +v0xbab2e1720_0 .net/s "x", 15 0, L_0xbab333a20; 1 drivers +L_0xbab33bd40 .extend/s 32, L_0xbab333a20; +L_0xbab33bde0 .extend/s 32, L_0xbab333ac0; +L_0xbaad57660 .arith/mult 32, L_0xbab33bd40, L_0xbab33bde0; +L_0xbab333980 .part L_0xbaad57660, 31, 1; +L_0xbaad57700 .repeat 8, 8, L_0xbab333980; +L_0xbab33be80 .concat [ 32 8 0 0], L_0xbaad57660, L_0xbaad57700; +L_0xbab33bf20 .arith/sum 40, L_0xbaa879690, L_0xbab33be80; +S_0xbab2ddf80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50100 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2de100 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2ddf80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4df80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4dfc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e000 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e17c0_0 .net/s *"_ivl_0", 31 0, L_0xbab340000; 1 drivers +v0xbab2e1860_0 .net/s *"_ivl_2", 31 0, L_0xbab3400a0; 1 drivers +v0xbab2e1900_0 .net *"_ivl_7", 0 0, L_0xbab333b60; 1 drivers +v0xbab2e19a0_0 .net *"_ivl_9", 7 0, L_0xbaad57840; 1 drivers +L_0xbaa8796d8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e1a40_0 .net/s "acc_in", 39 0, L_0xbaa8796d8; 1 drivers +v0xbab2e1ae0_0 .net/s "acc_out", 39 0, L_0xbab3401e0; alias, 1 drivers +v0xbab2e1b80_0 .net/s "product", 31 0, L_0xbaad577a0; 1 drivers +v0xbab2e1c20_0 .net/s "product_ext", 39 0, L_0xbab340140; 1 drivers +v0xbab2e1cc0_0 .net/s "w", 15 0, L_0xbab333ca0; 1 drivers +v0xbab2e1d60_0 .net/s "x", 15 0, L_0xbab333c00; 1 drivers +L_0xbab340000 .extend/s 32, L_0xbab333c00; +L_0xbab3400a0 .extend/s 32, L_0xbab333ca0; +L_0xbaad577a0 .arith/mult 32, L_0xbab340000, L_0xbab3400a0; +L_0xbab333b60 .part L_0xbaad577a0, 31, 1; +L_0xbaad57840 .repeat 8, 8, L_0xbab333b60; +L_0xbab340140 .concat [ 32 8 0 0], L_0xbaad577a0, L_0xbaad57840; +L_0xbab3401e0 .arith/sum 40, L_0xbaa8796d8, L_0xbab340140; +S_0xbab2de280 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50140 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2de400 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2de280; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e040 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e080 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e0c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e1e00_0 .net/s *"_ivl_0", 31 0, L_0xbab340280; 1 drivers +v0xbab2e1ea0_0 .net/s *"_ivl_2", 31 0, L_0xbab340320; 1 drivers +v0xbab2e1f40_0 .net *"_ivl_7", 0 0, L_0xbab333d40; 1 drivers +v0xbab2e1fe0_0 .net *"_ivl_9", 7 0, L_0xbaad57980; 1 drivers +L_0xbaa879720 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e2080_0 .net/s "acc_in", 39 0, L_0xbaa879720; 1 drivers +v0xbab2e2120_0 .net/s "acc_out", 39 0, L_0xbab340460; alias, 1 drivers +v0xbab2e21c0_0 .net/s "product", 31 0, L_0xbaad578e0; 1 drivers +v0xbab2e2260_0 .net/s "product_ext", 39 0, L_0xbab3403c0; 1 drivers +v0xbab2e2300_0 .net/s "w", 15 0, L_0xbab333e80; 1 drivers +v0xbab2e23a0_0 .net/s "x", 15 0, L_0xbab333de0; 1 drivers +L_0xbab340280 .extend/s 32, L_0xbab333de0; +L_0xbab340320 .extend/s 32, L_0xbab333e80; +L_0xbaad578e0 .arith/mult 32, L_0xbab340280, L_0xbab340320; +L_0xbab333d40 .part L_0xbaad578e0, 31, 1; +L_0xbaad57980 .repeat 8, 8, L_0xbab333d40; +L_0xbab3403c0 .concat [ 32 8 0 0], L_0xbaad578e0, L_0xbaad57980; +L_0xbab340460 .arith/sum 40, L_0xbaa879720, L_0xbab3403c0; +S_0xbab2de580 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50180 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2de700 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2de580; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e100 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e140 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e180 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e2440_0 .net/s *"_ivl_0", 31 0, L_0xbab340500; 1 drivers +v0xbab2e24e0_0 .net/s *"_ivl_2", 31 0, L_0xbab3405a0; 1 drivers +v0xbab2e2580_0 .net *"_ivl_7", 0 0, L_0xbab333f20; 1 drivers +v0xbab2e2620_0 .net *"_ivl_9", 7 0, L_0xbaad57ac0; 1 drivers +L_0xbaa879768 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e26c0_0 .net/s "acc_in", 39 0, L_0xbaa879768; 1 drivers +v0xbab2e2760_0 .net/s "acc_out", 39 0, L_0xbab3406e0; alias, 1 drivers +v0xbab2e2800_0 .net/s "product", 31 0, L_0xbaad57a20; 1 drivers +v0xbab2e28a0_0 .net/s "product_ext", 39 0, L_0xbab340640; 1 drivers +v0xbab2e2940_0 .net/s "w", 15 0, L_0xbab3440a0; 1 drivers +v0xbab2e29e0_0 .net/s "x", 15 0, L_0xbab344000; 1 drivers +L_0xbab340500 .extend/s 32, L_0xbab344000; +L_0xbab3405a0 .extend/s 32, L_0xbab3440a0; +L_0xbaad57a20 .arith/mult 32, L_0xbab340500, L_0xbab3405a0; +L_0xbab333f20 .part L_0xbaad57a20, 31, 1; +L_0xbaad57ac0 .repeat 8, 8, L_0xbab333f20; +L_0xbab340640 .concat [ 32 8 0 0], L_0xbaad57a20, L_0xbaad57ac0; +L_0xbab3406e0 .arith/sum 40, L_0xbaa879768, L_0xbab340640; +S_0xbab2de880 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50080 .param/l "i" 1 5 80, +C4<00>; +L_0xbab069500 .functor BUFZ 40, L_0xbab33b520, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2dea00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad501c0 .param/l "i" 1 5 80, +C4<01>; +L_0xbab069570 .functor BUFZ 40, L_0xbab33b7a0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2deb80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50200 .param/l "i" 1 5 80, +C4<010>; +L_0xbab0695e0 .functor BUFZ 40, L_0xbab33ba20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2ded00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50240 .param/l "i" 1 5 80, +C4<011>; +L_0xbab069650 .functor BUFZ 40, L_0xbab33bca0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2dee80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50280 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab0696c0 .functor BUFZ 40, L_0xbab33bf20, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2df000 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad502c0 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab069730 .functor BUFZ 40, L_0xbab3401e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2df180 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50300 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab0697a0 .functor BUFZ 40, L_0xbab340460, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2df300 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50340 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab069810 .functor BUFZ 40, L_0xbab3406e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2df480 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50380 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2df600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2df480; + .timescale 0 0; +P_0xbaad503c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab340780 .arith/sum 40, L_0xbab069500, L_0xbab069570; +S_0xbab2df780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2df480; + .timescale 0 0; +P_0xbaad50400 .param/l "node" 1 5 94, +C4<01>; +L_0xbab340820 .arith/sum 40, L_0xbab0695e0, L_0xbab069650; +S_0xbab2df900 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2df480; + .timescale 0 0; +P_0xbaad50440 .param/l "node" 1 5 94, +C4<010>; +L_0xbab3408c0 .arith/sum 40, L_0xbab0696c0, L_0xbab069730; +S_0xbab2dfa80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2df480; + .timescale 0 0; +P_0xbaad50480 .param/l "node" 1 5 94, +C4<011>; +L_0xbab340960 .arith/sum 40, L_0xbab0697a0, L_0xbab069810; +S_0xbab2dfc00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad504c0 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2dfd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2dfc00; + .timescale 0 0; +P_0xbaad50500 .param/l "node" 1 5 94, +C4<00>; +L_0xbab340a00 .arith/sum 40, L_0xbab340780, L_0xbab340820; +S_0xbab2e4000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2dfc00; + .timescale 0 0; +P_0xbaad50540 .param/l "node" 1 5 94, +C4<01>; +L_0xbab340aa0 .arith/sum 40, L_0xbab3408c0, L_0xbab340960; +S_0xbab2e4180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2dcf00; + .timescale 0 0; +P_0xbaad50580 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2e4300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2e4180; + .timescale 0 0; +P_0xbaad505c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab340b40 .arith/sum 40, L_0xbab340a00, L_0xbab340aa0; +S_0xbab2e4480 .scope generate, "GEN_NEURON[6]" "GEN_NEURON[6]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad50640 .param/l "n" 1 3 34, +C4<0110>; +S_0xbab2e4600 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2e4480; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc600 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc640 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc680 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc6c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc700 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc740 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab2eb700_0 .net *"_ivl_0", 31 0, L_0xbab340dc0; 1 drivers +v0xbab2eb7a0_0 .net *"_ivl_11", 31 0, L_0xbaad57d40; 1 drivers +v0xbab2eb840_0 .net *"_ivl_14", 31 0, L_0xbab340e60; 1 drivers +L_0xbaa879888 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2eb8e0_0 .net *"_ivl_17", 28 0, L_0xbaa879888; 1 drivers +L_0xbaa8798d0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2eb980_0 .net/2u *"_ivl_18", 31 0, L_0xbaa8798d0; 1 drivers +v0xbab2eba20_0 .net *"_ivl_21", 31 0, L_0xbaad57de0; 1 drivers +L_0xbaa879918 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2ebac0_0 .net/2u *"_ivl_22", 31 0, L_0xbaa879918; 1 drivers +v0xbab2ebb60_0 .net *"_ivl_25", 31 0, L_0xbaad57e80; 1 drivers +v0xbab2ebc00_0 .net *"_ivl_29", 0 0, L_0xbab345360; 1 drivers +L_0xbaa8797b0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ebca0_0 .net *"_ivl_3", 28 0, L_0xbaa8797b0; 1 drivers +v0xbab2ebd40_0 .net *"_ivl_31", 23 0, L_0xbaad58a00; 1 drivers +L_0xbaa8797f8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab2ebde0_0 .net/2u *"_ivl_4", 31 0, L_0xbaa8797f8; 1 drivers +v0xbab2ebe80_0 .net *"_ivl_7", 31 0, L_0xbaad57ca0; 1 drivers +L_0xbaa879840 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab2ebf20_0 .net/2u *"_ivl_8", 31 0, L_0xbaa879840; 1 drivers +v0xbab2f8000_0 .var/s "acc", 39 0; +v0xbab2f80a0_0 .net/s "acc_next", 39 0, L_0xbab342760; 1 drivers +v0xbab2f8140_0 .net/s "bias", 15 0, L_0xbab3454a0; 1 drivers +v0xbab2f81e0_0 .net/s "bias_ext", 39 0, L_0xbab342800; 1 drivers +v0xbab2f8280_0 .var "busy", 0 0; +v0xbab2f8320_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab2f83c0_0 .var "done", 0 0; +v0xbab2f8460_0 .net/s "final_acc", 39 0, L_0xbab3428a0; 1 drivers +v0xbab2f8500_0 .var "group_index", 2 0; +v0xbab2f85a0_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab2f8640_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab2f86e0_0 .net/s "w_bus", 1023 0, L_0xbab345400; 1 drivers +v0xbab2f8780_0 .net/s "w_group", 127 0, L_0xbab3443c0; 1 drivers +v0xbab2f8820_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab2f88c0_0 .net/s "x_group", 127 0, L_0xbab344320; 1 drivers +v0xbab2f8960_0 .var/s "y", 15 0; +L_0xbab340dc0 .concat [ 3 29 0 0], v0xbab2f8500_0, L_0xbaa8797b0; +L_0xbaad57ca0 .arith/mult 32, L_0xbab340dc0, L_0xbaa8797f8; +L_0xbaad57d40 .arith/mult 32, L_0xbaad57ca0, L_0xbaa879840; +L_0xbab344320 .part/v o0xbaa846110, L_0xbaad57d40, 128; +L_0xbab340e60 .concat [ 3 29 0 0], v0xbab2f8500_0, L_0xbaa879888; +L_0xbaad57de0 .arith/mult 32, L_0xbab340e60, L_0xbaa8798d0; +L_0xbaad57e80 .arith/mult 32, L_0xbaad57de0, L_0xbaa879918; +L_0xbab3443c0 .part/v L_0xbab345400, L_0xbaad57e80, 128; +L_0xbab345360 .part L_0xbab3454a0, 15, 1; +L_0xbaad58a00 .repeat 24, 24, L_0xbab345360; +L_0xbab342800 .concat [ 16 24 0 0], L_0xbab3454a0, L_0xbaad58a00; +L_0xbab3428a0 .arith/sum 40, L_0xbab342760, L_0xbab342800; +S_0xbab2e4780 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2e4600; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab295300 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab295340 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab295380 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2953c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2eb340_0 .net/s "acc_in", 39 0, v0xbab2f8000_0; 1 drivers +v0xbab2eb3e0_0 .net/s "acc_out", 39 0, L_0xbab342760; alias, 1 drivers +v0xbab2eb480 .array "products", 7 0; +v0xbab2eb480_0 .net/s v0xbab2eb480 0, 39 0, L_0xbab3410e0; 1 drivers +v0xbab2eb480_1 .net/s v0xbab2eb480 1, 39 0, L_0xbab341360; 1 drivers +v0xbab2eb480_2 .net/s v0xbab2eb480 2, 39 0, L_0xbab3415e0; 1 drivers +v0xbab2eb480_3 .net/s v0xbab2eb480 3, 39 0, L_0xbab341860; 1 drivers +v0xbab2eb480_4 .net/s v0xbab2eb480 4, 39 0, L_0xbab341ae0; 1 drivers +v0xbab2eb480_5 .net/s v0xbab2eb480 5, 39 0, L_0xbab341d60; 1 drivers +v0xbab2eb480_6 .net/s v0xbab2eb480 6, 39 0, L_0xbab341fe0; 1 drivers +v0xbab2eb480_7 .net/s v0xbab2eb480 7, 39 0, L_0xbab342260; 1 drivers +v0xbab2eb520 .array "tree", 31 0; +v0xbab2eb520_0 .net/s v0xbab2eb520 0, 39 0, L_0xbab069880; 1 drivers +v0xbab2eb520_1 .net/s v0xbab2eb520 1, 39 0, L_0xbab0698f0; 1 drivers +v0xbab2eb520_2 .net/s v0xbab2eb520 2, 39 0, L_0xbab069960; 1 drivers +v0xbab2eb520_3 .net/s v0xbab2eb520 3, 39 0, L_0xbab0699d0; 1 drivers +v0xbab2eb520_4 .net/s v0xbab2eb520 4, 39 0, L_0xbab069a40; 1 drivers +v0xbab2eb520_5 .net/s v0xbab2eb520 5, 39 0, L_0xbab069ab0; 1 drivers +v0xbab2eb520_6 .net/s v0xbab2eb520 6, 39 0, L_0xbab069b20; 1 drivers +v0xbab2eb520_7 .net/s v0xbab2eb520 7, 39 0, L_0xbab069b90; 1 drivers +v0xbab2eb520_8 .net/s v0xbab2eb520 8, 39 0, L_0xbab342300; 1 drivers +v0xbab2eb520_9 .net/s v0xbab2eb520 9, 39 0, L_0xbab3423a0; 1 drivers +v0xbab2eb520_10 .net/s v0xbab2eb520 10, 39 0, L_0xbab342440; 1 drivers +v0xbab2eb520_11 .net/s v0xbab2eb520 11, 39 0, L_0xbab3424e0; 1 drivers +o0xbaa852650 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_12 .net/s v0xbab2eb520 12, 39 0, o0xbaa852650; 0 drivers +o0xbaa852680 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_13 .net/s v0xbab2eb520 13, 39 0, o0xbaa852680; 0 drivers +o0xbaa8526b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_14 .net/s v0xbab2eb520 14, 39 0, o0xbaa8526b0; 0 drivers +o0xbaa8526e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_15 .net/s v0xbab2eb520 15, 39 0, o0xbaa8526e0; 0 drivers +v0xbab2eb520_16 .net/s v0xbab2eb520 16, 39 0, L_0xbab342580; 1 drivers +v0xbab2eb520_17 .net/s v0xbab2eb520 17, 39 0, L_0xbab342620; 1 drivers +o0xbaa852770 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_18 .net/s v0xbab2eb520 18, 39 0, o0xbaa852770; 0 drivers +o0xbaa8527a0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_19 .net/s v0xbab2eb520 19, 39 0, o0xbaa8527a0; 0 drivers +o0xbaa8527d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_20 .net/s v0xbab2eb520 20, 39 0, o0xbaa8527d0; 0 drivers +o0xbaa852800 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_21 .net/s v0xbab2eb520 21, 39 0, o0xbaa852800; 0 drivers +o0xbaa852830 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_22 .net/s v0xbab2eb520 22, 39 0, o0xbaa852830; 0 drivers +o0xbaa852860 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_23 .net/s v0xbab2eb520 23, 39 0, o0xbaa852860; 0 drivers +v0xbab2eb520_24 .net/s v0xbab2eb520 24, 39 0, L_0xbab3426c0; 1 drivers +o0xbaa8528c0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_25 .net/s v0xbab2eb520 25, 39 0, o0xbaa8528c0; 0 drivers +o0xbaa8528f0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_26 .net/s v0xbab2eb520 26, 39 0, o0xbaa8528f0; 0 drivers +o0xbaa852920 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_27 .net/s v0xbab2eb520 27, 39 0, o0xbaa852920; 0 drivers +o0xbaa852950 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_28 .net/s v0xbab2eb520 28, 39 0, o0xbaa852950; 0 drivers +o0xbaa852980 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_29 .net/s v0xbab2eb520 29, 39 0, o0xbaa852980; 0 drivers +o0xbaa8529b0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_30 .net/s v0xbab2eb520 30, 39 0, o0xbaa8529b0; 0 drivers +o0xbaa8529e0 .functor BUFZ 40, c4; HiZ drive +v0xbab2eb520_31 .net/s v0xbab2eb520 31, 39 0, o0xbaa8529e0; 0 drivers +v0xbab2eb5c0_0 .net/s "w_bus", 127 0, L_0xbab3443c0; alias, 1 drivers +v0xbab2eb660_0 .net/s "x_bus", 127 0, L_0xbab344320; alias, 1 drivers +L_0xbab344500 .part L_0xbab344320, 0, 16; +L_0xbab3445a0 .part L_0xbab3443c0, 0, 16; +L_0xbab3446e0 .part L_0xbab344320, 16, 16; +L_0xbab344780 .part L_0xbab3443c0, 16, 16; +L_0xbab3448c0 .part L_0xbab344320, 32, 16; +L_0xbab344960 .part L_0xbab3443c0, 32, 16; +L_0xbab344aa0 .part L_0xbab344320, 48, 16; +L_0xbab344b40 .part L_0xbab3443c0, 48, 16; +L_0xbab344c80 .part L_0xbab344320, 64, 16; +L_0xbab344d20 .part L_0xbab3443c0, 64, 16; +L_0xbab344e60 .part L_0xbab344320, 80, 16; +L_0xbab344f00 .part L_0xbab3443c0, 80, 16; +L_0xbab345040 .part L_0xbab344320, 96, 16; +L_0xbab3450e0 .part L_0xbab3443c0, 96, 16; +L_0xbab345220 .part L_0xbab344320, 112, 16; +L_0xbab3452c0 .part L_0xbab3443c0, 112, 16; +L_0xbab342760 .arith/sum 40, v0xbab2f8000_0, L_0xbab3426c0; +S_0xbab2e4900 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50680 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2e4a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e4900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e1c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e200 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e240 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e8140_0 .net/s *"_ivl_0", 31 0, L_0xbab340f00; 1 drivers +v0xbab2e81e0_0 .net/s *"_ivl_2", 31 0, L_0xbab340fa0; 1 drivers +v0xbab2e8280_0 .net *"_ivl_7", 0 0, L_0xbab344460; 1 drivers +v0xbab2e8320_0 .net *"_ivl_9", 7 0, L_0xbaad58000; 1 drivers +L_0xbaa879960 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e83c0_0 .net/s "acc_in", 39 0, L_0xbaa879960; 1 drivers +v0xbab2e8460_0 .net/s "acc_out", 39 0, L_0xbab3410e0; alias, 1 drivers +v0xbab2e8500_0 .net/s "product", 31 0, L_0xbaad57f20; 1 drivers +v0xbab2e85a0_0 .net/s "product_ext", 39 0, L_0xbab341040; 1 drivers +v0xbab2e8640_0 .net/s "w", 15 0, L_0xbab3445a0; 1 drivers +v0xbab2e86e0_0 .net/s "x", 15 0, L_0xbab344500; 1 drivers +L_0xbab340f00 .extend/s 32, L_0xbab344500; +L_0xbab340fa0 .extend/s 32, L_0xbab3445a0; +L_0xbaad57f20 .arith/mult 32, L_0xbab340f00, L_0xbab340fa0; +L_0xbab344460 .part L_0xbaad57f20, 31, 1; +L_0xbaad58000 .repeat 8, 8, L_0xbab344460; +L_0xbab341040 .concat [ 32 8 0 0], L_0xbaad57f20, L_0xbaad58000; +L_0xbab3410e0 .arith/sum 40, L_0xbaa879960, L_0xbab341040; +S_0xbab2e4c00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad506c0 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2e4d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e4c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e280 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e2c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e300 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e8780_0 .net/s *"_ivl_0", 31 0, L_0xbab341180; 1 drivers +v0xbab2e8820_0 .net/s *"_ivl_2", 31 0, L_0xbab341220; 1 drivers +v0xbab2e88c0_0 .net *"_ivl_7", 0 0, L_0xbab344640; 1 drivers +v0xbab2e8960_0 .net *"_ivl_9", 7 0, L_0xbaad58140; 1 drivers +L_0xbaa8799a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e8a00_0 .net/s "acc_in", 39 0, L_0xbaa8799a8; 1 drivers +v0xbab2e8aa0_0 .net/s "acc_out", 39 0, L_0xbab341360; alias, 1 drivers +v0xbab2e8b40_0 .net/s "product", 31 0, L_0xbaad580a0; 1 drivers +v0xbab2e8be0_0 .net/s "product_ext", 39 0, L_0xbab3412c0; 1 drivers +v0xbab2e8c80_0 .net/s "w", 15 0, L_0xbab344780; 1 drivers +v0xbab2e8d20_0 .net/s "x", 15 0, L_0xbab3446e0; 1 drivers +L_0xbab341180 .extend/s 32, L_0xbab3446e0; +L_0xbab341220 .extend/s 32, L_0xbab344780; +L_0xbaad580a0 .arith/mult 32, L_0xbab341180, L_0xbab341220; +L_0xbab344640 .part L_0xbaad580a0, 31, 1; +L_0xbaad58140 .repeat 8, 8, L_0xbab344640; +L_0xbab3412c0 .concat [ 32 8 0 0], L_0xbaad580a0, L_0xbaad58140; +L_0xbab341360 .arith/sum 40, L_0xbaa8799a8, L_0xbab3412c0; +S_0xbab2e4f00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50700 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2e5080 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e4f00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e340 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e380 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e3c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e8dc0_0 .net/s *"_ivl_0", 31 0, L_0xbab341400; 1 drivers +v0xbab2e8e60_0 .net/s *"_ivl_2", 31 0, L_0xbab3414a0; 1 drivers +v0xbab2e8f00_0 .net *"_ivl_7", 0 0, L_0xbab344820; 1 drivers +v0xbab2e8fa0_0 .net *"_ivl_9", 7 0, L_0xbaad58280; 1 drivers +L_0xbaa8799f0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e9040_0 .net/s "acc_in", 39 0, L_0xbaa8799f0; 1 drivers +v0xbab2e90e0_0 .net/s "acc_out", 39 0, L_0xbab3415e0; alias, 1 drivers +v0xbab2e9180_0 .net/s "product", 31 0, L_0xbaad581e0; 1 drivers +v0xbab2e9220_0 .net/s "product_ext", 39 0, L_0xbab341540; 1 drivers +v0xbab2e92c0_0 .net/s "w", 15 0, L_0xbab344960; 1 drivers +v0xbab2e9360_0 .net/s "x", 15 0, L_0xbab3448c0; 1 drivers +L_0xbab341400 .extend/s 32, L_0xbab3448c0; +L_0xbab3414a0 .extend/s 32, L_0xbab344960; +L_0xbaad581e0 .arith/mult 32, L_0xbab341400, L_0xbab3414a0; +L_0xbab344820 .part L_0xbaad581e0, 31, 1; +L_0xbaad58280 .repeat 8, 8, L_0xbab344820; +L_0xbab341540 .concat [ 32 8 0 0], L_0xbaad581e0, L_0xbaad58280; +L_0xbab3415e0 .arith/sum 40, L_0xbaa8799f0, L_0xbab341540; +S_0xbab2e5200 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50740 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2e5380 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e5200; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e400 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e440 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e480 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e9400_0 .net/s *"_ivl_0", 31 0, L_0xbab341680; 1 drivers +v0xbab2e94a0_0 .net/s *"_ivl_2", 31 0, L_0xbab341720; 1 drivers +v0xbab2e9540_0 .net *"_ivl_7", 0 0, L_0xbab344a00; 1 drivers +v0xbab2e95e0_0 .net *"_ivl_9", 7 0, L_0xbaad583c0; 1 drivers +L_0xbaa879a38 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e9680_0 .net/s "acc_in", 39 0, L_0xbaa879a38; 1 drivers +v0xbab2e9720_0 .net/s "acc_out", 39 0, L_0xbab341860; alias, 1 drivers +v0xbab2e97c0_0 .net/s "product", 31 0, L_0xbaad58320; 1 drivers +v0xbab2e9860_0 .net/s "product_ext", 39 0, L_0xbab3417c0; 1 drivers +v0xbab2e9900_0 .net/s "w", 15 0, L_0xbab344b40; 1 drivers +v0xbab2e99a0_0 .net/s "x", 15 0, L_0xbab344aa0; 1 drivers +L_0xbab341680 .extend/s 32, L_0xbab344aa0; +L_0xbab341720 .extend/s 32, L_0xbab344b40; +L_0xbaad58320 .arith/mult 32, L_0xbab341680, L_0xbab341720; +L_0xbab344a00 .part L_0xbaad58320, 31, 1; +L_0xbaad583c0 .repeat 8, 8, L_0xbab344a00; +L_0xbab3417c0 .concat [ 32 8 0 0], L_0xbaad58320, L_0xbaad583c0; +L_0xbab341860 .arith/sum 40, L_0xbaa879a38, L_0xbab3417c0; +S_0xbab2e5500 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad507c0 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2e5680 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e5500; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e4c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e500 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e540 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2e9a40_0 .net/s *"_ivl_0", 31 0, L_0xbab341900; 1 drivers +v0xbab2e9ae0_0 .net/s *"_ivl_2", 31 0, L_0xbab3419a0; 1 drivers +v0xbab2e9b80_0 .net *"_ivl_7", 0 0, L_0xbab344be0; 1 drivers +v0xbab2e9c20_0 .net *"_ivl_9", 7 0, L_0xbaad58500; 1 drivers +L_0xbaa879a80 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2e9cc0_0 .net/s "acc_in", 39 0, L_0xbaa879a80; 1 drivers +v0xbab2e9d60_0 .net/s "acc_out", 39 0, L_0xbab341ae0; alias, 1 drivers +v0xbab2e9e00_0 .net/s "product", 31 0, L_0xbaad58460; 1 drivers +v0xbab2e9ea0_0 .net/s "product_ext", 39 0, L_0xbab341a40; 1 drivers +v0xbab2e9f40_0 .net/s "w", 15 0, L_0xbab344d20; 1 drivers +v0xbab2e9fe0_0 .net/s "x", 15 0, L_0xbab344c80; 1 drivers +L_0xbab341900 .extend/s 32, L_0xbab344c80; +L_0xbab3419a0 .extend/s 32, L_0xbab344d20; +L_0xbaad58460 .arith/mult 32, L_0xbab341900, L_0xbab3419a0; +L_0xbab344be0 .part L_0xbaad58460, 31, 1; +L_0xbaad58500 .repeat 8, 8, L_0xbab344be0; +L_0xbab341a40 .concat [ 32 8 0 0], L_0xbaad58460, L_0xbaad58500; +L_0xbab341ae0 .arith/sum 40, L_0xbaa879a80, L_0xbab341a40; +S_0xbab2e5800 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50800 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2e5980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e5800; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e580 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e5c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e600 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2ea080_0 .net/s *"_ivl_0", 31 0, L_0xbab341b80; 1 drivers +v0xbab2ea120_0 .net/s *"_ivl_2", 31 0, L_0xbab341c20; 1 drivers +v0xbab2ea1c0_0 .net *"_ivl_7", 0 0, L_0xbab344dc0; 1 drivers +v0xbab2ea260_0 .net *"_ivl_9", 7 0, L_0xbaad58640; 1 drivers +L_0xbaa879ac8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ea300_0 .net/s "acc_in", 39 0, L_0xbaa879ac8; 1 drivers +v0xbab2ea3a0_0 .net/s "acc_out", 39 0, L_0xbab341d60; alias, 1 drivers +v0xbab2ea440_0 .net/s "product", 31 0, L_0xbaad585a0; 1 drivers +v0xbab2ea4e0_0 .net/s "product_ext", 39 0, L_0xbab341cc0; 1 drivers +v0xbab2ea580_0 .net/s "w", 15 0, L_0xbab344f00; 1 drivers +v0xbab2ea620_0 .net/s "x", 15 0, L_0xbab344e60; 1 drivers +L_0xbab341b80 .extend/s 32, L_0xbab344e60; +L_0xbab341c20 .extend/s 32, L_0xbab344f00; +L_0xbaad585a0 .arith/mult 32, L_0xbab341b80, L_0xbab341c20; +L_0xbab344dc0 .part L_0xbaad585a0, 31, 1; +L_0xbaad58640 .repeat 8, 8, L_0xbab344dc0; +L_0xbab341cc0 .concat [ 32 8 0 0], L_0xbaad585a0, L_0xbaad58640; +L_0xbab341d60 .arith/sum 40, L_0xbaa879ac8, L_0xbab341cc0; +S_0xbab2e5b00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50840 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2e5c80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e5b00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e640 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e680 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e6c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2ea6c0_0 .net/s *"_ivl_0", 31 0, L_0xbab341e00; 1 drivers +v0xbab2ea760_0 .net/s *"_ivl_2", 31 0, L_0xbab341ea0; 1 drivers +v0xbab2ea800_0 .net *"_ivl_7", 0 0, L_0xbab344fa0; 1 drivers +v0xbab2ea8a0_0 .net *"_ivl_9", 7 0, L_0xbaad58780; 1 drivers +L_0xbaa879b10 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2ea940_0 .net/s "acc_in", 39 0, L_0xbaa879b10; 1 drivers +v0xbab2ea9e0_0 .net/s "acc_out", 39 0, L_0xbab341fe0; alias, 1 drivers +v0xbab2eaa80_0 .net/s "product", 31 0, L_0xbaad586e0; 1 drivers +v0xbab2eab20_0 .net/s "product_ext", 39 0, L_0xbab341f40; 1 drivers +v0xbab2eabc0_0 .net/s "w", 15 0, L_0xbab3450e0; 1 drivers +v0xbab2eac60_0 .net/s "x", 15 0, L_0xbab345040; 1 drivers +L_0xbab341e00 .extend/s 32, L_0xbab345040; +L_0xbab341ea0 .extend/s 32, L_0xbab3450e0; +L_0xbaad586e0 .arith/mult 32, L_0xbab341e00, L_0xbab341ea0; +L_0xbab344fa0 .part L_0xbaad586e0, 31, 1; +L_0xbaad58780 .repeat 8, 8, L_0xbab344fa0; +L_0xbab341f40 .concat [ 32 8 0 0], L_0xbaad586e0, L_0xbaad58780; +L_0xbab341fe0 .arith/sum 40, L_0xbaa879b10, L_0xbab341f40; +S_0xbab2e5e00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50880 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2e5f80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2e5e00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e700 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e740 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e780 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2ead00_0 .net/s *"_ivl_0", 31 0, L_0xbab342080; 1 drivers +v0xbab2eada0_0 .net/s *"_ivl_2", 31 0, L_0xbab342120; 1 drivers +v0xbab2eae40_0 .net *"_ivl_7", 0 0, L_0xbab345180; 1 drivers +v0xbab2eaee0_0 .net *"_ivl_9", 7 0, L_0xbaad588c0; 1 drivers +L_0xbaa879b58 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2eaf80_0 .net/s "acc_in", 39 0, L_0xbaa879b58; 1 drivers +v0xbab2eb020_0 .net/s "acc_out", 39 0, L_0xbab342260; alias, 1 drivers +v0xbab2eb0c0_0 .net/s "product", 31 0, L_0xbaad58820; 1 drivers +v0xbab2eb160_0 .net/s "product_ext", 39 0, L_0xbab3421c0; 1 drivers +v0xbab2eb200_0 .net/s "w", 15 0, L_0xbab3452c0; 1 drivers +v0xbab2eb2a0_0 .net/s "x", 15 0, L_0xbab345220; 1 drivers +L_0xbab342080 .extend/s 32, L_0xbab345220; +L_0xbab342120 .extend/s 32, L_0xbab3452c0; +L_0xbaad58820 .arith/mult 32, L_0xbab342080, L_0xbab342120; +L_0xbab345180 .part L_0xbaad58820, 31, 1; +L_0xbaad588c0 .repeat 8, 8, L_0xbab345180; +L_0xbab3421c0 .concat [ 32 8 0 0], L_0xbaad58820, L_0xbaad588c0; +L_0xbab342260 .arith/sum 40, L_0xbaa879b58, L_0xbab3421c0; +S_0xbab2e6100 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50780 .param/l "i" 1 5 80, +C4<00>; +L_0xbab069880 .functor BUFZ 40, L_0xbab3410e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6280 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad508c0 .param/l "i" 1 5 80, +C4<01>; +L_0xbab0698f0 .functor BUFZ 40, L_0xbab341360, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6400 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50900 .param/l "i" 1 5 80, +C4<010>; +L_0xbab069960 .functor BUFZ 40, L_0xbab3415e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6580 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50940 .param/l "i" 1 5 80, +C4<011>; +L_0xbab0699d0 .functor BUFZ 40, L_0xbab341860, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6700 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50980 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab069a40 .functor BUFZ 40, L_0xbab341ae0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6880 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad509c0 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab069ab0 .functor BUFZ 40, L_0xbab341d60, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6a00 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50a00 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab069b20 .functor BUFZ 40, L_0xbab341fe0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6b80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50a40 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab069b90 .functor BUFZ 40, L_0xbab342260, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2e6d00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50a80 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2e6e80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2e6d00; + .timescale 0 0; +P_0xbaad50ac0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab342300 .arith/sum 40, L_0xbab069880, L_0xbab0698f0; +S_0xbab2e7000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2e6d00; + .timescale 0 0; +P_0xbaad50b00 .param/l "node" 1 5 94, +C4<01>; +L_0xbab3423a0 .arith/sum 40, L_0xbab069960, L_0xbab0699d0; +S_0xbab2e7180 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2e6d00; + .timescale 0 0; +P_0xbaad50b40 .param/l "node" 1 5 94, +C4<010>; +L_0xbab342440 .arith/sum 40, L_0xbab069a40, L_0xbab069ab0; +S_0xbab2e7300 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2e6d00; + .timescale 0 0; +P_0xbaad50b80 .param/l "node" 1 5 94, +C4<011>; +L_0xbab3424e0 .arith/sum 40, L_0xbab069b20, L_0xbab069b90; +S_0xbab2e7480 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50bc0 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2e7600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2e7480; + .timescale 0 0; +P_0xbaad50c00 .param/l "node" 1 5 94, +C4<00>; +L_0xbab342580 .arith/sum 40, L_0xbab342300, L_0xbab3423a0; +S_0xbab2e7780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2e7480; + .timescale 0 0; +P_0xbaad50c40 .param/l "node" 1 5 94, +C4<01>; +L_0xbab342620 .arith/sum 40, L_0xbab342440, L_0xbab3424e0; +S_0xbab2e7900 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2e4780; + .timescale 0 0; +P_0xbaad50c80 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2e7a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2e7900; + .timescale 0 0; +P_0xbaad50cc0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab3426c0 .arith/sum 40, L_0xbab342580, L_0xbab342620; +S_0xbab2e7c00 .scope generate, "GEN_NEURON[7]" "GEN_NEURON[7]" 3 34, 3 34 0, S_0x102e308c0; + .timescale 0 0; +P_0xbaad50d40 .param/l "n" 1 3 34, +C4<0111>; +S_0xbab2e7d80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xbab2e7c00; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc780 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>; +P_0xbab2bc7c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0xbab2bc800 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>; +P_0xbab2bc840 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>; +P_0xbab2bc880 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>; +P_0xbab2bc8c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab300000_0 .net *"_ivl_0", 31 0, L_0xbab342940; 1 drivers +v0xbab3000a0_0 .net *"_ivl_11", 31 0, L_0xbaad58b40; 1 drivers +v0xbab300140_0 .net *"_ivl_14", 31 0, L_0xbab3429e0; 1 drivers +L_0xbaa879c78 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab3001e0_0 .net *"_ivl_17", 28 0, L_0xbaa879c78; 1 drivers +L_0xbaa879cc0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab300280_0 .net/2u *"_ivl_18", 31 0, L_0xbaa879cc0; 1 drivers +v0xbab300320_0 .net *"_ivl_21", 31 0, L_0xbaad58be0; 1 drivers +L_0xbaa879d08 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab3003c0_0 .net/2u *"_ivl_22", 31 0, L_0xbaa879d08; 1 drivers +v0xbab300460_0 .net *"_ivl_25", 31 0, L_0xbaad58c80; 1 drivers +v0xbab300500_0 .net *"_ivl_29", 0 0, L_0xbab346580; 1 drivers +L_0xbaa879ba0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab3005a0_0 .net *"_ivl_3", 28 0, L_0xbaa879ba0; 1 drivers +v0xbab300640_0 .net *"_ivl_31", 23 0, L_0xbaad597c0; 1 drivers +L_0xbaa879be8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab3006e0_0 .net/2u *"_ivl_4", 31 0, L_0xbaa879be8; 1 drivers +v0xbab300780_0 .net *"_ivl_7", 31 0, L_0xbaad58aa0; 1 drivers +L_0xbaa879c30 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0xbab300820_0 .net/2u *"_ivl_8", 31 0, L_0xbaa879c30; 1 drivers +v0xbab3008c0_0 .var/s "acc", 39 0; +v0xbab300960_0 .net/s "acc_next", 39 0, L_0xbab34c320; 1 drivers +v0xbab300a00_0 .net/s "bias", 15 0, L_0xbab3466c0; 1 drivers +v0xbab300aa0_0 .net/s "bias_ext", 39 0, L_0xbab34c3c0; 1 drivers +v0xbab300b40_0 .var "busy", 0 0; +v0xbab300be0_0 .net "clk", 0 0, o0xbaa845fc0; alias, 0 drivers +v0xbab300c80_0 .var "done", 0 0; +v0xbab300d20_0 .net/s "final_acc", 39 0, L_0xbab34c460; 1 drivers +v0xbab300dc0_0 .var "group_index", 2 0; +v0xbab300e60_0 .net "rst", 0 0, o0xbaa846080; alias, 0 drivers +v0xbab300f00_0 .net "start", 0 0, o0xbaa8460b0; alias, 0 drivers +v0xbab300fa0_0 .net/s "w_bus", 1023 0, L_0xbab346620; 1 drivers +v0xbab301040_0 .net/s "w_group", 127 0, L_0xbab3455e0; 1 drivers +v0xbab3010e0_0 .net/s "x_bus", 1023 0, o0xbaa846110; alias, 0 drivers +v0xbab301180_0 .net/s "x_group", 127 0, L_0xbab345540; 1 drivers +v0xbab301220_0 .var/s "y", 15 0; +L_0xbab342940 .concat [ 3 29 0 0], v0xbab300dc0_0, L_0xbaa879ba0; +L_0xbaad58aa0 .arith/mult 32, L_0xbab342940, L_0xbaa879be8; +L_0xbaad58b40 .arith/mult 32, L_0xbaad58aa0, L_0xbaa879c30; +L_0xbab345540 .part/v o0xbaa846110, L_0xbaad58b40, 128; +L_0xbab3429e0 .concat [ 3 29 0 0], v0xbab300dc0_0, L_0xbaa879c78; +L_0xbaad58be0 .arith/mult 32, L_0xbab3429e0, L_0xbaa879cc0; +L_0xbaad58c80 .arith/mult 32, L_0xbaad58be0, L_0xbaa879d08; +L_0xbab3455e0 .part/v L_0xbab346620, L_0xbaad58c80, 128; +L_0xbab346580 .part L_0xbab3466c0, 15, 1; +L_0xbaad597c0 .repeat 24, 24, L_0xbab346580; +L_0xbab34c3c0 .concat [ 16 24 0 0], L_0xbab3466c0, L_0xbaad597c0; +L_0xbab34c460 .arith/sum 40, L_0xbab34c320, L_0xbab34c3c0; +S_0xbab2fc000 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab2e7d80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbab295600 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0xbab295640 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0xbab295680 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab2956c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab2fbc00_0 .net/s "acc_in", 39 0, v0xbab3008c0_0; 1 drivers +v0xbab2fbca0_0 .net/s "acc_out", 39 0, L_0xbab34c320; alias, 1 drivers +v0xbab2fbd40 .array "products", 7 0; +v0xbab2fbd40_0 .net/s v0xbab2fbd40 0, 39 0, L_0xbab342c60; 1 drivers +v0xbab2fbd40_1 .net/s v0xbab2fbd40 1, 39 0, L_0xbab342ee0; 1 drivers +v0xbab2fbd40_2 .net/s v0xbab2fbd40 2, 39 0, L_0xbab343160; 1 drivers +v0xbab2fbd40_3 .net/s v0xbab2fbd40 3, 39 0, L_0xbab3433e0; 1 drivers +v0xbab2fbd40_4 .net/s v0xbab2fbd40 4, 39 0, L_0xbab343660; 1 drivers +v0xbab2fbd40_5 .net/s v0xbab2fbd40 5, 39 0, L_0xbab3438e0; 1 drivers +v0xbab2fbd40_6 .net/s v0xbab2fbd40 6, 39 0, L_0xbab343b60; 1 drivers +v0xbab2fbd40_7 .net/s v0xbab2fbd40 7, 39 0, L_0xbab343de0; 1 drivers +v0xbab2fbde0 .array "tree", 31 0; +v0xbab2fbde0_0 .net/s v0xbab2fbde0 0, 39 0, L_0xbab069c00; 1 drivers +v0xbab2fbde0_1 .net/s v0xbab2fbde0 1, 39 0, L_0xbab069c70; 1 drivers +v0xbab2fbde0_2 .net/s v0xbab2fbde0 2, 39 0, L_0xbab069ce0; 1 drivers +v0xbab2fbde0_3 .net/s v0xbab2fbde0 3, 39 0, L_0xbab069d50; 1 drivers +v0xbab2fbde0_4 .net/s v0xbab2fbde0 4, 39 0, L_0xbab069dc0; 1 drivers +v0xbab2fbde0_5 .net/s v0xbab2fbde0 5, 39 0, L_0xbab069e30; 1 drivers +v0xbab2fbde0_6 .net/s v0xbab2fbde0 6, 39 0, L_0xbab069ea0; 1 drivers +v0xbab2fbde0_7 .net/s v0xbab2fbde0 7, 39 0, L_0xbab069f10; 1 drivers +v0xbab2fbde0_8 .net/s v0xbab2fbde0 8, 39 0, L_0xbab343e80; 1 drivers +v0xbab2fbde0_9 .net/s v0xbab2fbde0 9, 39 0, L_0xbab343f20; 1 drivers +v0xbab2fbde0_10 .net/s v0xbab2fbde0 10, 39 0, L_0xbab34c000; 1 drivers +v0xbab2fbde0_11 .net/s v0xbab2fbde0 11, 39 0, L_0xbab34c0a0; 1 drivers +o0xbaa8548a0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_12 .net/s v0xbab2fbde0 12, 39 0, o0xbaa8548a0; 0 drivers +o0xbaa8548d0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_13 .net/s v0xbab2fbde0 13, 39 0, o0xbaa8548d0; 0 drivers +o0xbaa854900 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_14 .net/s v0xbab2fbde0 14, 39 0, o0xbaa854900; 0 drivers +o0xbaa854930 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_15 .net/s v0xbab2fbde0 15, 39 0, o0xbaa854930; 0 drivers +v0xbab2fbde0_16 .net/s v0xbab2fbde0 16, 39 0, L_0xbab34c140; 1 drivers +v0xbab2fbde0_17 .net/s v0xbab2fbde0 17, 39 0, L_0xbab34c1e0; 1 drivers +o0xbaa8549c0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_18 .net/s v0xbab2fbde0 18, 39 0, o0xbaa8549c0; 0 drivers +o0xbaa8549f0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_19 .net/s v0xbab2fbde0 19, 39 0, o0xbaa8549f0; 0 drivers +o0xbaa854a20 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_20 .net/s v0xbab2fbde0 20, 39 0, o0xbaa854a20; 0 drivers +o0xbaa854a50 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_21 .net/s v0xbab2fbde0 21, 39 0, o0xbaa854a50; 0 drivers +o0xbaa854a80 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_22 .net/s v0xbab2fbde0 22, 39 0, o0xbaa854a80; 0 drivers +o0xbaa854ab0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_23 .net/s v0xbab2fbde0 23, 39 0, o0xbaa854ab0; 0 drivers +v0xbab2fbde0_24 .net/s v0xbab2fbde0 24, 39 0, L_0xbab34c280; 1 drivers +o0xbaa854b10 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_25 .net/s v0xbab2fbde0 25, 39 0, o0xbaa854b10; 0 drivers +o0xbaa854b40 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_26 .net/s v0xbab2fbde0 26, 39 0, o0xbaa854b40; 0 drivers +o0xbaa854b70 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_27 .net/s v0xbab2fbde0 27, 39 0, o0xbaa854b70; 0 drivers +o0xbaa854ba0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_28 .net/s v0xbab2fbde0 28, 39 0, o0xbaa854ba0; 0 drivers +o0xbaa854bd0 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_29 .net/s v0xbab2fbde0 29, 39 0, o0xbaa854bd0; 0 drivers +o0xbaa854c00 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_30 .net/s v0xbab2fbde0 30, 39 0, o0xbaa854c00; 0 drivers +o0xbaa854c30 .functor BUFZ 40, c4; HiZ drive +v0xbab2fbde0_31 .net/s v0xbab2fbde0 31, 39 0, o0xbaa854c30; 0 drivers +v0xbab2fbe80_0 .net/s "w_bus", 127 0, L_0xbab3455e0; alias, 1 drivers +v0xbab2fbf20_0 .net/s "x_bus", 127 0, L_0xbab345540; alias, 1 drivers +L_0xbab345720 .part L_0xbab345540, 0, 16; +L_0xbab3457c0 .part L_0xbab3455e0, 0, 16; +L_0xbab345900 .part L_0xbab345540, 16, 16; +L_0xbab3459a0 .part L_0xbab3455e0, 16, 16; +L_0xbab345ae0 .part L_0xbab345540, 32, 16; +L_0xbab345b80 .part L_0xbab3455e0, 32, 16; +L_0xbab345cc0 .part L_0xbab345540, 48, 16; +L_0xbab345d60 .part L_0xbab3455e0, 48, 16; +L_0xbab345ea0 .part L_0xbab345540, 64, 16; +L_0xbab345f40 .part L_0xbab3455e0, 64, 16; +L_0xbab346080 .part L_0xbab345540, 80, 16; +L_0xbab346120 .part L_0xbab3455e0, 80, 16; +L_0xbab346260 .part L_0xbab345540, 96, 16; +L_0xbab346300 .part L_0xbab3455e0, 96, 16; +L_0xbab346440 .part L_0xbab345540, 112, 16; +L_0xbab3464e0 .part L_0xbab3455e0, 112, 16; +L_0xbab34c320 .arith/sum 40, v0xbab3008c0_0, L_0xbab34c280; +S_0xbab2fc180 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50d80 .param/l "i" 1 5 20, +C4<00>; +S_0xbab2fc300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fc180; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e7c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e800 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e840 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2f8a00_0 .net/s *"_ivl_0", 31 0, L_0xbab342a80; 1 drivers +v0xbab2f8aa0_0 .net/s *"_ivl_2", 31 0, L_0xbab342b20; 1 drivers +v0xbab2f8b40_0 .net *"_ivl_7", 0 0, L_0xbab345680; 1 drivers +v0xbab2f8be0_0 .net *"_ivl_9", 7 0, L_0xbaad58dc0; 1 drivers +L_0xbaa879d50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2f8c80_0 .net/s "acc_in", 39 0, L_0xbaa879d50; 1 drivers +v0xbab2f8d20_0 .net/s "acc_out", 39 0, L_0xbab342c60; alias, 1 drivers +v0xbab2f8dc0_0 .net/s "product", 31 0, L_0xbaad58d20; 1 drivers +v0xbab2f8e60_0 .net/s "product_ext", 39 0, L_0xbab342bc0; 1 drivers +v0xbab2f8f00_0 .net/s "w", 15 0, L_0xbab3457c0; 1 drivers +v0xbab2f8fa0_0 .net/s "x", 15 0, L_0xbab345720; 1 drivers +L_0xbab342a80 .extend/s 32, L_0xbab345720; +L_0xbab342b20 .extend/s 32, L_0xbab3457c0; +L_0xbaad58d20 .arith/mult 32, L_0xbab342a80, L_0xbab342b20; +L_0xbab345680 .part L_0xbaad58d20, 31, 1; +L_0xbaad58dc0 .repeat 8, 8, L_0xbab345680; +L_0xbab342bc0 .concat [ 32 8 0 0], L_0xbaad58d20, L_0xbaad58dc0; +L_0xbab342c60 .arith/sum 40, L_0xbaa879d50, L_0xbab342bc0; +S_0xbab2fc480 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50dc0 .param/l "i" 1 5 20, +C4<01>; +S_0xbab2fc600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fc480; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e880 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e8c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e900 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2f9040_0 .net/s *"_ivl_0", 31 0, L_0xbab342d00; 1 drivers +v0xbab2f90e0_0 .net/s *"_ivl_2", 31 0, L_0xbab342da0; 1 drivers +v0xbab2f9180_0 .net *"_ivl_7", 0 0, L_0xbab345860; 1 drivers +v0xbab2f9220_0 .net *"_ivl_9", 7 0, L_0xbaad58f00; 1 drivers +L_0xbaa879d98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2f92c0_0 .net/s "acc_in", 39 0, L_0xbaa879d98; 1 drivers +v0xbab2f9360_0 .net/s "acc_out", 39 0, L_0xbab342ee0; alias, 1 drivers +v0xbab2f9400_0 .net/s "product", 31 0, L_0xbaad58e60; 1 drivers +v0xbab2f94a0_0 .net/s "product_ext", 39 0, L_0xbab342e40; 1 drivers +v0xbab2f9540_0 .net/s "w", 15 0, L_0xbab3459a0; 1 drivers +v0xbab2f95e0_0 .net/s "x", 15 0, L_0xbab345900; 1 drivers +L_0xbab342d00 .extend/s 32, L_0xbab345900; +L_0xbab342da0 .extend/s 32, L_0xbab3459a0; +L_0xbaad58e60 .arith/mult 32, L_0xbab342d00, L_0xbab342da0; +L_0xbab345860 .part L_0xbaad58e60, 31, 1; +L_0xbaad58f00 .repeat 8, 8, L_0xbab345860; +L_0xbab342e40 .concat [ 32 8 0 0], L_0xbaad58e60, L_0xbaad58f00; +L_0xbab342ee0 .arith/sum 40, L_0xbaa879d98, L_0xbab342e40; +S_0xbab2fc780 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50e00 .param/l "i" 1 5 20, +C4<010>; +S_0xbab2fc900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fc780; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4e940 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4e980 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4e9c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2f9680_0 .net/s *"_ivl_0", 31 0, L_0xbab342f80; 1 drivers +v0xbab2f9720_0 .net/s *"_ivl_2", 31 0, L_0xbab343020; 1 drivers +v0xbab2f97c0_0 .net *"_ivl_7", 0 0, L_0xbab345a40; 1 drivers +v0xbab2f9860_0 .net *"_ivl_9", 7 0, L_0xbaad59040; 1 drivers +L_0xbaa879de0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2f9900_0 .net/s "acc_in", 39 0, L_0xbaa879de0; 1 drivers +v0xbab2f99a0_0 .net/s "acc_out", 39 0, L_0xbab343160; alias, 1 drivers +v0xbab2f9a40_0 .net/s "product", 31 0, L_0xbaad58fa0; 1 drivers +v0xbab2f9ae0_0 .net/s "product_ext", 39 0, L_0xbab3430c0; 1 drivers +v0xbab2f9b80_0 .net/s "w", 15 0, L_0xbab345b80; 1 drivers +v0xbab2f9c20_0 .net/s "x", 15 0, L_0xbab345ae0; 1 drivers +L_0xbab342f80 .extend/s 32, L_0xbab345ae0; +L_0xbab343020 .extend/s 32, L_0xbab345b80; +L_0xbaad58fa0 .arith/mult 32, L_0xbab342f80, L_0xbab343020; +L_0xbab345a40 .part L_0xbaad58fa0, 31, 1; +L_0xbaad59040 .repeat 8, 8, L_0xbab345a40; +L_0xbab3430c0 .concat [ 32 8 0 0], L_0xbaad58fa0, L_0xbaad59040; +L_0xbab343160 .arith/sum 40, L_0xbaa879de0, L_0xbab3430c0; +S_0xbab2fca80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50e40 .param/l "i" 1 5 20, +C4<011>; +S_0xbab2fcc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fca80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ea00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ea40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ea80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2f9cc0_0 .net/s *"_ivl_0", 31 0, L_0xbab343200; 1 drivers +v0xbab2f9d60_0 .net/s *"_ivl_2", 31 0, L_0xbab3432a0; 1 drivers +v0xbab2f9e00_0 .net *"_ivl_7", 0 0, L_0xbab345c20; 1 drivers +v0xbab2f9ea0_0 .net *"_ivl_9", 7 0, L_0xbaad59180; 1 drivers +L_0xbaa879e28 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2f9f40_0 .net/s "acc_in", 39 0, L_0xbaa879e28; 1 drivers +v0xbab2f9fe0_0 .net/s "acc_out", 39 0, L_0xbab3433e0; alias, 1 drivers +v0xbab2fa080_0 .net/s "product", 31 0, L_0xbaad590e0; 1 drivers +v0xbab2fa120_0 .net/s "product_ext", 39 0, L_0xbab343340; 1 drivers +v0xbab2fa1c0_0 .net/s "w", 15 0, L_0xbab345d60; 1 drivers +v0xbab2fa260_0 .net/s "x", 15 0, L_0xbab345cc0; 1 drivers +L_0xbab343200 .extend/s 32, L_0xbab345cc0; +L_0xbab3432a0 .extend/s 32, L_0xbab345d60; +L_0xbaad590e0 .arith/mult 32, L_0xbab343200, L_0xbab3432a0; +L_0xbab345c20 .part L_0xbaad590e0, 31, 1; +L_0xbaad59180 .repeat 8, 8, L_0xbab345c20; +L_0xbab343340 .concat [ 32 8 0 0], L_0xbaad590e0, L_0xbaad59180; +L_0xbab3433e0 .arith/sum 40, L_0xbaa879e28, L_0xbab343340; +S_0xbab2fcd80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50ec0 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab2fcf00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fcd80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4eac0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4eb00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4eb40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2fa300_0 .net/s *"_ivl_0", 31 0, L_0xbab343480; 1 drivers +v0xbab2fa3a0_0 .net/s *"_ivl_2", 31 0, L_0xbab343520; 1 drivers +v0xbab2fa440_0 .net *"_ivl_7", 0 0, L_0xbab345e00; 1 drivers +v0xbab2fa4e0_0 .net *"_ivl_9", 7 0, L_0xbaad592c0; 1 drivers +L_0xbaa879e70 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2fa580_0 .net/s "acc_in", 39 0, L_0xbaa879e70; 1 drivers +v0xbab2fa620_0 .net/s "acc_out", 39 0, L_0xbab343660; alias, 1 drivers +v0xbab2fa6c0_0 .net/s "product", 31 0, L_0xbaad59220; 1 drivers +v0xbab2fa760_0 .net/s "product_ext", 39 0, L_0xbab3435c0; 1 drivers +v0xbab2fa800_0 .net/s "w", 15 0, L_0xbab345f40; 1 drivers +v0xbab2fa8a0_0 .net/s "x", 15 0, L_0xbab345ea0; 1 drivers +L_0xbab343480 .extend/s 32, L_0xbab345ea0; +L_0xbab343520 .extend/s 32, L_0xbab345f40; +L_0xbaad59220 .arith/mult 32, L_0xbab343480, L_0xbab343520; +L_0xbab345e00 .part L_0xbaad59220, 31, 1; +L_0xbaad592c0 .repeat 8, 8, L_0xbab345e00; +L_0xbab3435c0 .concat [ 32 8 0 0], L_0xbaad59220, L_0xbaad592c0; +L_0xbab343660 .arith/sum 40, L_0xbaa879e70, L_0xbab3435c0; +S_0xbab2fd080 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50f00 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab2fd200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fd080; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4eb80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ebc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ec00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2fa940_0 .net/s *"_ivl_0", 31 0, L_0xbab343700; 1 drivers +v0xbab2fa9e0_0 .net/s *"_ivl_2", 31 0, L_0xbab3437a0; 1 drivers +v0xbab2faa80_0 .net *"_ivl_7", 0 0, L_0xbab345fe0; 1 drivers +v0xbab2fab20_0 .net *"_ivl_9", 7 0, L_0xbaad59400; 1 drivers +L_0xbaa879eb8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2fabc0_0 .net/s "acc_in", 39 0, L_0xbaa879eb8; 1 drivers +v0xbab2fac60_0 .net/s "acc_out", 39 0, L_0xbab3438e0; alias, 1 drivers +v0xbab2fad00_0 .net/s "product", 31 0, L_0xbaad59360; 1 drivers +v0xbab2fada0_0 .net/s "product_ext", 39 0, L_0xbab343840; 1 drivers +v0xbab2fae40_0 .net/s "w", 15 0, L_0xbab346120; 1 drivers +v0xbab2faee0_0 .net/s "x", 15 0, L_0xbab346080; 1 drivers +L_0xbab343700 .extend/s 32, L_0xbab346080; +L_0xbab3437a0 .extend/s 32, L_0xbab346120; +L_0xbaad59360 .arith/mult 32, L_0xbab343700, L_0xbab3437a0; +L_0xbab345fe0 .part L_0xbaad59360, 31, 1; +L_0xbaad59400 .repeat 8, 8, L_0xbab345fe0; +L_0xbab343840 .concat [ 32 8 0 0], L_0xbaad59360, L_0xbaad59400; +L_0xbab3438e0 .arith/sum 40, L_0xbaa879eb8, L_0xbab343840; +S_0xbab2fd380 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50f40 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab2fd500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fd380; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ec40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ec80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ecc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2faf80_0 .net/s *"_ivl_0", 31 0, L_0xbab343980; 1 drivers +v0xbab2fb020_0 .net/s *"_ivl_2", 31 0, L_0xbab343a20; 1 drivers +v0xbab2fb0c0_0 .net *"_ivl_7", 0 0, L_0xbab3461c0; 1 drivers +v0xbab2fb160_0 .net *"_ivl_9", 7 0, L_0xbaad59540; 1 drivers +L_0xbaa879f00 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2fb200_0 .net/s "acc_in", 39 0, L_0xbaa879f00; 1 drivers +v0xbab2fb2a0_0 .net/s "acc_out", 39 0, L_0xbab343b60; alias, 1 drivers +v0xbab2fb340_0 .net/s "product", 31 0, L_0xbaad594a0; 1 drivers +v0xbab2fb3e0_0 .net/s "product_ext", 39 0, L_0xbab343ac0; 1 drivers +v0xbab2fb480_0 .net/s "w", 15 0, L_0xbab346300; 1 drivers +v0xbab2fb520_0 .net/s "x", 15 0, L_0xbab346260; 1 drivers +L_0xbab343980 .extend/s 32, L_0xbab346260; +L_0xbab343a20 .extend/s 32, L_0xbab346300; +L_0xbaad594a0 .arith/mult 32, L_0xbab343980, L_0xbab343a20; +L_0xbab3461c0 .part L_0xbaad594a0, 31, 1; +L_0xbaad59540 .repeat 8, 8, L_0xbab3461c0; +L_0xbab343ac0 .concat [ 32 8 0 0], L_0xbaad594a0, L_0xbaad59540; +L_0xbab343b60 .arith/sum 40, L_0xbaa879f00, L_0xbab343ac0; +S_0xbab2fd680 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50f80 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab2fd800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab2fd680; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0xbaad4ed00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0xbaad4ed40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0xbaad4ed80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0xbab2fb5c0_0 .net/s *"_ivl_0", 31 0, L_0xbab343c00; 1 drivers +v0xbab2fb660_0 .net/s *"_ivl_2", 31 0, L_0xbab343ca0; 1 drivers +v0xbab2fb700_0 .net *"_ivl_7", 0 0, L_0xbab3463a0; 1 drivers +v0xbab2fb7a0_0 .net *"_ivl_9", 7 0, L_0xbaad59680; 1 drivers +L_0xbaa879f48 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab2fb840_0 .net/s "acc_in", 39 0, L_0xbaa879f48; 1 drivers +v0xbab2fb8e0_0 .net/s "acc_out", 39 0, L_0xbab343de0; alias, 1 drivers +v0xbab2fb980_0 .net/s "product", 31 0, L_0xbaad595e0; 1 drivers +v0xbab2fba20_0 .net/s "product_ext", 39 0, L_0xbab343d40; 1 drivers +v0xbab2fbac0_0 .net/s "w", 15 0, L_0xbab3464e0; 1 drivers +v0xbab2fbb60_0 .net/s "x", 15 0, L_0xbab346440; 1 drivers +L_0xbab343c00 .extend/s 32, L_0xbab346440; +L_0xbab343ca0 .extend/s 32, L_0xbab3464e0; +L_0xbaad595e0 .arith/mult 32, L_0xbab343c00, L_0xbab343ca0; +L_0xbab3463a0 .part L_0xbaad595e0, 31, 1; +L_0xbaad59680 .repeat 8, 8, L_0xbab3463a0; +L_0xbab343d40 .concat [ 32 8 0 0], L_0xbaad595e0, L_0xbaad59680; +L_0xbab343de0 .arith/sum 40, L_0xbaa879f48, L_0xbab343d40; +S_0xbab2fd980 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50e80 .param/l "i" 1 5 80, +C4<00>; +L_0xbab069c00 .functor BUFZ 40, L_0xbab342c60, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fdb00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad50fc0 .param/l "i" 1 5 80, +C4<01>; +L_0xbab069c70 .functor BUFZ 40, L_0xbab342ee0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fdc80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51000 .param/l "i" 1 5 80, +C4<010>; +L_0xbab069ce0 .functor BUFZ 40, L_0xbab343160, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fde00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51040 .param/l "i" 1 5 80, +C4<011>; +L_0xbab069d50 .functor BUFZ 40, L_0xbab3433e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fdf80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51080 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab069dc0 .functor BUFZ 40, L_0xbab343660, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fe100 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad510c0 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab069e30 .functor BUFZ 40, L_0xbab3438e0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fe280 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51100 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab069ea0 .functor BUFZ 40, L_0xbab343b60, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fe400 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51140 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab069f10 .functor BUFZ 40, L_0xbab343de0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>; +S_0xbab2fe580 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51180 .param/l "level" 1 5 92, +C4<00>; +S_0xbab2fe700 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2fe580; + .timescale 0 0; +P_0xbaad511c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab343e80 .arith/sum 40, L_0xbab069c00, L_0xbab069c70; +S_0xbab2fe880 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2fe580; + .timescale 0 0; +P_0xbaad51200 .param/l "node" 1 5 94, +C4<01>; +L_0xbab343f20 .arith/sum 40, L_0xbab069ce0, L_0xbab069d50; +S_0xbab2fea00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab2fe580; + .timescale 0 0; +P_0xbaad51240 .param/l "node" 1 5 94, +C4<010>; +L_0xbab34c000 .arith/sum 40, L_0xbab069dc0, L_0xbab069e30; +S_0xbab2feb80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab2fe580; + .timescale 0 0; +P_0xbaad51280 .param/l "node" 1 5 94, +C4<011>; +L_0xbab34c0a0 .arith/sum 40, L_0xbab069ea0, L_0xbab069f10; +S_0xbab2fed00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad512c0 .param/l "level" 1 5 92, +C4<01>; +S_0xbab2fee80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2fed00; + .timescale 0 0; +P_0xbaad51300 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34c140 .arith/sum 40, L_0xbab343e80, L_0xbab343f20; +S_0xbab2ff000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab2fed00; + .timescale 0 0; +P_0xbaad51340 .param/l "node" 1 5 94, +C4<01>; +L_0xbab34c1e0 .arith/sum 40, L_0xbab34c000, L_0xbab34c0a0; +S_0xbab2ff180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab2fc000; + .timescale 0 0; +P_0xbaad51380 .param/l "level" 1 5 92, +C4<010>; +S_0xbab2ff300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab2ff180; + .timescale 0 0; +P_0xbaad513c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34c280 .arith/sum 40, L_0xbab34c140, L_0xbab34c1e0; +S_0x102e305e0 .scope module, "memory_interface" "memory_interface" 7 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 16 "wdata"; + .port_info 6 /INPUT 1 "lb_n"; + .port_info 7 /INPUT 1 "ub_n"; + .port_info 8 /OUTPUT 16 "rdata"; + .port_info 9 /OUTPUT 1 "ready"; + .port_info 10 /OUTPUT 1 "mem_req"; + .port_info 11 /OUTPUT 1 "mem_wr"; + .port_info 12 /OUTPUT 22 "mem_addr"; + .port_info 13 /OUTPUT 16 "mem_wdata"; + .port_info 14 /OUTPUT 1 "mem_lb_n"; + .port_info 15 /OUTPUT 1 "mem_ub_n"; + .port_info 16 /INPUT 16 "mem_rdata"; + .port_info 17 /INPUT 1 "mem_ready"; +P_0x102e30760 .param/l "ADDR_WIDTH" 0 7 2, +C4<00000000000000000000000000010110>; +P_0x102e307a0 .param/l "DATA_WIDTH" 0 7 3, +C4<00000000000000000000000000010000>; +P_0x102e307e0 .param/l "STATE_IDLE" 1 7 28, C4<00>; +P_0x102e30820 .param/l "STATE_WAIT" 1 7 29, C4<01>; +o0xbaa855650 .functor BUFZ 22, c4; HiZ drive +v0xbab3019a0_0 .net "addr", 21 0, o0xbaa855650; 0 drivers +o0xbaa855680 .functor BUFZ 1, c4; HiZ drive +v0xbab301a40_0 .net "clk", 0 0, o0xbaa855680; 0 drivers +o0xbaa8556b0 .functor BUFZ 1, c4; HiZ drive +v0xbab301ae0_0 .net "lb_n", 0 0, o0xbaa8556b0; 0 drivers +v0xbab301b80_0 .var "mem_addr", 21 0; +v0xbab301c20_0 .var "mem_lb_n", 0 0; +o0xbaa855740 .functor BUFZ 16, c4; HiZ drive +v0xbab301cc0_0 .net "mem_rdata", 15 0, o0xbaa855740; 0 drivers +o0xbaa855770 .functor BUFZ 1, c4; HiZ drive +v0xbab301d60_0 .net "mem_ready", 0 0, o0xbaa855770; 0 drivers +v0xbab301e00_0 .var "mem_req", 0 0; +v0xbab301ea0_0 .var "mem_ub_n", 0 0; +v0xbab301f40_0 .var "mem_wdata", 15 0; +v0xbab301fe0_0 .var "mem_wr", 0 0; +v0xbab302080_0 .var "rdata", 15 0; +v0xbab302120_0 .var "ready", 0 0; +o0xbaa8558c0 .functor BUFZ 1, c4; HiZ drive +v0xbab3021c0_0 .net "req", 0 0, o0xbaa8558c0; 0 drivers +o0xbaa8558f0 .functor BUFZ 1, c4; HiZ drive +v0xbab302260_0 .net "rst", 0 0, o0xbaa8558f0; 0 drivers +v0xbab302300_0 .var "state", 1 0; +o0xbaa855950 .functor BUFZ 1, c4; HiZ drive +v0xbab3023a0_0 .net "ub_n", 0 0, o0xbaa855950; 0 drivers +o0xbaa855980 .functor BUFZ 16, c4; HiZ drive +v0xbab302440_0 .net "wdata", 15 0, o0xbaa855980; 0 drivers +o0xbaa8559b0 .functor BUFZ 1, c4; HiZ drive +v0xbab3024e0_0 .net "wr", 0 0, o0xbaa8559b0; 0 drivers +E_0xbaad3a100 .event posedge, v0xbab301a40_0; +S_0x102e25b60 .scope module, "memory_model" "memory_model" 8 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 16 "wdata"; + .port_info 6 /OUTPUT 16 "rdata"; + .port_info 7 /OUTPUT 1 "ready"; +P_0x102e30a40 .param/l "ADDR_WIDTH" 0 8 2, +C4<00000000000000000000000000010110>; +P_0x102e30a80 .param/l "DATA_WIDTH" 0 8 3, +C4<00000000000000000000000000010000>; +P_0x102e30ac0 .param/l "DEPTH" 0 8 4, +C4<00000000000000000001000000000000>; +P_0x102e30b00 .param/l "READ_LATENCY" 0 8 5, +C4<00000000000000000000000000000010>; +o0xbaa855d40 .functor BUFZ 22, c4; HiZ drive +v0xbab302580_0 .net "addr", 21 0, o0xbaa855d40; 0 drivers +v0xbab302620_0 .var "busy", 0 0; +o0xbaa855da0 .functor BUFZ 1, c4; HiZ drive +v0xbab3026c0_0 .net "clk", 0 0, o0xbaa855da0; 0 drivers +v0xbab302760_0 .var/i "delay_count", 31 0; +v0xbab302800_0 .var/i "i", 31 0; +v0xbab3028a0 .array "mem", 4095 0, 15 0; +v0xbab302940_0 .var "pending_addr", 21 0; +v0xbab3029e0_0 .var "pending_wdata", 15 0; +v0xbab302a80_0 .var "pending_wr", 0 0; +v0xbab302b20_0 .var "rdata", 15 0; +v0xbab302bc0_0 .var "ready", 0 0; +o0xbaa855f20 .functor BUFZ 1, c4; HiZ drive +v0xbab302c60_0 .net "req", 0 0, o0xbaa855f20; 0 drivers +o0xbaa855f50 .functor BUFZ 1, c4; HiZ drive +v0xbab302d00_0 .net "rst", 0 0, o0xbaa855f50; 0 drivers +o0xbaa855f80 .functor BUFZ 16, c4; HiZ drive +v0xbab302da0_0 .net "wdata", 15 0, o0xbaa855f80; 0 drivers +o0xbaa855fb0 .functor BUFZ 1, c4; HiZ drive +v0xbab302e40_0 .net "wr", 0 0, o0xbaa855fb0; 0 drivers +E_0xbaad3a140 .event posedge, v0xbab3026c0_0; +S_0x102e25ce0 .scope module, "neuron_memory" "neuron_memory" 9 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /OUTPUT 1 "mem_req"; + .port_info 4 /OUTPUT 1 "mem_wr"; + .port_info 5 /OUTPUT 22 "mem_addr"; + .port_info 6 /OUTPUT 8 "mem_wdata"; + .port_info 7 /INPUT 8 "mem_rdata"; + .port_info 8 /INPUT 1 "mem_ready"; + .port_info 9 /INPUT 22 "x_base"; + .port_info 10 /INPUT 22 "w_base"; + .port_info 11 /INPUT 22 "bias_addr"; + .port_info 12 /OUTPUT 8 "y"; + .port_info 13 /OUTPUT 1 "busy"; + .port_info 14 /OUTPUT 1 "done"; +P_0x102e36080 .param/l "ACC_WIDTH" 0 9 8, +C4<00000000000000000000000000100000>; +P_0x102e360c0 .param/l "ADDR_WIDTH" 0 9 4, +C4<00000000000000000000000000010110>; +P_0x102e36100 .param/l "DATA_WIDTH" 0 9 5, +C4<00000000000000000000000000001000>; +P_0x102e36140 .param/l "N_INPUTS" 0 9 6, +C4<00000000000000000000000000100000>; +P_0x102e36180 .param/l "PARALLEL" 0 9 7, +C4<00000000000000000000000000001000>; +P_0x102e361c0 .param/l "STATE_IDLE" 1 9 49, C4<0000>; +P_0x102e36200 .param/l "STATE_READ_BIAS" 1 9 52, C4<0011>; +P_0x102e36240 .param/l "STATE_READ_W" 1 9 51, C4<0010>; +P_0x102e36280 .param/l "STATE_READ_X" 1 9 50, C4<0001>; +P_0x102e362c0 .param/l "STATE_START_N" 1 9 53, C4<0100>; +P_0x102e36300 .param/l "STATE_WAIT_N" 1 9 54, C4<0101>; +L_0xbab06bb80 .functor BUFZ 1, v0xbab309b80_0, C4<0>, C4<0>, C4<0>; +L_0xbab06bbf0 .functor BUFZ 1, v0xbab309d60_0, C4<0>, C4<0>, C4<0>; +L_0xbab06bc60 .functor BUFZ 22, v0xbab312e40_0, C4<0000000000000000000000>, C4<0000000000000000000000>, C4<0000000000000000000000>; +L_0xbab06bcd0 .functor BUFZ 8, v0xbab313520_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0xbab312b20_0 .net *"_ivl_131", 0 0, L_0xbab3468a0; 1 drivers +L_0xbaa879f90 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0xbab312bc0_0 .net/2u *"_ivl_132", 7 0, L_0xbaa879f90; 1 drivers +v0xbab312c60_0 .net *"_ivl_134", 15 0, L_0xbab34c820; 1 drivers +L_0xbaa879fd8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0xbab312d00_0 .net/2u *"_ivl_136", 7 0, L_0xbaa879fd8; 1 drivers +v0xbab312da0_0 .net *"_ivl_138", 15 0, L_0xbab34c8c0; 1 drivers +v0xbab312e40_0 .var "access_addr", 21 0; +v0xbab312ee0_0 .net "access_mem_addr", 21 0, v0xbab309900_0; 1 drivers +v0xbab312f80_0 .net "access_mem_lb_n", 0 0, v0xbab3099a0_0; 1 drivers +v0xbab313020_0 .net "access_mem_rdata", 15 0, L_0xbab346940; 1 drivers +v0xbab3130c0_0 .net "access_mem_req", 0 0, v0xbab309b80_0; 1 drivers +v0xbab313160_0 .net "access_mem_ub_n", 0 0, v0xbab309c20_0; 1 drivers +v0xbab313200_0 .net "access_mem_wdata", 15 0, v0xbab309cc0_0; 1 drivers +v0xbab3132a0_0 .net "access_mem_wr", 0 0, v0xbab309d60_0; 1 drivers +v0xbab313340_0 .net/s "access_rdata", 7 0, v0xbab309e00_0; 1 drivers +v0xbab3133e0_0 .net "access_ready", 0 0, v0xbab309ea0_0; 1 drivers +v0xbab313480_0 .var "access_req", 0 0; +v0xbab313520_0 .var/s "access_wdata", 7 0; +v0xbab3135c0_0 .var "access_wr", 0 0; +o0xbaa859760 .functor BUFZ 22, c4; HiZ drive +v0xbab313660_0 .net "bias_addr", 21 0, o0xbaa859760; 0 drivers +v0xbab313700_0 .var/s "bias_reg", 7 0; +v0xbab3137a0_0 .var "busy", 0 0; +o0xbaa856dc0 .functor BUFZ 1, c4; HiZ drive +v0xbab313840_0 .net "clk", 0 0, o0xbaa856dc0; 0 drivers +v0xbab3138e0_0 .var "done", 0 0; +v0xbab313980_0 .var "index", 5 0; +v0xbab313a20_0 .net "mem_addr", 21 0, L_0xbab06bc60; 1 drivers +o0xbaa859850 .functor BUFZ 8, c4; HiZ drive +v0xbab313ac0_0 .net/s "mem_rdata", 7 0, o0xbaa859850; 0 drivers +o0xbaa856e80 .functor BUFZ 1, c4; HiZ drive +v0xbab313b60_0 .net "mem_ready", 0 0, o0xbaa856e80; 0 drivers +v0xbab313c00_0 .net "mem_req", 0 0, L_0xbab06bb80; 1 drivers +v0xbab313ca0_0 .net/s "mem_wdata", 7 0, L_0xbab06bcd0; 1 drivers +v0xbab313d40_0 .net "mem_wr", 0 0, L_0xbab06bbf0; 1 drivers +v0xbab313de0_0 .net "neuron_busy", 0 0, v0xbab3123a0_0; 1 drivers +v0xbab313e80_0 .net "neuron_done", 0 0, v0xbab3124e0_0; 1 drivers +v0xbab313f20_0 .var "neuron_start", 0 0; +v0xbab31c000_0 .net/s "neuron_y", 7 0, v0xbab312a80_0; 1 drivers +o0xbaa857000 .functor BUFZ 1, c4; HiZ drive +v0xbab31c0a0_0 .net "rst", 0 0, o0xbaa857000; 0 drivers +o0xbaa859910 .functor BUFZ 1, c4; HiZ drive +v0xbab31c140_0 .net "start", 0 0, o0xbaa859910; 0 drivers +v0xbab31c1e0_0 .var "state", 3 0; +o0xbaa859970 .functor BUFZ 22, c4; HiZ drive +v0xbab31c280_0 .net "w_base", 21 0, o0xbaa859970; 0 drivers +v0xbab31c320_0 .net/s "w_bus", 255 0, L_0xbab34c780; 1 drivers +v0xbab31c3c0 .array/s "w_mem", 31 0, 7 0; +o0xbaa859fa0 .functor BUFZ 22, c4; HiZ drive +v0xbab31c460_0 .net "x_base", 21 0, o0xbaa859fa0; 0 drivers +v0xbab31c500_0 .net/s "x_bus", 255 0, L_0xbab34c6e0; 1 drivers +v0xbab31c5a0 .array/s "x_mem", 31 0, 7 0; +v0xbab31c640_0 .var/s "y", 7 0; +v0xbab31c5a0_0 .array/port v0xbab31c5a0, 0; +v0xbab31c5a0_1 .array/port v0xbab31c5a0, 1; +v0xbab31c5a0_2 .array/port v0xbab31c5a0, 2; +v0xbab31c5a0_3 .array/port v0xbab31c5a0, 3; +LS_0xbab34c6e0_0_0 .concat8 [ 8 8 8 8], v0xbab31c5a0_0, v0xbab31c5a0_1, v0xbab31c5a0_2, v0xbab31c5a0_3; +v0xbab31c5a0_4 .array/port v0xbab31c5a0, 4; +v0xbab31c5a0_5 .array/port v0xbab31c5a0, 5; +v0xbab31c5a0_6 .array/port v0xbab31c5a0, 6; +v0xbab31c5a0_7 .array/port v0xbab31c5a0, 7; +LS_0xbab34c6e0_0_4 .concat8 [ 8 8 8 8], v0xbab31c5a0_4, v0xbab31c5a0_5, v0xbab31c5a0_6, v0xbab31c5a0_7; +v0xbab31c5a0_8 .array/port v0xbab31c5a0, 8; +v0xbab31c5a0_9 .array/port v0xbab31c5a0, 9; +v0xbab31c5a0_10 .array/port v0xbab31c5a0, 10; +v0xbab31c5a0_11 .array/port v0xbab31c5a0, 11; +LS_0xbab34c6e0_0_8 .concat8 [ 8 8 8 8], v0xbab31c5a0_8, v0xbab31c5a0_9, v0xbab31c5a0_10, v0xbab31c5a0_11; +v0xbab31c5a0_12 .array/port v0xbab31c5a0, 12; +v0xbab31c5a0_13 .array/port v0xbab31c5a0, 13; +v0xbab31c5a0_14 .array/port v0xbab31c5a0, 14; +v0xbab31c5a0_15 .array/port v0xbab31c5a0, 15; +LS_0xbab34c6e0_0_12 .concat8 [ 8 8 8 8], v0xbab31c5a0_12, v0xbab31c5a0_13, v0xbab31c5a0_14, v0xbab31c5a0_15; +v0xbab31c5a0_16 .array/port v0xbab31c5a0, 16; +v0xbab31c5a0_17 .array/port v0xbab31c5a0, 17; +v0xbab31c5a0_18 .array/port v0xbab31c5a0, 18; +v0xbab31c5a0_19 .array/port v0xbab31c5a0, 19; +LS_0xbab34c6e0_0_16 .concat8 [ 8 8 8 8], v0xbab31c5a0_16, v0xbab31c5a0_17, v0xbab31c5a0_18, v0xbab31c5a0_19; +v0xbab31c5a0_20 .array/port v0xbab31c5a0, 20; +v0xbab31c5a0_21 .array/port v0xbab31c5a0, 21; +v0xbab31c5a0_22 .array/port v0xbab31c5a0, 22; +v0xbab31c5a0_23 .array/port v0xbab31c5a0, 23; +LS_0xbab34c6e0_0_20 .concat8 [ 8 8 8 8], v0xbab31c5a0_20, v0xbab31c5a0_21, v0xbab31c5a0_22, v0xbab31c5a0_23; +v0xbab31c5a0_24 .array/port v0xbab31c5a0, 24; +v0xbab31c5a0_25 .array/port v0xbab31c5a0, 25; +v0xbab31c5a0_26 .array/port v0xbab31c5a0, 26; +v0xbab31c5a0_27 .array/port v0xbab31c5a0, 27; +LS_0xbab34c6e0_0_24 .concat8 [ 8 8 8 8], v0xbab31c5a0_24, v0xbab31c5a0_25, v0xbab31c5a0_26, v0xbab31c5a0_27; +v0xbab31c5a0_28 .array/port v0xbab31c5a0, 28; +v0xbab31c5a0_29 .array/port v0xbab31c5a0, 29; +v0xbab31c5a0_30 .array/port v0xbab31c5a0, 30; +v0xbab31c5a0_31 .array/port v0xbab31c5a0, 31; +LS_0xbab34c6e0_0_28 .concat8 [ 8 8 8 8], v0xbab31c5a0_28, v0xbab31c5a0_29, v0xbab31c5a0_30, v0xbab31c5a0_31; +LS_0xbab34c6e0_1_0 .concat8 [ 32 32 32 32], LS_0xbab34c6e0_0_0, LS_0xbab34c6e0_0_4, LS_0xbab34c6e0_0_8, LS_0xbab34c6e0_0_12; +LS_0xbab34c6e0_1_4 .concat8 [ 32 32 32 32], LS_0xbab34c6e0_0_16, LS_0xbab34c6e0_0_20, LS_0xbab34c6e0_0_24, LS_0xbab34c6e0_0_28; +L_0xbab34c6e0 .concat8 [ 128 128 0 0], LS_0xbab34c6e0_1_0, LS_0xbab34c6e0_1_4; +v0xbab31c3c0_0 .array/port v0xbab31c3c0, 0; +v0xbab31c3c0_1 .array/port v0xbab31c3c0, 1; +v0xbab31c3c0_2 .array/port v0xbab31c3c0, 2; +v0xbab31c3c0_3 .array/port v0xbab31c3c0, 3; +LS_0xbab34c780_0_0 .concat8 [ 8 8 8 8], v0xbab31c3c0_0, v0xbab31c3c0_1, v0xbab31c3c0_2, v0xbab31c3c0_3; +v0xbab31c3c0_4 .array/port v0xbab31c3c0, 4; +v0xbab31c3c0_5 .array/port v0xbab31c3c0, 5; +v0xbab31c3c0_6 .array/port v0xbab31c3c0, 6; +v0xbab31c3c0_7 .array/port v0xbab31c3c0, 7; +LS_0xbab34c780_0_4 .concat8 [ 8 8 8 8], v0xbab31c3c0_4, v0xbab31c3c0_5, v0xbab31c3c0_6, v0xbab31c3c0_7; +v0xbab31c3c0_8 .array/port v0xbab31c3c0, 8; +v0xbab31c3c0_9 .array/port v0xbab31c3c0, 9; +v0xbab31c3c0_10 .array/port v0xbab31c3c0, 10; +v0xbab31c3c0_11 .array/port v0xbab31c3c0, 11; +LS_0xbab34c780_0_8 .concat8 [ 8 8 8 8], v0xbab31c3c0_8, v0xbab31c3c0_9, v0xbab31c3c0_10, v0xbab31c3c0_11; +v0xbab31c3c0_12 .array/port v0xbab31c3c0, 12; +v0xbab31c3c0_13 .array/port v0xbab31c3c0, 13; +v0xbab31c3c0_14 .array/port v0xbab31c3c0, 14; +v0xbab31c3c0_15 .array/port v0xbab31c3c0, 15; +LS_0xbab34c780_0_12 .concat8 [ 8 8 8 8], v0xbab31c3c0_12, v0xbab31c3c0_13, v0xbab31c3c0_14, v0xbab31c3c0_15; +v0xbab31c3c0_16 .array/port v0xbab31c3c0, 16; +v0xbab31c3c0_17 .array/port v0xbab31c3c0, 17; +v0xbab31c3c0_18 .array/port v0xbab31c3c0, 18; +v0xbab31c3c0_19 .array/port v0xbab31c3c0, 19; +LS_0xbab34c780_0_16 .concat8 [ 8 8 8 8], v0xbab31c3c0_16, v0xbab31c3c0_17, v0xbab31c3c0_18, v0xbab31c3c0_19; +v0xbab31c3c0_20 .array/port v0xbab31c3c0, 20; +v0xbab31c3c0_21 .array/port v0xbab31c3c0, 21; +v0xbab31c3c0_22 .array/port v0xbab31c3c0, 22; +v0xbab31c3c0_23 .array/port v0xbab31c3c0, 23; +LS_0xbab34c780_0_20 .concat8 [ 8 8 8 8], v0xbab31c3c0_20, v0xbab31c3c0_21, v0xbab31c3c0_22, v0xbab31c3c0_23; +v0xbab31c3c0_24 .array/port v0xbab31c3c0, 24; +v0xbab31c3c0_25 .array/port v0xbab31c3c0, 25; +v0xbab31c3c0_26 .array/port v0xbab31c3c0, 26; +v0xbab31c3c0_27 .array/port v0xbab31c3c0, 27; +LS_0xbab34c780_0_24 .concat8 [ 8 8 8 8], v0xbab31c3c0_24, v0xbab31c3c0_25, v0xbab31c3c0_26, v0xbab31c3c0_27; +v0xbab31c3c0_28 .array/port v0xbab31c3c0, 28; +v0xbab31c3c0_29 .array/port v0xbab31c3c0, 29; +v0xbab31c3c0_30 .array/port v0xbab31c3c0, 30; +v0xbab31c3c0_31 .array/port v0xbab31c3c0, 31; +LS_0xbab34c780_0_28 .concat8 [ 8 8 8 8], v0xbab31c3c0_28, v0xbab31c3c0_29, v0xbab31c3c0_30, v0xbab31c3c0_31; +LS_0xbab34c780_1_0 .concat8 [ 32 32 32 32], LS_0xbab34c780_0_0, LS_0xbab34c780_0_4, LS_0xbab34c780_0_8, LS_0xbab34c780_0_12; +LS_0xbab34c780_1_4 .concat8 [ 32 32 32 32], LS_0xbab34c780_0_16, LS_0xbab34c780_0_20, LS_0xbab34c780_0_24, LS_0xbab34c780_0_28; +L_0xbab34c780 .concat8 [ 128 128 0 0], LS_0xbab34c780_1_0, LS_0xbab34c780_1_4; +L_0xbab3468a0 .part v0xbab312e40_0, 0, 1; +L_0xbab34c820 .concat [ 8 8 0 0], L_0xbaa879f90, o0xbaa859850; +L_0xbab34c8c0 .concat [ 8 8 0 0], o0xbaa859850, L_0xbaa879fd8; +L_0xbab346940 .functor MUXZ 16, L_0xbab34c8c0, L_0xbab34c820, L_0xbab3468a0, C4<>; +S_0xbab2ff480 .scope generate, "GEN_BUS[0]" "GEN_BUS[0]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51440 .param/l "i" 1 9 79, +C4<00>; +v0xbab302ee0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_0; 1 drivers +v0xbab302f80_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_0; 1 drivers +S_0xbab2ff600 .scope generate, "GEN_BUS[1]" "GEN_BUS[1]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51480 .param/l "i" 1 9 79, +C4<01>; +v0xbab303020_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_1; 1 drivers +v0xbab3030c0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_1; 1 drivers +S_0xbab2ff780 .scope generate, "GEN_BUS[2]" "GEN_BUS[2]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad514c0 .param/l "i" 1 9 79, +C4<010>; +v0xbab303160_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_2; 1 drivers +v0xbab303200_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_2; 1 drivers +S_0xbab2ff900 .scope generate, "GEN_BUS[3]" "GEN_BUS[3]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51500 .param/l "i" 1 9 79, +C4<011>; +v0xbab3032a0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_3; 1 drivers +v0xbab303340_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_3; 1 drivers +S_0xbab2ffa80 .scope generate, "GEN_BUS[4]" "GEN_BUS[4]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51580 .param/l "i" 1 9 79, +C4<0100>; +v0xbab3033e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_4; 1 drivers +v0xbab303480_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_4; 1 drivers +S_0xbab2ffc00 .scope generate, "GEN_BUS[5]" "GEN_BUS[5]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad515c0 .param/l "i" 1 9 79, +C4<0101>; +v0xbab303520_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_5; 1 drivers +v0xbab3035c0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_5; 1 drivers +S_0xbab2ffd80 .scope generate, "GEN_BUS[6]" "GEN_BUS[6]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51600 .param/l "i" 1 9 79, +C4<0110>; +v0xbab303660_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_6; 1 drivers +v0xbab303700_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_6; 1 drivers +S_0xbab304000 .scope generate, "GEN_BUS[7]" "GEN_BUS[7]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51640 .param/l "i" 1 9 79, +C4<0111>; +v0xbab3037a0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_7; 1 drivers +v0xbab303840_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_7; 1 drivers +S_0xbab304180 .scope generate, "GEN_BUS[8]" "GEN_BUS[8]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51540 .param/l "i" 1 9 79, +C4<01000>; +v0xbab3038e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_8; 1 drivers +v0xbab303980_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_8; 1 drivers +S_0xbab304300 .scope generate, "GEN_BUS[9]" "GEN_BUS[9]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51680 .param/l "i" 1 9 79, +C4<01001>; +v0xbab303a20_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_9; 1 drivers +v0xbab303ac0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_9; 1 drivers +S_0xbab304480 .scope generate, "GEN_BUS[10]" "GEN_BUS[10]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad516c0 .param/l "i" 1 9 79, +C4<01010>; +v0xbab303b60_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_10; 1 drivers +v0xbab303c00_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_10; 1 drivers +S_0xbab304600 .scope generate, "GEN_BUS[11]" "GEN_BUS[11]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51700 .param/l "i" 1 9 79, +C4<01011>; +v0xbab303ca0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_11; 1 drivers +v0xbab303d40_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_11; 1 drivers +S_0xbab304780 .scope generate, "GEN_BUS[12]" "GEN_BUS[12]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51740 .param/l "i" 1 9 79, +C4<01100>; +v0xbab303de0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_12; 1 drivers +v0xbab303e80_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_12; 1 drivers +S_0xbab304900 .scope generate, "GEN_BUS[13]" "GEN_BUS[13]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51780 .param/l "i" 1 9 79, +C4<01101>; +v0xbab303f20_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_13; 1 drivers +v0xbab308000_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_13; 1 drivers +S_0xbab304a80 .scope generate, "GEN_BUS[14]" "GEN_BUS[14]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad517c0 .param/l "i" 1 9 79, +C4<01110>; +v0xbab3080a0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_14; 1 drivers +v0xbab308140_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_14; 1 drivers +S_0xbab304c00 .scope generate, "GEN_BUS[15]" "GEN_BUS[15]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51800 .param/l "i" 1 9 79, +C4<01111>; +v0xbab3081e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_15; 1 drivers +v0xbab308280_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_15; 1 drivers +S_0xbab304d80 .scope generate, "GEN_BUS[16]" "GEN_BUS[16]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51840 .param/l "i" 1 9 79, +C4<010000>; +v0xbab308320_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_16; 1 drivers +v0xbab3083c0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_16; 1 drivers +S_0xbab304f00 .scope generate, "GEN_BUS[17]" "GEN_BUS[17]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51880 .param/l "i" 1 9 79, +C4<010001>; +v0xbab308460_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_17; 1 drivers +v0xbab308500_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_17; 1 drivers +S_0xbab305080 .scope generate, "GEN_BUS[18]" "GEN_BUS[18]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad518c0 .param/l "i" 1 9 79, +C4<010010>; +v0xbab3085a0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_18; 1 drivers +v0xbab308640_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_18; 1 drivers +S_0xbab305200 .scope generate, "GEN_BUS[19]" "GEN_BUS[19]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51900 .param/l "i" 1 9 79, +C4<010011>; +v0xbab3086e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_19; 1 drivers +v0xbab308780_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_19; 1 drivers +S_0xbab305380 .scope generate, "GEN_BUS[20]" "GEN_BUS[20]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51940 .param/l "i" 1 9 79, +C4<010100>; +v0xbab308820_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_20; 1 drivers +v0xbab3088c0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_20; 1 drivers +S_0xbab305500 .scope generate, "GEN_BUS[21]" "GEN_BUS[21]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51980 .param/l "i" 1 9 79, +C4<010101>; +v0xbab308960_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_21; 1 drivers +v0xbab308a00_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_21; 1 drivers +S_0xbab305680 .scope generate, "GEN_BUS[22]" "GEN_BUS[22]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad519c0 .param/l "i" 1 9 79, +C4<010110>; +v0xbab308aa0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_22; 1 drivers +v0xbab308b40_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_22; 1 drivers +S_0xbab305800 .scope generate, "GEN_BUS[23]" "GEN_BUS[23]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51a00 .param/l "i" 1 9 79, +C4<010111>; +v0xbab308be0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_23; 1 drivers +v0xbab308c80_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_23; 1 drivers +S_0xbab305980 .scope generate, "GEN_BUS[24]" "GEN_BUS[24]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51a40 .param/l "i" 1 9 79, +C4<011000>; +v0xbab308d20_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_24; 1 drivers +v0xbab308dc0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_24; 1 drivers +S_0xbab305b00 .scope generate, "GEN_BUS[25]" "GEN_BUS[25]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51a80 .param/l "i" 1 9 79, +C4<011001>; +v0xbab308e60_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_25; 1 drivers +v0xbab308f00_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_25; 1 drivers +S_0xbab305c80 .scope generate, "GEN_BUS[26]" "GEN_BUS[26]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51ac0 .param/l "i" 1 9 79, +C4<011010>; +v0xbab308fa0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_26; 1 drivers +v0xbab309040_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_26; 1 drivers +S_0xbab305e00 .scope generate, "GEN_BUS[27]" "GEN_BUS[27]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51b00 .param/l "i" 1 9 79, +C4<011011>; +v0xbab3090e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_27; 1 drivers +v0xbab309180_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_27; 1 drivers +S_0xbab305f80 .scope generate, "GEN_BUS[28]" "GEN_BUS[28]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51b40 .param/l "i" 1 9 79, +C4<011100>; +v0xbab309220_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_28; 1 drivers +v0xbab3092c0_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_28; 1 drivers +S_0xbab306100 .scope generate, "GEN_BUS[29]" "GEN_BUS[29]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51b80 .param/l "i" 1 9 79, +C4<011101>; +v0xbab309360_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_29; 1 drivers +v0xbab309400_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_29; 1 drivers +S_0xbab306280 .scope generate, "GEN_BUS[30]" "GEN_BUS[30]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51bc0 .param/l "i" 1 9 79, +C4<011110>; +v0xbab3094a0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_30; 1 drivers +v0xbab309540_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_30; 1 drivers +S_0xbab306400 .scope generate, "GEN_BUS[31]" "GEN_BUS[31]" 9 79, 9 79 0, S_0x102e25ce0; + .timescale -9 -12; +P_0xbaad51c00 .param/l "i" 1 9 79, +C4<011111>; +v0xbab3095e0_0 .net *"_ivl_2", 7 0, v0xbab31c5a0_31; 1 drivers +v0xbab309680_0 .net *"_ivl_5", 7 0, v0xbab31c3c0_31; 1 drivers +S_0xbab306580 .scope module, "u_mem" "int8_memory_access" 9 142, 10 1 0, S_0x102e25ce0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "req"; + .port_info 3 /INPUT 1 "wr"; + .port_info 4 /INPUT 22 "addr"; + .port_info 5 /INPUT 8 "wdata"; + .port_info 6 /OUTPUT 8 "rdata"; + .port_info 7 /OUTPUT 1 "ready"; + .port_info 8 /OUTPUT 1 "mem_req"; + .port_info 9 /OUTPUT 1 "mem_wr"; + .port_info 10 /OUTPUT 22 "mem_addr"; + .port_info 11 /OUTPUT 16 "mem_wdata"; + .port_info 12 /OUTPUT 1 "mem_lb_n"; + .port_info 13 /OUTPUT 1 "mem_ub_n"; + .port_info 14 /INPUT 16 "mem_rdata"; + .port_info 15 /INPUT 1 "mem_ready"; +P_0xbaad4edc0 .param/l "ADDR_WIDTH" 0 10 2, +C4<00000000000000000000000000010110>; +P_0xbaad4ee00 .param/l "STATE_IDLE" 1 10 40, C4<00>; +P_0xbaad4ee40 .param/l "STATE_WAIT" 1 10 41, C4<01>; +v0xbab309720_0 .net "addr", 21 0, v0xbab312e40_0; 1 drivers +v0xbab3097c0_0 .var "addr_reg", 21 0; +v0xbab309860_0 .net "clk", 0 0, o0xbaa856dc0; alias, 0 drivers +v0xbab309900_0 .var "mem_addr", 21 0; +v0xbab3099a0_0 .var "mem_lb_n", 0 0; +v0xbab309a40_0 .net "mem_rdata", 15 0, L_0xbab346940; alias, 1 drivers +v0xbab309ae0_0 .net "mem_ready", 0 0, o0xbaa856e80; alias, 0 drivers +v0xbab309b80_0 .var "mem_req", 0 0; +v0xbab309c20_0 .var "mem_ub_n", 0 0; +v0xbab309cc0_0 .var "mem_wdata", 15 0; +v0xbab309d60_0 .var "mem_wr", 0 0; +v0xbab309e00_0 .var/s "rdata", 7 0; +v0xbab309ea0_0 .var "ready", 0 0; +v0xbab309f40_0 .net "req", 0 0, v0xbab313480_0; 1 drivers +v0xbab309fe0_0 .net "rst", 0 0, o0xbaa857000; alias, 0 drivers +v0xbab30a080_0 .var "state", 1 0; +v0xbab30a120_0 .net/s "wdata", 7 0, v0xbab313520_0; 1 drivers +v0xbab30a1c0_0 .net "wr", 0 0, v0xbab3135c0_0; 1 drivers +E_0xbaad3a1c0 .event posedge, v0xbab309860_0; +S_0xbab306700 .scope module, "u_neuron" "neuron_parallel" 9 203, 4 1 0, S_0x102e25ce0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bc900 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>; +P_0xbab2bc940 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>; +P_0xbab2bc980 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000100>; +P_0xbab2bc9c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000010>; +P_0xbab2bca00 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000100000>; +P_0xbab2bca40 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab311860_0 .net *"_ivl_0", 31 0, L_0xbab34c960; 1 drivers +v0xbab311900_0 .net *"_ivl_11", 31 0, L_0xbaad59900; 1 drivers +v0xbab3119a0_0 .net *"_ivl_14", 31 0, L_0xbab34ca00; 1 drivers +L_0xbaa87a0f8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab311a40_0 .net *"_ivl_17", 29 0, L_0xbaa87a0f8; 1 drivers +L_0xbaa87a140 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab311ae0_0 .net/2u *"_ivl_18", 31 0, L_0xbaa87a140; 1 drivers +v0xbab311b80_0 .net *"_ivl_21", 31 0, L_0xbaad599a0; 1 drivers +L_0xbaa87a188 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab311c20_0 .net/2u *"_ivl_22", 31 0, L_0xbaa87a188; 1 drivers +v0xbab311cc0_0 .net *"_ivl_25", 31 0, L_0xbaad59a40; 1 drivers +v0xbab311d60_0 .net *"_ivl_29", 0 0, L_0xbab347a20; 1 drivers +L_0xbaa87a020 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab311e00_0 .net *"_ivl_3", 29 0, L_0xbaa87a020; 1 drivers +v0xbab311ea0_0 .net *"_ivl_31", 23 0, L_0xbaad5a580; 1 drivers +L_0xbaa87a068 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab311f40_0 .net/2u *"_ivl_4", 31 0, L_0xbaa87a068; 1 drivers +v0xbab311fe0_0 .net *"_ivl_7", 31 0, L_0xbaad59860; 1 drivers +L_0xbaa87a0b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab312080_0 .net/2u *"_ivl_8", 31 0, L_0xbaa87a0b0; 1 drivers +v0xbab312120_0 .var/s "acc", 31 0; +v0xbab3121c0_0 .net/s "acc_next", 31 0, L_0xbab34e300; 1 drivers +v0xbab312260_0 .net/s "bias", 7 0, v0xbab313700_0; 1 drivers +v0xbab312300_0 .net/s "bias_ext", 31 0, L_0xbab34e3a0; 1 drivers +v0xbab3123a0_0 .var "busy", 0 0; +v0xbab312440_0 .net "clk", 0 0, o0xbaa856dc0; alias, 0 drivers +v0xbab3124e0_0 .var "done", 0 0; +v0xbab312580_0 .net/s "final_acc", 31 0, L_0xbab34e440; 1 drivers +v0xbab312620_0 .var "group_index", 1 0; +v0xbab3126c0_0 .net "rst", 0 0, o0xbaa857000; alias, 0 drivers +v0xbab312760_0 .net "start", 0 0, v0xbab313f20_0; 1 drivers +v0xbab312800_0 .net/s "w_bus", 255 0, L_0xbab34c780; alias, 1 drivers +v0xbab3128a0_0 .net/s "w_group", 63 0, L_0xbab346a80; 1 drivers +v0xbab312940_0 .net/s "x_bus", 255 0, L_0xbab34c6e0; alias, 1 drivers +v0xbab3129e0_0 .net/s "x_group", 63 0, L_0xbab3469e0; 1 drivers +v0xbab312a80_0 .var/s "y", 7 0; +L_0xbab34c960 .concat [ 2 30 0 0], v0xbab312620_0, L_0xbaa87a020; +L_0xbaad59860 .arith/mult 32, L_0xbab34c960, L_0xbaa87a068; +L_0xbaad59900 .arith/mult 32, L_0xbaad59860, L_0xbaa87a0b0; +L_0xbab3469e0 .part/v L_0xbab34c6e0, L_0xbaad59900, 64; +L_0xbab34ca00 .concat [ 2 30 0 0], v0xbab312620_0, L_0xbaa87a0f8; +L_0xbaad599a0 .arith/mult 32, L_0xbab34ca00, L_0xbaa87a140; +L_0xbaad59a40 .arith/mult 32, L_0xbaad599a0, L_0xbaa87a188; +L_0xbab346a80 .part/v L_0xbab34c780, L_0xbaad59a40, 64; +L_0xbab347a20 .part v0xbab313700_0, 7, 1; +L_0xbaad5a580 .repeat 24, 24, L_0xbab347a20; +L_0xbab34e3a0 .concat [ 8 24 0 0], v0xbab313700_0, L_0xbaad5a580; +L_0xbab34e440 .arith/sum 32, L_0xbab34e300, L_0xbab34e3a0; +S_0xbab306880 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab306700; + .timescale 0 0; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbab295b00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>; +P_0xbab295b40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>; +P_0xbab295b80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab295bc0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab3114a0_0 .net/s "acc_in", 31 0, v0xbab312120_0; 1 drivers +v0xbab311540_0 .net/s "acc_out", 31 0, L_0xbab34e300; alias, 1 drivers +v0xbab3115e0 .array "products", 7 0; +v0xbab3115e0_0 .net/s v0xbab3115e0 0, 31 0, L_0xbab34cc80; 1 drivers +v0xbab3115e0_1 .net/s v0xbab3115e0 1, 31 0, L_0xbab34cf00; 1 drivers +v0xbab3115e0_2 .net/s v0xbab3115e0 2, 31 0, L_0xbab34d180; 1 drivers +v0xbab3115e0_3 .net/s v0xbab3115e0 3, 31 0, L_0xbab34d400; 1 drivers +v0xbab3115e0_4 .net/s v0xbab3115e0 4, 31 0, L_0xbab34d680; 1 drivers +v0xbab3115e0_5 .net/s v0xbab3115e0 5, 31 0, L_0xbab34d900; 1 drivers +v0xbab3115e0_6 .net/s v0xbab3115e0 6, 31 0, L_0xbab34db80; 1 drivers +v0xbab3115e0_7 .net/s v0xbab3115e0 7, 31 0, L_0xbab34de00; 1 drivers +v0xbab311680 .array "tree", 31 0; +v0xbab311680_0 .net/s v0xbab311680 0, 31 0, L_0xbab06bd40; 1 drivers +v0xbab311680_1 .net/s v0xbab311680 1, 31 0, L_0xbab06bdb0; 1 drivers +v0xbab311680_2 .net/s v0xbab311680 2, 31 0, L_0xbab06be20; 1 drivers +v0xbab311680_3 .net/s v0xbab311680 3, 31 0, L_0xbab06be90; 1 drivers +v0xbab311680_4 .net/s v0xbab311680 4, 31 0, L_0xbab06bf00; 1 drivers +v0xbab311680_5 .net/s v0xbab311680 5, 31 0, L_0xbab06bf70; 1 drivers +v0xbab311680_6 .net/s v0xbab311680 6, 31 0, L_0xbab35c000; 1 drivers +v0xbab311680_7 .net/s v0xbab311680 7, 31 0, L_0xbab360000; 1 drivers +v0xbab311680_8 .net/s v0xbab311680 8, 31 0, L_0xbab34dea0; 1 drivers +v0xbab311680_9 .net/s v0xbab311680 9, 31 0, L_0xbab34df40; 1 drivers +v0xbab311680_10 .net/s v0xbab311680 10, 31 0, L_0xbab34dfe0; 1 drivers +v0xbab311680_11 .net/s v0xbab311680 11, 31 0, L_0xbab34e080; 1 drivers +o0xbaa858b60 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_12 .net/s v0xbab311680 12, 31 0, o0xbaa858b60; 0 drivers +o0xbaa858b90 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_13 .net/s v0xbab311680 13, 31 0, o0xbaa858b90; 0 drivers +o0xbaa858bc0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_14 .net/s v0xbab311680 14, 31 0, o0xbaa858bc0; 0 drivers +o0xbaa858bf0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_15 .net/s v0xbab311680 15, 31 0, o0xbaa858bf0; 0 drivers +v0xbab311680_16 .net/s v0xbab311680 16, 31 0, L_0xbab34e120; 1 drivers +v0xbab311680_17 .net/s v0xbab311680 17, 31 0, L_0xbab34e1c0; 1 drivers +o0xbaa858c80 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_18 .net/s v0xbab311680 18, 31 0, o0xbaa858c80; 0 drivers +o0xbaa858cb0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_19 .net/s v0xbab311680 19, 31 0, o0xbaa858cb0; 0 drivers +o0xbaa858ce0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_20 .net/s v0xbab311680 20, 31 0, o0xbaa858ce0; 0 drivers +o0xbaa858d10 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_21 .net/s v0xbab311680 21, 31 0, o0xbaa858d10; 0 drivers +o0xbaa858d40 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_22 .net/s v0xbab311680 22, 31 0, o0xbaa858d40; 0 drivers +o0xbaa858d70 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_23 .net/s v0xbab311680 23, 31 0, o0xbaa858d70; 0 drivers +v0xbab311680_24 .net/s v0xbab311680 24, 31 0, L_0xbab34e260; 1 drivers +o0xbaa858dd0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_25 .net/s v0xbab311680 25, 31 0, o0xbaa858dd0; 0 drivers +o0xbaa858e00 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_26 .net/s v0xbab311680 26, 31 0, o0xbaa858e00; 0 drivers +o0xbaa858e30 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_27 .net/s v0xbab311680 27, 31 0, o0xbaa858e30; 0 drivers +o0xbaa858e60 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_28 .net/s v0xbab311680 28, 31 0, o0xbaa858e60; 0 drivers +o0xbaa858e90 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_29 .net/s v0xbab311680 29, 31 0, o0xbaa858e90; 0 drivers +o0xbaa858ec0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_30 .net/s v0xbab311680 30, 31 0, o0xbaa858ec0; 0 drivers +o0xbaa858ef0 .functor BUFZ 32, c4; HiZ drive +v0xbab311680_31 .net/s v0xbab311680 31, 31 0, o0xbaa858ef0; 0 drivers +v0xbab311720_0 .net/s "w_bus", 63 0, L_0xbab346a80; alias, 1 drivers +v0xbab3117c0_0 .net/s "x_bus", 63 0, L_0xbab3469e0; alias, 1 drivers +L_0xbab346bc0 .part L_0xbab3469e0, 0, 8; +L_0xbab346c60 .part L_0xbab346a80, 0, 8; +L_0xbab346da0 .part L_0xbab3469e0, 8, 8; +L_0xbab346e40 .part L_0xbab346a80, 8, 8; +L_0xbab346f80 .part L_0xbab3469e0, 16, 8; +L_0xbab347020 .part L_0xbab346a80, 16, 8; +L_0xbab347160 .part L_0xbab3469e0, 24, 8; +L_0xbab347200 .part L_0xbab346a80, 24, 8; +L_0xbab347340 .part L_0xbab3469e0, 32, 8; +L_0xbab3473e0 .part L_0xbab346a80, 32, 8; +L_0xbab347520 .part L_0xbab3469e0, 40, 8; +L_0xbab3475c0 .part L_0xbab346a80, 40, 8; +L_0xbab347700 .part L_0xbab3469e0, 48, 8; +L_0xbab3477a0 .part L_0xbab346a80, 48, 8; +L_0xbab3478e0 .part L_0xbab3469e0, 56, 8; +L_0xbab347980 .part L_0xbab346a80, 56, 8; +L_0xbab34e300 .arith/sum 32, v0xbab312120_0, L_0xbab34e260; +S_0xbab306a00 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51c40 .param/l "i" 1 5 20, +C4<00>; +S_0xbab306b80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab306a00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4ee80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4eec0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4ef00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab30a260_0 .net/s *"_ivl_0", 15 0, L_0xbab34caa0; 1 drivers +v0xbab30a300_0 .net/s *"_ivl_2", 15 0, L_0xbab34cb40; 1 drivers +v0xbab30a3a0_0 .net *"_ivl_7", 0 0, L_0xbab346b20; 1 drivers +v0xbab30a440_0 .net *"_ivl_9", 15 0, L_0xbaad59b80; 1 drivers +L_0xbaa87a1d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab30a4e0_0 .net/s "acc_in", 31 0, L_0xbaa87a1d0; 1 drivers +v0xbab30a580_0 .net/s "acc_out", 31 0, L_0xbab34cc80; alias, 1 drivers +v0xbab30a620_0 .net/s "product", 15 0, L_0xbaad59ae0; 1 drivers +v0xbab30a6c0_0 .net/s "product_ext", 31 0, L_0xbab34cbe0; 1 drivers +v0xbab30a760_0 .net/s "w", 7 0, L_0xbab346c60; 1 drivers +v0xbab30a800_0 .net/s "x", 7 0, L_0xbab346bc0; 1 drivers +L_0xbab34caa0 .extend/s 16, L_0xbab346bc0; +L_0xbab34cb40 .extend/s 16, L_0xbab346c60; +L_0xbaad59ae0 .arith/mult 16, L_0xbab34caa0, L_0xbab34cb40; +L_0xbab346b20 .part L_0xbaad59ae0, 15, 1; +L_0xbaad59b80 .repeat 16, 16, L_0xbab346b20; +L_0xbab34cbe0 .concat [ 16 16 0 0], L_0xbaad59ae0, L_0xbaad59b80; +L_0xbab34cc80 .arith/sum 32, L_0xbaa87a1d0, L_0xbab34cbe0; +S_0xbab306d00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51c80 .param/l "i" 1 5 20, +C4<01>; +S_0xbab306e80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab306d00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4ef40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4ef80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4efc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab30a8a0_0 .net/s *"_ivl_0", 15 0, L_0xbab34cd20; 1 drivers +v0xbab30a940_0 .net/s *"_ivl_2", 15 0, L_0xbab34cdc0; 1 drivers +v0xbab30a9e0_0 .net *"_ivl_7", 0 0, L_0xbab346d00; 1 drivers +v0xbab30aa80_0 .net *"_ivl_9", 15 0, L_0xbaad59cc0; 1 drivers +L_0xbaa87a218 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab30ab20_0 .net/s "acc_in", 31 0, L_0xbaa87a218; 1 drivers +v0xbab30abc0_0 .net/s "acc_out", 31 0, L_0xbab34cf00; alias, 1 drivers +v0xbab30ac60_0 .net/s "product", 15 0, L_0xbaad59c20; 1 drivers +v0xbab30ad00_0 .net/s "product_ext", 31 0, L_0xbab34ce60; 1 drivers +v0xbab30ada0_0 .net/s "w", 7 0, L_0xbab346e40; 1 drivers +v0xbab30ae40_0 .net/s "x", 7 0, L_0xbab346da0; 1 drivers +L_0xbab34cd20 .extend/s 16, L_0xbab346da0; +L_0xbab34cdc0 .extend/s 16, L_0xbab346e40; +L_0xbaad59c20 .arith/mult 16, L_0xbab34cd20, L_0xbab34cdc0; +L_0xbab346d00 .part L_0xbaad59c20, 15, 1; +L_0xbaad59cc0 .repeat 16, 16, L_0xbab346d00; +L_0xbab34ce60 .concat [ 16 16 0 0], L_0xbaad59c20, L_0xbaad59cc0; +L_0xbab34cf00 .arith/sum 32, L_0xbaa87a218, L_0xbab34ce60; +S_0xbab307000 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51cc0 .param/l "i" 1 5 20, +C4<010>; +S_0xbab307180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab307000; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab30aee0_0 .net/s *"_ivl_0", 15 0, L_0xbab34cfa0; 1 drivers +v0xbab30af80_0 .net/s *"_ivl_2", 15 0, L_0xbab34d040; 1 drivers +v0xbab30b020_0 .net *"_ivl_7", 0 0, L_0xbab346ee0; 1 drivers +v0xbab30b0c0_0 .net *"_ivl_9", 15 0, L_0xbaad59e00; 1 drivers +L_0xbaa87a260 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab30b160_0 .net/s "acc_in", 31 0, L_0xbaa87a260; 1 drivers +v0xbab30b200_0 .net/s "acc_out", 31 0, L_0xbab34d180; alias, 1 drivers +v0xbab30b2a0_0 .net/s "product", 15 0, L_0xbaad59d60; 1 drivers +v0xbab30b340_0 .net/s "product_ext", 31 0, L_0xbab34d0e0; 1 drivers +v0xbab30b3e0_0 .net/s "w", 7 0, L_0xbab347020; 1 drivers +v0xbab30b480_0 .net/s "x", 7 0, L_0xbab346f80; 1 drivers +L_0xbab34cfa0 .extend/s 16, L_0xbab346f80; +L_0xbab34d040 .extend/s 16, L_0xbab347020; +L_0xbaad59d60 .arith/mult 16, L_0xbab34cfa0, L_0xbab34d040; +L_0xbab346ee0 .part L_0xbaad59d60, 15, 1; +L_0xbaad59e00 .repeat 16, 16, L_0xbab346ee0; +L_0xbab34d0e0 .concat [ 16 16 0 0], L_0xbaad59d60, L_0xbaad59e00; +L_0xbab34d180 .arith/sum 32, L_0xbaa87a260, L_0xbab34d0e0; +S_0xbab307300 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51d00 .param/l "i" 1 5 20, +C4<011>; +S_0xbab307480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab307300; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f0c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab30b520_0 .net/s *"_ivl_0", 15 0, L_0xbab34d220; 1 drivers +v0xbab30b5c0_0 .net/s *"_ivl_2", 15 0, L_0xbab34d2c0; 1 drivers +v0xbab30b660_0 .net *"_ivl_7", 0 0, L_0xbab3470c0; 1 drivers +v0xbab30b700_0 .net *"_ivl_9", 15 0, L_0xbaad59f40; 1 drivers +L_0xbaa87a2a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab30b7a0_0 .net/s "acc_in", 31 0, L_0xbaa87a2a8; 1 drivers +v0xbab30b840_0 .net/s "acc_out", 31 0, L_0xbab34d400; alias, 1 drivers +v0xbab30b8e0_0 .net/s "product", 15 0, L_0xbaad59ea0; 1 drivers +v0xbab30b980_0 .net/s "product_ext", 31 0, L_0xbab34d360; 1 drivers +v0xbab30ba20_0 .net/s "w", 7 0, L_0xbab347200; 1 drivers +v0xbab30bac0_0 .net/s "x", 7 0, L_0xbab347160; 1 drivers +L_0xbab34d220 .extend/s 16, L_0xbab347160; +L_0xbab34d2c0 .extend/s 16, L_0xbab347200; +L_0xbaad59ea0 .arith/mult 16, L_0xbab34d220, L_0xbab34d2c0; +L_0xbab3470c0 .part L_0xbaad59ea0, 15, 1; +L_0xbaad59f40 .repeat 16, 16, L_0xbab3470c0; +L_0xbab34d360 .concat [ 16 16 0 0], L_0xbaad59ea0, L_0xbaad59f40; +L_0xbab34d400 .arith/sum 32, L_0xbaa87a2a8, L_0xbab34d360; +S_0xbab307600 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51d80 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab307780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab307600; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f1c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab30bb60_0 .net/s *"_ivl_0", 15 0, L_0xbab34d4a0; 1 drivers +v0xbab30bc00_0 .net/s *"_ivl_2", 15 0, L_0xbab34d540; 1 drivers +v0xbab30bca0_0 .net *"_ivl_7", 0 0, L_0xbab3472a0; 1 drivers +v0xbab30bd40_0 .net *"_ivl_9", 15 0, L_0xbaad5a080; 1 drivers +L_0xbaa87a2f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab30bde0_0 .net/s "acc_in", 31 0, L_0xbaa87a2f0; 1 drivers +v0xbab30be80_0 .net/s "acc_out", 31 0, L_0xbab34d680; alias, 1 drivers +v0xbab30bf20_0 .net/s "product", 15 0, L_0xbaad59fe0; 1 drivers +v0xbab310000_0 .net/s "product_ext", 31 0, L_0xbab34d5e0; 1 drivers +v0xbab3100a0_0 .net/s "w", 7 0, L_0xbab3473e0; 1 drivers +v0xbab310140_0 .net/s "x", 7 0, L_0xbab347340; 1 drivers +L_0xbab34d4a0 .extend/s 16, L_0xbab347340; +L_0xbab34d540 .extend/s 16, L_0xbab3473e0; +L_0xbaad59fe0 .arith/mult 16, L_0xbab34d4a0, L_0xbab34d540; +L_0xbab3472a0 .part L_0xbaad59fe0, 15, 1; +L_0xbaad5a080 .repeat 16, 16, L_0xbab3472a0; +L_0xbab34d5e0 .concat [ 16 16 0 0], L_0xbaad59fe0, L_0xbaad5a080; +L_0xbab34d680 .arith/sum 32, L_0xbaa87a2f0, L_0xbab34d5e0; +S_0xbab307900 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51dc0 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab307a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab307900; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f2c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab3101e0_0 .net/s *"_ivl_0", 15 0, L_0xbab34d720; 1 drivers +v0xbab310280_0 .net/s *"_ivl_2", 15 0, L_0xbab34d7c0; 1 drivers +v0xbab310320_0 .net *"_ivl_7", 0 0, L_0xbab347480; 1 drivers +v0xbab3103c0_0 .net *"_ivl_9", 15 0, L_0xbaad5a1c0; 1 drivers +L_0xbaa87a338 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab310460_0 .net/s "acc_in", 31 0, L_0xbaa87a338; 1 drivers +v0xbab310500_0 .net/s "acc_out", 31 0, L_0xbab34d900; alias, 1 drivers +v0xbab3105a0_0 .net/s "product", 15 0, L_0xbaad5a120; 1 drivers +v0xbab310640_0 .net/s "product_ext", 31 0, L_0xbab34d860; 1 drivers +v0xbab3106e0_0 .net/s "w", 7 0, L_0xbab3475c0; 1 drivers +v0xbab310780_0 .net/s "x", 7 0, L_0xbab347520; 1 drivers +L_0xbab34d720 .extend/s 16, L_0xbab347520; +L_0xbab34d7c0 .extend/s 16, L_0xbab3475c0; +L_0xbaad5a120 .arith/mult 16, L_0xbab34d720, L_0xbab34d7c0; +L_0xbab347480 .part L_0xbaad5a120, 15, 1; +L_0xbaad5a1c0 .repeat 16, 16, L_0xbab347480; +L_0xbab34d860 .concat [ 16 16 0 0], L_0xbaad5a120, L_0xbaad5a1c0; +L_0xbab34d900 .arith/sum 32, L_0xbaa87a338, L_0xbab34d860; +S_0xbab307c00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51e00 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab307d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab307c00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab310820_0 .net/s *"_ivl_0", 15 0, L_0xbab34d9a0; 1 drivers +v0xbab3108c0_0 .net/s *"_ivl_2", 15 0, L_0xbab34da40; 1 drivers +v0xbab310960_0 .net *"_ivl_7", 0 0, L_0xbab347660; 1 drivers +v0xbab310a00_0 .net *"_ivl_9", 15 0, L_0xbaad5a300; 1 drivers +L_0xbaa87a380 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab310aa0_0 .net/s "acc_in", 31 0, L_0xbaa87a380; 1 drivers +v0xbab310b40_0 .net/s "acc_out", 31 0, L_0xbab34db80; alias, 1 drivers +v0xbab310be0_0 .net/s "product", 15 0, L_0xbaad5a260; 1 drivers +v0xbab310c80_0 .net/s "product_ext", 31 0, L_0xbab34dae0; 1 drivers +v0xbab310d20_0 .net/s "w", 7 0, L_0xbab3477a0; 1 drivers +v0xbab310dc0_0 .net/s "x", 7 0, L_0xbab347700; 1 drivers +L_0xbab34d9a0 .extend/s 16, L_0xbab347700; +L_0xbab34da40 .extend/s 16, L_0xbab3477a0; +L_0xbaad5a260 .arith/mult 16, L_0xbab34d9a0, L_0xbab34da40; +L_0xbab347660 .part L_0xbaad5a260, 15, 1; +L_0xbaad5a300 .repeat 16, 16, L_0xbab347660; +L_0xbab34dae0 .concat [ 16 16 0 0], L_0xbaad5a260, L_0xbaad5a300; +L_0xbab34db80 .arith/sum 32, L_0xbaa87a380, L_0xbab34dae0; +S_0xbab318000 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51e40 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab318180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab318000; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f3c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab310e60_0 .net/s *"_ivl_0", 15 0, L_0xbab34dc20; 1 drivers +v0xbab310f00_0 .net/s *"_ivl_2", 15 0, L_0xbab34dcc0; 1 drivers +v0xbab310fa0_0 .net *"_ivl_7", 0 0, L_0xbab347840; 1 drivers +v0xbab311040_0 .net *"_ivl_9", 15 0, L_0xbaad5a440; 1 drivers +L_0xbaa87a3c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab3110e0_0 .net/s "acc_in", 31 0, L_0xbaa87a3c8; 1 drivers +v0xbab311180_0 .net/s "acc_out", 31 0, L_0xbab34de00; alias, 1 drivers +v0xbab311220_0 .net/s "product", 15 0, L_0xbaad5a3a0; 1 drivers +v0xbab3112c0_0 .net/s "product_ext", 31 0, L_0xbab34dd60; 1 drivers +v0xbab311360_0 .net/s "w", 7 0, L_0xbab347980; 1 drivers +v0xbab311400_0 .net/s "x", 7 0, L_0xbab3478e0; 1 drivers +L_0xbab34dc20 .extend/s 16, L_0xbab3478e0; +L_0xbab34dcc0 .extend/s 16, L_0xbab347980; +L_0xbaad5a3a0 .arith/mult 16, L_0xbab34dc20, L_0xbab34dcc0; +L_0xbab347840 .part L_0xbaad5a3a0, 15, 1; +L_0xbaad5a440 .repeat 16, 16, L_0xbab347840; +L_0xbab34dd60 .concat [ 16 16 0 0], L_0xbaad5a3a0, L_0xbaad5a440; +L_0xbab34de00 .arith/sum 32, L_0xbaa87a3c8, L_0xbab34dd60; +S_0xbab318300 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51d40 .param/l "i" 1 5 80, +C4<00>; +L_0xbab06bd40 .functor BUFZ 32, L_0xbab34cc80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318480 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51e80 .param/l "i" 1 5 80, +C4<01>; +L_0xbab06bdb0 .functor BUFZ 32, L_0xbab34cf00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318600 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51ec0 .param/l "i" 1 5 80, +C4<010>; +L_0xbab06be20 .functor BUFZ 32, L_0xbab34d180, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318780 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51f00 .param/l "i" 1 5 80, +C4<011>; +L_0xbab06be90 .functor BUFZ 32, L_0xbab34d400, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318900 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51f40 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab06bf00 .functor BUFZ 32, L_0xbab34d680, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318a80 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51f80 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab06bf70 .functor BUFZ 32, L_0xbab34d900, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318c00 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad51fc0 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab35c000 .functor BUFZ 32, L_0xbab34db80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318d80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad52000 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab360000 .functor BUFZ 32, L_0xbab34de00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab318f00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad52040 .param/l "level" 1 5 92, +C4<00>; +S_0xbab319080 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab318f00; + .timescale 0 0; +P_0xbaad52080 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34dea0 .arith/sum 32, L_0xbab06bd40, L_0xbab06bdb0; +S_0xbab319200 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab318f00; + .timescale 0 0; +P_0xbaad520c0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab34df40 .arith/sum 32, L_0xbab06be20, L_0xbab06be90; +S_0xbab319380 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab318f00; + .timescale 0 0; +P_0xbaad52100 .param/l "node" 1 5 94, +C4<010>; +L_0xbab34dfe0 .arith/sum 32, L_0xbab06bf00, L_0xbab06bf70; +S_0xbab319500 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab318f00; + .timescale 0 0; +P_0xbaad52140 .param/l "node" 1 5 94, +C4<011>; +L_0xbab34e080 .arith/sum 32, L_0xbab35c000, L_0xbab360000; +S_0xbab319680 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad52180 .param/l "level" 1 5 92, +C4<01>; +S_0xbab319800 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab319680; + .timescale 0 0; +P_0xbaad521c0 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34e120 .arith/sum 32, L_0xbab34dea0, L_0xbab34df40; +S_0xbab319980 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab319680; + .timescale 0 0; +P_0xbaad52200 .param/l "node" 1 5 94, +C4<01>; +L_0xbab34e1c0 .arith/sum 32, L_0xbab34dfe0, L_0xbab34e080; +S_0xbab319b00 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab306880; + .timescale 0 0; +P_0xbaad52240 .param/l "level" 1 5 92, +C4<010>; +S_0xbab319c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab319b00; + .timescale 0 0; +P_0xbaad52280 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34e260 .arith/sum 32, L_0xbab34e120, L_0xbab34e1c0; +S_0x102e23ae0 .scope module, "psram_controller" "psram_controller" 11 1; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "mem_req"; + .port_info 3 /INPUT 1 "mem_wr"; + .port_info 4 /INPUT 22 "mem_addr"; + .port_info 5 /INPUT 16 "mem_wdata"; + .port_info 6 /INPUT 1 "mem_lb_n"; + .port_info 7 /INPUT 1 "mem_ub_n"; + .port_info 8 /OUTPUT 16 "mem_rdata"; + .port_info 9 /OUTPUT 1 "mem_ready"; + .port_info 10 /OUTPUT 22 "psram_a"; + .port_info 11 /INOUT 16 "psram_dq"; + .port_info 12 /OUTPUT 1 "psram_ce_n"; + .port_info 13 /OUTPUT 1 "psram_oe_n"; + .port_info 14 /OUTPUT 1 "psram_we_n"; + .port_info 15 /OUTPUT 1 "psram_lb_n"; + .port_info 16 /OUTPUT 1 "psram_ub_n"; + .port_info 17 /OUTPUT 1 "psram_zz_n"; +P_0x102e36380 .param/l "ACCESS_CYCLES" 1 11 43, +C4<00000000000000000000000000000110>; +P_0x102e363c0 .param/l "ADDR_WIDTH" 0 11 2, +C4<00000000000000000000000000010110>; +P_0x102e36400 .param/l "CLK_FREQ_MHZ" 0 11 4, +C4<00000000000000000000000001010000>; +P_0x102e36440 .param/l "COUNTER_WIDTH" 1 11 49, +C4<00000000000000000000000000001110>; +P_0x102e36480 .param/l "DATA_WIDTH" 0 11 3, +C4<00000000000000000000000000010000>; +P_0x102e364c0 .param/l "INIT_CYCLES" 1 11 46, +C4<00000000000000000010111011100000>; +P_0x102e36500 .param/l "STATE_IDLE" 1 11 58, C4<001>; +P_0x102e36540 .param/l "STATE_INIT" 1 11 57, C4<000>; +P_0x102e36580 .param/l "STATE_READ" 1 11 59, C4<010>; +P_0x102e365c0 .param/l "STATE_WRITE" 1 11 60, C4<011>; +P_0x102e36600 .param/l "STATE_WRITE_WAIT" 1 11 61, C4<100>; +o0xbaa85a8d0 .functor BUFZ 16, c4; HiZ drive +; Elide local net with no drivers, v0xbab31c6e0_0 name=_ivl_0 +v0xbab31c780_0 .var "address_reg", 21 0; +o0xbaa85a930 .functor BUFZ 1, c4; HiZ drive +v0xbab31c820_0 .net "clk", 0 0, o0xbaa85a930; 0 drivers +v0xbab31c8c0_0 .var "counter", 13 0; +v0xbab31c960_0 .var "dq_oe", 0 0; +v0xbab31ca00_0 .var "dq_out", 15 0; +v0xbab31caa0_0 .var "lb_reg", 0 0; +o0xbaa85aa20 .functor BUFZ 22, c4; HiZ drive +v0xbab31cb40_0 .net "mem_addr", 21 0, o0xbaa85aa20; 0 drivers +o0xbaa85aa50 .functor BUFZ 1, c4; HiZ drive +v0xbab31cbe0_0 .net "mem_lb_n", 0 0, o0xbaa85aa50; 0 drivers +v0xbab31cc80_0 .var "mem_rdata", 15 0; +v0xbab31cd20_0 .var "mem_ready", 0 0; +o0xbaa85aae0 .functor BUFZ 1, c4; HiZ drive +v0xbab31cdc0_0 .net "mem_req", 0 0, o0xbaa85aae0; 0 drivers +o0xbaa85ab10 .functor BUFZ 1, c4; HiZ drive +v0xbab31ce60_0 .net "mem_ub_n", 0 0, o0xbaa85ab10; 0 drivers +o0xbaa85ab40 .functor BUFZ 16, c4; HiZ drive +v0xbab31cf00_0 .net "mem_wdata", 15 0, o0xbaa85ab40; 0 drivers +o0xbaa85ab70 .functor BUFZ 1, c4; HiZ drive +v0xbab31cfa0_0 .net "mem_wr", 0 0, o0xbaa85ab70; 0 drivers +v0xbab31d040_0 .var "psram_a", 21 0; +v0xbab31d0e0_0 .var "psram_ce_n", 0 0; +v0xbab31d180_0 .net "psram_dq", 15 0, L_0xbab347ac0; 1 drivers +v0xbab31d220_0 .var "psram_lb_n", 0 0; +v0xbab31d2c0_0 .var "psram_oe_n", 0 0; +v0xbab31d360_0 .var "psram_ub_n", 0 0; +v0xbab31d400_0 .var "psram_we_n", 0 0; +v0xbab31d4a0_0 .var "psram_zz_n", 0 0; +o0xbaa85ad20 .functor BUFZ 1, c4; HiZ drive +v0xbab31d540_0 .net "rst", 0 0, o0xbaa85ad20; 0 drivers +v0xbab31d5e0_0 .var "state", 2 0; +v0xbab31d680_0 .var "ub_reg", 0 0; +v0xbab31d720_0 .var "wdata_reg", 15 0; +v0xbab31d7c0_0 .var "wr_reg", 0 0; +E_0xbaad3a440 .event posedge, v0xbab31c820_0; +L_0xbab347ac0 .functor MUXZ 16, o0xbaa85a8d0, v0xbab31ca00_0, v0xbab31c960_0, C4<>; +S_0x102e23c60 .scope module, "tb" "tb" 12 3; + .timescale -9 -12; +P_0xbab294000 .param/l "ACC_WIDTH" 0 12 8, +C4<00000000000000000000000000100000>; +P_0xbab294040 .param/l "DATA_WIDTH" 0 12 5, +C4<00000000000000000000000000001000>; +P_0xbab294080 .param/l "N_INPUTS" 0 12 6, +C4<00000000000000000000000000100000>; +P_0xbab2940c0 .param/l "PARALLEL" 0 12 7, +C4<00000000000000000000000000001000>; +v0xbab322120_0 .var/s "bias", 7 0; +v0xbab3221c0_0 .net "busy", 0 0, v0xbab3219a0_0; 1 drivers +v0xbab322260_0 .var "clk", 0 0; +v0xbab322300_0 .net "done", 0 0, v0xbab321ae0_0; 1 drivers +v0xbab3223a0_0 .var/i "errors", 31 0; +v0xbab322440_0 .var/i "i", 31 0; +v0xbab3224e0_0 .var "rst", 0 0; +v0xbab322580_0 .var "start", 0 0; +v0xbab322620_0 .var/s "w_bus", 255 0; +v0xbab3226c0_0 .var/s "x_bus", 255 0; +v0xbab322760_0 .net/s "y", 7 0, v0xbab322080_0; 1 drivers +S_0xbab319e00 .scope module, "dut" "neuron_parallel" 12 30, 4 1 0, S_0x102e23c60; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 256 "x_bus"; + .port_info 4 /INPUT 256 "w_bus"; + .port_info 5 /INPUT 8 "bias"; + .port_info 6 /OUTPUT 8 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0xbab2bca80 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>; +P_0xbab2bcac0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>; +P_0xbab2bcb00 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000100>; +P_0xbab2bcb40 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000010>; +P_0xbab2bcb80 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000100000>; +P_0xbab2bcbc0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>; +v0xbab320e60_0 .net *"_ivl_0", 31 0, L_0xbab34e4e0; 1 drivers +v0xbab320f00_0 .net *"_ivl_11", 31 0, L_0xbaad5a6c0; 1 drivers +v0xbab320fa0_0 .net *"_ivl_14", 31 0, L_0xbab34e580; 1 drivers +L_0xbaa87a4e8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab321040_0 .net *"_ivl_17", 29 0, L_0xbaa87a4e8; 1 drivers +L_0xbaa87a530 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab3210e0_0 .net/2u *"_ivl_18", 31 0, L_0xbaa87a530; 1 drivers +v0xbab321180_0 .net *"_ivl_21", 31 0, L_0xbaad5a760; 1 drivers +L_0xbaa87a578 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab321220_0 .net/2u *"_ivl_22", 31 0, L_0xbaa87a578; 1 drivers +v0xbab3212c0_0 .net *"_ivl_25", 31 0, L_0xbaad5a800; 1 drivers +v0xbab321360_0 .net *"_ivl_29", 0 0, L_0xbab364be0; 1 drivers +L_0xbaa87a410 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab321400_0 .net *"_ivl_3", 29 0, L_0xbaa87a410; 1 drivers +v0xbab3214a0_0 .net *"_ivl_31", 23 0, L_0xbaad5b340; 1 drivers +L_0xbaa87a458 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab321540_0 .net/2u *"_ivl_4", 31 0, L_0xbaa87a458; 1 drivers +v0xbab3215e0_0 .net *"_ivl_7", 31 0, L_0xbaad5a620; 1 drivers +L_0xbaa87a4a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0xbab321680_0 .net/2u *"_ivl_8", 31 0, L_0xbaa87a4a0; 1 drivers +v0xbab321720_0 .var/s "acc", 31 0; +v0xbab3217c0_0 .net/s "acc_next", 31 0, L_0xbab34fe80; 1 drivers +v0xbab321860_0 .net/s "bias", 7 0, v0xbab322120_0; 1 drivers +v0xbab321900_0 .net/s "bias_ext", 31 0, L_0xbab34ff20; 1 drivers +v0xbab3219a0_0 .var "busy", 0 0; +v0xbab321a40_0 .net "clk", 0 0, v0xbab322260_0; 1 drivers +v0xbab321ae0_0 .var "done", 0 0; +v0xbab321b80_0 .net/s "final_acc", 31 0, L_0xbab368000; 1 drivers +v0xbab321c20_0 .var "group_index", 1 0; +v0xbab321cc0_0 .net "rst", 0 0, v0xbab3224e0_0; 1 drivers +v0xbab321d60_0 .net "start", 0 0, v0xbab322580_0; 1 drivers +v0xbab321e00_0 .net/s "w_bus", 255 0, v0xbab322620_0; 1 drivers +v0xbab321ea0_0 .net/s "w_group", 63 0, L_0xbab347c00; 1 drivers +v0xbab321f40_0 .net/s "x_bus", 255 0, v0xbab3226c0_0; 1 drivers +v0xbab321fe0_0 .net/s "x_group", 63 0, L_0xbab347b60; 1 drivers +v0xbab322080_0 .var/s "y", 7 0; +E_0xbaad3a480 .event posedge, v0xbab321a40_0; +L_0xbab34e4e0 .concat [ 2 30 0 0], v0xbab321c20_0, L_0xbaa87a410; +L_0xbaad5a620 .arith/mult 32, L_0xbab34e4e0, L_0xbaa87a458; +L_0xbaad5a6c0 .arith/mult 32, L_0xbaad5a620, L_0xbaa87a4a0; +L_0xbab347b60 .part/v v0xbab3226c0_0, L_0xbaad5a6c0, 64; +L_0xbab34e580 .concat [ 2 30 0 0], v0xbab321c20_0, L_0xbaa87a4e8; +L_0xbaad5a760 .arith/mult 32, L_0xbab34e580, L_0xbaa87a530; +L_0xbaad5a800 .arith/mult 32, L_0xbaad5a760, L_0xbaa87a578; +L_0xbab347c00 .part/v v0xbab322620_0, L_0xbaad5a800, 64; +L_0xbab364be0 .part v0xbab322120_0, 7, 1; +L_0xbaad5b340 .repeat 24, 24, L_0xbab364be0; +L_0xbab34ff20 .concat [ 8 24 0 0], v0xbab322120_0, L_0xbaad5b340; +L_0xbab368000 .arith/sum 32, L_0xbab34fe80, L_0xbab34ff20; +S_0xbab319f80 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xbab319e00; + .timescale 0 0; + .port_info 0 /INPUT 64 "x_bus"; + .port_info 1 /INPUT 64 "w_bus"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbab295f00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>; +P_0xbab295f40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>; +P_0xbab295f80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>; +P_0xbab295fc0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>; +v0xbab320aa0_0 .net/s "acc_in", 31 0, v0xbab321720_0; 1 drivers +v0xbab320b40_0 .net/s "acc_out", 31 0, L_0xbab34fe80; alias, 1 drivers +v0xbab320be0 .array "products", 7 0; +v0xbab320be0_0 .net/s v0xbab320be0 0, 31 0, L_0xbab34e800; 1 drivers +v0xbab320be0_1 .net/s v0xbab320be0 1, 31 0, L_0xbab34ea80; 1 drivers +v0xbab320be0_2 .net/s v0xbab320be0 2, 31 0, L_0xbab34ed00; 1 drivers +v0xbab320be0_3 .net/s v0xbab320be0 3, 31 0, L_0xbab34ef80; 1 drivers +v0xbab320be0_4 .net/s v0xbab320be0 4, 31 0, L_0xbab34f200; 1 drivers +v0xbab320be0_5 .net/s v0xbab320be0 5, 31 0, L_0xbab34f480; 1 drivers +v0xbab320be0_6 .net/s v0xbab320be0 6, 31 0, L_0xbab34f700; 1 drivers +v0xbab320be0_7 .net/s v0xbab320be0 7, 31 0, L_0xbab34f980; 1 drivers +v0xbab320c80 .array "tree", 31 0; +v0xbab320c80_0 .net/s v0xbab320c80 0, 31 0, L_0xbab360070; 1 drivers +v0xbab320c80_1 .net/s v0xbab320c80 1, 31 0, L_0xbab3600e0; 1 drivers +v0xbab320c80_2 .net/s v0xbab320c80 2, 31 0, L_0xbab360150; 1 drivers +v0xbab320c80_3 .net/s v0xbab320c80 3, 31 0, L_0xbab3601c0; 1 drivers +v0xbab320c80_4 .net/s v0xbab320c80 4, 31 0, L_0xbab360230; 1 drivers +v0xbab320c80_5 .net/s v0xbab320c80 5, 31 0, L_0xbab3602a0; 1 drivers +v0xbab320c80_6 .net/s v0xbab320c80 6, 31 0, L_0xbab360310; 1 drivers +v0xbab320c80_7 .net/s v0xbab320c80 7, 31 0, L_0xbab360380; 1 drivers +v0xbab320c80_8 .net/s v0xbab320c80 8, 31 0, L_0xbab34fa20; 1 drivers +v0xbab320c80_9 .net/s v0xbab320c80 9, 31 0, L_0xbab34fac0; 1 drivers +v0xbab320c80_10 .net/s v0xbab320c80 10, 31 0, L_0xbab34fb60; 1 drivers +v0xbab320c80_11 .net/s v0xbab320c80 11, 31 0, L_0xbab34fc00; 1 drivers +o0xbaa85c910 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_12 .net/s v0xbab320c80 12, 31 0, o0xbaa85c910; 0 drivers +o0xbaa85c940 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_13 .net/s v0xbab320c80 13, 31 0, o0xbaa85c940; 0 drivers +o0xbaa85c970 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_14 .net/s v0xbab320c80 14, 31 0, o0xbaa85c970; 0 drivers +o0xbaa85c9a0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_15 .net/s v0xbab320c80 15, 31 0, o0xbaa85c9a0; 0 drivers +v0xbab320c80_16 .net/s v0xbab320c80 16, 31 0, L_0xbab34fca0; 1 drivers +v0xbab320c80_17 .net/s v0xbab320c80 17, 31 0, L_0xbab34fd40; 1 drivers +o0xbaa85ca30 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_18 .net/s v0xbab320c80 18, 31 0, o0xbaa85ca30; 0 drivers +o0xbaa85ca60 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_19 .net/s v0xbab320c80 19, 31 0, o0xbaa85ca60; 0 drivers +o0xbaa85ca90 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_20 .net/s v0xbab320c80 20, 31 0, o0xbaa85ca90; 0 drivers +o0xbaa85cac0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_21 .net/s v0xbab320c80 21, 31 0, o0xbaa85cac0; 0 drivers +o0xbaa85caf0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_22 .net/s v0xbab320c80 22, 31 0, o0xbaa85caf0; 0 drivers +o0xbaa85cb20 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_23 .net/s v0xbab320c80 23, 31 0, o0xbaa85cb20; 0 drivers +v0xbab320c80_24 .net/s v0xbab320c80 24, 31 0, L_0xbab34fde0; 1 drivers +o0xbaa85cb80 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_25 .net/s v0xbab320c80 25, 31 0, o0xbaa85cb80; 0 drivers +o0xbaa85cbb0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_26 .net/s v0xbab320c80 26, 31 0, o0xbaa85cbb0; 0 drivers +o0xbaa85cbe0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_27 .net/s v0xbab320c80 27, 31 0, o0xbaa85cbe0; 0 drivers +o0xbaa85cc10 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_28 .net/s v0xbab320c80 28, 31 0, o0xbaa85cc10; 0 drivers +o0xbaa85cc40 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_29 .net/s v0xbab320c80 29, 31 0, o0xbaa85cc40; 0 drivers +o0xbaa85cc70 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_30 .net/s v0xbab320c80 30, 31 0, o0xbaa85cc70; 0 drivers +o0xbaa85cca0 .functor BUFZ 32, c4; HiZ drive +v0xbab320c80_31 .net/s v0xbab320c80 31, 31 0, o0xbaa85cca0; 0 drivers +v0xbab320d20_0 .net/s "w_bus", 63 0, L_0xbab347c00; alias, 1 drivers +v0xbab320dc0_0 .net/s "x_bus", 63 0, L_0xbab347b60; alias, 1 drivers +L_0xbab347d40 .part L_0xbab347b60, 0, 8; +L_0xbab347de0 .part L_0xbab347c00, 0, 8; +L_0xbab347f20 .part L_0xbab347b60, 8, 8; +L_0xbab364000 .part L_0xbab347c00, 8, 8; +L_0xbab364140 .part L_0xbab347b60, 16, 8; +L_0xbab3641e0 .part L_0xbab347c00, 16, 8; +L_0xbab364320 .part L_0xbab347b60, 24, 8; +L_0xbab3643c0 .part L_0xbab347c00, 24, 8; +L_0xbab364500 .part L_0xbab347b60, 32, 8; +L_0xbab3645a0 .part L_0xbab347c00, 32, 8; +L_0xbab3646e0 .part L_0xbab347b60, 40, 8; +L_0xbab364780 .part L_0xbab347c00, 40, 8; +L_0xbab3648c0 .part L_0xbab347b60, 48, 8; +L_0xbab364960 .part L_0xbab347c00, 48, 8; +L_0xbab364aa0 .part L_0xbab347b60, 56, 8; +L_0xbab364b40 .part L_0xbab347c00, 56, 8; +L_0xbab34fe80 .arith/sum 32, v0xbab321720_0, L_0xbab34fde0; +S_0xbab31a100 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52300 .param/l "i" 1 5 20, +C4<00>; +S_0xbab31a280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31a100; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f4c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31d860_0 .net/s *"_ivl_0", 15 0, L_0xbab34e620; 1 drivers +v0xbab31d900_0 .net/s *"_ivl_2", 15 0, L_0xbab34e6c0; 1 drivers +v0xbab31d9a0_0 .net *"_ivl_7", 0 0, L_0xbab347ca0; 1 drivers +v0xbab31da40_0 .net *"_ivl_9", 15 0, L_0xbaad5a940; 1 drivers +L_0xbaa87a5c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31dae0_0 .net/s "acc_in", 31 0, L_0xbaa87a5c0; 1 drivers +v0xbab31db80_0 .net/s "acc_out", 31 0, L_0xbab34e800; alias, 1 drivers +v0xbab31dc20_0 .net/s "product", 15 0, L_0xbaad5a8a0; 1 drivers +v0xbab31dcc0_0 .net/s "product_ext", 31 0, L_0xbab34e760; 1 drivers +v0xbab31dd60_0 .net/s "w", 7 0, L_0xbab347de0; 1 drivers +v0xbab31de00_0 .net/s "x", 7 0, L_0xbab347d40; 1 drivers +L_0xbab34e620 .extend/s 16, L_0xbab347d40; +L_0xbab34e6c0 .extend/s 16, L_0xbab347de0; +L_0xbaad5a8a0 .arith/mult 16, L_0xbab34e620, L_0xbab34e6c0; +L_0xbab347ca0 .part L_0xbaad5a8a0, 15, 1; +L_0xbaad5a940 .repeat 16, 16, L_0xbab347ca0; +L_0xbab34e760 .concat [ 16 16 0 0], L_0xbaad5a8a0, L_0xbaad5a940; +L_0xbab34e800 .arith/sum 32, L_0xbaa87a5c0, L_0xbab34e760; +S_0xbab31a400 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52340 .param/l "i" 1 5 20, +C4<01>; +S_0xbab31a580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31a400; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f5c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31dea0_0 .net/s *"_ivl_0", 15 0, L_0xbab34e8a0; 1 drivers +v0xbab31df40_0 .net/s *"_ivl_2", 15 0, L_0xbab34e940; 1 drivers +v0xbab31dfe0_0 .net *"_ivl_7", 0 0, L_0xbab347e80; 1 drivers +v0xbab31e080_0 .net *"_ivl_9", 15 0, L_0xbaad5aa80; 1 drivers +L_0xbaa87a608 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31e120_0 .net/s "acc_in", 31 0, L_0xbaa87a608; 1 drivers +v0xbab31e1c0_0 .net/s "acc_out", 31 0, L_0xbab34ea80; alias, 1 drivers +v0xbab31e260_0 .net/s "product", 15 0, L_0xbaad5a9e0; 1 drivers +v0xbab31e300_0 .net/s "product_ext", 31 0, L_0xbab34e9e0; 1 drivers +v0xbab31e3a0_0 .net/s "w", 7 0, L_0xbab364000; 1 drivers +v0xbab31e440_0 .net/s "x", 7 0, L_0xbab347f20; 1 drivers +L_0xbab34e8a0 .extend/s 16, L_0xbab347f20; +L_0xbab34e940 .extend/s 16, L_0xbab364000; +L_0xbaad5a9e0 .arith/mult 16, L_0xbab34e8a0, L_0xbab34e940; +L_0xbab347e80 .part L_0xbaad5a9e0, 15, 1; +L_0xbaad5aa80 .repeat 16, 16, L_0xbab347e80; +L_0xbab34e9e0 .concat [ 16 16 0 0], L_0xbaad5a9e0, L_0xbaad5aa80; +L_0xbab34ea80 .arith/sum 32, L_0xbaa87a608, L_0xbab34e9e0; +S_0xbab31a700 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52380 .param/l "i" 1 5 20, +C4<010>; +S_0xbab31a880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31a700; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f680 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31e4e0_0 .net/s *"_ivl_0", 15 0, L_0xbab34eb20; 1 drivers +v0xbab31e580_0 .net/s *"_ivl_2", 15 0, L_0xbab34ebc0; 1 drivers +v0xbab31e620_0 .net *"_ivl_7", 0 0, L_0xbab3640a0; 1 drivers +v0xbab31e6c0_0 .net *"_ivl_9", 15 0, L_0xbaad5abc0; 1 drivers +L_0xbaa87a650 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31e760_0 .net/s "acc_in", 31 0, L_0xbaa87a650; 1 drivers +v0xbab31e800_0 .net/s "acc_out", 31 0, L_0xbab34ed00; alias, 1 drivers +v0xbab31e8a0_0 .net/s "product", 15 0, L_0xbaad5ab20; 1 drivers +v0xbab31e940_0 .net/s "product_ext", 31 0, L_0xbab34ec60; 1 drivers +v0xbab31e9e0_0 .net/s "w", 7 0, L_0xbab3641e0; 1 drivers +v0xbab31ea80_0 .net/s "x", 7 0, L_0xbab364140; 1 drivers +L_0xbab34eb20 .extend/s 16, L_0xbab364140; +L_0xbab34ebc0 .extend/s 16, L_0xbab3641e0; +L_0xbaad5ab20 .arith/mult 16, L_0xbab34eb20, L_0xbab34ebc0; +L_0xbab3640a0 .part L_0xbaad5ab20, 15, 1; +L_0xbaad5abc0 .repeat 16, 16, L_0xbab3640a0; +L_0xbab34ec60 .concat [ 16 16 0 0], L_0xbaad5ab20, L_0xbaad5abc0; +L_0xbab34ed00 .arith/sum 32, L_0xbaa87a650, L_0xbab34ec60; +S_0xbab31aa00 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad523c0 .param/l "i" 1 5 20, +C4<011>; +S_0xbab31ab80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31aa00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f6c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f700 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f740 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31eb20_0 .net/s *"_ivl_0", 15 0, L_0xbab34eda0; 1 drivers +v0xbab31ebc0_0 .net/s *"_ivl_2", 15 0, L_0xbab34ee40; 1 drivers +v0xbab31ec60_0 .net *"_ivl_7", 0 0, L_0xbab364280; 1 drivers +v0xbab31ed00_0 .net *"_ivl_9", 15 0, L_0xbaad5ad00; 1 drivers +L_0xbaa87a698 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31eda0_0 .net/s "acc_in", 31 0, L_0xbaa87a698; 1 drivers +v0xbab31ee40_0 .net/s "acc_out", 31 0, L_0xbab34ef80; alias, 1 drivers +v0xbab31eee0_0 .net/s "product", 15 0, L_0xbaad5ac60; 1 drivers +v0xbab31ef80_0 .net/s "product_ext", 31 0, L_0xbab34eee0; 1 drivers +v0xbab31f020_0 .net/s "w", 7 0, L_0xbab3643c0; 1 drivers +v0xbab31f0c0_0 .net/s "x", 7 0, L_0xbab364320; 1 drivers +L_0xbab34eda0 .extend/s 16, L_0xbab364320; +L_0xbab34ee40 .extend/s 16, L_0xbab3643c0; +L_0xbaad5ac60 .arith/mult 16, L_0xbab34eda0, L_0xbab34ee40; +L_0xbab364280 .part L_0xbaad5ac60, 15, 1; +L_0xbaad5ad00 .repeat 16, 16, L_0xbab364280; +L_0xbab34eee0 .concat [ 16 16 0 0], L_0xbaad5ac60, L_0xbaad5ad00; +L_0xbab34ef80 .arith/sum 32, L_0xbaa87a698, L_0xbab34eee0; +S_0xbab31ad00 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52440 .param/l "i" 1 5 20, +C4<0100>; +S_0xbab31ae80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31ad00; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f7c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f800 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31f160_0 .net/s *"_ivl_0", 15 0, L_0xbab34f020; 1 drivers +v0xbab31f200_0 .net/s *"_ivl_2", 15 0, L_0xbab34f0c0; 1 drivers +v0xbab31f2a0_0 .net *"_ivl_7", 0 0, L_0xbab364460; 1 drivers +v0xbab31f340_0 .net *"_ivl_9", 15 0, L_0xbaad5ae40; 1 drivers +L_0xbaa87a6e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31f3e0_0 .net/s "acc_in", 31 0, L_0xbaa87a6e0; 1 drivers +v0xbab31f480_0 .net/s "acc_out", 31 0, L_0xbab34f200; alias, 1 drivers +v0xbab31f520_0 .net/s "product", 15 0, L_0xbaad5ada0; 1 drivers +v0xbab31f5c0_0 .net/s "product_ext", 31 0, L_0xbab34f160; 1 drivers +v0xbab31f660_0 .net/s "w", 7 0, L_0xbab3645a0; 1 drivers +v0xbab31f700_0 .net/s "x", 7 0, L_0xbab364500; 1 drivers +L_0xbab34f020 .extend/s 16, L_0xbab364500; +L_0xbab34f0c0 .extend/s 16, L_0xbab3645a0; +L_0xbaad5ada0 .arith/mult 16, L_0xbab34f020, L_0xbab34f0c0; +L_0xbab364460 .part L_0xbaad5ada0, 15, 1; +L_0xbaad5ae40 .repeat 16, 16, L_0xbab364460; +L_0xbab34f160 .concat [ 16 16 0 0], L_0xbaad5ada0, L_0xbaad5ae40; +L_0xbab34f200 .arith/sum 32, L_0xbaa87a6e0, L_0xbab34f160; +S_0xbab31b000 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52480 .param/l "i" 1 5 20, +C4<0101>; +S_0xbab31b180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31b000; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f840 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f880 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f8c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31f7a0_0 .net/s *"_ivl_0", 15 0, L_0xbab34f2a0; 1 drivers +v0xbab31f840_0 .net/s *"_ivl_2", 15 0, L_0xbab34f340; 1 drivers +v0xbab31f8e0_0 .net *"_ivl_7", 0 0, L_0xbab364640; 1 drivers +v0xbab31f980_0 .net *"_ivl_9", 15 0, L_0xbaad5af80; 1 drivers +L_0xbaa87a728 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab31fa20_0 .net/s "acc_in", 31 0, L_0xbaa87a728; 1 drivers +v0xbab31fac0_0 .net/s "acc_out", 31 0, L_0xbab34f480; alias, 1 drivers +v0xbab31fb60_0 .net/s "product", 15 0, L_0xbaad5aee0; 1 drivers +v0xbab31fc00_0 .net/s "product_ext", 31 0, L_0xbab34f3e0; 1 drivers +v0xbab31fca0_0 .net/s "w", 7 0, L_0xbab364780; 1 drivers +v0xbab31fd40_0 .net/s "x", 7 0, L_0xbab3646e0; 1 drivers +L_0xbab34f2a0 .extend/s 16, L_0xbab3646e0; +L_0xbab34f340 .extend/s 16, L_0xbab364780; +L_0xbaad5aee0 .arith/mult 16, L_0xbab34f2a0, L_0xbab34f340; +L_0xbab364640 .part L_0xbaad5aee0, 15, 1; +L_0xbaad5af80 .repeat 16, 16, L_0xbab364640; +L_0xbab34f3e0 .concat [ 16 16 0 0], L_0xbaad5aee0, L_0xbaad5af80; +L_0xbab34f480 .arith/sum 32, L_0xbaa87a728, L_0xbab34f3e0; +S_0xbab31b300 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad524c0 .param/l "i" 1 5 20, +C4<0110>; +S_0xbab31b480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31b300; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4f940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4f980 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab31fde0_0 .net/s *"_ivl_0", 15 0, L_0xbab34f520; 1 drivers +v0xbab31fe80_0 .net/s *"_ivl_2", 15 0, L_0xbab34f5c0; 1 drivers +v0xbab31ff20_0 .net *"_ivl_7", 0 0, L_0xbab364820; 1 drivers +v0xbab320000_0 .net *"_ivl_9", 15 0, L_0xbaad5b0c0; 1 drivers +L_0xbaa87a770 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab3200a0_0 .net/s "acc_in", 31 0, L_0xbaa87a770; 1 drivers +v0xbab320140_0 .net/s "acc_out", 31 0, L_0xbab34f700; alias, 1 drivers +v0xbab3201e0_0 .net/s "product", 15 0, L_0xbaad5b020; 1 drivers +v0xbab320280_0 .net/s "product_ext", 31 0, L_0xbab34f660; 1 drivers +v0xbab320320_0 .net/s "w", 7 0, L_0xbab364960; 1 drivers +v0xbab3203c0_0 .net/s "x", 7 0, L_0xbab3648c0; 1 drivers +L_0xbab34f520 .extend/s 16, L_0xbab3648c0; +L_0xbab34f5c0 .extend/s 16, L_0xbab364960; +L_0xbaad5b020 .arith/mult 16, L_0xbab34f520, L_0xbab34f5c0; +L_0xbab364820 .part L_0xbaad5b020, 15, 1; +L_0xbaad5b0c0 .repeat 16, 16, L_0xbab364820; +L_0xbab34f660 .concat [ 16 16 0 0], L_0xbaad5b020, L_0xbaad5b0c0; +L_0xbab34f700 .arith/sum 32, L_0xbaa87a770, L_0xbab34f660; +S_0xbab31b600 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52500 .param/l "i" 1 5 20, +C4<0111>; +S_0xbab31b780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xbab31b600; + .timescale 0 0; + .port_info 0 /INPUT 8 "x"; + .port_info 1 /INPUT 8 "w"; + .port_info 2 /INPUT 32 "acc_in"; + .port_info 3 /OUTPUT 32 "acc_out"; +P_0xbaad4f9c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>; +P_0xbaad4fa00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>; +P_0xbaad4fa40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>; +v0xbab320460_0 .net/s *"_ivl_0", 15 0, L_0xbab34f7a0; 1 drivers +v0xbab320500_0 .net/s *"_ivl_2", 15 0, L_0xbab34f840; 1 drivers +v0xbab3205a0_0 .net *"_ivl_7", 0 0, L_0xbab364a00; 1 drivers +v0xbab320640_0 .net *"_ivl_9", 15 0, L_0xbaad5b200; 1 drivers +L_0xbaa87a7b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0xbab3206e0_0 .net/s "acc_in", 31 0, L_0xbaa87a7b8; 1 drivers +v0xbab320780_0 .net/s "acc_out", 31 0, L_0xbab34f980; alias, 1 drivers +v0xbab320820_0 .net/s "product", 15 0, L_0xbaad5b160; 1 drivers +v0xbab3208c0_0 .net/s "product_ext", 31 0, L_0xbab34f8e0; 1 drivers +v0xbab320960_0 .net/s "w", 7 0, L_0xbab364b40; 1 drivers +v0xbab320a00_0 .net/s "x", 7 0, L_0xbab364aa0; 1 drivers +L_0xbab34f7a0 .extend/s 16, L_0xbab364aa0; +L_0xbab34f840 .extend/s 16, L_0xbab364b40; +L_0xbaad5b160 .arith/mult 16, L_0xbab34f7a0, L_0xbab34f840; +L_0xbab364a00 .part L_0xbaad5b160, 15, 1; +L_0xbaad5b200 .repeat 16, 16, L_0xbab364a00; +L_0xbab34f8e0 .concat [ 16 16 0 0], L_0xbaad5b160, L_0xbaad5b200; +L_0xbab34f980 .arith/sum 32, L_0xbaa87a7b8, L_0xbab34f8e0; +S_0xbab31b900 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52400 .param/l "i" 1 5 80, +C4<00>; +L_0xbab360070 .functor BUFZ 32, L_0xbab34e800, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab31ba80 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52540 .param/l "i" 1 5 80, +C4<01>; +L_0xbab3600e0 .functor BUFZ 32, L_0xbab34ea80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab31bc00 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52580 .param/l "i" 1 5 80, +C4<010>; +L_0xbab360150 .functor BUFZ 32, L_0xbab34ed00, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab31bd80 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad525c0 .param/l "i" 1 5 80, +C4<011>; +L_0xbab3601c0 .functor BUFZ 32, L_0xbab34ef80, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab324000 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52600 .param/l "i" 1 5 80, +C4<0100>; +L_0xbab360230 .functor BUFZ 32, L_0xbab34f200, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab324180 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52640 .param/l "i" 1 5 80, +C4<0101>; +L_0xbab3602a0 .functor BUFZ 32, L_0xbab34f480, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab324300 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52680 .param/l "i" 1 5 80, +C4<0110>; +L_0xbab360310 .functor BUFZ 32, L_0xbab34f700, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab324480 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad526c0 .param/l "i" 1 5 80, +C4<0111>; +L_0xbab360380 .functor BUFZ 32, L_0xbab34f980, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +S_0xbab324600 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52700 .param/l "level" 1 5 92, +C4<00>; +S_0xbab324780 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab324600; + .timescale 0 0; +P_0xbaad52740 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34fa20 .arith/sum 32, L_0xbab360070, L_0xbab3600e0; +S_0xbab324900 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab324600; + .timescale 0 0; +P_0xbaad52780 .param/l "node" 1 5 94, +C4<01>; +L_0xbab34fac0 .arith/sum 32, L_0xbab360150, L_0xbab3601c0; +S_0xbab324a80 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xbab324600; + .timescale 0 0; +P_0xbaad527c0 .param/l "node" 1 5 94, +C4<010>; +L_0xbab34fb60 .arith/sum 32, L_0xbab360230, L_0xbab3602a0; +S_0xbab324c00 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xbab324600; + .timescale 0 0; +P_0xbaad52800 .param/l "node" 1 5 94, +C4<011>; +L_0xbab34fc00 .arith/sum 32, L_0xbab360310, L_0xbab360380; +S_0xbab324d80 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52840 .param/l "level" 1 5 92, +C4<01>; +S_0xbab324f00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab324d80; + .timescale 0 0; +P_0xbaad52880 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34fca0 .arith/sum 32, L_0xbab34fa20, L_0xbab34fac0; +S_0xbab325080 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xbab324d80; + .timescale 0 0; +P_0xbaad528c0 .param/l "node" 1 5 94, +C4<01>; +L_0xbab34fd40 .arith/sum 32, L_0xbab34fb60, L_0xbab34fc00; +S_0xbab325200 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xbab319f80; + .timescale 0 0; +P_0xbaad52900 .param/l "level" 1 5 92, +C4<010>; +S_0xbab325380 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xbab325200; + .timescale 0 0; +P_0xbaad52940 .param/l "node" 1 5 94, +C4<00>; +L_0xbab34fde0 .arith/sum 32, L_0xbab34fca0, L_0xbab34fd40; +S_0xbab325500 .scope task, "run_neuron" "run_neuron" 12 51, 12 51 0, S_0x102e23c60; + .timescale -9 -12; +E_0xbaad3a700 .event anyedge, v0xbab321ae0_0; TD_tb.run_neuron ; - %wait E_0x7e2c81380; + %wait E_0xbaad3a480; %pushi/vec4 1, 0, 1; - %store/vec4 v0x7e30b94a0_0, 0, 1; - %wait E_0x7e2c81380; + %store/vec4 v0xbab322580_0, 0, 1; + %wait E_0xbaad3a480; %pushi/vec4 0, 0, 1; - %store/vec4 v0x7e30b94a0_0, 0, 1; -T_1.0 ; - %load/vec4 v0x7e30b9220_0; + %store/vec4 v0xbab322580_0, 0, 1; +T_0.0 ; + %load/vec4 v0xbab322300_0; %pad/u 32; %pushi/vec4 1, 0, 32; %cmp/e; %flag_get/vec4 4; %cmpi/ne 1, 0, 1; - %jmp/0xz T_1.1, 6; - %wait E_0x7e2c81600; - %jmp T_1.0; -T_1.1 ; - %wait E_0x7e2c81380; + %jmp/0xz T_0.1, 6; + %wait E_0xbaad3a700; + %jmp T_0.0; +T_0.1 ; + %wait E_0xbaad3a480; %end; -S_0x7e2ca0300 .scope task, "test_1" "test_1" 3 91, 3 91 0, S_0x1012716f0; +S_0xbab325680 .scope task, "test_1" "test_1" 12 78, 12 78 0, S_0x102e23c60; .timescale -9 -12; TD_tb.test_1 ; - %vpi_call/w 3 93 "$display", "\000" {0 0 0}; - %vpi_call/w 3 94 "$display", "TEST 1: DIVERSE VECTOR" {0 0 0}; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b95e0_0, 0, 1024; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b9540_0, 0, 1024; - %pushi/real 1308622848, 4065; load=0.609375 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %store/vec4 v0x7e30b9040_0, 0, 16; - %pushi/real 1610612736, 4066; load=1.50000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %vpi_call/w 12 80 "$display", "\000" {0 0 0}; + %vpi_call/w 12 81 "$display", "TEST 1: DIVERSE VECTOR" {0 0 0}; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab3226c0_0, 0, 256; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab322620_0, 0, 256; + %pushi/vec4 1, 0, 8; + %store/vec4 v0xbab322120_0, 0, 8; + %pushi/vec4 3, 0, 8; %ix/load 4, 0, 0; %flag_set/imm 4, 0; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 4067; load=2.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 2, 0, 8; %ix/load 4, 0, 0; %flag_set/imm 4, 0; - %store/vec4 v0x7e30b9540_0, 4, 16; - %pushi/real 1073741824, 4067; load=2.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %store/vec4 v0xbab322620_0, 4, 8; + %pushi/vec4 4, 0, 8; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 255, 0, 8; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %store/vec4 v0xbab322620_0, 4, 8; + %pushi/vec4 2, 0, 8; %ix/load 4, 16, 0; %flag_set/imm 4, 0; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 1, 0, 8; %ix/load 4, 16, 0; %flag_set/imm 4, 0; - %store/vec4 v0x7e30b9540_0, 4, 16; - %pushi/real 1073741824, 4065; load=0.500000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %ix/load 4, 32, 0; - %flag_set/imm 4, 0; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 4064; load=0.250000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %ix/load 4, 32, 0; - %flag_set/imm 4, 0; - %store/vec4 v0x7e30b9540_0, 4, 16; - %fork TD_tb.run_neuron, S_0x7e2ca0180; + %store/vec4 v0xbab322620_0, 4, 8; + %fork TD_tb.run_neuron, S_0xbab325500; %join; - %vpi_call/w 3 111 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; - %vpi_call/w 3 112 "$display", "EXPECTED = 444" {0 0 0}; - %load/vec4 v0x7e30b9680_0; - %cmpi/ne 444, 0, 16; - %jmp/0xz T_2.2, 6; - %vpi_call/w 3 115 "$display", "FAIL - TEST 1" {0 0 0}; - %load/vec4 v0x7e30b92c0_0; + %vpi_call/w 12 98 "$display", "RTL = %0d", v0xbab322760_0 {0 0 0}; + %vpi_call/w 12 99 "$display", "EXPECTED = 5" {0 0 0}; + %load/vec4 v0xbab322760_0; + %cmpi/ne 5, 0, 8; + %jmp/0xz T_1.2, 6; + %vpi_call/w 12 102 "$display", "FAIL - TEST 1" {0 0 0}; + %load/vec4 v0xbab3223a0_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b92c0_0, 0, 32; - %jmp T_2.3; -T_2.2 ; - %vpi_call/w 3 119 "$display", "PASS - TEST 1" {0 0 0}; -T_2.3 ; + %store/vec4 v0xbab3223a0_0, 0, 32; + %jmp T_1.3; +T_1.2 ; + %vpi_call/w 12 106 "$display", "PASS - TEST 1" {0 0 0}; +T_1.3 ; %end; -S_0x7e2ca0480 .scope task, "test_2" "test_2" 3 130, 3 130 0, S_0x1012716f0; +S_0xbab325800 .scope task, "test_2" "test_2" 12 117, 12 117 0, S_0x102e23c60; .timescale -9 -12; TD_tb.test_2 ; - %vpi_call/w 3 132 "$display", "\000" {0 0 0}; - %vpi_call/w 3 133 "$display", "TEST 2: RELU" {0 0 0}; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b95e0_0, 0, 1024; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b9540_0, 0, 1024; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x7e30b9040_0, 0, 16; + %vpi_call/w 12 119 "$display", "\000" {0 0 0}; + %vpi_call/w 12 120 "$display", "TEST 2: RELU" {0 0 0}; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab3226c0_0, 0, 256; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab322620_0, 0, 256; + %pushi/vec4 0, 0, 8; + %store/vec4 v0xbab322120_0, 0, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; -T_3.4 ; Top of for-loop - %load/vec4 v0x7e30b9360_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_3.5, 5; - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab322440_0, 0, 32; +T_2.4 ; Top of for-loop + %load/vec4 v0xbab322440_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_2.5, 5; + %pushi/vec4 1, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 255, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b9540_0, 4, 16; -T_3.6 ; for-loop step statement - %load/vec4 v0x7e30b9360_0; + %store/vec4 v0xbab322620_0, 4, 8; +T_2.6 ; for-loop step statement + %load/vec4 v0xbab322440_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; - %jmp T_3.4; -T_3.5 ; for-loop exit label - %fork TD_tb.run_neuron, S_0x7e2ca0180; + %store/vec4 v0xbab322440_0, 0, 32; + %jmp T_2.4; +T_2.5 ; for-loop exit label + %fork TD_tb.run_neuron, S_0xbab325500; %join; - %vpi_call/w 3 146 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; - %vpi_call/w 3 147 "$display", "EXPECTED = 0" {0 0 0}; - %load/vec4 v0x7e30b9680_0; - %cmpi/ne 0, 0, 16; - %jmp/0xz T_3.7, 6; - %vpi_call/w 3 150 "$display", "FAIL - TEST 2" {0 0 0}; - %load/vec4 v0x7e30b92c0_0; + %vpi_call/w 12 133 "$display", "RTL = %0d", v0xbab322760_0 {0 0 0}; + %vpi_call/w 12 134 "$display", "EXPECTED = 0" {0 0 0}; + %load/vec4 v0xbab322760_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_2.7, 6; + %vpi_call/w 12 137 "$display", "FAIL - TEST 2" {0 0 0}; + %load/vec4 v0xbab3223a0_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b92c0_0, 0, 32; - %jmp T_3.8; -T_3.7 ; - %vpi_call/w 3 154 "$display", "PASS - TEST 2" {0 0 0}; -T_3.8 ; + %store/vec4 v0xbab3223a0_0, 0, 32; + %jmp T_2.8; +T_2.7 ; + %vpi_call/w 12 141 "$display", "PASS - TEST 2" {0 0 0}; +T_2.8 ; %end; -S_0x7e2ca0600 .scope task, "test_3" "test_3" 3 165, 3 165 0, S_0x1012716f0; +S_0xbab325980 .scope task, "test_3" "test_3" 12 152, 12 152 0, S_0x102e23c60; .timescale -9 -12; TD_tb.test_3 ; - %vpi_call/w 3 167 "$display", "\000" {0 0 0}; - %vpi_call/w 3 168 "$display", "TEST 3: POSITIVE SATURATION" {0 0 0}; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b95e0_0, 0, 1024; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b9540_0, 0, 1024; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x7e30b9040_0, 0, 16; + %vpi_call/w 12 154 "$display", "\000" {0 0 0}; + %vpi_call/w 12 155 "$display", "TEST 3: POSITIVE SATURATION" {0 0 0}; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab3226c0_0, 0, 256; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab322620_0, 0, 256; + %pushi/vec4 0, 0, 8; + %store/vec4 v0xbab322120_0, 0, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; -T_4.9 ; Top of for-loop - %load/vec4 v0x7e30b9360_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_4.10, 5; - %pushi/real 2130706432, 4072; load=127.000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab322440_0, 0, 32; +T_3.9 ; Top of for-loop + %load/vec4 v0xbab322440_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_3.10, 5; + %pushi/vec4 100, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 4067; load=2.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 2, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b9540_0, 4, 16; -T_4.11 ; for-loop step statement - %load/vec4 v0x7e30b9360_0; + %store/vec4 v0xbab322620_0, 4, 8; +T_3.11 ; for-loop step statement + %load/vec4 v0xbab322440_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; - %jmp T_4.9; -T_4.10 ; for-loop exit label - %fork TD_tb.run_neuron, S_0x7e2ca0180; + %store/vec4 v0xbab322440_0, 0, 32; + %jmp T_3.9; +T_3.10 ; for-loop exit label + %fork TD_tb.run_neuron, S_0xbab325500; %join; - %vpi_call/w 3 181 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; - %vpi_call/w 3 182 "$display", "EXPECTED = 32767" {0 0 0}; - %load/vec4 v0x7e30b9680_0; - %cmpi/ne 32767, 0, 16; - %jmp/0xz T_4.12, 6; - %vpi_call/w 3 185 "$display", "FAIL - TEST 3" {0 0 0}; - %load/vec4 v0x7e30b92c0_0; + %vpi_call/w 12 168 "$display", "RTL = %0d", v0xbab322760_0 {0 0 0}; + %vpi_call/w 12 169 "$display", "EXPECTED = 127" {0 0 0}; + %load/vec4 v0xbab322760_0; + %cmpi/ne 127, 0, 8; + %jmp/0xz T_3.12, 6; + %vpi_call/w 12 172 "$display", "FAIL - TEST 3" {0 0 0}; + %load/vec4 v0xbab3223a0_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b92c0_0, 0, 32; - %jmp T_4.13; -T_4.12 ; - %vpi_call/w 3 189 "$display", "PASS - TEST 3" {0 0 0}; -T_4.13 ; + %store/vec4 v0xbab3223a0_0, 0, 32; + %jmp T_3.13; +T_3.12 ; + %vpi_call/w 12 176 "$display", "PASS - TEST 3" {0 0 0}; +T_3.13 ; %end; -S_0x7e2ca0780 .scope task, "test_4" "test_4" 3 206, 3 206 0, S_0x1012716f0; +S_0xbab325b00 .scope task, "test_4" "test_4" 12 193, 12 193 0, S_0x102e23c60; .timescale -9 -12; TD_tb.test_4 ; - %vpi_call/w 3 208 "$display", "\000" {0 0 0}; - %vpi_call/w 3 209 "$display", "TEST 4: MIXED VALUES + NEGATIVE BIAS" {0 0 0}; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b95e0_0, 0, 1024; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b9540_0, 0, 1024; - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %store/vec4 v0x7e30b9040_0, 0, 16; + %vpi_call/w 12 195 "$display", "\000" {0 0 0}; + %vpi_call/w 12 196 "$display", "TEST 4: MIXED VALUES + NEGATIVE BIAS" {0 0 0}; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab3226c0_0, 0, 256; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab322620_0, 0, 256; + %pushi/vec4 240, 0, 8; + %store/vec4 v0xbab322120_0, 0, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; -T_5.14 ; Top of for-loop - %load/vec4 v0x7e30b9360_0; - %cmpi/s 64, 0, 32; - %jmp/0xz T_5.15, 5; - %load/vec4 v0x7e30b9360_0; + %store/vec4 v0xbab322440_0, 0, 32; +T_4.14 ; Top of for-loop + %load/vec4 v0xbab322440_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_4.15, 5; + %load/vec4 v0xbab322440_0; %pushi/vec4 2, 0, 32; %mod/s; %cmpi/e 0, 0, 32; - %jmp/0xz T_5.17, 4; - %pushi/real 1073741824, 4067; load=2.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %jmp/0xz T_4.17, 4; + %pushi/vec4 2, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 4065; load=0.500000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 1, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b9540_0, 4, 16; - %jmp T_5.18; -T_5.17 ; - %pushi/real 1073741824, 20450; load=-1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab322620_0, 4, 8; + %jmp T_4.18; +T_4.17 ; + %pushi/vec4 255, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b95e0_0, 4, 16; - %pushi/real 1073741824, 4066; load=1.00000 - %store/real v0x7e30b8fa0_0; - %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; - %load/vec4 v0x7e30b9360_0; - %muli 16, 0, 32; + %store/vec4 v0xbab3226c0_0, 4, 8; + %pushi/vec4 1, 0, 8; + %load/vec4 v0xbab322440_0; + %muli 8, 0, 32; %ix/vec4/s 4; - %store/vec4 v0x7e30b9540_0, 4, 16; -T_5.18 ; -T_5.16 ; for-loop step statement - %load/vec4 v0x7e30b9360_0; + %store/vec4 v0xbab322620_0, 4, 8; +T_4.18 ; +T_4.16 ; for-loop step statement + %load/vec4 v0xbab322440_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b9360_0, 0, 32; - %jmp T_5.14; -T_5.15 ; for-loop exit label - %fork TD_tb.run_neuron, S_0x7e2ca0180; + %store/vec4 v0xbab322440_0, 0, 32; + %jmp T_4.14; +T_4.15 ; for-loop exit label + %fork TD_tb.run_neuron, S_0xbab325500; %join; - %vpi_call/w 3 228 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; - %vpi_call/w 3 229 "$display", "EXPECTED = 0" {0 0 0}; - %load/vec4 v0x7e30b9680_0; - %cmpi/ne 0, 0, 16; - %jmp/0xz T_5.19, 6; - %vpi_call/w 3 232 "$display", "FAIL - TEST 4" {0 0 0}; - %load/vec4 v0x7e30b92c0_0; + %vpi_call/w 12 215 "$display", "RTL = %0d", v0xbab322760_0 {0 0 0}; + %vpi_call/w 12 216 "$display", "EXPECTED = 0" {0 0 0}; + %load/vec4 v0xbab322760_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_4.19, 6; + %vpi_call/w 12 219 "$display", "FAIL - TEST 4" {0 0 0}; + %load/vec4 v0xbab3223a0_0; %addi 1, 0, 32; - %store/vec4 v0x7e30b92c0_0, 0, 32; - %jmp T_5.20; -T_5.19 ; - %vpi_call/w 3 236 "$display", "PASS - TEST 4" {0 0 0}; -T_5.20 ; + %store/vec4 v0xbab3223a0_0, 0, 32; + %jmp T_4.20; +T_4.19 ; + %vpi_call/w 12 223 "$display", "PASS - TEST 4" {0 0 0}; +T_4.20 ; %end; - .scope S_0x1012679f0; + .scope S_0x102e22e30; +T_5 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2a90e0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2a9040_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2a8b40_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2a94a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2a8dc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2a8f00_0, 0; + %jmp T_5.1; +T_5.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2a8f00_0, 0; + %load/vec4 v0xbab2a9180_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_5.4, 9; + %load/vec4 v0xbab2a8dc0_0; + %nor/r; + %and; +T_5.4; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2a9040_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2a8b40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2a8dc0_0, 0; + %jmp T_5.3; +T_5.2 ; + %load/vec4 v0xbab2a8dc0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.5, 8; + %load/vec4 v0xbab2a9040_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_5.7, 4; + %load/vec4 v0xbab2a8fa0_0; + %assign/vec4 v0xbab2a8b40_0, 0; + %load/vec4 v0xbab2a8fa0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_5.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2a94a0_0, 0; + %jmp T_5.10; +T_5.9 ; + %load/vec4 v0xbab2a8fa0_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_5.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2a94a0_0, 0; + %jmp T_5.12; +T_5.11 ; + %load/vec4 v0xbab2a8fa0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2a94a0_0, 0; +T_5.12 ; +T_5.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2a8dc0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2a8f00_0, 0; + %jmp T_5.8; +T_5.7 ; + %load/vec4 v0xbab2a8be0_0; + %assign/vec4 v0xbab2a8b40_0, 0; + %load/vec4 v0xbab2a9040_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2a9040_0, 0; +T_5.8 ; +T_5.5 ; +T_5.3 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0xbab2a6b80; T_6 ; - %wait E_0x7e2c81380; - %load/vec4 v0x7e30b8aa0_0; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2b99a0_0; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %pushi/vec4 0, 0, 3; - %assign/vec4 v0x7e30b8a00_0, 0; + %assign/vec4 v0xbab2b9900_0, 0; %pushi/vec4 0, 0, 40; - %assign/vec4 v0x7e30b83c0_0, 0; + %assign/vec4 v0xbab2b9400_0, 0; %pushi/vec4 0, 0, 16; - %assign/vec4 v0x7e30b8e60_0, 0; + %assign/vec4 v0xbab2b9d60_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7e30b86e0_0, 0; + %assign/vec4 v0xbab2b9680_0, 0; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7e30b8820_0, 0; + %assign/vec4 v0xbab2b97c0_0, 0; %jmp T_6.1; T_6.0 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7e30b8820_0, 0; - %load/vec4 v0x7e30b8b40_0; + %assign/vec4 v0xbab2b97c0_0, 0; + %load/vec4 v0xbab2b9a40_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_6.4, 9; - %load/vec4 v0x7e30b86e0_0; + %load/vec4 v0xbab2b9680_0; %nor/r; %and; T_6.4; %flag_set/vec4 8; %jmp/0xz T_6.2, 8; %pushi/vec4 0, 0, 3; - %assign/vec4 v0x7e30b8a00_0, 0; + %assign/vec4 v0xbab2b9900_0, 0; %pushi/vec4 0, 0, 40; - %assign/vec4 v0x7e30b83c0_0, 0; + %assign/vec4 v0xbab2b9400_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x7e30b86e0_0, 0; + %assign/vec4 v0xbab2b9680_0, 0; %jmp T_6.3; T_6.2 ; - %load/vec4 v0x7e30b86e0_0; + %load/vec4 v0xbab2b9680_0; %flag_set/vec4 8; %jmp/0xz T_6.5, 8; - %load/vec4 v0x7e30b8a00_0; + %load/vec4 v0xbab2b9900_0; %pad/u 32; %cmpi/e 7, 0, 32; %jmp/0xz T_6.7, 4; - %load/vec4 v0x7e30b88c0_0; - %assign/vec4 v0x7e30b83c0_0, 0; - %load/vec4 v0x7e30b8960_0; + %load/vec4 v0xbab2b9860_0; + %assign/vec4 v0xbab2b9400_0, 0; + %load/vec4 v0xbab2b9860_0; %cmpi/s 0, 0, 40; %flag_or 5, 4; %jmp/0xz T_6.9, 5; %pushi/vec4 0, 0, 16; - %assign/vec4 v0x7e30b8e60_0, 0; + %assign/vec4 v0xbab2b9d60_0, 0; %jmp T_6.10; T_6.9 ; - %load/vec4 v0x7e30b8960_0; - %cmpi/s 32767, 0, 40; + %load/vec4 v0xbab2b9860_0; + %cmpi/s 127, 0, 40; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_6.11, 5; - %pushi/vec4 32767, 0, 16; - %assign/vec4 v0x7e30b8e60_0, 0; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2b9d60_0, 0; %jmp T_6.12; T_6.11 ; - %load/vec4 v0x7e30b8960_0; + %load/vec4 v0xbab2b9860_0; %parti/s 16, 0, 2; - %assign/vec4 v0x7e30b8e60_0, 0; + %assign/vec4 v0xbab2b9d60_0, 0; T_6.12 ; T_6.10 ; %pushi/vec4 0, 0, 1; - %assign/vec4 v0x7e30b86e0_0, 0; + %assign/vec4 v0xbab2b9680_0, 0; %pushi/vec4 1, 0, 1; - %assign/vec4 v0x7e30b8820_0, 0; + %assign/vec4 v0xbab2b97c0_0, 0; %jmp T_6.8; T_6.7 ; - %load/vec4 v0x7e30b8460_0; - %assign/vec4 v0x7e30b83c0_0, 0; - %load/vec4 v0x7e30b8a00_0; + %load/vec4 v0xbab2b94a0_0; + %assign/vec4 v0xbab2b9400_0, 0; + %load/vec4 v0xbab2b9900_0; %addi 1, 0, 3; - %assign/vec4 v0x7e30b8a00_0, 0; + %assign/vec4 v0xbab2b9900_0, 0; T_6.8 ; T_6.5 ; T_6.3 ; T_6.1 ; %jmp T_6; .thread T_6; - .scope S_0x1012716f0; + .scope S_0xbab2b2400; T_7 ; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x7e30b9180_0, 0, 1; -T_7.0 ; - %delay 5000, 0; - %load/vec4 v0x7e30b9180_0; - %inv; - %store/vec4 v0x7e30b9180_0, 0, 1; - %jmp T_7.0; -T_7.1 ; - %end; - .thread T_7; - .scope S_0x1012716f0; -T_8 ; - %vpi_call/w 3 246 "$dumpfile", "sim/neuron_parallel.vcd" {0 0 0}; - %vpi_call/w 3 247 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1012716f0 {0 0 0}; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x7e30b9400_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x7e30b94a0_0, 0, 1; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b95e0_0, 0, 1024; - %pushi/vec4 0, 0, 1024; - %store/vec4 v0x7e30b9540_0, 0, 1024; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2c2260_0; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2c21c0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2c1cc0_0, 0; %pushi/vec4 0, 0, 16; - %store/vec4 v0x7e30b9040_0, 0, 16; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x7e30b92c0_0, 0, 32; - %pushi/vec4 2, 0, 32; -T_8.0 %dup/vec4; - %cmpi/s 0, 0, 32; - %jmp/1xz T_8.1, 5; - %jmp/1 T_8.1, 4; - %subi 1, 0, 32; - %wait E_0x7e2c81380; - %jmp T_8.0; -T_8.1 ; - %pop/vec4 1; + %assign/vec4 v0xbab2c2620_0, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v0x7e30b9400_0, 0, 1; - %vpi_call/w 3 260 "$display", "\000" {0 0 0}; - %vpi_call/w 3 261 "$display", "==============================" {0 0 0}; - %vpi_call/w 3 262 "$display", "NEURON_PARALLEL TESTBENCH" {0 0 0}; - %vpi_call/w 3 263 "$display", "==============================" {0 0 0}; - %fork TD_tb.test_1, S_0x7e2ca0300; - %join; - %fork TD_tb.test_2, S_0x7e2ca0480; - %join; - %fork TD_tb.test_3, S_0x7e2ca0600; - %join; - %fork TD_tb.test_4, S_0x7e2ca0780; - %join; - %vpi_call/w 3 270 "$display", "\000" {0 0 0}; - %vpi_call/w 3 271 "$display", "==============================" {0 0 0}; - %load/vec4 v0x7e30b92c0_0; - %cmpi/e 0, 0, 32; - %jmp/0xz T_8.2, 4; - %vpi_call/w 3 274 "$display", "ALL TESTS PASSED" {0 0 0}; + %assign/vec4 v0xbab2c1f40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2c2080_0, 0; + %jmp T_7.1; +T_7.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2c2080_0, 0; + %load/vec4 v0xbab2c2300_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_7.4, 9; + %load/vec4 v0xbab2c1f40_0; + %nor/r; + %and; +T_7.4; + %flag_set/vec4 8; + %jmp/0xz T_7.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2c21c0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2c1cc0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2c1f40_0, 0; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0xbab2c1f40_0; + %flag_set/vec4 8; + %jmp/0xz T_7.5, 8; + %load/vec4 v0xbab2c21c0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_7.7, 4; + %load/vec4 v0xbab2c2120_0; + %assign/vec4 v0xbab2c1cc0_0, 0; + %load/vec4 v0xbab2c2120_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_7.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2c2620_0, 0; + %jmp T_7.10; +T_7.9 ; + %load/vec4 v0xbab2c2120_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_7.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2c2620_0, 0; + %jmp T_7.12; +T_7.11 ; + %load/vec4 v0xbab2c2120_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2c2620_0, 0; +T_7.12 ; +T_7.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2c1f40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2c2080_0, 0; + %jmp T_7.8; +T_7.7 ; + %load/vec4 v0xbab2c1d60_0; + %assign/vec4 v0xbab2c1cc0_0, 0; + %load/vec4 v0xbab2c21c0_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2c21c0_0, 0; +T_7.8 ; +T_7.5 ; +T_7.3 ; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0xbab2c5c80; +T_8 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2d2b20_0; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2d2a80_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2d2580_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2d2ee0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2d2800_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2d2940_0, 0; + %jmp T_8.1; +T_8.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2d2940_0, 0; + %load/vec4 v0xbab2d2bc0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_8.4, 9; + %load/vec4 v0xbab2d2800_0; + %nor/r; + %and; +T_8.4; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2d2a80_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2d2580_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2d2800_0, 0; %jmp T_8.3; T_8.2 ; - %vpi_call/w 3 277 "$display", "FAILURES = %0d", v0x7e30b92c0_0 {0 0 0}; + %load/vec4 v0xbab2d2800_0; + %flag_set/vec4 8; + %jmp/0xz T_8.5, 8; + %load/vec4 v0xbab2d2a80_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_8.7, 4; + %load/vec4 v0xbab2d29e0_0; + %assign/vec4 v0xbab2d2580_0, 0; + %load/vec4 v0xbab2d29e0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_8.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2d2ee0_0, 0; + %jmp T_8.10; +T_8.9 ; + %load/vec4 v0xbab2d29e0_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_8.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2d2ee0_0, 0; + %jmp T_8.12; +T_8.11 ; + %load/vec4 v0xbab2d29e0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2d2ee0_0, 0; +T_8.12 ; +T_8.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2d2800_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2d2940_0, 0; + %jmp T_8.8; +T_8.7 ; + %load/vec4 v0xbab2d2620_0; + %assign/vec4 v0xbab2d2580_0, 0; + %load/vec4 v0xbab2d2a80_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2d2a80_0, 0; +T_8.8 ; +T_8.5 ; T_8.3 ; - %vpi_call/w 3 280 "$display", "==============================" {0 0 0}; - %vpi_call/w 3 281 "$display", "\000" {0 0 0}; - %vpi_call/w 3 283 "$finish" {0 0 0}; - %end; +T_8.1 ; + %jmp T_8; .thread T_8; + .scope S_0xbab2d5500; +T_9 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2db3e0_0; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2db340_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2dae40_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2db7a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2db0c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2db200_0, 0; + %jmp T_9.1; +T_9.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2db200_0, 0; + %load/vec4 v0xbab2db480_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.4, 9; + %load/vec4 v0xbab2db0c0_0; + %nor/r; + %and; +T_9.4; + %flag_set/vec4 8; + %jmp/0xz T_9.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2db340_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2dae40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2db0c0_0, 0; + %jmp T_9.3; +T_9.2 ; + %load/vec4 v0xbab2db0c0_0; + %flag_set/vec4 8; + %jmp/0xz T_9.5, 8; + %load/vec4 v0xbab2db340_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_9.7, 4; + %load/vec4 v0xbab2db2a0_0; + %assign/vec4 v0xbab2dae40_0, 0; + %load/vec4 v0xbab2db2a0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_9.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2db7a0_0, 0; + %jmp T_9.10; +T_9.9 ; + %load/vec4 v0xbab2db2a0_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_9.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2db7a0_0, 0; + %jmp T_9.12; +T_9.11 ; + %load/vec4 v0xbab2db2a0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2db7a0_0, 0; +T_9.12 ; +T_9.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2db0c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2db200_0, 0; + %jmp T_9.8; +T_9.7 ; + %load/vec4 v0xbab2daee0_0; + %assign/vec4 v0xbab2dae40_0, 0; + %load/vec4 v0xbab2db340_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2db340_0, 0; +T_9.8 ; +T_9.5 ; +T_9.3 ; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0xbab2dcd80; +T_10 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2e3ca0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2e3c00_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2e3700_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2e80a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2e3980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2e3ac0_0, 0; + %jmp T_10.1; +T_10.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2e3ac0_0, 0; + %load/vec4 v0xbab2e3d40_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_10.4, 9; + %load/vec4 v0xbab2e3980_0; + %nor/r; + %and; +T_10.4; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2e3c00_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2e3700_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2e3980_0, 0; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0xbab2e3980_0; + %flag_set/vec4 8; + %jmp/0xz T_10.5, 8; + %load/vec4 v0xbab2e3c00_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_10.7, 4; + %load/vec4 v0xbab2e3b60_0; + %assign/vec4 v0xbab2e3700_0, 0; + %load/vec4 v0xbab2e3b60_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_10.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2e80a0_0, 0; + %jmp T_10.10; +T_10.9 ; + %load/vec4 v0xbab2e3b60_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_10.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2e80a0_0, 0; + %jmp T_10.12; +T_10.11 ; + %load/vec4 v0xbab2e3b60_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2e80a0_0, 0; +T_10.12 ; +T_10.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2e3980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2e3ac0_0, 0; + %jmp T_10.8; +T_10.7 ; + %load/vec4 v0xbab2e37a0_0; + %assign/vec4 v0xbab2e3700_0, 0; + %load/vec4 v0xbab2e3c00_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2e3c00_0, 0; +T_10.8 ; +T_10.5 ; +T_10.3 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_0xbab2e4600; +T_11 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab2f85a0_0; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2f8500_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2f8000_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2f8960_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2f8280_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2f83c0_0, 0; + %jmp T_11.1; +T_11.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2f83c0_0, 0; + %load/vec4 v0xbab2f8640_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_11.4, 9; + %load/vec4 v0xbab2f8280_0; + %nor/r; + %and; +T_11.4; + %flag_set/vec4 8; + %jmp/0xz T_11.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab2f8500_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab2f8000_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2f8280_0, 0; + %jmp T_11.3; +T_11.2 ; + %load/vec4 v0xbab2f8280_0; + %flag_set/vec4 8; + %jmp/0xz T_11.5, 8; + %load/vec4 v0xbab2f8500_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_11.7, 4; + %load/vec4 v0xbab2f8460_0; + %assign/vec4 v0xbab2f8000_0, 0; + %load/vec4 v0xbab2f8460_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_11.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab2f8960_0, 0; + %jmp T_11.10; +T_11.9 ; + %load/vec4 v0xbab2f8460_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_11.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab2f8960_0, 0; + %jmp T_11.12; +T_11.11 ; + %load/vec4 v0xbab2f8460_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab2f8960_0, 0; +T_11.12 ; +T_11.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab2f8280_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab2f83c0_0, 0; + %jmp T_11.8; +T_11.7 ; + %load/vec4 v0xbab2f80a0_0; + %assign/vec4 v0xbab2f8000_0, 0; + %load/vec4 v0xbab2f8500_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab2f8500_0, 0; +T_11.8 ; +T_11.5 ; +T_11.3 ; +T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0xbab2e7d80; +T_12 ; + %wait E_0xbaad38ec0; + %load/vec4 v0xbab300e60_0; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab300dc0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab3008c0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab301220_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab300b40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab300c80_0, 0; + %jmp T_12.1; +T_12.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab300c80_0, 0; + %load/vec4 v0xbab300f00_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_12.4, 9; + %load/vec4 v0xbab300b40_0; + %nor/r; + %and; +T_12.4; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab300dc0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0xbab3008c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab300b40_0, 0; + %jmp T_12.3; +T_12.2 ; + %load/vec4 v0xbab300b40_0; + %flag_set/vec4 8; + %jmp/0xz T_12.5, 8; + %load/vec4 v0xbab300dc0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_12.7, 4; + %load/vec4 v0xbab300d20_0; + %assign/vec4 v0xbab3008c0_0, 0; + %load/vec4 v0xbab300d20_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_12.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab301220_0, 0; + %jmp T_12.10; +T_12.9 ; + %load/vec4 v0xbab300d20_0; + %cmpi/s 127, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_12.11, 5; + %pushi/vec4 127, 0, 16; + %assign/vec4 v0xbab301220_0, 0; + %jmp T_12.12; +T_12.11 ; + %load/vec4 v0xbab300d20_0; + %parti/s 16, 0, 2; + %assign/vec4 v0xbab301220_0, 0; +T_12.12 ; +T_12.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab300b40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab300c80_0, 0; + %jmp T_12.8; +T_12.7 ; + %load/vec4 v0xbab300960_0; + %assign/vec4 v0xbab3008c0_0, 0; + %load/vec4 v0xbab300dc0_0; + %addi 1, 0, 3; + %assign/vec4 v0xbab300dc0_0, 0; +T_12.8 ; +T_12.5 ; +T_12.3 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x102e305e0; +T_13 ; + %wait E_0xbaad3a100; + %load/vec4 v0xbab302260_0; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab302300_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab302080_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302120_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab301c20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab301ea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab301e00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab301fe0_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab301b80_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab301f40_0, 0; + %jmp T_13.1; +T_13.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302120_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab301e00_0, 0; + %load/vec4 v0xbab302300_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_13.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_13.3, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab302300_0, 0; + %jmp T_13.5; +T_13.2 ; + %load/vec4 v0xbab3021c0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.6, 8; + %load/vec4 v0xbab3024e0_0; + %assign/vec4 v0xbab301fe0_0, 0; + %load/vec4 v0xbab3019a0_0; + %assign/vec4 v0xbab301b80_0, 0; + %load/vec4 v0xbab302440_0; + %assign/vec4 v0xbab301f40_0, 0; + %load/vec4 v0xbab301ae0_0; + %assign/vec4 v0xbab301c20_0, 0; + %load/vec4 v0xbab3023a0_0; + %assign/vec4 v0xbab301ea0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab301e00_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0xbab302300_0, 0; +T_13.6 ; + %jmp T_13.5; +T_13.3 ; + %load/vec4 v0xbab301d60_0; + %flag_set/vec4 8; + %jmp/0xz T_13.8, 8; + %load/vec4 v0xbab301fe0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_13.10, 8; + %load/vec4 v0xbab301cc0_0; + %assign/vec4 v0xbab302080_0, 0; +T_13.10 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab302120_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab302300_0, 0; +T_13.8 ; + %jmp T_13.5; +T_13.5 ; + %pop/vec4 1; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x102e25b60; +T_14 ; + %wait E_0xbaad3a140; + %load/vec4 v0xbab302d00_0; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab302b20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302bc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302a80_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab302940_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab3029e0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0xbab302760_0, 0; + %pushi/vec4 0, 0, 32; + %store/vec4 v0xbab302800_0, 0, 32; +T_14.2 ; Top of for-loop + %load/vec4 v0xbab302800_0; + %cmpi/s 4096, 0, 32; + %jmp/0xz T_14.3, 5; + %pushi/vec4 0, 0, 16; + %ix/getv/s 3, v0xbab302800_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xbab3028a0, 0, 4; +T_14.4 ; for-loop step statement + %load/vec4 v0xbab302800_0; + %addi 1, 0, 32; + %store/vec4 v0xbab302800_0, 0, 32; + %jmp T_14.2; +T_14.3 ; for-loop exit label + %jmp T_14.1; +T_14.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302bc0_0, 0; + %load/vec4 v0xbab302620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_14.5, 8; + %load/vec4 v0xbab302c60_0; + %flag_set/vec4 8; + %jmp/0xz T_14.7, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab302620_0, 0; + %load/vec4 v0xbab302e40_0; + %assign/vec4 v0xbab302a80_0, 0; + %load/vec4 v0xbab302580_0; + %assign/vec4 v0xbab302940_0, 0; + %load/vec4 v0xbab302da0_0; + %assign/vec4 v0xbab3029e0_0, 0; + %pushi/vec4 2, 0, 32; + %assign/vec4 v0xbab302760_0, 0; +T_14.7 ; + %jmp T_14.6; +T_14.5 ; + %load/vec4 v0xbab302760_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_14.9, 5; + %load/vec4 v0xbab302760_0; + %subi 1, 0, 32; + %assign/vec4 v0xbab302760_0, 0; + %jmp T_14.10; +T_14.9 ; + %load/vec4 v0xbab302a80_0; + %flag_set/vec4 8; + %jmp/0xz T_14.11, 8; + %load/vec4 v0xbab302940_0; + %pad/u 32; + %cmpi/u 4096, 0, 32; + %jmp/0xz T_14.13, 5; + %load/vec4 v0xbab3029e0_0; + %ix/getv 3, v0xbab302940_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xbab3028a0, 0, 4; +T_14.13 ; + %jmp T_14.12; +T_14.11 ; + %load/vec4 v0xbab302940_0; + %pad/u 32; + %cmpi/u 4096, 0, 32; + %jmp/0xz T_14.15, 5; + %ix/getv 4, v0xbab302940_0; + %load/vec4a v0xbab3028a0, 4; + %assign/vec4 v0xbab302b20_0, 0; + %jmp T_14.16; +T_14.15 ; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab302b20_0, 0; +T_14.16 ; +T_14.12 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab302bc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab302620_0, 0; +T_14.10 ; +T_14.6 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0xbab306580; +T_15 ; + %wait E_0xbaad3a1c0; + %load/vec4 v0xbab309fe0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab30a080_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab3097c0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab309e00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309ea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309b80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309d60_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab309900_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab309cc0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3099a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab309c20_0, 0; + %jmp T_15.1; +T_15.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309ea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309b80_0, 0; + %load/vec4 v0xbab30a080_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_15.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_15.3, 6; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab30a080_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309b80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3099a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab309c20_0, 0; + %jmp T_15.5; +T_15.2 ; + %load/vec4 v0xbab309f40_0; + %flag_set/vec4 8; + %jmp/0xz T_15.6, 8; + %load/vec4 v0xbab309720_0; + %assign/vec4 v0xbab3097c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab309b80_0, 0; + %load/vec4 v0xbab30a1c0_0; + %assign/vec4 v0xbab309d60_0, 0; + %load/vec4 v0xbab309720_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %assign/vec4 v0xbab309900_0, 0; + %load/vec4 v0xbab309720_0; + %parti/s 1, 0, 2; + %cmpi/e 0, 0, 1; + %jmp/0xz T_15.8, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3099a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab309c20_0, 0; + %pushi/vec4 0, 0, 8; + %load/vec4 v0xbab30a120_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0xbab309cc0_0, 0; + %jmp T_15.9; +T_15.8 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3099a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab309c20_0, 0; + %load/vec4 v0xbab30a120_0; + %concati/vec4 0, 0, 8; + %assign/vec4 v0xbab309cc0_0, 0; +T_15.9 ; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0xbab30a080_0, 0; +T_15.6 ; + %jmp T_15.5; +T_15.3 ; + %load/vec4 v0xbab309ae0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.10, 8; + %load/vec4 v0xbab3097c0_0; + %parti/s 1, 0, 2; + %cmpi/e 0, 0, 1; + %jmp/0xz T_15.12, 4; + %load/vec4 v0xbab309a40_0; + %parti/s 8, 0, 2; + %assign/vec4 v0xbab309e00_0, 0; + %jmp T_15.13; +T_15.12 ; + %load/vec4 v0xbab309a40_0; + %parti/s 8, 8, 5; + %assign/vec4 v0xbab309e00_0, 0; +T_15.13 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab309ea0_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab30a080_0, 0; +T_15.10 ; + %jmp T_15.5; +T_15.5 ; + %pop/vec4 1; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0xbab306700; +T_16 ; + %wait E_0xbaad3a1c0; + %load/vec4 v0xbab3126c0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab312620_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0xbab312120_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab312a80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3123a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3124e0_0, 0; + %jmp T_16.1; +T_16.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3124e0_0, 0; + %load/vec4 v0xbab312760_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_16.4, 9; + %load/vec4 v0xbab3123a0_0; + %nor/r; + %and; +T_16.4; + %flag_set/vec4 8; + %jmp/0xz T_16.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab312620_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0xbab312120_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3123a0_0, 0; + %jmp T_16.3; +T_16.2 ; + %load/vec4 v0xbab3123a0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.5, 8; + %load/vec4 v0xbab312620_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_16.7, 4; + %load/vec4 v0xbab312580_0; + %assign/vec4 v0xbab312120_0, 0; + %load/vec4 v0xbab312580_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_16.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab312a80_0, 0; + %jmp T_16.10; +T_16.9 ; + %load/vec4 v0xbab312580_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_16.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0xbab312a80_0, 0; + %jmp T_16.12; +T_16.11 ; + %load/vec4 v0xbab312580_0; + %parti/s 8, 0, 2; + %assign/vec4 v0xbab312a80_0, 0; +T_16.12 ; +T_16.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3123a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3124e0_0, 0; + %jmp T_16.8; +T_16.7 ; + %load/vec4 v0xbab3121c0_0; + %assign/vec4 v0xbab312120_0, 0; + %load/vec4 v0xbab312620_0; + %addi 1, 0, 2; + %assign/vec4 v0xbab312620_0, 0; +T_16.8 ; +T_16.5 ; +T_16.3 ; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x102e25ce0; +T_17 ; + %wait E_0xbaad3a1c0; + %load/vec4 v0xbab31c0a0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0xbab313980_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab313700_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab313480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3135c0_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab313520_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab313f20_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab31c640_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3137a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3138e0_0, 0; + %jmp T_17.1; +T_17.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab313480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab313f20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3138e0_0, 0; + %load/vec4 v0xbab31c1e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_17.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_17.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_17.6, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_17.7, 6; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3137a0_0, 0; + %jmp T_17.9; +T_17.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3137a0_0, 0; + %load/vec4 v0xbab31c140_0; + %flag_set/vec4 8; + %jmp/0xz T_17.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3137a0_0, 0; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0xbab313980_0, 0; + %load/vec4 v0xbab31c460_0; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3135c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313480_0, 0; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; +T_17.10 ; + %jmp T_17.9; +T_17.3 ; + %load/vec4 v0xbab3133e0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.12, 8; + %load/vec4 v0xbab313340_0; + %load/vec4 v0xbab313980_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xbab31c5a0, 0, 4; + %load/vec4 v0xbab313980_0; + %pad/u 32; + %cmpi/e 31, 0, 32; + %jmp/0xz T_17.14, 4; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0xbab313980_0, 0; + %load/vec4 v0xbab31c280_0; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3135c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313480_0, 0; + %pushi/vec4 2, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; + %jmp T_17.15; +T_17.14 ; + %load/vec4 v0xbab313980_0; + %addi 1, 0, 6; + %assign/vec4 v0xbab313980_0, 0; + %load/vec4 v0xbab31c460_0; + %load/vec4 v0xbab313980_0; + %pad/u 22; + %add; + %addi 1, 0, 22; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313480_0, 0; +T_17.15 ; +T_17.12 ; + %jmp T_17.9; +T_17.4 ; + %load/vec4 v0xbab3133e0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.16, 8; + %load/vec4 v0xbab313340_0; + %load/vec4 v0xbab313980_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xbab31c3c0, 0, 4; + %load/vec4 v0xbab313980_0; + %pad/u 32; + %cmpi/e 31, 0, 32; + %jmp/0xz T_17.18, 4; + %load/vec4 v0xbab313660_0; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3135c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313480_0, 0; + %pushi/vec4 3, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; + %jmp T_17.19; +T_17.18 ; + %load/vec4 v0xbab313980_0; + %addi 1, 0, 6; + %assign/vec4 v0xbab313980_0, 0; + %load/vec4 v0xbab31c280_0; + %load/vec4 v0xbab313980_0; + %pad/u 22; + %add; + %addi 1, 0, 22; + %assign/vec4 v0xbab312e40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313480_0, 0; +T_17.19 ; +T_17.16 ; + %jmp T_17.9; +T_17.5 ; + %load/vec4 v0xbab3133e0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.20, 8; + %load/vec4 v0xbab313340_0; + %assign/vec4 v0xbab313700_0, 0; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; +T_17.20 ; + %jmp T_17.9; +T_17.6 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab313f20_0, 0; + %pushi/vec4 5, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; + %jmp T_17.9; +T_17.7 ; + %load/vec4 v0xbab313e80_0; + %flag_set/vec4 8; + %jmp/0xz T_17.22, 8; + %load/vec4 v0xbab31c000_0; + %assign/vec4 v0xbab31c640_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3137a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3138e0_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0xbab31c1e0_0, 0; +T_17.22 ; + %jmp T_17.9; +T_17.9 ; + %pop/vec4 1; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x102e23ae0; +T_18 ; + %wait E_0xbaad3a440; + %load/vec4 v0xbab31d540_0; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab31c780_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab31d720_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d7c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31caa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d680_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab31cc80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31cd20_0, 0; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0xbab31d040_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0xbab31ca00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %jmp T_18.1; +T_18.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31cd20_0, 0; + %load/vec4 v0xbab31d5e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_18.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_18.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_18.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_18.5, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_18.6, 6; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31caa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d680_0, 0; + %jmp T_18.8; +T_18.2 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %load/vec4 v0xbab31c8c0_0; + %pad/u 32; + %cmpi/e 11999, 0, 32; + %jmp/0xz T_18.9, 4; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %jmp T_18.10; +T_18.9 ; + %load/vec4 v0xbab31c8c0_0; + %addi 1, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; +T_18.10 ; + %jmp T_18.8; +T_18.3 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %load/vec4 v0xbab31cdc0_0; + %flag_set/vec4 8; + %jmp/0xz T_18.11, 8; + %load/vec4 v0xbab31cb40_0; + %assign/vec4 v0xbab31c780_0, 0; + %load/vec4 v0xbab31cf00_0; + %assign/vec4 v0xbab31d720_0, 0; + %load/vec4 v0xbab31cfa0_0; + %assign/vec4 v0xbab31d7c0_0, 0; + %load/vec4 v0xbab31cbe0_0; + %assign/vec4 v0xbab31caa0_0, 0; + %load/vec4 v0xbab31ce60_0; + %assign/vec4 v0xbab31d680_0, 0; + %load/vec4 v0xbab31cb40_0; + %assign/vec4 v0xbab31d040_0, 0; + %load/vec4 v0xbab31cbe0_0; + %assign/vec4 v0xbab31d220_0, 0; + %load/vec4 v0xbab31ce60_0; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %load/vec4 v0xbab31cfa0_0; + %flag_set/vec4 8; + %jmp/0xz T_18.13, 8; + %load/vec4 v0xbab31cf00_0; + %assign/vec4 v0xbab31ca00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %jmp T_18.14; +T_18.13 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; +T_18.14 ; +T_18.11 ; + %jmp T_18.8; +T_18.4 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %load/vec4 v0xbab31caa0_0; + %assign/vec4 v0xbab31d220_0, 0; + %load/vec4 v0xbab31d680_0; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %load/vec4 v0xbab31c8c0_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_18.15, 4; + %load/vec4 v0xbab31d180_0; + %assign/vec4 v0xbab31cc80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31cd20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %jmp T_18.16; +T_18.15 ; + %load/vec4 v0xbab31c8c0_0; + %addi 1, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; +T_18.16 ; + %jmp T_18.8; +T_18.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %load/vec4 v0xbab31caa0_0; + %assign/vec4 v0xbab31d220_0, 0; + %load/vec4 v0xbab31d680_0; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %load/vec4 v0xbab31c8c0_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_18.17, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %jmp T_18.18; +T_18.17 ; + %load/vec4 v0xbab31c8c0_0; + %addi 1, 0, 14; + %assign/vec4 v0xbab31c8c0_0, 0; +T_18.18 ; + %jmp T_18.8; +T_18.6 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d400_0, 0; + %load/vec4 v0xbab31caa0_0; + %assign/vec4 v0xbab31d220_0, 0; + %load/vec4 v0xbab31d680_0; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d4a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab31c960_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31d360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab31cd20_0, 0; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xbab31d5e0_0, 0; + %jmp T_18.8; +T_18.8 ; + %pop/vec4 1; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0xbab319e00; +T_19 ; + %wait E_0xbaad3a480; + %load/vec4 v0xbab321cc0_0; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab321c20_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0xbab321720_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab322080_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3219a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab321ae0_0, 0; + %jmp T_19.1; +T_19.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab321ae0_0, 0; + %load/vec4 v0xbab321d60_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_19.4, 9; + %load/vec4 v0xbab3219a0_0; + %nor/r; + %and; +T_19.4; + %flag_set/vec4 8; + %jmp/0xz T_19.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0xbab321c20_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0xbab321720_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab3219a0_0, 0; + %jmp T_19.3; +T_19.2 ; + %load/vec4 v0xbab3219a0_0; + %flag_set/vec4 8; + %jmp/0xz T_19.5, 8; + %load/vec4 v0xbab321c20_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_19.7, 4; + %load/vec4 v0xbab321b80_0; + %assign/vec4 v0xbab321720_0, 0; + %load/vec4 v0xbab321b80_0; + %cmpi/s 0, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_19.9, 5; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xbab322080_0, 0; + %jmp T_19.10; +T_19.9 ; + %load/vec4 v0xbab321b80_0; + %cmpi/s 127, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_19.11, 5; + %pushi/vec4 127, 0, 8; + %assign/vec4 v0xbab322080_0, 0; + %jmp T_19.12; +T_19.11 ; + %load/vec4 v0xbab321b80_0; + %parti/s 8, 0, 2; + %assign/vec4 v0xbab322080_0, 0; +T_19.12 ; +T_19.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0xbab3219a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0xbab321ae0_0, 0; + %jmp T_19.8; +T_19.7 ; + %load/vec4 v0xbab3217c0_0; + %assign/vec4 v0xbab321720_0, 0; + %load/vec4 v0xbab321c20_0; + %addi 1, 0, 2; + %assign/vec4 v0xbab321c20_0, 0; +T_19.8 ; +T_19.5 ; +T_19.3 ; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x102e23c60; +T_20 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xbab322260_0, 0, 1; +T_20.0 ; + %delay 5000, 0; + %load/vec4 v0xbab322260_0; + %inv; + %store/vec4 v0xbab322260_0, 0, 1; + %jmp T_20.0; +T_20.1 ; + %end; + .thread T_20; + .scope S_0x102e23c60; +T_21 ; + %vpi_call/w 12 233 "$dumpfile", "sim/neuron_parallel.vcd" {0 0 0}; + %vpi_call/w 12 234 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x102e23c60 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0xbab3224e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xbab322580_0, 0, 1; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab3226c0_0, 0, 256; + %pushi/vec4 0, 0, 256; + %store/vec4 v0xbab322620_0, 0, 256; + %pushi/vec4 0, 0, 8; + %store/vec4 v0xbab322120_0, 0, 8; + %pushi/vec4 0, 0, 32; + %store/vec4 v0xbab3223a0_0, 0, 32; + %pushi/vec4 2, 0, 32; +T_21.0 %dup/vec4; + %cmpi/s 0, 0, 32; + %jmp/1xz T_21.1, 5; + %jmp/1 T_21.1, 4; + %subi 1, 0, 32; + %wait E_0xbaad3a480; + %jmp T_21.0; +T_21.1 ; + %pop/vec4 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xbab3224e0_0, 0, 1; + %vpi_call/w 12 247 "$display", "\000" {0 0 0}; + %vpi_call/w 12 248 "$display", "==============================" {0 0 0}; + %vpi_call/w 12 249 "$display", "NEURON_PARALLEL TESTBENCH (INT8)" {0 0 0}; + %vpi_call/w 12 250 "$display", "==============================" {0 0 0}; + %fork TD_tb.test_1, S_0xbab325680; + %join; + %fork TD_tb.test_2, S_0xbab325800; + %join; + %fork TD_tb.test_3, S_0xbab325980; + %join; + %fork TD_tb.test_4, S_0xbab325b00; + %join; + %vpi_call/w 12 257 "$display", "\000" {0 0 0}; + %vpi_call/w 12 258 "$display", "==============================" {0 0 0}; + %load/vec4 v0xbab3223a0_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_21.2, 4; + %vpi_call/w 12 261 "$display", "ALL TESTS PASSED" {0 0 0}; + %jmp T_21.3; +T_21.2 ; + %vpi_call/w 12 264 "$display", "FAILURES = %0d", v0xbab3223a0_0 {0 0 0}; +T_21.3 ; + %vpi_call/w 12 267 "$display", "==============================" {0 0 0}; + %vpi_call/w 12 268 "$display", "\000" {0 0 0}; + %vpi_call/w 12 270 "$finish" {0 0 0}; + %end; + .thread T_21; # The file index is used to find the file name in the following table. -:file_names 7; +:file_names 13; "N/A"; ""; "-"; - "sim/neuron_parallel_tb.v"; + "rtl/layer.v"; "rtl/neuron_parallel.v"; "rtl/mac8.v"; "rtl/mac_unit.v"; + "rtl/memory_interface.v"; + "rtl/memory_model.v"; + "rtl/neuron_memory.v"; + "rtl/int8_memory_access.v"; + "rtl/psram_controller.v"; + "sim/neuron_parallel_tb.v";