feat: real N=16 hybrid systolic top-level, synthesis-only pass (EXP-0091)

Adds n16_system_ddr3_top.v, directly adapted from n2_system_ddr3_top.v's
own proven structure: same real MIG, spi_host_bridge_v3.v, flash_spi_
master.v, host_mem_bridge.v, all completely unmodified (confirms
EXP-0090's zero-protocol-change finding holds at full N=16 scale). The
real differences: neural_director_grouped.v replaces neural_director_
packed.v, 4x systolic_group.v replace 2x packed_slot.v, and the shared
arbiter grows to a real 21-way NUM_REQ (4 group weight-fetch + 16 PE
activation/writeback + 1 host_mem_bridge).

Real synthesis-only result: 0 Errors, 0 Critical Warnings, 128 DSP48E1
of 240 (53.33%) -- an exact real match to docs/ARCHITECTURE_ANALYSIS.md
S5.6's own original brainstorm DSP projection, now confirmed by real
synthesis instead of estimated.

Found and root-caused a real Vivado project quirk (not an RTL bug --
verified separately via a clean Icarus elaboration with stub modules
for mig_7series_0/STARTUPE2): a fresh add_files + update_compile_order
didn't make synth_design -top <newmodule> find the module. Fixed by
explicitly setting the fileset's own top property before synth_design.
CLAUDE.md updated with this as the real, confirmed procedure for adding
any future brand-new top-level module.

Honestly scoped: synthesis-only (connectivity/width correctness), NOT
yet a real functional xsim test and NOT yet real P&R timing -- both
real, disclosed next steps.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/logs/experiments.log

@@ -6171,3 +6171,72 @@ spi_host_bridge_v3.v (no changes needed, per Part 2's own real finding)
 next_action: build the real N=16 top-level, verify it end-to-end (real
 xsim against the real DDR3 model, matching this project's own
 established multi-level verification discipline), then real P&R.
+
+EXP-0091 -- real N=16 (4x4 hybrid systolic) top-level: synthesis-only
+check PASSES, real utilization confirms the original DSP projection
+exactly (2026-09-21, continuing "Ok procedi ad implementare quel che
+manca")
+
+CONTEXT: EXP-0089 (systolic_group.v/packed_pe.v) and EXP-0090
+(neural_director_grouped.v) built and separately verified the two new
+real subsystems this architecture needs. The remaining real gap was a
+top-level module actually wiring everything together at N=16 scale.
+
+NEW MODULE: `n16_system_ddr3_top.v`, directly adapted from n2_system_
+ddr3_top.v's own real, proven structure -- same real MIG public
+wrapper, same spi_host_bridge_v3.v, flash_spi_master.v, host_mem_
+bridge.v, ALL instantiated completely unmodified (confirms EXP-0090's
+own real finding: the host SPI/WRITE_JOB protocol needs zero changes
+at N=16). The only real differences: neural_director_grouped.v
+replaces neural_director_packed.v, 4x systolic_group.v replace 2x
+packed_slot.v, and the shared arbiter grows from NUM_REQ=3 to
+NUM_REQ=21 (4 groups' own weight-fetch requesters at slots 0-3, the 16
+PEs' own activation-fetch+writeback requesters at slots 4-19 -- 4
+consecutive slots per group -- and host_mem_bridge.v at slot 20).
+N_SLOTS=16 (the real total parallel-PE count) is passed to spi_host_
+bridge_v3.v purely for its own informational REG_READ(0x03) -- that
+parameter never gates any real control logic there.
+
+REAL VIVADO PROJECT QUIRK FOUND (not an RTL bug -- confirmed
+separately): adding these 4 new files via `add_files` + `update_
+compile_order` and then calling `synth_design -top n16_system_ddr3_
+top` failed immediately with "module 'n16_system_ddr3_top' not found",
+despite the file being correctly present, enabled, and marked
+`USED_IN: synthesis` in the project. Before assuming an RTL bug,
+verified the RTL itself independently: a clean Icarus elaboration of
+n16_system_ddr3_top.v and every real dependency (using two small stub
+modules for the real Xilinx primitives Icarus can't resolve on its
+own, mig_7series_0 and STARTUPE2) completed with **0 errors** --
+proving the RTL was correct all along and the issue was Vivado's own
+project state. Fix: explicitly `set_property top n16_system_ddr3_top
+$fileset` BEFORE calling `synth_design -top ...` (rather than relying
+on the `-top` command-line override alone) -- real, reproducible fix,
+now the confirmed real procedure for adding any brand-new top-level
+module to this project going forward.
+
+REAL RESULT: **synth_design completed successfully, 0 Errors, 0
+Critical Warnings, 108 Warnings** (all real and expected -- e.g.
+result_writeback.v's own `ctrl_rdata` being unused, since that module
+is write-only by design, already known/expected since EXP-0088, not
+new). Real utilization: **128 DSP48E1 / 240 (53.33%)** -- an EXACT
+real match to docs/ARCHITECTURE_ANALYSIS.md S5.6's own original
+brainstorm projection ("16 cores x 8 DSP/core = 128/240, 53%"), now
+confirmed by real synthesis, not a projection any more. 20053 LUTs
+(31.63%), real, healthy headroom remaining on this part.
+
+DECISION: real, verified third step. This is SYNTHESIS-ONLY --
+honestly disclosed, NOT yet a real P&R signoff (no place_design/
+route_design run, no real timing number for this design) and NOT yet
+a real functional xsim test (the sub-modules are separately verified,
+but this top-level's own bus-slicing/arbiter-wiring correctness --
+the same class of bug already found and fixed twice this session in
+similar flattened-bus contexts -- has only been checked for
+SYNTAX/CONNECTIVITY validity via synthesis succeeding, not for
+FUNCTIONAL correctness).
+
+next_action: (1) a real functional xsim test (mirroring tb_n2_system_
+ddr3.v's own real-DDR3-model methodology, scaled to submit octets
+across all 4 groups and verify all 16 real results) before trusting
+this design at all -- synthesis succeeding proves connectivity, not
+correctness. (2) real, full P&R (place_design + route_design) for a
+real timing signoff, only after (1) passes.