feat: real N=16 hybrid systolic top-level, synthesis-only pass (EXP-0091)

Adds n16_system_ddr3_top.v, directly adapted from n2_system_ddr3_top.v's
own proven structure: same real MIG, spi_host_bridge_v3.v, flash_spi_
master.v, host_mem_bridge.v, all completely unmodified (confirms
EXP-0090's zero-protocol-change finding holds at full N=16 scale). The
real differences: neural_director_grouped.v replaces neural_director_
packed.v, 4x systolic_group.v replace 2x packed_slot.v, and the shared
arbiter grows to a real 21-way NUM_REQ (4 group weight-fetch + 16 PE
activation/writeback + 1 host_mem_bridge).

Real synthesis-only result: 0 Errors, 0 Critical Warnings, 128 DSP48E1
of 240 (53.33%) -- an exact real match to docs/ARCHITECTURE_ANALYSIS.md
S5.6's own original brainstorm DSP projection, now confirmed by real
synthesis instead of estimated.

Found and root-caused a real Vivado project quirk (not an RTL bug --
verified separately via a clean Icarus elaboration with stub modules
for mig_7series_0/STARTUPE2): a fresh add_files + update_compile_order
didn't make synth_design -top <newmodule> find the module. Fixed by
explicitly setting the fileset's own top property before synth_design.
CLAUDE.md updated with this as the real, confirmed procedure for adding
any future brand-new top-level module.

Honestly scoped: synthesis-only (connectivity/width correctness), NOT
yet a real functional xsim test and NOT yet real P&R timing -- both
real, disclosed next steps.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -659,7 +659,7 @@ specifically to document where/how it breaks rather than to succeed):
 
 ---
 
-### 5.6 [Steps 1–2 DONE, EXP-0089/0090] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
+### 5.6 [Steps 1–3 DONE, EXP-0089/0090/0091] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
 
 Captured from a 2026-09-20 brainstorming session as a purely exploratory
 idea; the same day, per the user's own explicit reprioritization, the real
@@ -671,8 +671,7 @@ systolic shift register) was resolved with the user directly (not guessed).
   xsim-verified (8/8 PASS across 2 consecutive group jobs).
 - Real out-of-context synthesis of one group (EXP-0090): **32 DSP48E1**
   (13.3%), confirming the original brainstorm's own quantified DSP
-  projection exactly (8 DSP/PE × 4 PEs = 32; scaled to 4 groups, 128/240 =
-  53%, matching the doc's own earlier estimate).
+  projection exactly (8 DSP/PE × 4 PEs = 32).
 - `neural_director_grouped.v` (EXP-0090) — real Director extension
   dispatching 8-position octets to free groups, a direct extension of
   `neural_director_packed.v`'s own already-proven 2-position pairing
@@ -684,10 +683,25 @@ systolic shift register) was resolved with the user directly (not guessed).
   surfaced a real, generalizable testbench-race lesson (tight back-to-
   back stimulus pulses on the same edge the DUT samples on — fixed with
   `@(negedge clk)` stimulus — see CLAUDE.md).
+- `n16_system_ddr3_top.v` (EXP-0091) — real N=16 top-level, directly
+  adapted from `n2_system_ddr3_top.v`'s own proven structure (same real
+  MIG, `spi_host_bridge_v3.v`, `flash_spi_master.v`, `host_mem_bridge.v`,
+  all completely unmodified — confirms the zero-protocol-change finding
+  above holds at full scale too), 4× `systolic_group.v` + `neural_
+  director_grouped.v` + a new 21-way arbiter (4 group weight-fetch + 16
+  PE activation/writeback + 1 host_mem_bridge). **Real synthesis-only
+  result: 0 Errors, 128 DSP48E1/240 (53.33%)** — an exact real match to
+  this section's own original DSP projection, now confirmed by real
+  synthesis rather than estimated.
 
-**Not yet done**: a real N=16 (4-group) top-level module + a real,
-appropriately-sized arbiter, and real in-context P&R for the whole system
-— see EXP-0090's own `next_action`.
+**Not yet done, real and disclosed**: this top-level has only been
+checked for **synthesis-level connectivity**, NOT yet for **functional
+correctness** (a real xsim test against the real DDR3 model, exercising
+all 4 groups, is the next real step — the same class of bus-slicing bug
+already found and fixed twice this session in similar flattened-bus
+contexts could still be lurking here undetected by synthesis alone) and
+NOT yet for **real timing** (no place_design/route_design run yet) — see
+EXP-0091's own `next_action`.
 
 **The problem it targets**: plain N=16 independent cores (§5.5's own
 "documentary, expected to break" framing) means 16 independent DDR3