feat: real N=16 hybrid systolic top-level, synthesis-only pass (EXP-0091)

Adds n16_system_ddr3_top.v, directly adapted from n2_system_ddr3_top.v's
own proven structure: same real MIG, spi_host_bridge_v3.v, flash_spi_
master.v, host_mem_bridge.v, all completely unmodified (confirms
EXP-0090's zero-protocol-change finding holds at full N=16 scale). The
real differences: neural_director_grouped.v replaces neural_director_
packed.v, 4x systolic_group.v replace 2x packed_slot.v, and the shared
arbiter grows to a real 21-way NUM_REQ (4 group weight-fetch + 16 PE
activation/writeback + 1 host_mem_bridge).

Real synthesis-only result: 0 Errors, 0 Critical Warnings, 128 DSP48E1
of 240 (53.33%) -- an exact real match to docs/ARCHITECTURE_ANALYSIS.md
S5.6's own original brainstorm DSP projection, now confirmed by real
synthesis instead of estimated.

Found and root-caused a real Vivado project quirk (not an RTL bug --
verified separately via a clean Icarus elaboration with stub modules
for mig_7series_0/STARTUPE2): a fresh add_files + update_compile_order
didn't make synth_design -top <newmodule> find the module. Fixed by
explicitly setting the fileset's own top property before synth_design.
CLAUDE.md updated with this as the real, confirmed procedure for adding
any future brand-new top-level module.

Honestly scoped: synthesis-only (connectivity/width correctness), NOT
yet a real functional xsim test and NOT yet real P&R timing -- both
real, disclosed next steps.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

CLAUDE.md

@@ -70,6 +70,17 @@ unmodified by v3, e.g. `layer_prefetch_ctrl.v`/`layer_weight_buffer.v`).
   [get_filesets sources_1]` and `constrs_1`) for `*/imports/*` paths
   before trusting the next P&R — don't assume only the previously-fixed
   files are still direct references.
+- **Adding a brand-new TOP-LEVEL module** (not just a sub-module) to the
+  project: `add_files` + `update_compile_order` alone did NOT make
+  `synth_design -top <newmodule>` find it (EXP-0091) — failed with
+  "module '<newmodule>' not found" even though the file was correctly
+  present, `IS_ENABLED`, and `USED_IN: synthesis`. Before assuming an RTL
+  bug, verify the RTL independently first (a clean Icarus elaboration
+  with small stub modules for any real Xilinx primitives it can't resolve,
+  e.g. `mig_7series_0`/`STARTUPE2`, is enough to rule that out cheaply).
+  Real fix: explicitly `set_property top <newmodule> [get_filesets
+  sources_1]` *before* calling `synth_design -top ...` — the `-top`
+  command-line flag alone wasn't sufficient this time.
 - **Testbench stimulus must use nonblocking assignment (`<=`), not blocking
   (`=`), when driving a DUT's inputs from a separate `always`/`initial`
   block.** Blocking assignment races the DUT's own `posedge`-triggered