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test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014)

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Post-M10, user-requested final benchmark campaign: 6 realistic
workloads (16-256 independent neurons in a shared-input dense-layer
shape, a random-seeded 2-layer network with real cross-node PSRAM
forwarding, and a 6-node 2-hop dependency diamond) x 4 concurrency
levels (N_SLOTS=1/2/4/8) through the real, full neural_multiprocessor
system (real V1 PSRAM chain, real slot_mem_arbiter). 24/24 runs PASS
bit-exact against a software golden model (11,520 individual neuron/
node checks, zero mismatches).

Three real bugs found and fixed during the campaign itself (ERR-0009):
1. neural_director.v (M5) had a real RTL bug at N_SLOTS=1
   ($clog2(1)=0 makes a replication expression illegal) - never
   caught because M5-M10 only ever tested N_SLOTS=2/4/8. Fixed with
   a width-agnostic '0 literal; M5's own testbench re-verified
   unaffected.
2/3. Two testbench sizing bugs in tb_benchmark_suite.v itself
   (psram_model DEPTH too small for the Large workload's address
   range; N_NODES too small for the Stress workload's node-id range,
   causing a real deadlock via node-id wraparound colliding with an
   already-DISPATCHED node - a real, honest consequence of DEC-0008's
   own "no node-slot reclamation" design choice).

Headline finding: real parallel scaling is essentially flat beyond
N_SLOTS=2 - the single shared PSRAM port saturates at ~91%
utilization regardless of slot count, so memory-bound workloads gain
only 1.05-1.06x real speedup from N=1 to N=8. Once real POST-P&R Fmax
degradation is also factored in, N_SLOTS=4 is measurably 21% SLOWER
in real wall-clock time than N_SLOTS=1 for the largest workload
tested. N_SLOTS=2 is recommended as the default (DEC-0014,
superseding DEC-0012's resource-only "N_SLOTS=8 ceiling" framing for
general use).

Full 21-section report (every number classified THEORETICAL/
SIMULATED/POST-P&R MEASURED/DERIVED, per the user's own
methodology requirements): hardware/v2/docs/benchmarks/
final-benchmark.md

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0014)/
experiments (EXP-0014)/errors (ERR-0009)/development.log,
ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 19:58:30 +02:00
co-authored by Claude Sonnet 5
parent 91bbbe2fe5
commit 3cdaeaee35
12 changed files with 1369 additions and 4 deletions
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hardware/v2/rtl/neural_director.v
+11 -4
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@@ -104,11 +104,18 @@ module neural_director #(
wire any_slot_free = |slot_free;
// first-free slot index (priority encoder, lowest index wins --
// "first-free", per §9's initial policy, not load-balanced)
// "first-free", per §9's initial policy, not load-balanced).
// Reset/default values below use '0 rather than
// {$clog2(N_SLOTS){1'b0}} -- at N_SLOTS=1, $clog2(1)=0 makes that
// replication a ZERO-width replication, illegal outside a
// concatenation (IEEE 1800 11.4.12.1); found when this module was
// first synthesized/simulated at N_SLOTS=1 by the post-M10
// benchmark campaign (never exercised at N_SLOTS=1 through M5-M9).
// '0 self-sizes correctly for any width, including 0.
reg [$clog2(N_SLOTS)-1:0] free_slot_idx;
integer fi;
always @(*) begin
free_slot_idx = {$clog2(N_SLOTS){1'b0}};
free_slot_idx = '0;
for (fi = N_SLOTS-1; fi >= 0; fi = fi - 1) begin
if (slot_free[fi]) free_slot_idx = fi[$clog2(N_SLOTS)-1:0];
end
@@ -122,7 +129,7 @@ module neural_director #(
reg [$clog2(N_SLOTS)-1:0] done_slot_idx;
integer di;
always @(*) begin
done_slot_idx = {$clog2(N_SLOTS){1'b0}};
done_slot_idx = '0;
for (di = N_SLOTS-1; di >= 0; di = di - 1) begin
if (slot_job_done[di]) done_slot_idx = di[$clog2(N_SLOTS)-1:0];
end
@@ -143,7 +150,7 @@ module neural_director #(
slot_result_addr <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
slot_node_id <= {(16*N_SLOTS){1'b0}};
job_out_done <= 1'b0;
job_out_slot <= {$clog2(N_SLOTS){1'b0}};
job_out_slot <= '0;
end else begin
slot_job_start <= {N_SLOTS{1'b0}};
job_out_done <= 1'b0;