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test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014)

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Post-M10, user-requested final benchmark campaign: 6 realistic
workloads (16-256 independent neurons in a shared-input dense-layer
shape, a random-seeded 2-layer network with real cross-node PSRAM
forwarding, and a 6-node 2-hop dependency diamond) x 4 concurrency
levels (N_SLOTS=1/2/4/8) through the real, full neural_multiprocessor
system (real V1 PSRAM chain, real slot_mem_arbiter). 24/24 runs PASS
bit-exact against a software golden model (11,520 individual neuron/
node checks, zero mismatches).

Three real bugs found and fixed during the campaign itself (ERR-0009):
1. neural_director.v (M5) had a real RTL bug at N_SLOTS=1
   ($clog2(1)=0 makes a replication expression illegal) - never
   caught because M5-M10 only ever tested N_SLOTS=2/4/8. Fixed with
   a width-agnostic '0 literal; M5's own testbench re-verified
   unaffected.
2/3. Two testbench sizing bugs in tb_benchmark_suite.v itself
   (psram_model DEPTH too small for the Large workload's address
   range; N_NODES too small for the Stress workload's node-id range,
   causing a real deadlock via node-id wraparound colliding with an
   already-DISPATCHED node - a real, honest consequence of DEC-0008's
   own "no node-slot reclamation" design choice).

Headline finding: real parallel scaling is essentially flat beyond
N_SLOTS=2 - the single shared PSRAM port saturates at ~91%
utilization regardless of slot count, so memory-bound workloads gain
only 1.05-1.06x real speedup from N=1 to N=8. Once real POST-P&R Fmax
degradation is also factored in, N_SLOTS=4 is measurably 21% SLOWER
in real wall-clock time than N_SLOTS=1 for the largest workload
tested. N_SLOTS=2 is recommended as the default (DEC-0014,
superseding DEC-0012's resource-only "N_SLOTS=8 ceiling" framing for
general use).

Full 21-section report (every number classified THEORETICAL/
SIMULATED/POST-P&R MEASURED/DERIVED, per the user's own
methodology requirements): hardware/v2/docs/benchmarks/
final-benchmark.md

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0014)/
experiments (EXP-0014)/errors (ERR-0009)/development.log,
ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 19:58:30 +02:00
co-authored by Claude Sonnet 5
parent 91bbbe2fe5
commit 3cdaeaee35
12 changed files with 1369 additions and 4 deletions
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hardware/v2/logs/timing.log
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@@ -101,3 +101,17 @@ Conclusion: over 6 real placement seeds, ACC_WIDTH=24 has a HIGHER
EXP-0002's single-seed result (176.21 < 183.12, i.e. ACC=24 looked
WORSE) was placement-seed noise, not a real trend. See decisions.log
DEC-0013.
[2026-09-05] EXP-0014 -- neural_multiprocessor N_SLOTS=1 and N_SLOTS=4
(final benchmark campaign), real nextpnr-ecp5 --45k --package CABGA381
--speed 8 --freq 80 --lpf-allow-unconstrained
N_SLOTS=1: Fmax = 152.46 MHz -- PASS at 80MHz
N_SLOTS=4: Fmax = 113.38 MHz -- PASS at 80MHz
(N_SLOTS=2 reference, EXP-0009: 142.45 MHz)
Full real N_SLOTS sweep for the complete system (dataflow_core + real
V1 PSRAM chain + slot_mem_arbiter): 1 -> 152.46 MHz, 2 -> 142.45 MHz,
4 -> 113.38 MHz. Fmax falls monotonically as N_SLOTS grows (more
routing congestion around the shared director/dependency_manager/
arbiter hub), exactly the same trend already observed for
dataflow_core alone (M7/M10, EXP-0008/EXP-0011) but now measured for
the REAL FULL SYSTEM including the real PSRAM backend.