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test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014)

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Post-M10, user-requested final benchmark campaign: 6 realistic
workloads (16-256 independent neurons in a shared-input dense-layer
shape, a random-seeded 2-layer network with real cross-node PSRAM
forwarding, and a 6-node 2-hop dependency diamond) x 4 concurrency
levels (N_SLOTS=1/2/4/8) through the real, full neural_multiprocessor
system (real V1 PSRAM chain, real slot_mem_arbiter). 24/24 runs PASS
bit-exact against a software golden model (11,520 individual neuron/
node checks, zero mismatches).

Three real bugs found and fixed during the campaign itself (ERR-0009):
1. neural_director.v (M5) had a real RTL bug at N_SLOTS=1
   ($clog2(1)=0 makes a replication expression illegal) - never
   caught because M5-M10 only ever tested N_SLOTS=2/4/8. Fixed with
   a width-agnostic '0 literal; M5's own testbench re-verified
   unaffected.
2/3. Two testbench sizing bugs in tb_benchmark_suite.v itself
   (psram_model DEPTH too small for the Large workload's address
   range; N_NODES too small for the Stress workload's node-id range,
   causing a real deadlock via node-id wraparound colliding with an
   already-DISPATCHED node - a real, honest consequence of DEC-0008's
   own "no node-slot reclamation" design choice).

Headline finding: real parallel scaling is essentially flat beyond
N_SLOTS=2 - the single shared PSRAM port saturates at ~91%
utilization regardless of slot count, so memory-bound workloads gain
only 1.05-1.06x real speedup from N=1 to N=8. Once real POST-P&R Fmax
degradation is also factored in, N_SLOTS=4 is measurably 21% SLOWER
in real wall-clock time than N_SLOTS=1 for the largest workload
tested. N_SLOTS=2 is recommended as the default (DEC-0014,
superseding DEC-0012's resource-only "N_SLOTS=8 ceiling" framing for
general use).

Full 21-section report (every number classified THEORETICAL/
SIMULATED/POST-P&R MEASURED/DERIVED, per the user's own
methodology requirements): hardware/v2/docs/benchmarks/
final-benchmark.md

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0014)/
experiments (EXP-0014)/errors (ERR-0009)/development.log,
ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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michele
2026-09-05 19:58:30 +02:00
co-authored by Claude Sonnet 5
parent 91bbbe2fe5
commit 3cdaeaee35
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@@ -97,6 +97,25 @@ piu' alto (DEC-0012), riuso dei buffer M3 come cache condivisa
(DEC-0009), strumentazione stall%/utilization completa anche lato V1
(DEC-0011).
## Final Benchmark Campaign (post-roadmap, richiesta utente)
Dopo il completamento di M1-M10, una campagna di benchmark finale
completa e reale (`hardware/v2/sim/tb_benchmark_suite.v`, EXP-0014) ha
caratterizzato V2 end-to-end su 6 workload realistici (16-256 neuroni
indipendenti, un layer multilivello con forwarding reale via PSRAM, un
DAG a 6 nodi con risveglio a 2 hop) su N_SLOTS=1/2/4/8. 24/24 PASS
bit-exact dopo aver trovato e risolto 3 problemi reali (1 bug RTL in
`neural_director.v` mai testato a N_SLOTS=1, 2 bug nel testbench --
`logs/errors.log` ERR-0009). Scoperta principale: lo scaling parallelo
reale e' sostanzialmente PIATTO oltre N_SLOTS=2 (la vera porta PSRAM
condivisa satura al 91%, non il numero di processori) -- N_SLOTS=4 e'
misurabilmente PIU' LENTO in wall-clock reale di N_SLOTS=1 per il
workload Stress una volta considerato il vero Fmax POST-P&R.
**N_SLOTS=2 raccomandato come default** (`logs/decisions.log`
DEC-0014). Report completo (21 sezioni, THEORETICAL/SIMULATED/
POST-P&R/DERIVED classificati): `hardware/v2/docs/benchmarks/
final-benchmark.md`.
## Log
Vedi `hardware/v2/logs/` (`development.log` per la cronologia di sessione,