feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)

Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the
now-closed 32-bit DDR3 channel (EXP-0086), per this project's own
standing plan. Real result: the 2.86% benefit measured at the old
16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT:
100656.6835ns -- a 0.0064% regression, statistically a wash). The
wider channel's lower per-tile latency already absorbs the gap the
look-ahead prefetch used to hide. Kept wired in for correctness/
timing-neutrality (real P&R already signs off with it included), but
it's no longer a real performance win. Updated docs/ARCHITECTURE_
ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly.

Found and fixed 3 real testbench/simulation-setup bugs along the way:
- tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale
  CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the
  current real, closed 3225ps (EXP-0086).
- tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast
  syntax, invalid for xvlog's default plain-Verilog mode -- fixed via
  an intermediate 8-bit reg.
- Building a fresh sim_1 fileset needs the real MIG simulation
  dependency set added explicitly (mig_7series_0_mig.v is marked
  USED_IN_SIMULATION=0 in the project since testbenches bypass the
  public wrapper); verilog_define is a fileset-level property, not
  per-file, in this Vivado version.

New measurement-only fork (not part of the real synthesis target, per
fork-before-promote discipline): packed_slot_noprefetch.v +
tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct
per-tile activation-fetch sequencing for a fair A/B baseline.

Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3
x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3-
WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator
flagged as needing a custom-programmed order, no off-the-shelf SKU at
the required 310.077MHz) and a consolidated, board-layout-ready pinout
extract of PHYSICAL_REALIZATION.md's own pin tables.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/logs/experiments.log

@@ -5707,3 +5707,109 @@ closes"). (3) Build the result-writeback engine (ARCHITECTURE_ANALYSIS
 core-count scaling tests, each with its own real P&R signoff, per the
 user's own standing directive ("senza illusioni ma analizzando la
 situazione piu' performante").
+
+EXP-0087 -- real re-measurement of DDRManager (EXP-0083) benefit
+against the now-closed 32-bit channel: real result is that the
+benefit VANISHES (2026-09-20, user's own directive: "misuriamo il
+beneficio come consigli" -- re-measure once the wider channel's
+timing actually closes, per EXP-0086's own next_action)
+
+CONTEXT: EXP-0083's own real 2.86% stall-reduction figure for
+ddr_prefetch_mgr.v (single-slot look-ahead activation prefetch) was
+measured ONLY against the OLD 16-bit/155.039MHz DDR3 channel -- never
+re-verified at the real, now-closed 32-bit/155.039MHz config (EXP-0086).
+This experiment redoes that A/B measurement fairly, both variants now
+run against the SAME real 32-bit channel.
+
+METHOD: real xsim (Vivado's own project-integrated `launch_simulation`,
+not raw xvlog/xelab/xsim by hand) of `tb_n2_system_ddr3.v` against a
+freshly-built `sim_1` fileset, real `ddr3_model.sv` (2 real chip
+instances) + real `mig_7series_0_mig` (not the public wrapper, matching
+this project's own established SIM_BYPASS_INIT_CAL="FAST" override
+pattern). Real A/B pair:
+  - WITH prefetch: the CURRENT, real, committed `packed_slot.v` (wires
+    `ddr_prefetch_mgr.v`, unmodified).
+  - WITHOUT prefetch: a new, measurement-only fork,
+    `hardware/v3/sim/packed_slot_noprefetch.v`, reproducing the
+    pre-EXP-0083 baseline sequencing -- direct `act_tile_fetch.v`,
+    one req/wait/consume cycle per tile, no look-ahead overlap. Per
+    this project's own fork-before-promote discipline: NOT part of the
+    real synthesis target, sim-only, alongside its own driver testbench
+    `hardware/v3/sim/tb_n2_system_ddr3_noprefetch.v` (identical to
+    tb_n2_system_ddr3.v except the one module instantiation swapped).
+
+REAL SETUP BUGS FOUND AND FIXED BEFORE A TRUSTWORTHY MEASUREMENT WAS
+POSSIBLE (none of these were about the DDRManager itself -- all were
+real, pre-existing or fresh-fileset gaps in the test infrastructure):
+  1. `tb_n2_system_ddr3.v` and `tb_mig_native_adapter.v` both still had
+     `CLKIN_PERIOD = 2900` (the FAILED EXP-0084 clock period) hardcoded
+     -- stale since EXP-0086 reverted the REAL config to 3225ps. Fixed
+     both to 3225, so this and all future xsim runs against these
+     testbenches reflect the real, current, closed-timing hardware
+     config, not a superseded one.
+  2. `tb_n2_system_ddr3.v` used SystemVerilog-only `$signed(8'((expr) &
+     8'hFF))` sized-cast syntax in two golden-data helper functions --
+     silently invalid for `xvlog` in its default (non `-sv`) mode for a
+     plain `.v` file, exactly the class of bug CLAUDE.md's own
+     "no SV-only syntax in a plain .v file" lesson already warned about
+     (until now only checked for synthesizable RTL, this is the first
+     real hit in a TESTBENCH). Fixed with an intermediate 8-bit `reg`
+     doing the same width-truncation-before-`$signed()` job portably.
+  3. Building a FRESH `sim_1` fileset from scratch (rather than reusing
+     a pre-populated one) does not auto-pull in `mig_7series_0_mig.v`'s
+     own real simulation dependency set -- that file is marked
+     `USED_IN_SIMULATION=0` in the project (Vivado expects the PUBLIC
+     `mig_7series_0.v` wrapper to be the sim entry point; this project's
+     own testbenches deliberately bypass it to override
+     `SIM_BYPASS_INIT_CAL`). Fixed by explicitly adding the real 68-file
+     `user_design/rtl` tree, `ddr3_model.sv` (`x2Gb`/`sg125`/`x16`
+     defines -- a real, second gotcha: `verilog_define` is a
+     FILESET-level property in this Vivado version, not a per-file one,
+     `set_property verilog_define ... [get_files ...]` errors outright),
+     `wiredly.v`, and `glbl.v` to the fileset by hand, mirroring the
+     real vendor-shipped `xsim_files.prj` file list.
+
+REAL RESULT (both real xsim runs, 8/8 PASS, 0 errors, identical golden
+results, both against the SAME real 32-bit/3225ps closed-timing config):
+  WITH    ddr_prefetch_mgr.v: $finish at 100663.1335 ns
+  WITHOUT ddr_prefetch_mgr.v: $finish at 100656.6835 ns
+  -> WITH is 6.45 ns SLOWER than WITHOUT -- a 0.0064% real REGRESSION,
+     not a benefit. Statistically indistinguishable from zero (well
+     within normal run-to-run scheduling noise), but definitively NOT
+     the 2.86% improvement EXP-0083 measured at the old 16-bit width.
+
+REAL, HONEST INTERPRETATION (not asserted without the measurement above
+to back it): the 32-bit channel's real widening (EXP-0084/0086) already
+halves the real per-tile DDR3 round-trip latency (same burst count, ~2x
+the bits/cycle). EXP-0083's own real finding was that the look-ahead
+prefetch's benefit was ALREADY capped by `neural_processor_packed.v`'s
+own fixed one-operand-per-cycle consumption rate, not by DDR3 latency
+itself, even at 16-bit -- widening the channel further shrinks the real
+per-tile DDR3 wait below whatever gap the look-ahead could hide, so
+there is now essentially nothing left for `ddr_prefetch_mgr.v` to
+usefully overlap. This is a real, coherent explanation consistent with
+EXP-0083's own already-disclosed caveat ("this hypothesis overstated the
+achievable benefit... the pipeline accepts one operand per cycle"), not
+a new assumption.
+
+DECISION: `ddr_prefetch_mgr.v` stays wired into the real, committed
+`packed_slot.v` (no reason to rip it out -- real P&R signoff, EXP-0086,
+already shows the 32-bit config closes timing WITH it included, and it
+causes zero real harm). But its own real justification for existing is
+now "real, verified, functionally correct, timing-neutral" rather than
+"real, measured performance win" -- the performance case this project
+built it for (EXP-0083's own 2.86%) does not survive the wider channel.
+Building the larger multi-slot/whole-Director-queue scheduler version
+(the ORIGINAL, not-yet-built EXP-0083 stretch goal) is NOT justified by
+this real result -- the real bottleneck this experiment reveals is
+`neural_processor_packed.v`'s own one-operand-per-cycle consumption
+rate, not DDR3 latency, at the current core count.
+
+next_action: with DDR3 latency no longer the real constraint at N=2,
+core-count scaling (N=4/8/16, already directed by the user) is now the
+more promising real lever -- proceed there. The opportunistic BRAM
+cache idea (`docs/ARCHITECTURE_ANALYSIS.md` S5.6.1) targets the SAME
+now-diminished DDR3-latency lever this experiment just showed has
+little room left to give at N=2 -- worth real-measuring its own benefit
+carefully before investing further RTL effort, rather than assuming
+EXP-0083's original optimistic framing still applies.