feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)

Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the
now-closed 32-bit DDR3 channel (EXP-0086), per this project's own
standing plan. Real result: the 2.86% benefit measured at the old
16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT:
100656.6835ns -- a 0.0064% regression, statistically a wash). The
wider channel's lower per-tile latency already absorbs the gap the
look-ahead prefetch used to hide. Kept wired in for correctness/
timing-neutrality (real P&R already signs off with it included), but
it's no longer a real performance win. Updated docs/ARCHITECTURE_
ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly.

Found and fixed 3 real testbench/simulation-setup bugs along the way:
- tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale
  CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the
  current real, closed 3225ps (EXP-0086).
- tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast
  syntax, invalid for xvlog's default plain-Verilog mode -- fixed via
  an intermediate 8-bit reg.
- Building a fresh sim_1 fileset needs the real MIG simulation
  dependency set added explicitly (mig_7series_0_mig.v is marked
  USED_IN_SIMULATION=0 in the project since testbenches bypass the
  public wrapper); verilog_define is a fileset-level property, not
  per-file, in this Vivado version.

New measurement-only fork (not part of the real synthesis target, per
fork-before-promote discipline): packed_slot_noprefetch.v +
tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct
per-tile activation-fetch sequencing for a fair A/B baseline.

Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3
x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3-
WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator
flagged as needing a custom-programmed order, no off-the-shelf SKU at
the required 310.077MHz) and a consolidated, board-layout-ready pinout
extract of PHYSICAL_REALIZATION.md's own pin tables.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/PHYSICAL_REALIZATION.md

@@ -375,11 +375,14 @@ when it actually fires, instead of polling every loop iteration.
 - ESP32-side JTAG bit-banging firmware (§5.1) does not exist yet — it's
   software work on the host side, not part of this FPGA RTL.
 - `ddr_prefetch_mgr.v` (DDRManager phase 1, EXP-0083) is real, built, and
-  timing-verified, but was only measured for benefit at the OLD 16-bit/
-  155MHz signoff (2.86% real reduction in total simulated time, modest —
-  see `docs/ARCHITECTURE_ANALYSIS.md` §5.2). The larger multi-slot
-  DDRManager is not built. Its own real benefit should now be re-measured
-  against the closed 32-bit channel (EXP-0086) — not yet done.
+  timing-verified. Its real performance benefit was 2.86% at the OLD
+  16-bit/155MHz signoff, but a real re-measurement against the closed
+  32-bit channel (EXP-0087) found the benefit is now GONE (~0%, a
+  0.0064% regression, statistically a wash) — see
+  `docs/ARCHITECTURE_ANALYSIS.md` §5.2. Kept wired into `packed_slot.v`
+  for correctness/timing-neutrality only, not performance. The larger
+  multi-slot DDRManager is not built and, per EXP-0087, is not currently
+  justified.
 - `data_ready_n` (EXP-0085, user-requested active-low sticky IRQ) is real,
   built, functionally verified (49/49 including 10 new checks,
   `tb_spi_host_bridge_v3.v`), AND real P&R-verified at the closed EXP-0086