feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)

Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the
now-closed 32-bit DDR3 channel (EXP-0086), per this project's own
standing plan. Real result: the 2.86% benefit measured at the old
16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT:
100656.6835ns -- a 0.0064% regression, statistically a wash). The
wider channel's lower per-tile latency already absorbs the gap the
look-ahead prefetch used to hide. Kept wired in for correctness/
timing-neutrality (real P&R already signs off with it included), but
it's no longer a real performance win. Updated docs/ARCHITECTURE_
ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly.

Found and fixed 3 real testbench/simulation-setup bugs along the way:
- tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale
  CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the
  current real, closed 3225ps (EXP-0086).
- tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast
  syntax, invalid for xvlog's default plain-Verilog mode -- fixed via
  an intermediate 8-bit reg.
- Building a fresh sim_1 fileset needs the real MIG simulation
  dependency set added explicitly (mig_7series_0_mig.v is marked
  USED_IN_SIMULATION=0 in the project since testbenches bypass the
  public wrapper); verilog_define is a fileset-level property, not
  per-file, in this Vivado version.

New measurement-only fork (not part of the real synthesis target, per
fork-before-promote discipline): packed_slot_noprefetch.v +
tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct
per-tile activation-fetch sequencing for a fair A/B baseline.

Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3
x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3-
WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator
flagged as needing a custom-programmed order, no off-the-shelf SKU at
the required 310.077MHz) and a consolidated, board-layout-ready pinout
extract of PHYSICAL_REALIZATION.md's own pin tables.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -9,11 +9,13 @@ directly measured (real simulation trace, real P&R report) or a calculation
 built from directly-measured building blocks — the two are labeled
 explicitly throughout. Nothing here is guessed.
 
-**Status note (post EXP-0086)**: §5.1 (denser activation packing) is
+**Status note (post EXP-0087)**: §5.1 (denser activation packing) is
 **DONE and real-P&R-verified** (EXP-0081/0082); §5.2 (DDRManager) phase 1
-is **DONE and real-measured** (EXP-0083, a genuinely modest ~2.9% real
-benefit, measured against the OLD 16-bit signoff — re-measurement against
-the now-closed 32-bit channel is a real next step); §5.4 (32-bit widening)
+is **DONE, built, and RE-MEASURED against the closed 32-bit channel**
+(EXP-0083's original modest ~2.9% real benefit was measured only at the
+OLD 16-bit signoff — real re-measurement, EXP-0087, found the benefit is
+now ~0%/a wash at 32-bit, kept wired in for correctness/timing-neutrality
+only, not performance); §5.4 (32-bit widening)
 is **fully DONE — real-verified AND real timing-closed** (EXP-0084
 functional + EXP-0086 timing closure; honest intermediate story: the first
 timing attempt failed because of a SEPARATE, stacked clock speedup, not the
@@ -41,7 +43,7 @@ DDR3 channel.
 | → DDR3 can sustain, post-EXP-0081/0082 packing (2 tiles/burst, DONE) | **~50%** of one core's peak compute throughput | §3.2, current, real |
 | Real P&R timing margin (WNS), current trustworthy (32-bit, CLOSED) | **+0.096 ns** | measured, EXP-0086 real P&R |
 | Real DDR3 physical bandwidth ceiling, 32-bit channel (closed timing) | **~2.48 GB/s** | measured, real P&R signoff, EXP-0086 — 2× EXP-0083's 16-bit ~1.24 GB/s, real not projected |
-| DDRManager phase 1 (single-slot look-ahead prefetch) real benefit | **2.86%** reduction in total real simulated time | measured, real xsim A/B on `tb_n2_system_ddr3.v` (§5.2, EXP-0083) — measured against the OLD 16-bit signoff; modest, honestly reported, not oversold; re-measurement against the closed 32-bit channel is a real next step |
+| DDRManager phase 1 (single-slot look-ahead prefetch) real benefit | **~0% (0.0064% regression)** at the closed 32-bit channel | measured, real xsim A/B on `tb_n2_system_ddr3.v` (§5.2, EXP-0087) — the old 16-bit-only 2.86% figure (EXP-0083) does not survive the wider channel; kept wired in (timing-neutral, real P&R already signs off with it) but no longer a real performance win |
 | DSP48E1 headroom for scaling | 224/240 free (93%) | measured, real P&R utilization |
 
 The DSP headroom is real and large. The memory-bandwidth ceiling is real,
@@ -60,9 +62,10 @@ stacked an ADDITIONAL clock speedup (`ui_clk` +11.2%) in the same wizard
 session, which an unrelated, pre-existing compute-pipeline path couldn't
 absorb (§5.4.1) — width and clock rate turned out to be separable levers,
 and reverting just the clock period closed timing with the width gain
-intact. The DDRManager (§5.2) remains complementary — hides latency,
-doesn't raise the physical ceiling — and its own real benefit should now be
-re-measured against this closed, wider channel (not yet done).
+intact. The DDRManager (§5.2) was re-measured against this now-closed,
+wider channel (EXP-0087): its real benefit is gone (~0%, a 0.0064%
+regression) — the wider channel's own lower per-tile latency already
+absorbed the gap the look-ahead used to hide.
 
 ---
 
@@ -311,7 +314,7 @@ burst, new-burst crossing, back-to-back alternation), `tb_packed_slot.v`
 `tb_n2_system_ddr3.v` (8/8 PASS, real xsim against real `ddr3_model.sv`,
 JEDEC trace confirmed to show no more half-burst zero-padding).
 
-### 5.2 [Complementary, addresses latency not bandwidth] DDRManager with orchestrator-driven prefetch (user's proposal) — **phase 1 DONE (EXP-0083), real benefit smaller than the original hypothesis below predicted**
+### 5.2 [Complementary, addresses latency not bandwidth] DDRManager with orchestrator-driven prefetch (user's proposal) — **phase 1 DONE (EXP-0083); real benefit at the closed 32-bit channel is now ZERO (EXP-0087)**
 
 **The original hypothesis** (written before building anything, now corrected
 by real measurement — kept here so the correction is visible, not silently
@@ -333,13 +336,15 @@ DDR3 fetch latency itself (which is dominated by row activation/precharge,
 §3.3, and look-ahead cannot make a single fetch faster, only start it
 earlier).
 
-**Real, measured result** (`ddr_prefetch_mgr.v`, real P&R WNS +0.073ns, up
-from EXP-0082's +0.068ns, LUTs 5644, DSP48E1 16 unchanged):
+**Real, measured result at the OLD 16-bit channel** (`ddr_prefetch_mgr.v`,
+real P&R WNS +0.073ns, up from EXP-0082's +0.068ns, LUTs 5644, DSP48E1 16
+unchanged):
 - Real apples-to-apples comparison on the **real DDR3 backend**
   (`tb_n2_system_ddr3.v` via real xsim, same N=2/8-position workload,
   before vs after, same `ddr3_model.sv`): **2.86% reduction in total real
-  simulated time** (108370.88ns → 105268.43ns). This is the trustworthy
-  headline number.
+  simulated time** (108370.88ns → 105268.43ns) — EXP-0083's own headline
+  number, but see EXP-0087 below: this figure does NOT survive the 32-bit
+  channel and should not be quoted as the current real benefit.
 - On the fast SDR placeholder backend (used for isolated glue-logic
   testing, `tb_ddr_prefetch_mgr.v`): 0.9% reduction in a row-switch-heavy
   scenario, and -1.4% (i.e. not faster) in an isolated same-row best case —
@@ -348,6 +353,35 @@ from EXP-0082's +0.068ns, LUTs 5644, DSP48E1 16 unchanged):
   cleanly isolate the mechanism the real DDR3 backend's own row/bank timing
   does. Full detail: EXP-0083 in `hardware/v2/logs/experiments.log`.
 
+**Real RE-measurement at the closed 32-bit channel (EXP-0087) — the
+benefit is now GONE**: EXP-0083's 2.86% figure was only ever measured
+against the OLD 16-bit/155MHz channel. Once the 32-bit channel's own real
+timing closed (EXP-0086), this project's own standing plan
+("re-measure once the wider channel's timing actually closes") was
+carried out: a real, fair A/B on the SAME 32-bit/3225ps config, comparing
+the current, committed `packed_slot.v` (with `ddr_prefetch_mgr.v`) against
+a measurement-only fork reproducing the pre-EXP-0083 direct-fetch
+sequencing (`hardware/v3/sim/packed_slot_noprefetch.v`, not part of the
+real synthesis target). Real result, both runs 8/8 PASS, 0 errors,
+identical golden data:
+- WITH `ddr_prefetch_mgr.v`: $finish at 100663.1335 ns
+- WITHOUT `ddr_prefetch_mgr.v`: $finish at 100656.6835 ns
+- **WITH is 6.45ns SLOWER — a 0.0064% real regression**, statistically a
+  wash, definitively NOT a benefit any more.
+
+**Real, honest interpretation**: the 32-bit widening already halves the
+real per-tile DDR3 round-trip latency. EXP-0083's own real finding
+already showed the achievable benefit was capped by
+`neural_processor_packed.v`'s fixed one-operand-per-cycle consumption
+rate, not DDR3 latency, even at 16-bit — the wider channel shrinks the
+real per-tile wait below whatever small gap the look-ahead could still
+hide, leaving effectively nothing left to overlap. `ddr_prefetch_mgr.v`
+stays wired into the real, committed `packed_slot.v` (real P&R already
+signs off with it included, EXP-0086, and it causes zero real harm) —
+but its justification is now "real, correct, timing-neutral", not "real
+performance win". Building the larger multi-slot scheduler sketched below
+is **not justified** by this real result.
+
 **What it does NOT solve** (this part of the original reasoning holds):
 §3.2's bandwidth ceiling is a hard physical limit (bytes/second the DDR3
 channel can physically move) — prefetching earlier doesn't move more bytes
@@ -366,13 +400,17 @@ selection uses a registered index bit at both fill and read time, same
 "known long before the data it gates" discipline as `act_tile_fetch.v`'s
 own EXP-0081 layout — confirmed timing-safe by real P&R, not asserted.
 
-**Full multi-slot / whole-Director-queue scheduler — still NOT built,
-and now a more deliberate call, not just deferred**: given phase 1's real
-measured benefit was modest, the cost/benefit case for the larger design
-below should be re-examined against the 32-bit-widened channel's real
-numbers (§5.4) before committing more engineering time to it — building it
-now, on the still-16-bit channel, risks the same gap between hypothesis and
-measurement this phase-1 experiment just corrected.
+**Full multi-slot / whole-Director-queue scheduler — still NOT built, and
+now real-disconfirmed, not just deferred**: the re-examination against the
+32-bit channel's real numbers (EXP-0087, above) has now happened, and the
+result is that phase 1's own benefit is gone entirely at this core count
+— there is no real cost/benefit case left for the larger design below
+until a NEW real bottleneck reintroduces DDR3-latency-bound behavior
+(e.g. a higher core count where the shared bus is contended again, or a
+workload with heavier row-switching than this experiment's own test
+pattern). Revisit only if/when N=4/8/16 scaling (§5.5) reveals DDR3
+latency, not `neural_processor_packed.v`'s own consumption rate, as the
+real limiting factor again.
 
 **Concrete design sketch for the full version** (informed by what already
 exists in this codebase; kept for when it's revisited):
@@ -537,18 +575,21 @@ specifically to document where/how it breaks rather than to succeed):
    EXP-0086 real timing closure, WNS=+0.096ns). Doubles the physical
    ceiling itself (real, closed, ~2.48 GB/s), which §5.1 alone could not do.
 3. §5.2 (DDRManager) — phase 1 (single-slot look-ahead prefetch) is
-   **DONE** (EXP-0083, real but modest ~2.9% benefit, measured on the OLD
-   16-bit channel). **Next real step**: re-measure this SAME real A/B
-   against the now-closed 32-bit channel (EXP-0086), since a wider channel
-   may change how much idle-channel time there is left to fill — only
-   build the larger multi-slot scheduler version if that re-measurement
-   justifies it, not on the original (now-corrected) hypothesis alone. Not
-   yet done.
+   **DONE and RE-MEASURED** (EXP-0083's original ~2.9% benefit was
+   measured on the OLD 16-bit channel; EXP-0087 re-measured the same real
+   A/B against the now-closed 32-bit channel and found the benefit is
+   gone, ~0%/a 0.0064% regression — the wider channel's lower per-tile
+   latency already absorbed the gap the look-ahead used to hide). Kept
+   wired in for correctness/timing-neutrality; the larger multi-slot
+   scheduler is **not justified** by this real result — revisit only if
+   N=4/8/16 scaling below reintroduces DDR3-latency-bound behavior.
 4. Real N=2/4/8/16 tests, each with its own real P&R signoff (margin is
    thin, §2 — do not assume a prior N's timing closure predicts the next).
    N=8 is the real target configuration; N=16 is expected to expose real
    bus/arbitration/timing limits and is built specifically to document that
-   breakdown, not to be a viable production configuration.
+   breakdown, not to be a viable production configuration. With DDR3
+   latency no longer the real bottleneck at N=2 (EXP-0087), this is now
+   the more promising real lever to pursue next.
 
 ---
 
@@ -697,6 +738,6 @@ design task, not yet scoped, and out of this repository's own RTL scope
 | "~25% of peak sustainable" (pre-packing) / "~50%" (post-packing, current) | **Calculated** ratios; post-packing figure re-verified against real P&R (EXP-0082) and real simulation (§5.1) |
 | I/O bank/DQS pin counts for XC7A100T-CSG324 (banks 14/15/16/34/35) | **Measured** — queried directly from the real Vivado part database for this exact part/package, used in §5.4's dual-channel-vs-widening analysis |
 | Row-switch penalty as a fraction of real workloads | **Not measured** — depends on host-chosen memory layout, flagged as an open question, not asserted |
-| DDRManager phase-1 real stall-reduction benefit (2.86%) | **Measured** — real xsim A/B on `tb_n2_system_ddr3.v`, real DDR3 backend, before vs after `ddr_prefetch_mgr.v` (EXP-0083), against the OLD 16-bit channel. Modest, not the larger figure the original hypothesis (§5.2) suggested before it was built. Re-measurement against the closed 32-bit channel (EXP-0086) is a real next step, not yet done. |
-| Full multi-slot DDRManager's real benefit | **Not measured** — not built; §5.2 recommends re-measuring phase 1 against the 32-bit-widened channel before deciding whether to build it |
+| DDRManager phase-1 real stall-reduction benefit | **Measured** — real xsim A/B on `tb_n2_system_ddr3.v`, real DDR3 backend, before vs after `ddr_prefetch_mgr.v`. **2.86%** at the OLD 16-bit channel (EXP-0083); **~0% (0.0064% regression)** re-measured at the closed 32-bit channel (EXP-0087) — the benefit does not survive the wider channel, real and honestly reported, not oversold either direction. |
+| Full multi-slot DDRManager's real benefit | **Not measured, not built, and now real-disconfirmed as a priority** — phase 1's own re-measurement against the closed 32-bit channel (EXP-0087) found ~0% benefit; §5.2 recommends against building the larger version unless N=4/8/16 scaling reintroduces DDR3-latency-bound behavior |
 | 32-bit widening's real post-change bandwidth/timing numbers | **Measured** — real, closed P&R signoff (EXP-0086): WNS=+0.096ns, WHS=+0.036ns, 0 failing endpoints. The ~2.48 GB/s figure is now a real, closed-timing result, not a projection. |