feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -0,0 +1,230 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 1910/43848 4%
|
||||
Info: logic LUTs: 374/43848 0%
|
||||
Info: carry LUTs: 1536/43848 3%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 3048/43848 6%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 1505 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xc54ffca4
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 64/ 72 88%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 3048/ 43848 6%
|
||||
Info: TRELLIS_COMB: 2200/ 43848 5%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 2000 cells, random placement wirelen = 237944.
|
||||
Info: at initial placer iter 0, wirelen = 2833
|
||||
Info: at initial placer iter 1, wirelen = 2361
|
||||
Info: at initial placer iter 2, wirelen = 2391
|
||||
Info: at initial placer iter 3, wirelen = 2328
|
||||
Info: Running main analytical placer, max placement attempts per cell = 3552445.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 2347, spread = 88719, legal = 96946; time = 0.13s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 2990, spread = 77005, legal = 88952; time = 0.12s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 3774, spread = 74483, legal = 85580; time = 0.12s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 4347, spread = 77909, legal = 88520; time = 0.12s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 4517, spread = 75128, legal = 86754; time = 0.12s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 5126, spread = 74185, legal = 82449; time = 0.12s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 5229, spread = 73739, legal = 84387; time = 0.12s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 5827, spread = 72928, legal = 82109; time = 0.12s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 5739, spread = 72243, legal = 83492; time = 0.12s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 6366, spread = 71190, legal = 82622; time = 0.12s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 6226, spread = 71845, legal = 82524; time = 0.12s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 6126, spread = 72093, legal = 79506; time = 0.12s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 6327, spread = 70392, legal = 80435; time = 0.12s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 6688, spread = 68808, legal = 78516; time = 0.12s
|
||||
Info: at iteration #15, type ALL: wirelen solved = 7246, spread = 69205, legal = 79422; time = 0.12s
|
||||
Info: at iteration #16, type ALL: wirelen solved = 7128, spread = 69848, legal = 81864; time = 0.12s
|
||||
Info: at iteration #17, type ALL: wirelen solved = 6913, spread = 68240, legal = 77295; time = 0.12s
|
||||
Info: at iteration #18, type ALL: wirelen solved = 7495, spread = 69919, legal = 79795; time = 0.12s
|
||||
Info: at iteration #19, type ALL: wirelen solved = 7433, spread = 70131, legal = 80425; time = 0.12s
|
||||
Info: at iteration #20, type ALL: wirelen solved = 7332, spread = 70955, legal = 78731; time = 0.12s
|
||||
Info: at iteration #21, type ALL: wirelen solved = 7815, spread = 70691, legal = 82570; time = 0.12s
|
||||
Info: at iteration #22, type ALL: wirelen solved = 7907, spread = 66858, legal = 80330; time = 0.12s
|
||||
Info: HeAP Placer Time: 2.96s
|
||||
Info: of which solving equations: 0.44s
|
||||
Info: of which spreading cells: 0.08s
|
||||
Info: of which strict legalisation: 2.21s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 2470, wirelen = 77295
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 958, wirelen = 63401
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 347, wirelen = 54640
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 217, wirelen = 51562
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 399, wirelen = 49406
|
||||
Info: at iteration #25: temp = 0.000000, timing cost = 344, wirelen = 48261
|
||||
Info: at iteration #30: temp = 0.000000, timing cost = 416, wirelen = 47947
|
||||
Info: at iteration #30: temp = 0.000000, timing cost = 414, wirelen = 47960
|
||||
Info: SA placement time 1.60s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 106.38 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.46 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.29 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 7 endpoint(s)
|
||||
Info: + represents [1,7) endpoint(s)
|
||||
Info: [ 3100, 3532) |+
|
||||
Info: [ 3532, 3964) |**+
|
||||
Info: [ 3964, 4396) |****+
|
||||
Info: [ 4396, 4828) |**************+
|
||||
Info: [ 4828, 5260) |***************************+
|
||||
Info: [ 5260, 5692) |**********************+
|
||||
Info: [ 5692, 6124) |****************+
|
||||
Info: [ 6124, 6556) |************************************+
|
||||
Info: [ 6556, 6988) |*********************************+
|
||||
Info: [ 6988, 7420) |***********************+
|
||||
Info: [ 7420, 7852) |**************+
|
||||
Info: [ 7852, 8284) |*************+
|
||||
Info: [ 8284, 8716) |*******************+
|
||||
Info: [ 8716, 9148) |***************************+
|
||||
Info: [ 9148, 9580) |******************************************+
|
||||
Info: [ 9580, 10012) |**********************************************************+
|
||||
Info: [ 10012, 10444) |************************************************************
|
||||
Info: [ 10444, 10876) |*********************************************+
|
||||
Info: [ 10876, 11308) |*****************+
|
||||
Info: [ 11308, 11740) |*******************+
|
||||
Info: Checksum: 0xffbac1a4
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 13199 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 504 495 | 504 495 | 12908| 0.52 0.52|
|
||||
Info: 2000 | 963 1036 | 459 541 | 12547| 0.52 1.04|
|
||||
Info: 3000 | 1240 1759 | 277 723 | 12118| 0.84 1.88|
|
||||
Info: 4000 | 1522 2477 | 282 718 | 11659| 0.83 2.71|
|
||||
Info: 5000 | 1767 3232 | 245 755 | 11069| 1.01 3.72|
|
||||
Info: 6000 | 1942 4057 | 175 825 | 10312| 0.65 4.37|
|
||||
Info: 7000 | 2145 4854 | 203 797 | 9554| 0.33 4.69|
|
||||
Info: 8000 | 2501 5498 | 356 644 | 8951| 0.26 4.96|
|
||||
Info: 9000 | 2850 6149 | 349 651 | 8376| 0.35 5.30|
|
||||
Info: 10000 | 3183 6815 | 333 666 | 7803| 0.37 5.67|
|
||||
Info: 11000 | 3224 7639 | 41 824 | 6849| 0.11 5.78|
|
||||
Info: 12000 | 3292 8462 | 68 823 | 5921| 0.08 5.86|
|
||||
Info: 13000 | 3371 9233 | 79 771 | 5002| 0.10 5.96|
|
||||
Info: 14000 | 3444 9947 | 73 714 | 4085| 0.11 6.07|
|
||||
Info: 15000 | 3513 10733 | 69 786 | 3163| 0.10 6.17|
|
||||
Info: 16000 | 3575 11653 | 62 920 | 2242| 0.07 6.24|
|
||||
Info: 17000 | 3663 12489 | 88 836 | 1390| 0.24 6.49|
|
||||
Info: 18000 | 3752 13322 | 89 833 | 510| 0.23 6.72|
|
||||
Info: 18584 | 3797 13825 | 45 503 | 0| 0.31 7.02|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 7.02s
|
||||
Info: Checksum: 0x69cac44f
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[5].u_np.w0[5]_TRELLIS_FF_Q.Q
|
||||
Info: routing 3.07 3.46 Net dut.GEN_NP[5].u_np.w0[4][7] (73,21) -> (8,22)
|
||||
Info: Sink dut.GEN_NP[5].u_np.product_comb[5]_MULT18X18D_P9.B6
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
|
||||
Info: logic 3.07 6.53 Source dut.GEN_NP[5].u_np.product_comb[5]_MULT18X18D_P9.P13
|
||||
Info: routing 0.89 7.42 Net dut.GEN_NP[5].u_np.product_comb[5][13] (8,22) -> (8,23)
|
||||
Info: Sink dut.GEN_NP[5].u_np.prod1[5]_TRELLIS_FF_Q_13.M
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
|
||||
Info: setup 0.00 7.42 Source dut.GEN_NP[5].u_np.prod1[5]_TRELLIS_FF_Q_13.M
|
||||
Info: 3.46 ns logic, 3.96 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 2.85 2.85 Net rst$TRELLIS_IO_IN (90,47) -> (42,45)
|
||||
Info: Sink dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
|
||||
Info: logic 0.18 3.03 Source dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.F
|
||||
Info: routing 2.27 5.30 Net dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D_Z (42,45) -> (55,17)
|
||||
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.47 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.F
|
||||
Info: routing 0.22 5.70 Net dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR (55,17) -> (55,17)
|
||||
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
|
||||
Info: setup 0.29 5.99 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
|
||||
Info: 0.65 ns logic, 5.34 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
|
||||
Info: routing 3.77 4.16 Net checksum[6]$TRELLIS_IO_OUT (68,23) -> (0,23)
|
||||
Info: Sink checksum[6]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.77 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 134.70 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.99 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.16 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 8 endpoint(s)
|
||||
Info: + represents [1,8) endpoint(s)
|
||||
Info: [ 5076, 5412) |**+
|
||||
Info: [ 5412, 5748) |*****************+
|
||||
Info: [ 5748, 6084) |********************************+
|
||||
Info: [ 6084, 6420) |****************+
|
||||
Info: [ 6420, 6756) |*********************+
|
||||
Info: [ 6756, 7092) |**********************************+
|
||||
Info: [ 7092, 7428) |**************+
|
||||
Info: [ 7428, 7764) |***********+
|
||||
Info: [ 7764, 8100) |***************+
|
||||
Info: [ 8100, 8436) |******************+
|
||||
Info: [ 8436, 8772) |*****************+
|
||||
Info: [ 8772, 9108) |**************************+
|
||||
Info: [ 9108, 9444) |***************************+
|
||||
Info: [ 9444, 9780) |**************************************************+
|
||||
Info: [ 9780, 10116) |************************************************************
|
||||
Info: [ 10116, 10452) |**********************************+
|
||||
Info: [ 10452, 10788) |**********************+
|
||||
Info: [ 10788, 11124) |*************************+
|
||||
Info: [ 11124, 11460) |*****************+
|
||||
Info: [ 11460, 11796) |**************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user