feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep

Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).

Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).

Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.

Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/rtl/neural_processor_array.v

@@ -0,0 +1,90 @@
+// ============================================================
+// FPGA-Neural V2 -- Neural Processor Array (M2, docs/v2-description.md §8)
+//
+// Instantiates N_PROCESSORS independent neural_processor units (M1),
+// each with its OWN dedicated point-to-point job/operand/result
+// interface -- no shared bus, no arbitration, no mux at this level
+// (§7: "evitare grandi mux dinamici come quelli dell'architettura
+// V1"). Arbitrating which processor gets which job is explicitly the
+// Neural Director's job (M5) and the Memory Manager's job (M4), not
+// this array's -- at M2 the array is purely a resource/scaling
+// vehicle: does the design synthesize, route, and run correctly with
+// N independent copies, and how do LUT/FF/DSP/Fmax scale with N.
+//
+// Per-processor ports are flattened buses (port[i] occupies bits
+// [i*WIDTH +: WIDTH]), the same convention used throughout V1's own
+// multi-lane interfaces (e.g. x_bus/weights_bus).
+//
+// A blocked/errored processor (NP_ERROR, M1) never affects any other
+// processor's ports -- each is wired independently, confirmed in
+// tb_neural_processor_array.v by running N_PROCESSORS concurrently
+// with staggered start times and one deliberately-slower job.
+// ============================================================
+
+module neural_processor_array #(
+    parameter DATA_WIDTH    = 8,
+    parameter P_IN          = 8,
+    parameter ACC_WIDTH     = 32,
+    parameter N_PROCESSORS  = 4
+)(
+    input clk,
+    input rst,
+
+    input      [N_PROCESSORS-1:0]                      job_valid,
+    output     [N_PROCESSORS-1:0]                       job_ready,
+    input      [16*N_PROCESSORS-1:0]                    job_node_id,
+    input      signed [DATA_WIDTH*N_PROCESSORS-1:0]     job_bias,
+    input      [2*N_PROCESSORS-1:0]                     job_activation,
+
+    input      [N_PROCESSORS-1:0]                       operand_valid,
+    output     [N_PROCESSORS-1:0]                        operand_ready,
+    input      signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] input_data,
+    input      signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] weight_data,
+    input      [N_PROCESSORS-1:0]                       tile_last,
+
+    output     [N_PROCESSORS-1:0]                       result_valid,
+    input      [N_PROCESSORS-1:0]                       result_ready,
+    output     signed [DATA_WIDTH*N_PROCESSORS-1:0]     result_data,
+    output     [16*N_PROCESSORS-1:0]                    result_node_id,
+
+    output     [4*N_PROCESSORS-1:0]                     np_state,
+    output     [N_PROCESSORS-1:0]                       np_error
+);
+
+    genvar p;
+    generate
+        for (p = 0; p < N_PROCESSORS; p = p + 1) begin : GEN_NP
+
+            neural_processor #(
+                .DATA_WIDTH(DATA_WIDTH),
+                .P_IN(P_IN),
+                .ACC_WIDTH(ACC_WIDTH)
+            ) u_np (
+                .clk(clk),
+                .rst(rst),
+
+                .job_valid      (job_valid[p]),
+                .job_ready      (job_ready[p]),
+                .job_node_id    (job_node_id[p*16 +: 16]),
+                .job_bias       (job_bias[p*DATA_WIDTH +: DATA_WIDTH]),
+                .job_activation (job_activation[p*2 +: 2]),
+
+                .operand_valid  (operand_valid[p]),
+                .operand_ready  (operand_ready[p]),
+                .input_data     (input_data[p*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
+                .weight_data    (weight_data[p*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
+                .tile_last      (tile_last[p]),
+
+                .result_valid   (result_valid[p]),
+                .result_ready   (result_ready[p]),
+                .result_data    (result_data[p*DATA_WIDTH +: DATA_WIDTH]),
+                .result_node_id (result_node_id[p*16 +: 16]),
+
+                .np_state       (np_state[p*4 +: 4]),
+                .np_error       (np_error[p])
+            );
+
+        end
+    endgenerate
+
+endmodule