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feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep

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Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).

Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).

Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.

Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:15:11 +02:00
co-authored by Claude Sonnet 5
parent dc0b331d3e
commit 3026dcd997
41 changed files with 1076183 additions and 2 deletions
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hardware/v2/logs/timing.log
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@@ -20,3 +20,14 @@ Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
(no seed sweep run to confirm either way -- see experiments.log
EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
neural_processor_p8_acc24/nextpnr.log
[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
that will first prevent scaling N_PROCESSORS further at P_IN=8.