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feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep

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Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).

Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).

Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.

Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:15:11 +02:00
co-authored by Claude Sonnet 5
parent dc0b331d3e
commit 3026dcd997
41 changed files with 1076183 additions and 2 deletions
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@@ -98,3 +98,29 @@ NOTE: this session's V1 certification campaign (docs/validation/,
this V2-kickoff session (V1 is frozen, not to be touched) and was
not performed. See decisions.log DEC-0004.
STATUS: OPEN CAVEAT, not actioned in this session by design.
ERR-0005 (synthesis measurement artifact, WORKED AROUND, not an RTL bug)
DATE: 2026-09-05
MODULE: hardware/v2/rtl/neural_processor_array.v
SYMPTOM: synthesizing neural_processor_array as a bare top-level
module (every per-processor job/operand/result field exposed as a
real TRELLIS_IO pin) works at N_PROCESSORS=1 but fails place&route
at N_PROCESSORS=2 with "Unable to place cell ...$tr_io, no BELs
remaining to implement cell type 'TRELLIS_IO'".
ROOT CAUSE: not a logic/timing limit -- the LFE5U-45F-8BG381 package
has 245 TRELLIS_IO pins total; the array's wide per-processor buses
(input_data/weight_data alone are DATA_WIDTH*P_IN*N_PROCESSORS bits)
exceed that budget once N_PROCESSORS>=2, purely because these ports
have no on-chip consumer yet (the Memory Manager/M4 and Neural
Director/M5 that will drive them in the real system don't exist
yet).
WORKAROUND: hardware/v2/synthesis/harness_neural_processor_array.v --
a synthesis-only wrapper (NOT part of rtl/, not a functional
deliverable) that drives all wide buses from an internal free-
running LFSR and reduces outputs to a small checksum, keeping only
clk/rst/seed/checksum as real top-level pins. See its own header
comment and experiments.log EXP-0003 for the resulting real
resource/Fmax numbers.
STATUS: WORKED AROUND. Will become moot once M4/M5 exist and the array
is synthesized as part of a larger design with on-chip ports instead
of a bare top-level module.