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working with memory

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This commit is contained in:
michele
2026-09-02 13:09:20 +02:00
parent d4ae2417a4
commit 16769eaa4b
40 changed files with 1263404 additions and 3560 deletions
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sim/memory_interface_sim
Executable
+504
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@@ -0,0 +1,504 @@
#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
:ivl_version "13.0 (stable)" "(v13_0)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
S_0x1008dc9a0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x1008dbb60 .scope module, "memory_interface_tb" "memory_interface_tb" 3 3;
.timescale -9 -12;
P_0x1008dbce0 .param/l "ADDR_WIDTH" 0 3 5, +C4<00000000000000000000000000010110>;
P_0x1008dbd20 .param/l "DATA_WIDTH" 0 3 6, +C4<00000000000000000000000000010000>;
v0x83f094e60_0 .var "addr", 21 0;
v0x83f094f00_0 .var "clk", 0 0;
v0x83f094fa0_0 .net "mem_addr", 21 0, v0x1008cea80_0; 1 drivers
v0x83f095040_0 .net "mem_rdata", 15 0, v0x83f094780_0; 1 drivers
v0x83f0950e0_0 .net "mem_ready", 0 0, v0x83f094820_0; 1 drivers
v0x83f095180_0 .net "mem_req", 0 0, v0x1008d8580_0; 1 drivers
v0x83f095220_0 .net "mem_wdata", 15 0, v0x1008d8620_0; 1 drivers
v0x83f0952c0_0 .net "mem_wr", 0 0, v0x1008d86c0_0; 1 drivers
v0x83f095360_0 .net "rdata", 15 0, v0x1008d8760_0; 1 drivers
v0x83f095400_0 .net "ready", 0 0, v0x1008d8800_0; 1 drivers
v0x83f0954a0_0 .var "req", 0 0;
v0x83f095540_0 .var "rst", 0 0;
v0x83f0955e0_0 .var "wdata", 15 0;
v0x83f095680_0 .var "wr", 0 0;
S_0x1008d97e0 .scope module, "dut" "memory_interface" 3 46, 4 1 0, S_0x1008dbb60;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "req";
.port_info 3 /INPUT 1 "wr";
.port_info 4 /INPUT 22 "addr";
.port_info 5 /INPUT 16 "wdata";
.port_info 6 /OUTPUT 16 "rdata";
.port_info 7 /OUTPUT 1 "ready";
.port_info 8 /OUTPUT 1 "mem_req";
.port_info 9 /OUTPUT 1 "mem_wr";
.port_info 10 /OUTPUT 22 "mem_addr";
.port_info 11 /OUTPUT 16 "mem_wdata";
.port_info 12 /INPUT 16 "mem_rdata";
.port_info 13 /INPUT 1 "mem_ready";
P_0x1008dcb20 .param/l "ADDR_WIDTH" 0 4 2, +C4<00000000000000000000000000010110>;
P_0x1008dcb60 .param/l "DATA_WIDTH" 0 4 3, +C4<00000000000000000000000000010000>;
P_0x1008dcba0 .param/l "STATE_IDLE" 1 4 27, C4<00>;
P_0x1008dcbe0 .param/l "STATE_WAIT" 1 4 28, C4<01>;
v0x1008ce940_0 .net "addr", 21 0, v0x83f094e60_0; 1 drivers
v0x1008ce9e0_0 .net "clk", 0 0, v0x83f094f00_0; 1 drivers
v0x1008cea80_0 .var "mem_addr", 21 0;
v0x1008ceb20_0 .net "mem_rdata", 15 0, v0x83f094780_0; alias, 1 drivers
v0x1008cebc0_0 .net "mem_ready", 0 0, v0x83f094820_0; alias, 1 drivers
v0x1008d8580_0 .var "mem_req", 0 0;
v0x1008d8620_0 .var "mem_wdata", 15 0;
v0x1008d86c0_0 .var "mem_wr", 0 0;
v0x1008d8760_0 .var "rdata", 15 0;
v0x1008d8800_0 .var "ready", 0 0;
v0x1008de100_0 .net "req", 0 0, v0x83f0954a0_0; 1 drivers
v0x1008de1a0_0 .net "rst", 0 0, v0x83f095540_0; 1 drivers
v0x83f094000_0 .var "state", 1 0;
v0x83f0940a0_0 .net "wdata", 15 0, v0x83f0955e0_0; 1 drivers
v0x83f094140_0 .net "wr", 0 0, v0x83f095680_0; 1 drivers
E_0x83ec14080 .event posedge, v0x1008ce9e0_0;
S_0x1008de240 .scope module, "memory" "memory_model" 3 76, 5 1 0, S_0x1008dbb60;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "req";
.port_info 3 /INPUT 1 "wr";
.port_info 4 /INPUT 22 "addr";
.port_info 5 /INPUT 16 "wdata";
.port_info 6 /OUTPUT 16 "rdata";
.port_info 7 /OUTPUT 1 "ready";
P_0x1008de3c0 .param/l "ADDR_WIDTH" 0 5 2, +C4<00000000000000000000000000010110>;
P_0x1008de400 .param/l "DATA_WIDTH" 0 5 3, +C4<00000000000000000000000000010000>;
P_0x1008de440 .param/l "DEPTH" 0 5 4, +C4<00000000000000000001000000000000>;
P_0x1008de480 .param/l "READ_LATENCY" 0 5 5, +C4<00000000000000000000000000000010>;
v0x83f0941e0_0 .net "addr", 21 0, v0x1008cea80_0; alias, 1 drivers
v0x83f094280_0 .var "busy", 0 0;
v0x83f094320_0 .net "clk", 0 0, v0x83f094f00_0; alias, 1 drivers
v0x83f0943c0_0 .var/i "delay_count", 31 0;
v0x83f094460_0 .var/i "i", 31 0;
v0x83f094500 .array "mem", 4095 0, 15 0;
v0x83f0945a0_0 .var "pending_addr", 21 0;
v0x83f094640_0 .var "pending_wdata", 15 0;
v0x83f0946e0_0 .var "pending_wr", 0 0;
v0x83f094780_0 .var "rdata", 15 0;
v0x83f094820_0 .var "ready", 0 0;
v0x83f0948c0_0 .net "req", 0 0, v0x1008d8580_0; alias, 1 drivers
v0x83f094960_0 .net "rst", 0 0, v0x83f095540_0; alias, 1 drivers
v0x83f094a00_0 .net "wdata", 15 0, v0x1008d8620_0; alias, 1 drivers
v0x83f094aa0_0 .net "wr", 0 0, v0x1008d86c0_0; alias, 1 drivers
S_0x1008ded00 .scope task, "read_mem" "read_mem" 3 120, 3 120 0, S_0x1008dbb60;
.timescale -9 -12;
v0x83f094b40_0 .var "address", 21 0;
v0x83f094be0_0 .var "expected", 15 0;
v0x83f094c80_0 .var "received", 15 0;
E_0x83ec17000 .event anyedge, v0x1008d8800_0;
TD_memory_interface_tb.read_mem ;
%wait E_0x83ec14080;
%load/vec4 v0x83f094b40_0;
%assign/vec4 v0x83f094e60_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f095680_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x83f0954a0_0, 0;
%wait E_0x83ec14080;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f0954a0_0, 0;
T_0.0 ;
%load/vec4 v0x83f095400_0;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_0.1, 6;
%wait E_0x83ec17000;
%jmp T_0.0;
T_0.1 ;
%load/vec4 v0x83f095360_0;
%store/vec4 v0x83f094c80_0, 0, 16;
%wait E_0x83ec14080;
%load/vec4 v0x83f094c80_0;
%load/vec4 v0x83f094be0_0;
%cmp/e;
%jmp/0xz T_0.2, 6;
%vpi_call/w 3 144 "$display", "READ addr=0x%08h data=0x%04h PASS", v0x83f094b40_0, v0x83f094c80_0 {0 0 0};
%jmp T_0.3;
T_0.2 ;
%vpi_call/w 3 150 "$display", "READ addr=0x%08h got=0x%04h expected=0x%04h FAIL", v0x83f094b40_0, v0x83f094c80_0, v0x83f094be0_0 {0 0 0};
%vpi_call/w 3 157 "$fatal" {0 0 0};
T_0.3 ;
%end;
S_0x1008dee80 .scope task, "write_mem" "write_mem" 3 93, 3 93 0, S_0x1008dbb60;
.timescale -9 -12;
v0x83f094d20_0 .var "address", 21 0;
v0x83f094dc0_0 .var "data", 15 0;
TD_memory_interface_tb.write_mem ;
%wait E_0x83ec14080;
%load/vec4 v0x83f094d20_0;
%assign/vec4 v0x83f094e60_0, 0;
%load/vec4 v0x83f094dc0_0;
%assign/vec4 v0x83f0955e0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x83f095680_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x83f0954a0_0, 0;
%wait E_0x83ec14080;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f0954a0_0, 0;
T_1.4 ;
%load/vec4 v0x83f095400_0;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_1.5, 6;
%wait E_0x83ec17000;
%jmp T_1.4;
T_1.5 ;
%wait E_0x83ec14080;
%vpi_call/w 3 112 "$display", "WRITE addr=0x%08h data=0x%04h PASS", v0x83f094d20_0, v0x83f094dc0_0 {0 0 0};
%end;
.scope S_0x1008d97e0;
T_2 ;
%wait E_0x83ec14080;
%load/vec4 v0x1008de1a0_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x83f094000_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x1008d8760_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x1008d8800_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x1008d8580_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x1008d86c0_0, 0;
%pushi/vec4 0, 0, 22;
%assign/vec4 v0x1008cea80_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x1008d8620_0, 0;
%jmp T_2.1;
T_2.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x1008d8800_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x1008d8580_0, 0;
%load/vec4 v0x83f094000_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_2.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_2.3, 6;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x83f094000_0, 0;
%jmp T_2.5;
T_2.2 ;
%load/vec4 v0x1008de100_0;
%flag_set/vec4 8;
%jmp/0xz T_2.6, 8;
%load/vec4 v0x83f094140_0;
%assign/vec4 v0x1008d86c0_0, 0;
%load/vec4 v0x1008ce940_0;
%assign/vec4 v0x1008cea80_0, 0;
%load/vec4 v0x83f0940a0_0;
%assign/vec4 v0x1008d8620_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x1008d8580_0, 0;
%pushi/vec4 1, 0, 2;
%assign/vec4 v0x83f094000_0, 0;
T_2.6 ;
%jmp T_2.5;
T_2.3 ;
%load/vec4 v0x1008cebc0_0;
%flag_set/vec4 8;
%jmp/0xz T_2.8, 8;
%load/vec4 v0x1008d86c0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_2.10, 8;
%load/vec4 v0x1008ceb20_0;
%assign/vec4 v0x1008d8760_0, 0;
T_2.10 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x1008d8800_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x83f094000_0, 0;
T_2.8 ;
%jmp T_2.5;
T_2.5 ;
%pop/vec4 1;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_0x1008de240;
T_3 ;
%wait E_0x83ec14080;
%load/vec4 v0x83f094960_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x83f094780_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f094820_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f094280_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f0946e0_0, 0;
%pushi/vec4 0, 0, 22;
%assign/vec4 v0x83f0945a0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x83f094640_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x83f0943c0_0, 0;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x83f094460_0, 0, 32;
T_3.2 ; Top of for-loop
%load/vec4 v0x83f094460_0;
%cmpi/s 4096, 0, 32;
%jmp/0xz T_3.3, 5;
%pushi/vec4 0, 0, 16;
%ix/getv/s 3, v0x83f094460_0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x83f094500, 0, 4;
T_3.4 ; for-loop step statement
%load/vec4 v0x83f094460_0;
%addi 1, 0, 32;
%store/vec4 v0x83f094460_0, 0, 32;
%jmp T_3.2;
T_3.3 ; for-loop exit label
%jmp T_3.1;
T_3.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f094820_0, 0;
%load/vec4 v0x83f094280_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_3.5, 8;
%load/vec4 v0x83f0948c0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.7, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x83f094280_0, 0;
%load/vec4 v0x83f094aa0_0;
%assign/vec4 v0x83f0946e0_0, 0;
%load/vec4 v0x83f0941e0_0;
%assign/vec4 v0x83f0945a0_0, 0;
%load/vec4 v0x83f094a00_0;
%assign/vec4 v0x83f094640_0, 0;
%pushi/vec4 2, 0, 32;
%assign/vec4 v0x83f0943c0_0, 0;
T_3.7 ;
%jmp T_3.6;
T_3.5 ;
%load/vec4 v0x83f0943c0_0;
%cmpi/s 0, 0, 32;
%flag_or 5, 4; GT is !LE
%flag_inv 5;
%jmp/0xz T_3.9, 5;
%load/vec4 v0x83f0943c0_0;
%subi 1, 0, 32;
%assign/vec4 v0x83f0943c0_0, 0;
%jmp T_3.10;
T_3.9 ;
%load/vec4 v0x83f0946e0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.11, 8;
%load/vec4 v0x83f0945a0_0;
%pad/u 32;
%cmpi/u 4096, 0, 32;
%jmp/0xz T_3.13, 5;
%load/vec4 v0x83f094640_0;
%ix/getv 3, v0x83f0945a0_0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x83f094500, 0, 4;
T_3.13 ;
%jmp T_3.12;
T_3.11 ;
%load/vec4 v0x83f0945a0_0;
%pad/u 32;
%cmpi/u 4096, 0, 32;
%jmp/0xz T_3.15, 5;
%ix/getv 4, v0x83f0945a0_0;
%load/vec4a v0x83f094500, 4;
%assign/vec4 v0x83f094780_0, 0;
%jmp T_3.16;
T_3.15 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x83f094780_0, 0;
T_3.16 ;
T_3.12 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x83f094820_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x83f094280_0, 0;
T_3.10 ;
T_3.6 ;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_0x1008dbb60;
T_4 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x83f094f00_0, 0, 1;
T_4.0 ;
%delay 5000, 0;
%load/vec4 v0x83f094f00_0;
%inv;
%store/vec4 v0x83f094f00_0, 0, 1;
%jmp T_4.0;
T_4.1 ;
%end;
.thread T_4;
.scope S_0x1008dbb60;
T_5 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x83f095540_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x83f0954a0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x83f095680_0, 0, 1;
%pushi/vec4 0, 0, 22;
%store/vec4 v0x83f094e60_0, 0, 22;
%pushi/vec4 0, 0, 16;
%store/vec4 v0x83f0955e0_0, 0, 16;
%pushi/vec4 3, 0, 32;
T_5.0 %dup/vec4;
%cmpi/s 0, 0, 32;
%jmp/1xz T_5.1, 5;
%jmp/1 T_5.1, 4;
%subi 1, 0, 32;
%wait E_0x83ec14080;
%jmp T_5.0;
T_5.1 ;
%pop/vec4 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x83f095540_0, 0, 1;
%vpi_call/w 3 182 "$display", "\000" {0 0 0};
%vpi_call/w 3 183 "$display", "========================================" {0 0 0};
%vpi_call/w 3 184 "$display", "MEMORY INTERFACE V1 TEST" {0 0 0};
%vpi_call/w 3 185 "$display", "ADDR_WIDTH = %0d", P_0x1008dbce0 {0 0 0};
%vpi_call/w 3 186 "$display", "DATA_WIDTH = %0d", P_0x1008dbd20 {0 0 0};
%vpi_call/w 3 187 "$display", "========================================" {0 0 0};
%vpi_call/w 3 188 "$display", "\000" {0 0 0};
%pushi/vec4 1, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 4660, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 1, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 4660, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 16, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 43981, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 16, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 43981, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 256, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 21930, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 256, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 21930, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 512, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 1, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 513, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 2, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 514, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 3, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 512, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 1, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 513, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 2, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 514, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 3, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 768, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 0, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 768, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 0, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%pushi/vec4 769, 0, 22;
%store/vec4 v0x83f094d20_0, 0, 22;
%pushi/vec4 65535, 0, 16;
%store/vec4 v0x83f094dc0_0, 0, 16;
%fork TD_memory_interface_tb.write_mem, S_0x1008dee80;
%join;
%pushi/vec4 769, 0, 22;
%store/vec4 v0x83f094b40_0, 0, 22;
%pushi/vec4 65535, 0, 16;
%store/vec4 v0x83f094be0_0, 0, 16;
%fork TD_memory_interface_tb.read_mem, S_0x1008ded00;
%join;
%vpi_call/w 3 301 "$display", "\000" {0 0 0};
%vpi_call/w 3 302 "$display", "========================================" {0 0 0};
%vpi_call/w 3 303 "$display", "MEMORY INTERFACE V1 TEST PASSED" {0 0 0};
%vpi_call/w 3 304 "$display", "========================================" {0 0 0};
%vpi_call/w 3 305 "$display", "\000" {0 0 0};
%vpi_call/w 3 307 "$finish" {0 0 0};
%end;
.thread T_5;
.scope S_0x1008dbb60;
T_6 ;
%vpi_call/w 3 315 "$dumpfile", "sim/memory_interface.vcd" {0 0 0};
%vpi_call/w 3 316 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1008dbb60 {0 0 0};
%end;
.thread T_6;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"-";
"sim/memory_interface_tb.v";
"rtl/memory_interface.v";
"rtl/memory_model.v";