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working with memory

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michele
2026-09-02 13:09:20 +02:00
parent d4ae2417a4
commit 16769eaa4b
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sim/int8_memory_access.vcd
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$date
Wed Sep 2 12:39:25 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 16 ! mem_rdata [15:0] $end
$var wire 1 " mem_ready $end
$var wire 1 # ready $end
$var wire 8 $ rdata [7:0] $end
$var wire 1 % mem_wr $end
$var wire 16 & mem_wdata [15:0] $end
$var wire 1 ' mem_ub_n $end
$var wire 1 ( mem_req $end
$var wire 1 ) mem_lb_n $end
$var wire 22 * mem_addr [21:0] $end
$var parameter 32 + ADDR_WIDTH $end
$var real 1 , CLK_PERIOD $end
$var reg 22 - addr [21:0] $end
$var reg 1 . clk $end
$var reg 16 / model_rdata [15:0] $end
$var reg 1 0 model_ready $end
$var reg 1 1 req $end
$var reg 1 2 rst $end
$var reg 8 3 wdata [7:0] $end
$var reg 1 4 wr $end
$var integer 32 5 i [31:0] $end
$scope module dut $end
$var wire 22 6 addr [21:0] $end
$var wire 1 . clk $end
$var wire 16 7 mem_rdata [15:0] $end
$var wire 1 " mem_ready $end
$var wire 1 1 req $end
$var wire 1 2 rst $end
$var wire 8 8 wdata [7:0] $end
$var wire 1 4 wr $end
$var parameter 32 9 ADDR_WIDTH $end
$var parameter 2 : STATE_IDLE $end
$var parameter 2 ; STATE_WAIT $end
$var reg 22 < addr_reg [21:0] $end
$var reg 22 = mem_addr [21:0] $end
$var reg 1 ) mem_lb_n $end
$var reg 1 ( mem_req $end
$var reg 1 ' mem_ub_n $end
$var reg 16 > mem_wdata [15:0] $end
$var reg 1 % mem_wr $end
$var reg 8 ? rdata [7:0] $end
$var reg 1 # ready $end
$var reg 2 @ state [1:0] $end
$upscope $end
$scope task read_byte $end
$var reg 22 A byte_addr [21:0] $end
$var reg 8 B expected [7:0] $end
$upscope $end
$scope task write_byte $end
$var reg 22 C byte_addr [21:0] $end
$var reg 8 D data [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1 ;
b0 :
b10110 9
r12.5 ,
b10110 +
$end
#0
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