working with memory

2026-09-02 13:09:20 +02:00
parent d4ae2417a4
commit 16769eaa4b
40 changed files with 1263404 additions and 3560 deletions
@@ -0,0 +1,105 @@
+module memory_model #(
+    parameter ADDR_WIDTH   = 22,
+    parameter DATA_WIDTH   = 16,
+    parameter DEPTH        = 4096,
+    parameter READ_LATENCY = 2
+)(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    input  wire                   req,
+    input  wire                   wr,
+    input  wire [ADDR_WIDTH-1:0]  addr,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+
+    output reg  [DATA_WIDTH-1:0]  rdata,
+    output reg                    ready
+);
+
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+
+    reg                   busy;
+    reg                   pending_wr;
+    reg [ADDR_WIDTH-1:0]  pending_addr;
+    reg [DATA_WIDTH-1:0]  pending_wdata;
+
+    integer delay_count;
+    integer i;
+
+    always @(posedge clk) begin
+        if (rst) begin
+
+            rdata         <= {DATA_WIDTH{1'b0}};
+            ready         <= 1'b0;
+
+            busy          <= 1'b0;
+            pending_wr    <= 1'b0;
+            pending_addr  <= {ADDR_WIDTH{1'b0}};
+            pending_wdata <= {DATA_WIDTH{1'b0}};
+
+            delay_count   <= 0;
+
+            for (i = 0; i < DEPTH; i = i + 1)
+                mem[i] <= {DATA_WIDTH{1'b0}};
+
+        end else begin
+
+            // ready is a one-cycle pulse
+            ready <= 1'b0;
+
+            // ----------------------------------------------------
+            // Accept request
+            // ----------------------------------------------------
+
+            if (!busy) begin
+
+                if (req) begin
+
+                    busy          <= 1'b1;
+                    pending_wr    <= wr;
+                    pending_addr  <= addr;
+                    pending_wdata <= wdata;
+
+                    delay_count   <= READ_LATENCY;
+                end
+
+            end else begin
+
+                // ------------------------------------------------
+                // Wait
+                // ------------------------------------------------
+
+                if (delay_count > 0) begin
+
+                    delay_count <= delay_count - 1;
+
+                end else begin
+
+                    // --------------------------------------------
+                    // Complete transaction
+                    // --------------------------------------------
+
+                    if (pending_wr) begin
+
+                        // WRITE
+                        if (pending_addr < DEPTH)
+                            mem[pending_addr] <= pending_wdata;
+
+                    end else begin
+
+                        // READ
+                        if (pending_addr < DEPTH)
+                            rdata <= mem[pending_addr];
+                        else
+                            rdata <= {DATA_WIDTH{1'b0}};
+
+                    end
+
+                    ready <= 1'b1;
+                    busy  <= 1'b0;
+                end
+            end
+        end
+    end
+
+endmodule