test: certify runtime width early-termination (C.2), document BUG-003/004
n_inputs_real/n_neurons_real early termination for valid values is certified real: a "poison" region (data that would saturate the result if read past the claimed limit) confirms no over-read, cycle counts scale proportionally. n_inputs_real non-multiple-of-PARALLEL at runtime matches the documented silent-truncation risk exactly. n_inputs_real=0 / n_neurons_real=0 (BUG-003/004): confirmed incorrect behavior in every repetition, but the exact triggering mechanism was NOT fully isolated -- nearly-identical repeated tests produced different symptoms (clean hang vs. silently processing the full build width vs. a third cycle count matching neither). Reported in full, including the inconsistency itself, rather than picking the cleanest result. The two new permanent testbenches reflect this honestly: the solid early-termination checks are hard assertions, the n_*_real=0 probe is deliberately observe-only given the non-deterministic result. Full regression: 38/38 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// C.2 CERTIFICATION + BUG-003 OBSERVATION (certification campaign,
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// docs/validation/bugs.md / docs/validation/02-runtime-width.md).
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//
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// TESTS 1-3 (SOLID, CERTIFIED): early termination for valid
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// n_inputs_real values is real -- a "poison" region at indices 16-31
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// with saturating x=w=100 would corrupt the result if the RTL ever
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// read past the real limit. It doesn't. These three checks DO fail
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// the run (errors counted) if early termination breaks.
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//
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// TEST 4 (n_inputs_real=0) is DELIBERATELY NOT a hard pass/fail
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// assertion. Unlike BUG-002 (N_INPUTS=0, a compile-time parameter),
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// this runtime-reachable twin (n_inputs_real=0, exactly the port an
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// SPI host drives via SET_BASE sel=7,
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// docs/FPGA-NeuralNetwork-Engine.md §8.1) produced DIFFERENT results
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// across nearly-identical repeated test runs while investigating this
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// aspect -- sometimes a clean hang (busy/done never move), sometimes
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// a normal-looking completion that silently processes the FULL build
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// width instead of zero elements. The exact triggering condition was
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// NOT isolated despite multiple attempts -- see
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// docs/validation/02-runtime-width.md §2.3 for the full, undiscarded
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// record of every attempt. This test only REPORTS which of the two
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// (already known-incorrect) symptoms shows up on this particular run
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// -- it does not assert one is "the" correct current behavior, because
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// that has not been established.
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// ================================================================
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module tb;
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localparam DATA_WIDTH = 8;
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localparam N_INPUTS = 32;
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localparam PARALLEL = 8;
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localparam ACC_WIDTH = 32;
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reg clk;
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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reg rst, start;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus, w_bus;
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reg [1:0] activation;
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reg [15:0] n_inputs_real;
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wire busy, done;
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wire signed [DATA_WIDTH-1:0] y;
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integer cyc, i;
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integer errors;
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neuron_parallel #(
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.DATA_WIDTH(DATA_WIDTH), .N_INPUTS(N_INPUTS), .PARALLEL(PARALLEL), .ACC_WIDTH(ACC_WIDTH)
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) dut (
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.clk(clk), .rst(rst), .start(start),
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.x_bus(x_bus), .w_bus(w_bus), .bias(8'sd0),
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.activation(activation), .n_inputs_real(n_inputs_real),
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.y(y), .busy(busy), .done(done)
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);
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task automatic run_case(
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input [15:0] nreal,
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input integer is_bug003_probe, // 1 = TEST 4: observe-only, never counts as a failure either way (see file header)
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input signed [7:0] expect_y // meaningful only if is_bug003_probe == 0
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);
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begin
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n_inputs_real = nreal;
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rst = 1; start = 0;
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@(posedge clk); @(posedge clk);
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rst = 0;
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@(posedge clk);
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start = 1;
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@(posedge clk);
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start = 0;
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cyc = 0;
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while (!done && cyc < 200) begin
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@(posedge clk);
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cyc = cyc + 1;
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end
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if (is_bug003_probe) begin
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if (done)
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$display("n_inputs_real=%0d: OBSERVED -- completed at cycle %0d, y=%0d (limit silently ignored -- one of two known-incorrect symptoms, see docs/validation/02-runtime-width.md §2.3; NOT counted as pass or fail here)", nreal, cyc, y);
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else
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$display("n_inputs_real=%0d: OBSERVED -- no done in 200 cycles, busy=%b (hang -- the OTHER known-incorrect symptom, see docs/validation/02-runtime-width.md §2.3; NOT counted as pass or fail here)", nreal, busy);
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end else begin
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if (!done) begin
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$display("n_inputs_real=%0d: FAIL -- expected done, got none in 200 cycles", nreal);
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errors = errors + 1;
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end else if (y !== expect_y) begin
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$display("n_inputs_real=%0d: FAIL -- y=%0d expected=%0d", nreal, y, expect_y);
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errors = errors + 1;
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end else begin
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$display("n_inputs_real=%0d: PASS -- y=%0d cycles=%0d (no over-read into poison region)", nreal, y, cyc);
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end
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end
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end
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endtask
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initial begin
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errors = 0;
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activation = 2'd1; // ACT_RELU
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// real region (0-15): x=w=1 -> contributes 1 each if read
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for (i = 0; i < 16; i = i + 1) begin
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x_bus[i*8 +: 8] = 8'sd1;
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w_bus[i*8 +: 8] = 8'sd1;
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end
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// "poison" region (16-31): x=w=100 -> would saturate to 127 if
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// ever read past the real limit
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for (i = 16; i < 32; i = i + 1) begin
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x_bus[i*8 +: 8] = 8'sd100;
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w_bus[i*8 +: 8] = 8'sd100;
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end
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$display("--- TEST 1: n_inputs_real=16 -- early termination must NOT read the poison region ---");
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run_case(16'd16, 0, 8'sd16);
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$display("--- TEST 2: n_inputs_real=8 -- smaller early termination ---");
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run_case(16'd8, 0, 8'sd8);
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$display("--- TEST 3: n_inputs_real=32 (full) -- sanity: DOES read the poison region, saturates ---");
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run_case(16'd32, 0, 8'sd127);
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$display("--- TEST 4 (BUG-003 probe, observe-only): n_inputs_real=0 ---");
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run_case(16'd0, 1, 8'sd0);
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if (errors == 0)
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$display("ALL TESTS PASSED (early termination certified correct for valid n_inputs_real values, TESTS 1-3; TEST 4 is an observe-only BUG-003 probe, see docs/validation/02-runtime-width.md §2.3 -- not scored)");
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else
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$display("FAILED: %0d unexpected result(s) in TESTS 1-3 -- see messages above", errors);
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$finish;
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end
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endmodule
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