exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)
New hardware/v3/rtl/n2_system_top.v: synthesis wrapper around the EXP-0066-verified system (neural_director_packed.v + arbiter + real SDRAM controller + 2 real packed_slot.v instances). Real Vivado post-route: 16/240 DSP48E1, WNS -2.570ns @ 200MHz -> Fmax ~132.1MHz -- only -2.1% vs the isolated single core (134.9MHz, EXP-0059). Unlike V2/ECP5 (where the real full-system Fmax was measurably lower than the isolated-core number), this Director+ arbiter architecture shows no comparable penalty at N=2, real confirmation (not projection) that the earlier ~55-85x-over-ESP32-S3 estimate's key assumption holds at this scale. Full writeup in hardware/v2/logs/experiments.log EXP-0067. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
@@ -4111,3 +4111,54 @@ system-representative); (2) scale to the real target N (up to ~30
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packed cores per EXP-0059's own DSP budget projection) once N=2's real
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timing is known; (3) the real DDR3/MIG memory interface, replacing the
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SDR SDRAM placeholder used throughout -- separate, larger, not started.
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EXP-0067 -- real P&R of the EXP-0066 verified N=2 system: the first
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genuine multi-core Fmax number (2026-09-17)
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CONTEXT: EXP-0066's own next_action -- the number this entire V3 pivot
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has been building toward since EXP-0059: a real system-level Fmax that
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includes the Director, the shared-SDRAM arbiter, AND N>1 real compute+
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memory slots together, not an isolated core or a zero-interconnect
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compute array.
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METHOD: new hardware/v3/rtl/n2_system_top.v, flat structural synthesis
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wrapper around the EXP-0066-verified module chain (neural_director_
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packed.v + sdram_slot_arbiter2.v + real sdram_controller.v + 2x real
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packed_slot.v, each with its own full memory-reuse path). Activation
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stand-in ports exposed per-slot at the top level (same disclosed scope
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as packed_slot.v itself). Real Vivado synth + opt_design + place_design
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+ route_design, same 200MHz constraint and part (xc7a100tcsg324-1) as
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every prior V3 P&R check, via hardware/v3/synth/synth_n2_system_top.tcl.
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RESULT (real, post-route): 16/240 DSP48E1 (6.67%, exactly 2x8, matches
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EXP-0059's per-core count). WNS -2.570ns @ 200MHz -> real critical
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path 7.570ns -> Fmax ~132.1MHz.
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Comparison across every V3 P&R checkpoint so far:
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EXP-0059 isolated single core: 134.9MHz
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EXP-0063 single core + real memory path: 133.3MHz (-1.2%)
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EXP-0060 8-core array, zero interconnect: 131.7MHz (-2.4%)
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EXP-0067 full N=2 system (Director+arbiter+2 slots): 132.1MHz (-2.1%)
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DECISION: unlike the V2/ECP5 pattern (isolated dataflow-core Fmax
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92.63MHz vs real full-system Fmax 64-97MHz, a real ~0-30% gap
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depending on config), this V3 architecture shows NO comparable
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Director/arbiter Fmax penalty -- the shared scheduling and arbitration
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logic here is lightweight enough that it is not on (or not much on)
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the critical path, even in this first real multi-core measurement.
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This substantially de-risks the ~55-85x-over-ESP32-S3 projection
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first floated in EXP-0059: it was explicitly conditioned on "IF a real
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N-core system holds close to the isolated-core Fmax" -- this
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experiment is real (not projected) confirmation that it does, at
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N=2. Scaling to larger N (up to ~30 cores) may still show more
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congestion than N=2 did; this is not yet proof the ceiling holds at
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every N, only that the Director/arbiter architecture itself is not
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the bottleneck class V2 had.
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next_action: (1) the real DDR3/MIG memory interface remains the
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largest deferred piece (everything measured so far uses the declared
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SDR SDRAM placeholder); (2) if/when scaling to a larger N is
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attempted, watch specifically for placement congestion effects (the
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EXP-0060 8-core-array class of degradation) since that is the one
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variable not yet tested at higher N with the REAL Director+arbiter
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system, only with a zero-interconnect array.
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@@ -0,0 +1,192 @@
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`timescale 1ns/1ps
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// ============================================================
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// V3 -- synthesis top for the EXP-0066 verified N=2 multi-core
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// system: neural_director_packed.v + 2 real packed_slot.v instances
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// + sdram_slot_arbiter2.v + real sdram_controller.v, flat structural
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// wiring, for a real P&R resource/timing check (same out-of-context
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// methodology as EXP-0059/0063).
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//
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// Activation stand-in ports (see packed_slot.v's own header) are
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// exposed per-slot at the top level, matching this module's own
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// still-declared scope limit (no real activation fetch engine yet).
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// ============================================================
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module n2_system_top #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter BURST_LEN = 8,
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parameter ROW_BITS = 13,
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parameter COL_BITS = 10,
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parameter BANK_BITS = 2,
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parameter SDRAM_ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS,
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parameter ADDR_WIDTH = 26,
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parameter LAYER_BYTES = 128,
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parameter N_SLOTS = 2,
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parameter QUEUE_DEPTH = 8
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)(
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input wire clk,
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input wire rst,
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// ---- Director job submission ----
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input wire job_in_valid,
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output wire job_in_ready,
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input wire [ADDR_WIDTH-1:0] job_in_x_base,
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input wire [ADDR_WIDTH-1:0] job_in_w_base,
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input wire [15:0] job_in_n_tiles,
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input wire [ADDR_WIDTH-1:0] job_in_result_addr,
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input wire [15:0] job_in_node_id,
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output wire job_out_done,
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output wire [$clog2(N_SLOTS)-1:0] job_out_slot,
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// ---- activation stand-ins, slot 0 ----
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output wire [ADDR_WIDTH-1:0] s0_act_addr_a,
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output wire [ADDR_WIDTH-1:0] s0_act_addr_b,
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input wire signed [DATA_WIDTH*P_IN-1:0] s0_act_data_a,
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input wire signed [DATA_WIDTH*P_IN-1:0] s0_act_data_b,
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output wire signed [DATA_WIDTH-1:0] s0_result_data_a,
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output wire signed [DATA_WIDTH-1:0] s0_result_data_b,
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// ---- activation stand-ins, slot 1 ----
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output wire [ADDR_WIDTH-1:0] s1_act_addr_a,
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output wire [ADDR_WIDTH-1:0] s1_act_addr_b,
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input wire signed [DATA_WIDTH*P_IN-1:0] s1_act_data_a,
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input wire signed [DATA_WIDTH*P_IN-1:0] s1_act_data_b,
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output wire signed [DATA_WIDTH-1:0] s1_result_data_a,
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output wire signed [DATA_WIDTH-1:0] s1_result_data_b,
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// ---- real SDRAM pins ----
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output wire sdram_cke,
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output wire sdram_cs_n,
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output wire sdram_ras_n,
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output wire sdram_cas_n,
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output wire sdram_we_n,
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output wire [BANK_BITS-1:0] sdram_ba,
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output wire [ROW_BITS-1:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output wire [1:0] sdram_dqm
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);
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localparam BUFADDRW = $clog2(LAYER_BYTES);
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wire [N_SLOTS-1:0] slot_job_start;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base_a, slot_x_base_b, slot_w_base;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr_a, slot_result_addr_b;
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wire [16*N_SLOTS-1:0] slot_n_tiles, slot_node_id_a, slot_node_id_b;
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wire [N_SLOTS-1:0] slot_job_done;
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wire [3:0] dir_state;
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wire dir_error;
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wire queue_empty;
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neural_director_packed #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH)
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) u_dir (
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.clk(clk), .rst(rst),
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.job_in_valid(job_in_valid), .job_in_ready(job_in_ready),
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.job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base),
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.job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr),
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.job_in_node_id(job_in_node_id),
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.slot_job_start(slot_job_start),
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.slot_x_base_a(slot_x_base_a), .slot_x_base_b(slot_x_base_b),
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.slot_w_base(slot_w_base), .slot_n_tiles(slot_n_tiles),
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.slot_result_addr_a(slot_result_addr_a), .slot_result_addr_b(slot_result_addr_b),
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.slot_node_id_a(slot_node_id_a), .slot_node_id_b(slot_node_id_b),
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.slot_job_done(slot_job_done),
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.job_out_done(job_out_done), .job_out_slot(job_out_slot),
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.dir_state(dir_state), .dir_error(dir_error), .queue_empty(queue_empty)
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);
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wire [1:0] mem_active, mem_grant;
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wire [1:0] s_ctrl_req, s_ctrl_wr;
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wire [SDRAM_ADDR_WIDTH-1:0] s0_ctrl_addr, s1_ctrl_addr;
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wire [16*BURST_LEN-1:0] s0_ctrl_wdata, s1_ctrl_wdata;
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wire [2*BURST_LEN-1:0] s0_ctrl_wmask, s1_ctrl_wmask;
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wire [16*BURST_LEN-1:0] s0_ctrl_rdata, s1_ctrl_rdata;
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wire [1:0] s_ctrl_ready, s_ctrl_busy;
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wire ctrl_req, ctrl_wr;
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wire [SDRAM_ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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sdram_slot_arbiter2 #(.ADDR_WIDTH(SDRAM_ADDR_WIDTH), .BURST_LEN(BURST_LEN)) u_arb (
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.clk(clk), .rst(rst),
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.slot0_active(mem_active[0]), .slot0_grant(mem_grant[0]),
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.slot0_req(s_ctrl_req[0]), .slot0_wr(s_ctrl_wr[0]),
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.slot0_addr(s0_ctrl_addr), .slot0_wdata(s0_ctrl_wdata), .slot0_wmask(s0_ctrl_wmask),
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.slot0_rdata(s0_ctrl_rdata), .slot0_ready(s_ctrl_ready[0]), .slot0_busy(s_ctrl_busy[0]),
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.slot1_active(mem_active[1]), .slot1_grant(mem_grant[1]),
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.slot1_req(s_ctrl_req[1]), .slot1_wr(s_ctrl_wr[1]),
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.slot1_addr(s1_ctrl_addr), .slot1_wdata(s1_ctrl_wdata), .slot1_wmask(s1_ctrl_wmask),
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.slot1_rdata(s1_ctrl_rdata), .slot1_ready(s_ctrl_ready[1]), .slot1_busy(s_ctrl_busy[1]),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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sdram_controller #(
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.CLK_FREQ_MHZ(64), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr),
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.wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
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);
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wire [15:0] s0_nid_a, s0_nid_b, s1_nid_a, s1_nid_b;
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wire [ADDR_WIDTH-1:0] s0_raddr_a, s0_raddr_b, s1_raddr_a, s1_raddr_b;
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packed_slot #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH), .LAYER_BYTES(LAYER_BYTES)
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) u_slot0 (
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.clk(clk), .rst(rst),
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.job_start(slot_job_start[0]),
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.x_base_a(slot_x_base_a[0*ADDR_WIDTH +: ADDR_WIDTH]),
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.x_base_b(slot_x_base_b[0*ADDR_WIDTH +: ADDR_WIDTH]),
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.w_base(slot_w_base[0*ADDR_WIDTH +: ADDR_WIDTH]),
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.n_tiles(slot_n_tiles[0*16 +: 16]),
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.result_addr_a(slot_result_addr_a[0*ADDR_WIDTH +: ADDR_WIDTH]),
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.result_addr_b(slot_result_addr_b[0*ADDR_WIDTH +: ADDR_WIDTH]),
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.node_id_a(slot_node_id_a[0*16 +: 16]), .node_id_b(slot_node_id_b[0*16 +: 16]),
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.job_done(slot_job_done[0]),
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.result_data_a(s0_result_data_a), .result_data_b(s0_result_data_b),
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.result_node_id_a(s0_nid_a), .result_node_id_b(s0_nid_b),
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.result_addr_a_out(s0_raddr_a), .result_addr_b_out(s0_raddr_b),
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.mem_active(mem_active[0]), .mem_grant(mem_grant[0]),
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.act_tile_addr_a(s0_act_addr_a), .act_tile_addr_b(s0_act_addr_b),
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.act_tile_data_a(s0_act_data_a), .act_tile_data_b(s0_act_data_b),
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.ctrl_req(s_ctrl_req[0]), .ctrl_wr(s_ctrl_wr[0]), .ctrl_addr(s0_ctrl_addr),
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.ctrl_wdata(s0_ctrl_wdata), .ctrl_wmask(s0_ctrl_wmask),
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.ctrl_rdata(s0_ctrl_rdata), .ctrl_ready(s_ctrl_ready[0]), .ctrl_busy(s_ctrl_busy[0])
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);
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packed_slot #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH), .LAYER_BYTES(LAYER_BYTES)
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) u_slot1 (
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.clk(clk), .rst(rst),
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.job_start(slot_job_start[1]),
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.x_base_a(slot_x_base_a[1*ADDR_WIDTH +: ADDR_WIDTH]),
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.x_base_b(slot_x_base_b[1*ADDR_WIDTH +: ADDR_WIDTH]),
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.w_base(slot_w_base[1*ADDR_WIDTH +: ADDR_WIDTH]),
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.n_tiles(slot_n_tiles[1*16 +: 16]),
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.result_addr_a(slot_result_addr_a[1*ADDR_WIDTH +: ADDR_WIDTH]),
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.result_addr_b(slot_result_addr_b[1*ADDR_WIDTH +: ADDR_WIDTH]),
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.node_id_a(slot_node_id_a[1*16 +: 16]), .node_id_b(slot_node_id_b[1*16 +: 16]),
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.job_done(slot_job_done[1]),
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.result_data_a(s1_result_data_a), .result_data_b(s1_result_data_b),
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.result_node_id_a(s1_nid_a), .result_node_id_b(s1_nid_b),
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.result_addr_a_out(s1_raddr_a), .result_addr_b_out(s1_raddr_b),
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.mem_active(mem_active[1]), .mem_grant(mem_grant[1]),
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.act_tile_addr_a(s1_act_addr_a), .act_tile_addr_b(s1_act_addr_b),
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.act_tile_data_a(s1_act_data_a), .act_tile_data_b(s1_act_data_b),
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.ctrl_req(s_ctrl_req[1]), .ctrl_wr(s_ctrl_wr[1]), .ctrl_addr(s1_ctrl_addr),
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.ctrl_wdata(s1_ctrl_wdata), .ctrl_wmask(s1_ctrl_wmask),
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.ctrl_rdata(s1_ctrl_rdata), .ctrl_ready(s_ctrl_ready[1]), .ctrl_busy(s_ctrl_busy[1])
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);
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endmodule
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@@ -0,0 +1,18 @@
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_director_packed.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/sdram_slot_arbiter2.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/nms/rtl/sdram_controller.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/packed_slot.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_prefetch_ctrl.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_weight_buffer.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/weight_tile_gather.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_processor_packed.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/n2_system_top.v
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synth_design -top n2_system_top -part xc7a100tcsg324-1 -mode out_of_context
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create_clock -name clk -period 5.000 [get_ports clk]
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opt_design
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report_utilization -file /tmp/util_n2_system_postsynth.rpt
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place_design
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route_design
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report_utilization -file /tmp/util_n2_system_postroute.rpt
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report_timing_summary -file /tmp/timing_n2_system_postroute.rpt
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write_checkpoint -force /tmp/n2_system_postroute.dcp
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