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exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)

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New hardware/v3/rtl/n2_system_top.v: synthesis wrapper around the
EXP-0066-verified system (neural_director_packed.v + arbiter + real
SDRAM controller + 2 real packed_slot.v instances).

Real Vivado post-route: 16/240 DSP48E1, WNS -2.570ns @ 200MHz ->
Fmax ~132.1MHz -- only -2.1% vs the isolated single core (134.9MHz,
EXP-0059). Unlike V2/ECP5 (where the real full-system Fmax was
measurably lower than the isolated-core number), this Director+
arbiter architecture shows no comparable penalty at N=2, real
confirmation (not projection) that the earlier ~55-85x-over-ESP32-S3
estimate's key assumption holds at this scale.

Full writeup in hardware/v2/logs/experiments.log EXP-0067.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-17 00:21:01 +02:00
co-authored by Claude Sonnet 5
parent 09fbf01ea5
commit 0589620b58
3 changed files with 261 additions and 0 deletions
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hardware/v3/synth/synth_n2_system_top.tcl
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_director_packed.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/sdram_slot_arbiter2.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/nms/rtl/sdram_controller.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/packed_slot.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_prefetch_ctrl.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_weight_buffer.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/weight_tile_gather.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_processor_packed.v
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/n2_system_top.v
synth_design -top n2_system_top -part xc7a100tcsg324-1 -mode out_of_context
create_clock -name clk -period 5.000 [get_ports clk]
opt_design
report_utilization -file /tmp/util_n2_system_postsynth.rpt
place_design
route_design
report_utilization -file /tmp/util_n2_system_postroute.rpt
report_timing_summary -file /tmp/timing_n2_system_postroute.rpt
write_checkpoint -force /tmp/n2_system_postroute.dcp