docs: consolidate N=16 to N=8's own level of rigor (EXP-0098) -- whole family real and closed
N=2 re-verified with the same shared pipelined neural_processor_packed.v (EXP-0097's fix): real functional xsim 8/8 PASS (identical completion time to the pre-fix baseline), real full P&R WNS=+0.389ns (up from +0.099962ns), 0 failing endpoints, 16 DSP48E1 -- no regression. Real, consolidated family state, all sharing the same pipelined core: N=2: WNS=+0.389ns, 16 DSP48E1, 8/8 functional PASS N=8: WNS=+0.108ns, 64 DSP48E1, 16/16 functional PASS N=16: WNS=+0.269ns, 128 DSP48E1, 32/32 functional PASS Updated the project's own primary real docs (docs/PHYSICAL_REALIZATION.md S3, docs/ARCHITECTURE_ANALYSIS.md S5.6) to the same depth EXP-0096 gave N=8 alone -- not just the docs/latex/ deliverables. Clear two-track framing throughout: the physically fabricated board still uses N=8's original, unmodified core (WNS=0.000ns exact); this consolidated, improved family lives on the isolated n16-timing-closure branch, pending a real hardware decision on whether/when to adopt it. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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@@ -6962,3 +6962,52 @@ N=8 design, unaffected), and/or (2) actually build the NEXT physical
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board as N=16 instead of N=8, given N=16 is now real, functionally
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verified, AND timing-closed with a real, comfortable margin -- a real,
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consequential hardware decision, not an RTL one.
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EXP-0098 -- consolidating N=16 to the same real rigor as N=8: N=2
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re-verified too (the pipelined MAC core is SHARED across the whole
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real family), full real family state now closed at every N
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(2026-09-22, user's own explicit direction: "consolidare N=16 come
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faccio con N=8")
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CONTEXT: EXP-0097 verified the pipelined `neural_processor_packed.v`
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against N=8 and N=16, but never against N=2 -- a real, disclosed gap,
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since N=2 (`n2_system_ddr3_top.v`) is the SAME shared core and remains
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this project's own documented real fallback signoff (EXP-0088).
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Consolidating N=16 to N=8's own level of rigor means confirming the
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WHOLE real family, not just the two configurations directly asked
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about.
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REAL RESULT: functional xsim (`tb_n2_system_ddr3.v`, real DDR3 model):
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**8/8 PASS, 0 errors**, `$finish` at the EXACT SAME real completion
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time as the pre-fix baseline (101204.9335ns) -- zero observable
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end-to-end effect at this scale, same as N=16's own real finding.
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Real, full P&R (`n2_system_ddr3_top.v`, real XC7A100T-CSG324-2, same
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directive stack): **WNS=+0.389ns (up from the original real
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+0.099962ns), WHS=+0.017ns, 0 failing endpoints, 16 DSP48E1 (6.67%),
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6645 LUTs (10.48%)** -- a real, substantial margin improvement, no
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regression.
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REAL, CONSOLIDATED FAMILY STATE (branch `n16-timing-closure`, all
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three real top-levels sharing the SAME pipelined `neural_processor_
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packed.v`, all real, functionally verified AND timing-closed):
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N=2 (`n2_system_ddr3_top.v`): WNS=+0.389ns, 16 DSP48E1, 8/8 functional PASS
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N=8 (`n8_system_ddr3_top.v`): WNS=+0.108ns, 64 DSP48E1, 16/16 functional PASS
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N=16 (`n16_system_ddr3_top.v`): WNS=+0.269ns, 128 DSP48E1, 32/32 functional PASS
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DECISION: the real MAC-pipeline fix (EXP-0097) is a pure, unconditional
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improvement across the entire real product family -- every real
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configuration this project has ever built a dedicated top-level for
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now closes with real, comfortable, positive margin, not just N=16. No
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real regression found anywhere. This is now a real, trustworthy,
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fully-consolidated state for this branch, at the same level of rigor
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EXP-0096 established for N=8 alone.
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next_action: update the project's own primary real docs
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(`docs/PHYSICAL_REALIZATION.md` §3, `docs/ARCHITECTURE_ANALYSIS.md`
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§5.6 and its own top-of-document pointer) on this branch to reflect
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this consolidated real family state -- not yet done, the LaTeX
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deliverables (`docs/latex/*.tex`) were updated first per the user's
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own more immediate request, but the markdown docs are this project's
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own real, authoritative source of truth per CLAUDE.md's own "Read
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first" section and deserve the same update.
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