Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed
Warning: IO 'start' is unconstrained in LPF and will be automatically placed
Warning: IO 'rst' is unconstrained in LPF and will be automatically placed
Warning: IO 'done' is unconstrained in LPF and will be automatically placed
Warning: IO 'clk' is unconstrained in LPF and will be automatically placed
Warning: IO 'busy' is unconstrained in LPF and will be automatically placed

Info: Logic utilisation before packing:
Info:     Total LUT4s:       481/43848     1%
Info:         logic LUTs:     95/43848     0%
Info:         carry LUTs:    386/43848     0%
Info:           RAM LUTs:      0/ 5481     0%
Info:          RAMW LUTs:      0/10962     0%

Info:      Total DFFs:       198/43848     0%

Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     191 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x83be9e7c

Info: Device utilisation:
Info: 	          TRELLIS_IO:      37/    245    15%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    108     0%
Info: 	          MULT18X18D:       8/     72    11%
Info: 	              ALU54B:       0/     36     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    160     0%
Info: 	            SIOLOGIC:       0/     85     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     10     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:     198/  43848     0%
Info: 	        TRELLIS_COMB:     551/  43848     1%
Info: 	        TRELLIS_RAMW:       0/   5481     0%

Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 129 cells, random placement wirelen = 25757.
Info:     at initial placer iter 0, wirelen = 3145
Info:     at initial placer iter 1, wirelen = 2698
Info:     at initial placer iter 2, wirelen = 2587
Info:     at initial placer iter 3, wirelen = 2563
Info: Running main analytical placer, max placement attempts per cell = 79003.
Info:     at iteration #1, type ALL: wirelen solved = 2537, spread = 4133, legal = 5191; time = 0.01s
Info:     at iteration #2, type ALL: wirelen solved = 2554, spread = 3904, legal = 4675; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 2545, spread = 3704, legal = 4373; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 2549, spread = 3862, legal = 4324; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 2590, spread = 3707, legal = 4361; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 2544, spread = 3885, legal = 4543; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 2578, spread = 3986, legal = 4545; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 2595, spread = 3719, legal = 4059; time = 0.00s
Info:     at iteration #9, type ALL: wirelen solved = 2683, spread = 4065, legal = 4376; time = 0.00s
Info:     at iteration #10, type ALL: wirelen solved = 2650, spread = 3696, legal = 3917; time = 0.00s
Info:     at iteration #11, type ALL: wirelen solved = 2605, spread = 3682, legal = 4248; time = 0.00s
Info:     at iteration #12, type ALL: wirelen solved = 2652, spread = 3920, legal = 4328; time = 0.00s
Info:     at iteration #13, type ALL: wirelen solved = 2686, spread = 3988, legal = 4511; time = 0.00s
Info:     at iteration #14, type ALL: wirelen solved = 2675, spread = 3787, legal = 4235; time = 0.00s
Info:     at iteration #15, type ALL: wirelen solved = 2706, spread = 3567, legal = 4256; time = 0.00s
Info: HeAP Placer Time: 0.09s
Info:   of which solving equations: 0.05s
Info:   of which spreading cells: 0.01s
Info:   of which strict legalisation: 0.01s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 124, wirelen = 3917
Info:   at iteration #5: temp = 0.000000, timing cost = 93, wirelen = 2856
Info:   at iteration #10: temp = 0.000000, timing cost = 103, wirelen = 2805
Info:   at iteration #13: temp = 0.000000, timing cost = 103, wirelen = 2799 
Info: SA placement time 0.16s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 98.23 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.59 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 7.53 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  2320,   2801) |****+
Info: [  2801,   3282) |****+
Info: [  3282,   3763) | 
Info: [  3763,   4244) | 
Info: [  4244,   4725) | 
Info: [  4725,   5206) |*******+
Info: [  5206,   5687) |*********************+
Info: [  5687,   6168) |*********+
Info: [  6168,   6649) |*** 
Info: [  6649,   7130) |*+
Info: [  7130,   7611) | 
Info: [  7611,   8092) |****+
Info: [  8092,   8573) |*****************+
Info: [  8573,   9054) |********************+
Info: [  9054,   9535) |****************************************+
Info: [  9535,  10016) |************************************+
Info: [ 10016,  10497) |************************************************************ 
Info: [ 10497,  10978) |*********************************************************+
Info: [ 10978,  11459) |**********************************+
Info: [ 11459,  11940) |***+
Info: Checksum: 0x9ce6835b
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 1805 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      401        520 |  401   520 |      1232|       0.13       0.13|
Info:       2000 |      429       1378 |   28   858 |       263|       0.05       0.18|
Info:       2263 |      430       1606 |    1   228 |         0|       0.05       0.23|
Info: Routing complete.
Info: Router1 time 0.23s
Info: Checksum: 0xb5a832a6

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q
Info:    routing  0.87  1.27 Net u_layer.GEN_NEURON[3].u_neuron.w_group[10] (64,23) -> (65,22)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.B2
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50
Info:      logic  3.07  4.33 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.P5
Info:    routing  1.12  5.45 Net u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1][5] (65,22) -> (64,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.A
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
Info:      logic  0.35  5.81 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  5.81 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_COUT (64,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCO
Info:    routing  0.00  5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCI
Info:      logic  0.00  5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCO
Info:    routing  0.00  5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCI
Info:      logic  0.00  5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCO
Info:    routing  0.00  5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCI
Info:      logic  0.00  5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCO
Info:    routing  0.00  6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCI
Info:      logic  0.00  6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_COUT (65,21) -> (66,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCO
Info:    routing  0.00  6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_FCI_INT (66,21) -> (66,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCI
Info:      logic  0.00  6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCO
Info:    routing  0.00  6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT (66,21) -> (66,21)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.33  6.42 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F
Info:    routing  0.89  7.31 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S0 (66,21) -> (66,19)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.B
Info:      logic  0.35  7.66 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO
Info:    routing  0.00  7.66 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_COUT (66,19) -> (66,19)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
Info:    routing  0.00  7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (66,19) -> (66,19)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
Info:      logic  0.00  7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
Info:    routing  0.00  7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_COUT (66,19) -> (66,19)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.33  8.05 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.F
Info:    routing  0.87  8.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next[20] (66,19) -> (66,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
Info:      logic  0.35  9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:    routing  0.00  9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (66,18) -> (66,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:      logic  0.00  9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:    routing  0.00  9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (66,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:    routing  0.00  9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:      logic  0.00  9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:    routing  0.00  9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:    routing  0.00  9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:      logic  0.00  9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:    routing  0.00  9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:    routing  0.00  9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:      logic  0.00  9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:    routing  0.00  9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.06  9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:    routing  0.00  9.50 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:      logic  0.00  9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:    routing  0.00  9.50 Net $nextpnr_CCU2C_13$CIN (67,18) -> (68,18)
Info:                          Sink $nextpnr_CCU2C_13$CCU2_COMB0.FCI
Info:      logic  0.33  9.82 Source $nextpnr_CCU2C_13$CCU2_COMB0.F
Info:    routing  0.52  10.35 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D (68,18) -> (68,20)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.D
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info:                               /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info:                               /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info:      logic  0.18  10.53 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info:    routing  0.55  11.08 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (68,20) -> (67,20)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.D
Info:                          Defined in:
Info:                               /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info:      logic  0.18  11.26 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.F
Info:    routing  0.12  11.38 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI[5] (67,20) -> (67,20)
Info:                          Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI
Info:      setup  0.00  11.38 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI
Info: 6.43 ns logic, 4.95 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info:       type curr  total name
Info:     source  0.00  0.00 Source start$tr_io.O
Info:    routing  3.44  3.44 Net start$TRELLIS_IO_IN (0,23) -> (70,21)
Info:                          Sink u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.B
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16
Info:      logic  0.18  3.62 Source u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.F
Info:    routing  0.66  4.28 Net u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z[1] (70,21) -> (72,24)
Info:                          Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.C
Info:                          Defined in:
Info:                               /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info:      logic  0.18  4.46 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.F
Info:    routing  0.60  5.07 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D[3] (72,24) -> (72,24)
Info:                          Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info:                          Defined in:
Info:                               /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info:      logic  0.18  5.25 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info:    routing  0.47  5.71 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR (72,24) -> (72,23)
Info:                          Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR
Info:      setup  0.29  6.00 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR
Info: 0.83 ns logic, 5.17 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_4.Q
Info:    routing  4.37  4.76 Net y_bus[28]$TRELLIS_IO_OUT (66,20) -> (18,71)
Info:                          Sink y_bus[28]$tr_io.I
Info:                          Defined in:
Info:                               /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:6.26-6.31
Info: 0.40 ns logic, 4.37 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 87.88 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.00 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 4.76 ns

Info: Slack histogram:
Info:  legend: * represents 2 endpoint(s)
Info:          + represents [1,2) endpoint(s)
Info: [  1121,   1647) |***+
Info: [  1647,   2173) |*+
Info: [  2173,   2699) | 
Info: [  2699,   3225) | 
Info: [  3225,   3751) | 
Info: [  3751,   4277) |*****+
Info: [  4277,   4803) |**************+
Info: [  4803,   5329) |***+
Info: [  5329,   5855) |***+
Info: [  5855,   6381) |+
Info: [  6381,   6907) | 
Info: [  6907,   7433) |***+
Info: [  7433,   7959) |*******+
Info: [  7959,   8485) |****+
Info: [  8485,   9011) |********+
Info: [  9011,   9537) |****************+
Info: [  9537,  10063) |******************+
Info: [ 10063,  10589) |************************************************************ 
Info: [ 10589,  11115) |*************************************+
Info: [ 11115,  11641) |*************************+
37 warnings, 0 errors

Info: Program finished normally.
