#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
:ivl_version "13.0 (stable)" "(v13_0)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
S_0x100fcded0 .scope package, "$unit" "$unit" 2 1;
 .timescale 0 0;
S_0x100fce6d0 .scope module, "tb" "tb" 3 3;
 .timescale -9 -12;
P_0x96c517840 .param/l "ACC_WIDTH" 0 3 9, +C4<00000000000000000000000000100000>;
P_0x96c517880 .param/l "DATA_WIDTH" 0 3 5, +C4<00000000000000000000000000001000>;
P_0x96c5178c0 .param/l "N_INPUTS" 0 3 6, +C4<00000000000000000000000100000000>;
P_0x96c517900 .param/l "N_NEURONS" 0 3 7, +C4<00000000000000000000000000000100>;
P_0x96c517940 .param/l "PARALLEL" 0 3 8, +C4<00000000000000000000000000100000>;
v0x96d2a4aa0_0 .var/s "bias_bus", 31 0;
v0x96d2a4b40_0 .net "busy", 0 0, L_0x96c5d4000;  1 drivers
v0x96d2a4be0_0 .var "clk", 0 0;
v0x96d2a4c80_0 .net "done", 0 0, L_0x96c5d40a0;  1 drivers
v0x96d2a4d20_0 .var/i "errors", 31 0;
v0x96d2a4dc0_0 .var/i "expected", 31 0;
v0x96d2a4e60_0 .var/i "i", 31 0;
v0x96d2a4f00_0 .var "rst", 0 0;
v0x96d2a4fa0_0 .var "start", 0 0;
v0x96d2a5040_0 .var/s "weights_bus", 8191 0;
v0x96d2a50e0_0 .var/s "x_bus", 2047 0;
v0x96d2a5180_0 .net/s "y_bus", 31 0, L_0x96c5c7c00;  1 drivers
S_0x100fcf810 .scope module, "dut" "layer" 3 38, 4 1 0, S_0x100fce6d0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "start";
    .port_info 3 /INPUT 2048 "x_bus";
    .port_info 4 /INPUT 8192 "weights_bus";
    .port_info 5 /INPUT 32 "bias_bus";
    .port_info 6 /OUTPUT 32 "y_bus";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "done";
P_0x96c5175c0 .param/l "ACC_WIDTH" 0 4 6, +C4<00000000000000000000000000100000>;
P_0x96c517600 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
P_0x96c517640 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000100000000>;
P_0x96c517680 .param/l "N_NEURONS" 0 4 4, +C4<00000000000000000000000000000100>;
P_0x96c5176c0 .param/l "PARALLEL" 0 4 5, +C4<00000000000000000000000000100000>;
v0x96d2a43c0_0 .net/s "bias_bus", 31 0, v0x96d2a4aa0_0;  1 drivers
v0x96d2a4460_0 .net "busy", 0 0, L_0x96c5d4000;  alias, 1 drivers
v0x96d2a4500_0 .net "clk", 0 0, v0x96d2a4be0_0;  1 drivers
v0x96d2a45a0_0 .net "done", 0 0, L_0x96c5d40a0;  alias, 1 drivers
v0x96d2a4640_0 .net "neuron_busy", 3 0, L_0x96c5c7ca0;  1 drivers
v0x96d2a46e0_0 .net "neuron_done", 3 0, L_0x96c5c7d40;  1 drivers
v0x96d2a4780_0 .net "rst", 0 0, v0x96d2a4f00_0;  1 drivers
v0x96d2a4820_0 .net "start", 0 0, v0x96d2a4fa0_0;  1 drivers
v0x96d2a48c0_0 .net/s "weights_bus", 8191 0, v0x96d2a5040_0;  1 drivers
v0x96d2a4960_0 .net/s "x_bus", 2047 0, v0x96d2a50e0_0;  1 drivers
v0x96d2a4a00_0 .net/s "y_bus", 31 0, L_0x96c5c7c00;  alias, 1 drivers
L_0x96c5b00a0 .part v0x96d2a5040_0, 0, 2048;
L_0x96c5b0140 .part v0x96d2a4aa0_0, 0, 8;
L_0x96c5bc000 .part v0x96d2a5040_0, 2048, 2048;
L_0x96c5bc0a0 .part v0x96d2a4aa0_0, 8, 8;
L_0x96c5bff20 .part v0x96d2a5040_0, 4096, 2048;
L_0x96c5cc000 .part v0x96d2a4aa0_0, 16, 8;
L_0x96c5cfe80 .part v0x96d2a5040_0, 6144, 2048;
L_0x96c5cff20 .part v0x96d2a4aa0_0, 24, 8;
L_0x96c5c7c00 .concat8 [ 8 8 8 8], v0x96d25e300_0, v0x96d274320_0, v0x96d28a300_0, v0x96d2a4320_0;
L_0x96c5c7ca0 .concat8 [ 1 1 1 1], v0x96d25dc20_0, v0x96d26fc00_0, v0x96d289c20_0, v0x96d29fc00_0;
L_0x96c5c7d40 .concat8 [ 1 1 1 1], v0x96d25dd60_0, v0x96d26fd40_0, v0x96d289d60_0, v0x96d29fd40_0;
L_0x96c5d4000 .reduce/or L_0x96c5c7ca0;
L_0x96c5d40a0 .reduce/and L_0x96c5c7d40;
S_0x100fcf250 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 4 34, 4 34 0, S_0x100fcf810;
 .timescale 0 0;
P_0x96cc07d40 .param/l "n" 1 4 34, +C4<00>;
S_0x100fcec90 .scope module, "u_neuron" "neuron_parallel" 4 41, 5 1 0, S_0x100fcf250;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "start";
    .port_info 3 /INPUT 2048 "x_bus";
    .port_info 4 /INPUT 2048 "w_bus";
    .port_info 5 /INPUT 8 "bias";
    .port_info 6 /OUTPUT 8 "y";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "done";
P_0x100fc63e0 .param/l "ACC_WIDTH" 0 5 5, +C4<00000000000000000000000000100000>;
P_0x100fc6420 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
P_0x100fc6460 .param/l "GROUPS" 1 5 20, +C4<00000000000000000000000000001000>;
P_0x100fc64a0 .param/l "GROUP_INDEX_WIDTH" 1 5 21, +C4<00000000000000000000000000000011>;
P_0x100fc64e0 .param/l "N_INPUTS" 0 5 3, +C4<00000000000000000000000100000000>;
P_0x100fc6520 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000100000>;
v0x96d25d0e0_0 .net *"_ivl_0", 31 0, L_0x96c478fa0;  1 drivers
v0x96d25d180_0 .net *"_ivl_11", 31 0, L_0x96d2a52c0;  1 drivers
v0x96d25d220_0 .net *"_ivl_14", 31 0, L_0x96c479180;  1 drivers
L_0x96c8540e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25d2c0_0 .net *"_ivl_17", 28 0, L_0x96c8540e8;  1 drivers
L_0x96c854130 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d25d360_0 .net/2u *"_ivl_18", 31 0, L_0x96c854130;  1 drivers
v0x96d25d400_0 .net *"_ivl_21", 31 0, L_0x96d2a5360;  1 drivers
L_0x96c854178 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d25d4a0_0 .net/2u *"_ivl_22", 31 0, L_0x96c854178;  1 drivers
v0x96d25d540_0 .net *"_ivl_25", 31 0, L_0x96d2a5400;  1 drivers
v0x96d25d5e0_0 .net *"_ivl_29", 0 0, L_0x96c5b0000;  1 drivers
L_0x96c854010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25d680_0 .net *"_ivl_3", 28 0, L_0x96c854010;  1 drivers
v0x96d25d720_0 .net *"_ivl_31", 23 0, L_0x96d2aa4e0;  1 drivers
L_0x96c854058 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d25d7c0_0 .net/2u *"_ivl_4", 31 0, L_0x96c854058;  1 drivers
v0x96d25d860_0 .net *"_ivl_7", 31 0, L_0x96d2a5220;  1 drivers
L_0x96c8540a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d25d900_0 .net/2u *"_ivl_8", 31 0, L_0x96c8540a0;  1 drivers
v0x96d25d9a0_0 .var/s "acc", 31 0;
v0x96d25da40_0 .net/s "acc_next", 31 0, L_0x96c47b840;  1 drivers
v0x96d25dae0_0 .net/s "bias", 7 0, L_0x96c5b0140;  1 drivers
v0x96d25db80_0 .net/s "bias_ext", 31 0, L_0x96c47b8e0;  1 drivers
v0x96d25dc20_0 .var "busy", 0 0;
v0x96d25dcc0_0 .net "clk", 0 0, v0x96d2a4be0_0;  alias, 1 drivers
v0x96d25dd60_0 .var "done", 0 0;
v0x96d25de00_0 .net/s "final_acc", 31 0, L_0x96c47b980;  1 drivers
v0x96d25dea0_0 .var "group_index", 2 0;
v0x96d25df40_0 .net "rst", 0 0, v0x96d2a4f00_0;  alias, 1 drivers
v0x96d25dfe0_0 .net "start", 0 0, v0x96d2a4fa0_0;  alias, 1 drivers
v0x96d25e080_0 .net/s "w_bus", 2047 0, L_0x96c5b00a0;  1 drivers
v0x96d25e120_0 .net/s "w_group", 255 0, L_0x96c55c1e0;  1 drivers
v0x96d25e1c0_0 .net/s "x_bus", 2047 0, v0x96d2a50e0_0;  alias, 1 drivers
v0x96d25e260_0 .net/s "x_group", 255 0, L_0x96c55c500;  1 drivers
v0x96d25e300_0 .var/s "y", 7 0;
E_0x96d18bc40 .event posedge, v0x96d25dcc0_0;
L_0x96c478fa0 .concat [ 3 29 0 0], v0x96d25dea0_0, L_0x96c854010;
L_0x96d2a5220 .arith/mult 32, L_0x96c478fa0, L_0x96c854058;
L_0x96d2a52c0 .arith/mult 32, L_0x96d2a5220, L_0x96c8540a0;
L_0x96c55c500 .part/v v0x96d2a50e0_0, L_0x96d2a52c0, 256;
L_0x96c479180 .concat [ 3 29 0 0], v0x96d25dea0_0, L_0x96c8540e8;
L_0x96d2a5360 .arith/mult 32, L_0x96c479180, L_0x96c854130;
L_0x96d2a5400 .arith/mult 32, L_0x96d2a5360, L_0x96c854178;
L_0x96c55c1e0 .part/v L_0x96c5b00a0, L_0x96d2a5400, 256;
L_0x96c5b0000 .part L_0x96c5b0140, 7, 1;
L_0x96d2aa4e0 .repeat 24, 24, L_0x96c5b0000;
L_0x96c47b8e0 .concat [ 8 24 0 0], L_0x96c5b0140, L_0x96d2aa4e0;
L_0x96c47b980 .arith/sum 32, L_0x96c47b840, L_0x96c47b8e0;
S_0x100fc6560 .scope module, "u_mac8" "mac8" 5 52, 6 1 0, S_0x100fcec90;
 .timescale 0 0;
    .port_info 0 /INPUT 256 "x_bus";
    .port_info 1 /INPUT 256 "w_bus";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fcee10 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
P_0x100fcee50 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
P_0x100fcee90 .param/l "PARALLEL" 0 6 4, +C4<00000000000000000000000000100000>;
v0x96d25cc80_0 .net/s "acc_in", 31 0, v0x96d25d9a0_0;  1 drivers
v0x96d25cd20_0 .net/s "acc_out", 31 0, L_0x96c47b840;  alias, 1 drivers
v0x96d25cdc0_0 .var/i "j", 31 0;
v0x96d25ce60 .array "products", 31 0;
v0x96d25ce60_0 .net/s v0x96d25ce60 0, 31 0, L_0x96c478f00; 1 drivers
v0x96d25ce60_1 .net/s v0x96d25ce60 1, 31 0, L_0x96c479220; 1 drivers
v0x96d25ce60_2 .net/s v0x96d25ce60 2, 31 0, L_0x96c479360; 1 drivers
v0x96d25ce60_3 .net/s v0x96d25ce60 3, 31 0, L_0x96c4794a0; 1 drivers
v0x96d25ce60_4 .net/s v0x96d25ce60 4, 31 0, L_0x96c4795e0; 1 drivers
v0x96d25ce60_5 .net/s v0x96d25ce60 5, 31 0, L_0x96c479720; 1 drivers
v0x96d25ce60_6 .net/s v0x96d25ce60 6, 31 0, L_0x96c479860; 1 drivers
v0x96d25ce60_7 .net/s v0x96d25ce60 7, 31 0, L_0x96c4799a0; 1 drivers
v0x96d25ce60_8 .net/s v0x96d25ce60 8, 31 0, L_0x96c479ae0; 1 drivers
v0x96d25ce60_9 .net/s v0x96d25ce60 9, 31 0, L_0x96c479c20; 1 drivers
v0x96d25ce60_10 .net/s v0x96d25ce60 10, 31 0, L_0x96c479d60; 1 drivers
v0x96d25ce60_11 .net/s v0x96d25ce60 11, 31 0, L_0x96c479ea0; 1 drivers
v0x96d25ce60_12 .net/s v0x96d25ce60 12, 31 0, L_0x96c479fe0; 1 drivers
v0x96d25ce60_13 .net/s v0x96d25ce60 13, 31 0, L_0x96c47a120; 1 drivers
v0x96d25ce60_14 .net/s v0x96d25ce60 14, 31 0, L_0x96c47a260; 1 drivers
v0x96d25ce60_15 .net/s v0x96d25ce60 15, 31 0, L_0x96c47a3a0; 1 drivers
v0x96d25ce60_16 .net/s v0x96d25ce60 16, 31 0, L_0x96c47a4e0; 1 drivers
v0x96d25ce60_17 .net/s v0x96d25ce60 17, 31 0, L_0x96c47a620; 1 drivers
v0x96d25ce60_18 .net/s v0x96d25ce60 18, 31 0, L_0x96c47a760; 1 drivers
v0x96d25ce60_19 .net/s v0x96d25ce60 19, 31 0, L_0x96c47a8a0; 1 drivers
v0x96d25ce60_20 .net/s v0x96d25ce60 20, 31 0, L_0x96c47a9e0; 1 drivers
v0x96d25ce60_21 .net/s v0x96d25ce60 21, 31 0, L_0x96c47ab20; 1 drivers
v0x96d25ce60_22 .net/s v0x96d25ce60 22, 31 0, L_0x96c47ac60; 1 drivers
v0x96d25ce60_23 .net/s v0x96d25ce60 23, 31 0, L_0x96c47ada0; 1 drivers
v0x96d25ce60_24 .net/s v0x96d25ce60 24, 31 0, L_0x96c47aee0; 1 drivers
v0x96d25ce60_25 .net/s v0x96d25ce60 25, 31 0, L_0x96c47b020; 1 drivers
v0x96d25ce60_26 .net/s v0x96d25ce60 26, 31 0, L_0x96c47b160; 1 drivers
v0x96d25ce60_27 .net/s v0x96d25ce60 27, 31 0, L_0x96c47b2a0; 1 drivers
v0x96d25ce60_28 .net/s v0x96d25ce60 28, 31 0, L_0x96c47b3e0; 1 drivers
v0x96d25ce60_29 .net/s v0x96d25ce60 29, 31 0, L_0x96c47b520; 1 drivers
v0x96d25ce60_30 .net/s v0x96d25ce60 30, 31 0, L_0x96c47b660; 1 drivers
v0x96d25ce60_31 .net/s v0x96d25ce60 31, 31 0, L_0x96c47b7a0; 1 drivers
v0x96d25cf00_0 .var/s "sum", 31 0;
v0x96d25cfa0_0 .net/s "w_bus", 255 0, L_0x96c55c1e0;  alias, 1 drivers
v0x96d25d040_0 .net/s "x_bus", 255 0, L_0x96c55c500;  alias, 1 drivers
E_0x96d18bc80/0 .event anyedge, v0x96d25cf00_0, v0x96d1146e0_0, v0x96d114d20_0, v0x96d115360_0;
E_0x96d18bc80/1 .event anyedge, v0x96d1159a0_0, v0x96d115fe0_0, v0x96d116620_0, v0x96d116c60_0;
E_0x96d18bc80/2 .event anyedge, v0x96d1172a0_0, v0x96d1178e0_0, v0x96d117f20_0, v0x96d2505a0_0;
E_0x96d18bc80/3 .event anyedge, v0x96d250be0_0, v0x96d251220_0, v0x96d251860_0, v0x96d251ea0_0;
E_0x96d18bc80/4 .event anyedge, v0x96d2524e0_0, v0x96d252b20_0, v0x96d253160_0, v0x96d2537a0_0;
E_0x96d18bc80/5 .event anyedge, v0x96d253de0_0, v0x96d254460_0, v0x96d254aa0_0, v0x96d2550e0_0;
E_0x96d18bc80/6 .event anyedge, v0x96d255720_0, v0x96d255d60_0, v0x96d2563a0_0, v0x96d2569e0_0;
E_0x96d18bc80/7 .event anyedge, v0x96d257020_0, v0x96d257660_0, v0x96d257ca0_0, v0x96d25c320_0;
E_0x96d18bc80/8 .event anyedge, v0x96d25c960_0;
E_0x96d18bc80 .event/or E_0x96d18bc80/0, E_0x96d18bc80/1, E_0x96d18bc80/2, E_0x96d18bc80/3, E_0x96d18bc80/4, E_0x96d18bc80/5, E_0x96d18bc80/6, E_0x96d18bc80/7, E_0x96d18bc80/8;
L_0x96c55c640 .part L_0x96c55c500, 0, 8;
L_0x96c55c6e0 .part L_0x96c55c1e0, 0, 8;
L_0x96c55c820 .part L_0x96c55c500, 8, 8;
L_0x96c55c8c0 .part L_0x96c55c1e0, 8, 8;
L_0x96c55ca00 .part L_0x96c55c500, 16, 8;
L_0x96c55caa0 .part L_0x96c55c1e0, 16, 8;
L_0x96c55cbe0 .part L_0x96c55c500, 24, 8;
L_0x96c55cc80 .part L_0x96c55c1e0, 24, 8;
L_0x96c55cdc0 .part L_0x96c55c500, 32, 8;
L_0x96c55ce60 .part L_0x96c55c1e0, 32, 8;
L_0x96c55cfa0 .part L_0x96c55c500, 40, 8;
L_0x96c55d040 .part L_0x96c55c1e0, 40, 8;
L_0x96c55d180 .part L_0x96c55c500, 48, 8;
L_0x96c55d220 .part L_0x96c55c1e0, 48, 8;
L_0x96c55d360 .part L_0x96c55c500, 56, 8;
L_0x96c55d400 .part L_0x96c55c1e0, 56, 8;
L_0x96c55d540 .part L_0x96c55c500, 64, 8;
L_0x96c55d5e0 .part L_0x96c55c1e0, 64, 8;
L_0x96c55d720 .part L_0x96c55c500, 72, 8;
L_0x96c55d7c0 .part L_0x96c55c1e0, 72, 8;
L_0x96c55d900 .part L_0x96c55c500, 80, 8;
L_0x96c55d9a0 .part L_0x96c55c1e0, 80, 8;
L_0x96c55dae0 .part L_0x96c55c500, 88, 8;
L_0x96c55db80 .part L_0x96c55c1e0, 88, 8;
L_0x96c55dcc0 .part L_0x96c55c500, 96, 8;
L_0x96c55dd60 .part L_0x96c55c1e0, 96, 8;
L_0x96c55dea0 .part L_0x96c55c500, 104, 8;
L_0x96c55df40 .part L_0x96c55c1e0, 104, 8;
L_0x96c55e080 .part L_0x96c55c500, 112, 8;
L_0x96c55e120 .part L_0x96c55c1e0, 112, 8;
L_0x96c55e260 .part L_0x96c55c500, 120, 8;
L_0x96c55e300 .part L_0x96c55c1e0, 120, 8;
L_0x96c55e440 .part L_0x96c55c500, 128, 8;
L_0x96c55e4e0 .part L_0x96c55c1e0, 128, 8;
L_0x96c55e620 .part L_0x96c55c500, 136, 8;
L_0x96c55e6c0 .part L_0x96c55c1e0, 136, 8;
L_0x96c55e800 .part L_0x96c55c500, 144, 8;
L_0x96c55e8a0 .part L_0x96c55c1e0, 144, 8;
L_0x96c55e9e0 .part L_0x96c55c500, 152, 8;
L_0x96c55ea80 .part L_0x96c55c1e0, 152, 8;
L_0x96c55ebc0 .part L_0x96c55c500, 160, 8;
L_0x96c55ec60 .part L_0x96c55c1e0, 160, 8;
L_0x96c55eda0 .part L_0x96c55c500, 168, 8;
L_0x96c55ee40 .part L_0x96c55c1e0, 168, 8;
L_0x96c55ef80 .part L_0x96c55c500, 176, 8;
L_0x96c55f020 .part L_0x96c55c1e0, 176, 8;
L_0x96c55f160 .part L_0x96c55c500, 184, 8;
L_0x96c55f200 .part L_0x96c55c1e0, 184, 8;
L_0x96c55f340 .part L_0x96c55c500, 192, 8;
L_0x96c55f3e0 .part L_0x96c55c1e0, 192, 8;
L_0x96c55f520 .part L_0x96c55c500, 200, 8;
L_0x96c55f5c0 .part L_0x96c55c1e0, 200, 8;
L_0x96c55f700 .part L_0x96c55c500, 208, 8;
L_0x96c55f7a0 .part L_0x96c55c1e0, 208, 8;
L_0x96c55f8e0 .part L_0x96c55c500, 216, 8;
L_0x96c55f980 .part L_0x96c55c1e0, 216, 8;
L_0x96c55fac0 .part L_0x96c55c500, 224, 8;
L_0x96c55fb60 .part L_0x96c55c1e0, 224, 8;
L_0x96c55fca0 .part L_0x96c55c500, 232, 8;
L_0x96c55fd40 .part L_0x96c55c1e0, 232, 8;
L_0x96c55fe80 .part L_0x96c55c500, 240, 8;
L_0x96c55ff20 .part L_0x96c55c1e0, 240, 8;
L_0x96c528140 .part L_0x96c55c500, 248, 8;
L_0x96c5000a0 .part L_0x96c55c1e0, 248, 8;
L_0x96c47b840 .arith/sum 32, v0x96d25d9a0_0, v0x96d25cf00_0;
S_0x100fc1a30 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07d80 .param/l "i" 1 6 17, +C4<00>;
S_0x100fc1bb0 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x100fc1a30;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fcf3d0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x100fcf410 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x100fcf450 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d1143c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a54a0;  1 drivers
v0x96d114460_0 .net/s *"_ivl_2", 15 0, L_0x96d2a5540;  1 drivers
v0x96d114500_0 .net *"_ivl_7", 0 0, L_0x96c55c5a0;  1 drivers
v0x96d1145a0_0 .net *"_ivl_9", 15 0, L_0x96d2a5680;  1 drivers
L_0x96c8541c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d114640_0 .net/s "acc_in", 31 0, L_0x96c8541c0;  1 drivers
v0x96d1146e0_0 .net/s "acc_out", 31 0, L_0x96c478f00;  alias, 1 drivers
v0x96d114780_0 .net/s "product", 15 0, L_0x96d2a55e0;  1 drivers
v0x96d114820_0 .net/s "product_ext", 31 0, L_0x96c4790e0;  1 drivers
v0x96d1148c0_0 .net/s "w", 7 0, L_0x96c55c6e0;  1 drivers
v0x96d114960_0 .net/s "x", 7 0, L_0x96c55c640;  1 drivers
L_0x96d2a54a0 .extend/s 16, L_0x96c55c640;
L_0x96d2a5540 .extend/s 16, L_0x96c55c6e0;
L_0x96d2a55e0 .arith/mult 16, L_0x96d2a54a0, L_0x96d2a5540;
L_0x96c55c5a0 .part L_0x96d2a55e0, 15, 1;
L_0x96d2a5680 .repeat 16, 16, L_0x96c55c5a0;
L_0x96c4790e0 .concat [ 16 16 0 0], L_0x96d2a55e0, L_0x96d2a5680;
L_0x96c478f00 .arith/sum 32, L_0x96c8541c0, L_0x96c4790e0;
S_0x100fba940 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07dc0 .param/l "i" 1 6 17, +C4<01>;
S_0x100fbaac0 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x100fba940;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fcf990 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x100fcf9d0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x100fcfa10 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d114a00_0 .net/s *"_ivl_0", 15 0, L_0x96d2a5720;  1 drivers
v0x96d114aa0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a57c0;  1 drivers
v0x96d114b40_0 .net *"_ivl_7", 0 0, L_0x96c55c780;  1 drivers
v0x96d114be0_0 .net *"_ivl_9", 15 0, L_0x96d2a5900;  1 drivers
L_0x96c854208 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d114c80_0 .net/s "acc_in", 31 0, L_0x96c854208;  1 drivers
v0x96d114d20_0 .net/s "acc_out", 31 0, L_0x96c479220;  alias, 1 drivers
v0x96d114dc0_0 .net/s "product", 15 0, L_0x96d2a5860;  1 drivers
v0x96d114e60_0 .net/s "product_ext", 31 0, L_0x96c478820;  1 drivers
v0x96d114f00_0 .net/s "w", 7 0, L_0x96c55c8c0;  1 drivers
v0x96d114fa0_0 .net/s "x", 7 0, L_0x96c55c820;  1 drivers
L_0x96d2a5720 .extend/s 16, L_0x96c55c820;
L_0x96d2a57c0 .extend/s 16, L_0x96c55c8c0;
L_0x96d2a5860 .arith/mult 16, L_0x96d2a5720, L_0x96d2a57c0;
L_0x96c55c780 .part L_0x96d2a5860, 15, 1;
L_0x96d2a5900 .repeat 16, 16, L_0x96c55c780;
L_0x96c478820 .concat [ 16 16 0 0], L_0x96d2a5860, L_0x96d2a5900;
L_0x96c479220 .arith/sum 32, L_0x96c854208, L_0x96c478820;
S_0x100fbe1f0 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07e00 .param/l "i" 1 6 17, +C4<010>;
S_0x96d24c000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x100fbe1f0;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fce850 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x100fce890 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x100fce8d0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d115040_0 .net/s *"_ivl_0", 15 0, L_0x96d2a59a0;  1 drivers
v0x96d1150e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a5a40;  1 drivers
v0x96d115180_0 .net *"_ivl_7", 0 0, L_0x96c55c960;  1 drivers
v0x96d115220_0 .net *"_ivl_9", 15 0, L_0x96d2a5b80;  1 drivers
L_0x96c854250 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d1152c0_0 .net/s "acc_in", 31 0, L_0x96c854250;  1 drivers
v0x96d115360_0 .net/s "acc_out", 31 0, L_0x96c479360;  alias, 1 drivers
v0x96d115400_0 .net/s "product", 15 0, L_0x96d2a5ae0;  1 drivers
v0x96d1154a0_0 .net/s "product_ext", 31 0, L_0x96c4792c0;  1 drivers
v0x96d115540_0 .net/s "w", 7 0, L_0x96c55caa0;  1 drivers
v0x96d1155e0_0 .net/s "x", 7 0, L_0x96c55ca00;  1 drivers
L_0x96d2a59a0 .extend/s 16, L_0x96c55ca00;
L_0x96d2a5a40 .extend/s 16, L_0x96c55caa0;
L_0x96d2a5ae0 .arith/mult 16, L_0x96d2a59a0, L_0x96d2a5a40;
L_0x96c55c960 .part L_0x96d2a5ae0, 15, 1;
L_0x96d2a5b80 .repeat 16, 16, L_0x96c55c960;
L_0x96c4792c0 .concat [ 16 16 0 0], L_0x96d2a5ae0, L_0x96d2a5b80;
L_0x96c479360 .arith/sum 32, L_0x96c854250, L_0x96c4792c0;
S_0x96d24c180 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07e40 .param/l "i" 1 6 17, +C4<011>;
S_0x96d24c300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24c180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fd0d90 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x100fd0dd0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x100fd0e10 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d115680_0 .net/s *"_ivl_0", 15 0, L_0x96d2a5c20;  1 drivers
v0x96d115720_0 .net/s *"_ivl_2", 15 0, L_0x96d2a5cc0;  1 drivers
v0x96d1157c0_0 .net *"_ivl_7", 0 0, L_0x96c55cb40;  1 drivers
v0x96d115860_0 .net *"_ivl_9", 15 0, L_0x96d2a5e00;  1 drivers
L_0x96c854298 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d115900_0 .net/s "acc_in", 31 0, L_0x96c854298;  1 drivers
v0x96d1159a0_0 .net/s "acc_out", 31 0, L_0x96c4794a0;  alias, 1 drivers
v0x96d115a40_0 .net/s "product", 15 0, L_0x96d2a5d60;  1 drivers
v0x96d115ae0_0 .net/s "product_ext", 31 0, L_0x96c479400;  1 drivers
v0x96d115b80_0 .net/s "w", 7 0, L_0x96c55cc80;  1 drivers
v0x96d115c20_0 .net/s "x", 7 0, L_0x96c55cbe0;  1 drivers
L_0x96d2a5c20 .extend/s 16, L_0x96c55cbe0;
L_0x96d2a5cc0 .extend/s 16, L_0x96c55cc80;
L_0x96d2a5d60 .arith/mult 16, L_0x96d2a5c20, L_0x96d2a5cc0;
L_0x96c55cb40 .part L_0x96d2a5d60, 15, 1;
L_0x96d2a5e00 .repeat 16, 16, L_0x96c55cb40;
L_0x96c479400 .concat [ 16 16 0 0], L_0x96d2a5d60, L_0x96d2a5e00;
L_0x96c4794a0 .arith/sum 32, L_0x96c854298, L_0x96c479400;
S_0x96d24c480 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07e80 .param/l "i" 1 6 17, +C4<0100>;
S_0x96d24c600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24c480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x100fd0b90 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x100fd0bd0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x100fd0c10 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d115cc0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a5ea0;  1 drivers
v0x96d115d60_0 .net/s *"_ivl_2", 15 0, L_0x96d2a5f40;  1 drivers
v0x96d115e00_0 .net *"_ivl_7", 0 0, L_0x96c55cd20;  1 drivers
v0x96d115ea0_0 .net *"_ivl_9", 15 0, L_0x96d2a6080;  1 drivers
L_0x96c8542e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d115f40_0 .net/s "acc_in", 31 0, L_0x96c8542e0;  1 drivers
v0x96d115fe0_0 .net/s "acc_out", 31 0, L_0x96c4795e0;  alias, 1 drivers
v0x96d116080_0 .net/s "product", 15 0, L_0x96d2a5fe0;  1 drivers
v0x96d116120_0 .net/s "product_ext", 31 0, L_0x96c479540;  1 drivers
v0x96d1161c0_0 .net/s "w", 7 0, L_0x96c55ce60;  1 drivers
v0x96d116260_0 .net/s "x", 7 0, L_0x96c55cdc0;  1 drivers
L_0x96d2a5ea0 .extend/s 16, L_0x96c55cdc0;
L_0x96d2a5f40 .extend/s 16, L_0x96c55ce60;
L_0x96d2a5fe0 .arith/mult 16, L_0x96d2a5ea0, L_0x96d2a5f40;
L_0x96c55cd20 .part L_0x96d2a5fe0, 15, 1;
L_0x96d2a6080 .repeat 16, 16, L_0x96c55cd20;
L_0x96c479540 .concat [ 16 16 0 0], L_0x96d2a5fe0, L_0x96d2a6080;
L_0x96c4795e0 .arith/sum 32, L_0x96c8542e0, L_0x96c479540;
S_0x96d24c780 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07ec0 .param/l "i" 1 6 17, +C4<0101>;
S_0x96d24c900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24c780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c000 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c040 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c080 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d116300_0 .net/s *"_ivl_0", 15 0, L_0x96d2a6120;  1 drivers
v0x96d1163a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a61c0;  1 drivers
v0x96d116440_0 .net *"_ivl_7", 0 0, L_0x96c55cf00;  1 drivers
v0x96d1164e0_0 .net *"_ivl_9", 15 0, L_0x96d2a6300;  1 drivers
L_0x96c854328 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d116580_0 .net/s "acc_in", 31 0, L_0x96c854328;  1 drivers
v0x96d116620_0 .net/s "acc_out", 31 0, L_0x96c479720;  alias, 1 drivers
v0x96d1166c0_0 .net/s "product", 15 0, L_0x96d2a6260;  1 drivers
v0x96d116760_0 .net/s "product_ext", 31 0, L_0x96c479680;  1 drivers
v0x96d116800_0 .net/s "w", 7 0, L_0x96c55d040;  1 drivers
v0x96d1168a0_0 .net/s "x", 7 0, L_0x96c55cfa0;  1 drivers
L_0x96d2a6120 .extend/s 16, L_0x96c55cfa0;
L_0x96d2a61c0 .extend/s 16, L_0x96c55d040;
L_0x96d2a6260 .arith/mult 16, L_0x96d2a6120, L_0x96d2a61c0;
L_0x96c55cf00 .part L_0x96d2a6260, 15, 1;
L_0x96d2a6300 .repeat 16, 16, L_0x96c55cf00;
L_0x96c479680 .concat [ 16 16 0 0], L_0x96d2a6260, L_0x96d2a6300;
L_0x96c479720 .arith/sum 32, L_0x96c854328, L_0x96c479680;
S_0x96d24ca80 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07f00 .param/l "i" 1 6 17, +C4<0110>;
S_0x96d24cc00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24ca80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c0c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d116940_0 .net/s *"_ivl_0", 15 0, L_0x96d2a63a0;  1 drivers
v0x96d1169e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a6440;  1 drivers
v0x96d116a80_0 .net *"_ivl_7", 0 0, L_0x96c55d0e0;  1 drivers
v0x96d116b20_0 .net *"_ivl_9", 15 0, L_0x96d2a6580;  1 drivers
L_0x96c854370 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d116bc0_0 .net/s "acc_in", 31 0, L_0x96c854370;  1 drivers
v0x96d116c60_0 .net/s "acc_out", 31 0, L_0x96c479860;  alias, 1 drivers
v0x96d116d00_0 .net/s "product", 15 0, L_0x96d2a64e0;  1 drivers
v0x96d116da0_0 .net/s "product_ext", 31 0, L_0x96c4797c0;  1 drivers
v0x96d116e40_0 .net/s "w", 7 0, L_0x96c55d220;  1 drivers
v0x96d116ee0_0 .net/s "x", 7 0, L_0x96c55d180;  1 drivers
L_0x96d2a63a0 .extend/s 16, L_0x96c55d180;
L_0x96d2a6440 .extend/s 16, L_0x96c55d220;
L_0x96d2a64e0 .arith/mult 16, L_0x96d2a63a0, L_0x96d2a6440;
L_0x96c55d0e0 .part L_0x96d2a64e0, 15, 1;
L_0x96d2a6580 .repeat 16, 16, L_0x96c55d0e0;
L_0x96c4797c0 .concat [ 16 16 0 0], L_0x96d2a64e0, L_0x96d2a6580;
L_0x96c479860 .arith/sum 32, L_0x96c854370, L_0x96c4797c0;
S_0x96d24cd80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07f40 .param/l "i" 1 6 17, +C4<0111>;
S_0x96d24cf00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24cd80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c1c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d116f80_0 .net/s *"_ivl_0", 15 0, L_0x96d2a6620;  1 drivers
v0x96d117020_0 .net/s *"_ivl_2", 15 0, L_0x96d2a66c0;  1 drivers
v0x96d1170c0_0 .net *"_ivl_7", 0 0, L_0x96c55d2c0;  1 drivers
v0x96d117160_0 .net *"_ivl_9", 15 0, L_0x96d2a6800;  1 drivers
L_0x96c8543b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d117200_0 .net/s "acc_in", 31 0, L_0x96c8543b8;  1 drivers
v0x96d1172a0_0 .net/s "acc_out", 31 0, L_0x96c4799a0;  alias, 1 drivers
v0x96d117340_0 .net/s "product", 15 0, L_0x96d2a6760;  1 drivers
v0x96d1173e0_0 .net/s "product_ext", 31 0, L_0x96c479900;  1 drivers
v0x96d117480_0 .net/s "w", 7 0, L_0x96c55d400;  1 drivers
v0x96d117520_0 .net/s "x", 7 0, L_0x96c55d360;  1 drivers
L_0x96d2a6620 .extend/s 16, L_0x96c55d360;
L_0x96d2a66c0 .extend/s 16, L_0x96c55d400;
L_0x96d2a6760 .arith/mult 16, L_0x96d2a6620, L_0x96d2a66c0;
L_0x96c55d2c0 .part L_0x96d2a6760, 15, 1;
L_0x96d2a6800 .repeat 16, 16, L_0x96c55d2c0;
L_0x96c479900 .concat [ 16 16 0 0], L_0x96d2a6760, L_0x96d2a6800;
L_0x96c4799a0 .arith/sum 32, L_0x96c8543b8, L_0x96c479900;
S_0x96d24d080 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07f80 .param/l "i" 1 6 17, +C4<01000>;
S_0x96d24d200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24d080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c2c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d1175c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a68a0;  1 drivers
v0x96d117660_0 .net/s *"_ivl_2", 15 0, L_0x96d2a6940;  1 drivers
v0x96d117700_0 .net *"_ivl_7", 0 0, L_0x96c55d4a0;  1 drivers
v0x96d1177a0_0 .net *"_ivl_9", 15 0, L_0x96d2a6a80;  1 drivers
L_0x96c854400 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d117840_0 .net/s "acc_in", 31 0, L_0x96c854400;  1 drivers
v0x96d1178e0_0 .net/s "acc_out", 31 0, L_0x96c479ae0;  alias, 1 drivers
v0x96d117980_0 .net/s "product", 15 0, L_0x96d2a69e0;  1 drivers
v0x96d117a20_0 .net/s "product_ext", 31 0, L_0x96c479a40;  1 drivers
v0x96d117ac0_0 .net/s "w", 7 0, L_0x96c55d5e0;  1 drivers
v0x96d117b60_0 .net/s "x", 7 0, L_0x96c55d540;  1 drivers
L_0x96d2a68a0 .extend/s 16, L_0x96c55d540;
L_0x96d2a6940 .extend/s 16, L_0x96c55d5e0;
L_0x96d2a69e0 .arith/mult 16, L_0x96d2a68a0, L_0x96d2a6940;
L_0x96c55d4a0 .part L_0x96d2a69e0, 15, 1;
L_0x96d2a6a80 .repeat 16, 16, L_0x96c55d4a0;
L_0x96c479a40 .concat [ 16 16 0 0], L_0x96d2a69e0, L_0x96d2a6a80;
L_0x96c479ae0 .arith/sum 32, L_0x96c854400, L_0x96c479a40;
S_0x96d24d380 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96cc07fc0 .param/l "i" 1 6 17, +C4<01001>;
S_0x96d24d500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24d380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d117c00_0 .net/s *"_ivl_0", 15 0, L_0x96d2a6bc0;  1 drivers
v0x96d117ca0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a6c60;  1 drivers
v0x96d117d40_0 .net *"_ivl_7", 0 0, L_0x96c55d680;  1 drivers
v0x96d117de0_0 .net *"_ivl_9", 15 0, L_0x96d2a6da0;  1 drivers
L_0x96c854448 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d117e80_0 .net/s "acc_in", 31 0, L_0x96c854448;  1 drivers
v0x96d117f20_0 .net/s "acc_out", 31 0, L_0x96c479c20;  alias, 1 drivers
v0x96d250000_0 .net/s "product", 15 0, L_0x96d2a6d00;  1 drivers
v0x96d2500a0_0 .net/s "product_ext", 31 0, L_0x96c479b80;  1 drivers
v0x96d250140_0 .net/s "w", 7 0, L_0x96c55d7c0;  1 drivers
v0x96d2501e0_0 .net/s "x", 7 0, L_0x96c55d720;  1 drivers
L_0x96d2a6bc0 .extend/s 16, L_0x96c55d720;
L_0x96d2a6c60 .extend/s 16, L_0x96c55d7c0;
L_0x96d2a6d00 .arith/mult 16, L_0x96d2a6bc0, L_0x96d2a6c60;
L_0x96c55d680 .part L_0x96d2a6d00, 15, 1;
L_0x96d2a6da0 .repeat 16, 16, L_0x96c55d680;
L_0x96c479b80 .concat [ 16 16 0 0], L_0x96d2a6d00, L_0x96d2a6da0;
L_0x96c479c20 .arith/sum 32, L_0x96c854448, L_0x96c479b80;
S_0x96d24d680 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c580000 .param/l "i" 1 6 17, +C4<01010>;
S_0x96d24d800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24d680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c3c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d250280_0 .net/s *"_ivl_0", 15 0, L_0x96d2a6e40;  1 drivers
v0x96d250320_0 .net/s *"_ivl_2", 15 0, L_0x96d2a6ee0;  1 drivers
v0x96d2503c0_0 .net *"_ivl_7", 0 0, L_0x96c55d860;  1 drivers
v0x96d250460_0 .net *"_ivl_9", 15 0, L_0x96d2a7020;  1 drivers
L_0x96c854490 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d250500_0 .net/s "acc_in", 31 0, L_0x96c854490;  1 drivers
v0x96d2505a0_0 .net/s "acc_out", 31 0, L_0x96c479d60;  alias, 1 drivers
v0x96d250640_0 .net/s "product", 15 0, L_0x96d2a6f80;  1 drivers
v0x96d2506e0_0 .net/s "product_ext", 31 0, L_0x96c479cc0;  1 drivers
v0x96d250780_0 .net/s "w", 7 0, L_0x96c55d9a0;  1 drivers
v0x96d250820_0 .net/s "x", 7 0, L_0x96c55d900;  1 drivers
L_0x96d2a6e40 .extend/s 16, L_0x96c55d900;
L_0x96d2a6ee0 .extend/s 16, L_0x96c55d9a0;
L_0x96d2a6f80 .arith/mult 16, L_0x96d2a6e40, L_0x96d2a6ee0;
L_0x96c55d860 .part L_0x96d2a6f80, 15, 1;
L_0x96d2a7020 .repeat 16, 16, L_0x96c55d860;
L_0x96c479cc0 .concat [ 16 16 0 0], L_0x96d2a6f80, L_0x96d2a7020;
L_0x96c479d60 .arith/sum 32, L_0x96c854490, L_0x96c479cc0;
S_0x96d24d980 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584000 .param/l "i" 1 6 17, +C4<01011>;
S_0x96d24db00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24d980;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c4c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2508c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a6b20;  1 drivers
v0x96d250960_0 .net/s *"_ivl_2", 15 0, L_0x96d2a70c0;  1 drivers
v0x96d250a00_0 .net *"_ivl_7", 0 0, L_0x96c55da40;  1 drivers
v0x96d250aa0_0 .net *"_ivl_9", 15 0, L_0x96d2a7200;  1 drivers
L_0x96c8544d8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d250b40_0 .net/s "acc_in", 31 0, L_0x96c8544d8;  1 drivers
v0x96d250be0_0 .net/s "acc_out", 31 0, L_0x96c479ea0;  alias, 1 drivers
v0x96d250c80_0 .net/s "product", 15 0, L_0x96d2a7160;  1 drivers
v0x96d250d20_0 .net/s "product_ext", 31 0, L_0x96c479e00;  1 drivers
v0x96d250dc0_0 .net/s "w", 7 0, L_0x96c55db80;  1 drivers
v0x96d250e60_0 .net/s "x", 7 0, L_0x96c55dae0;  1 drivers
L_0x96d2a6b20 .extend/s 16, L_0x96c55dae0;
L_0x96d2a70c0 .extend/s 16, L_0x96c55db80;
L_0x96d2a7160 .arith/mult 16, L_0x96d2a6b20, L_0x96d2a70c0;
L_0x96c55da40 .part L_0x96d2a7160, 15, 1;
L_0x96d2a7200 .repeat 16, 16, L_0x96c55da40;
L_0x96c479e00 .concat [ 16 16 0 0], L_0x96d2a7160, L_0x96d2a7200;
L_0x96c479ea0 .arith/sum 32, L_0x96c8544d8, L_0x96c479e00;
S_0x96d24dc80 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584040 .param/l "i" 1 6 17, +C4<01100>;
S_0x96d24de00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24dc80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c5c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d250f00_0 .net/s *"_ivl_0", 15 0, L_0x96d2a72a0;  1 drivers
v0x96d250fa0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a7340;  1 drivers
v0x96d251040_0 .net *"_ivl_7", 0 0, L_0x96c55dc20;  1 drivers
v0x96d2510e0_0 .net *"_ivl_9", 15 0, L_0x96d2a7480;  1 drivers
L_0x96c854520 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d251180_0 .net/s "acc_in", 31 0, L_0x96c854520;  1 drivers
v0x96d251220_0 .net/s "acc_out", 31 0, L_0x96c479fe0;  alias, 1 drivers
v0x96d2512c0_0 .net/s "product", 15 0, L_0x96d2a73e0;  1 drivers
v0x96d251360_0 .net/s "product_ext", 31 0, L_0x96c479f40;  1 drivers
v0x96d251400_0 .net/s "w", 7 0, L_0x96c55dd60;  1 drivers
v0x96d2514a0_0 .net/s "x", 7 0, L_0x96c55dcc0;  1 drivers
L_0x96d2a72a0 .extend/s 16, L_0x96c55dcc0;
L_0x96d2a7340 .extend/s 16, L_0x96c55dd60;
L_0x96d2a73e0 .arith/mult 16, L_0x96d2a72a0, L_0x96d2a7340;
L_0x96c55dc20 .part L_0x96d2a73e0, 15, 1;
L_0x96d2a7480 .repeat 16, 16, L_0x96c55dc20;
L_0x96c479f40 .concat [ 16 16 0 0], L_0x96d2a73e0, L_0x96d2a7480;
L_0x96c479fe0 .arith/sum 32, L_0x96c854520, L_0x96c479f40;
S_0x96d24df80 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584080 .param/l "i" 1 6 17, +C4<01101>;
S_0x96d24e100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24df80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c600 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c640 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c680 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d251540_0 .net/s *"_ivl_0", 15 0, L_0x96d2a7520;  1 drivers
v0x96d2515e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a75c0;  1 drivers
v0x96d251680_0 .net *"_ivl_7", 0 0, L_0x96c55de00;  1 drivers
v0x96d251720_0 .net *"_ivl_9", 15 0, L_0x96d2a7700;  1 drivers
L_0x96c854568 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2517c0_0 .net/s "acc_in", 31 0, L_0x96c854568;  1 drivers
v0x96d251860_0 .net/s "acc_out", 31 0, L_0x96c47a120;  alias, 1 drivers
v0x96d251900_0 .net/s "product", 15 0, L_0x96d2a7660;  1 drivers
v0x96d2519a0_0 .net/s "product_ext", 31 0, L_0x96c47a080;  1 drivers
v0x96d251a40_0 .net/s "w", 7 0, L_0x96c55df40;  1 drivers
v0x96d251ae0_0 .net/s "x", 7 0, L_0x96c55dea0;  1 drivers
L_0x96d2a7520 .extend/s 16, L_0x96c55dea0;
L_0x96d2a75c0 .extend/s 16, L_0x96c55df40;
L_0x96d2a7660 .arith/mult 16, L_0x96d2a7520, L_0x96d2a75c0;
L_0x96c55de00 .part L_0x96d2a7660, 15, 1;
L_0x96d2a7700 .repeat 16, 16, L_0x96c55de00;
L_0x96c47a080 .concat [ 16 16 0 0], L_0x96d2a7660, L_0x96d2a7700;
L_0x96c47a120 .arith/sum 32, L_0x96c854568, L_0x96c47a080;
S_0x96d24e280 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c5840c0 .param/l "i" 1 6 17, +C4<01110>;
S_0x96d24e400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24e280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c6c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d251b80_0 .net/s *"_ivl_0", 15 0, L_0x96d2a77a0;  1 drivers
v0x96d251c20_0 .net/s *"_ivl_2", 15 0, L_0x96d2a7840;  1 drivers
v0x96d251cc0_0 .net *"_ivl_7", 0 0, L_0x96c55dfe0;  1 drivers
v0x96d251d60_0 .net *"_ivl_9", 15 0, L_0x96d2a7980;  1 drivers
L_0x96c8545b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d251e00_0 .net/s "acc_in", 31 0, L_0x96c8545b0;  1 drivers
v0x96d251ea0_0 .net/s "acc_out", 31 0, L_0x96c47a260;  alias, 1 drivers
v0x96d251f40_0 .net/s "product", 15 0, L_0x96d2a78e0;  1 drivers
v0x96d251fe0_0 .net/s "product_ext", 31 0, L_0x96c47a1c0;  1 drivers
v0x96d252080_0 .net/s "w", 7 0, L_0x96c55e120;  1 drivers
v0x96d252120_0 .net/s "x", 7 0, L_0x96c55e080;  1 drivers
L_0x96d2a77a0 .extend/s 16, L_0x96c55e080;
L_0x96d2a7840 .extend/s 16, L_0x96c55e120;
L_0x96d2a78e0 .arith/mult 16, L_0x96d2a77a0, L_0x96d2a7840;
L_0x96c55dfe0 .part L_0x96d2a78e0, 15, 1;
L_0x96d2a7980 .repeat 16, 16, L_0x96c55dfe0;
L_0x96c47a1c0 .concat [ 16 16 0 0], L_0x96d2a78e0, L_0x96d2a7980;
L_0x96c47a260 .arith/sum 32, L_0x96c8545b0, L_0x96c47a1c0;
S_0x96d24e580 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584100 .param/l "i" 1 6 17, +C4<01111>;
S_0x96d24e700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24e580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c7c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2521c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a7a20;  1 drivers
v0x96d252260_0 .net/s *"_ivl_2", 15 0, L_0x96d2a7ac0;  1 drivers
v0x96d252300_0 .net *"_ivl_7", 0 0, L_0x96c55e1c0;  1 drivers
v0x96d2523a0_0 .net *"_ivl_9", 15 0, L_0x96d2a7c00;  1 drivers
L_0x96c8545f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d252440_0 .net/s "acc_in", 31 0, L_0x96c8545f8;  1 drivers
v0x96d2524e0_0 .net/s "acc_out", 31 0, L_0x96c47a3a0;  alias, 1 drivers
v0x96d252580_0 .net/s "product", 15 0, L_0x96d2a7b60;  1 drivers
v0x96d252620_0 .net/s "product_ext", 31 0, L_0x96c47a300;  1 drivers
v0x96d2526c0_0 .net/s "w", 7 0, L_0x96c55e300;  1 drivers
v0x96d252760_0 .net/s "x", 7 0, L_0x96c55e260;  1 drivers
L_0x96d2a7a20 .extend/s 16, L_0x96c55e260;
L_0x96d2a7ac0 .extend/s 16, L_0x96c55e300;
L_0x96d2a7b60 .arith/mult 16, L_0x96d2a7a20, L_0x96d2a7ac0;
L_0x96c55e1c0 .part L_0x96d2a7b60, 15, 1;
L_0x96d2a7c00 .repeat 16, 16, L_0x96c55e1c0;
L_0x96c47a300 .concat [ 16 16 0 0], L_0x96d2a7b60, L_0x96d2a7c00;
L_0x96c47a3a0 .arith/sum 32, L_0x96c8545f8, L_0x96c47a300;
S_0x96d24e880 .scope generate, "GEN_MAC[16]" "GEN_MAC[16]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584140 .param/l "i" 1 6 17, +C4<010000>;
S_0x96d24ea00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24e880;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c8c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d252800_0 .net/s *"_ivl_0", 15 0, L_0x96d2a7ca0;  1 drivers
v0x96d2528a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a7d40;  1 drivers
v0x96d252940_0 .net *"_ivl_7", 0 0, L_0x96c55e3a0;  1 drivers
v0x96d2529e0_0 .net *"_ivl_9", 15 0, L_0x96d2a7e80;  1 drivers
L_0x96c854640 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d252a80_0 .net/s "acc_in", 31 0, L_0x96c854640;  1 drivers
v0x96d252b20_0 .net/s "acc_out", 31 0, L_0x96c47a4e0;  alias, 1 drivers
v0x96d252bc0_0 .net/s "product", 15 0, L_0x96d2a7de0;  1 drivers
v0x96d252c60_0 .net/s "product_ext", 31 0, L_0x96c47a440;  1 drivers
v0x96d252d00_0 .net/s "w", 7 0, L_0x96c55e4e0;  1 drivers
v0x96d252da0_0 .net/s "x", 7 0, L_0x96c55e440;  1 drivers
L_0x96d2a7ca0 .extend/s 16, L_0x96c55e440;
L_0x96d2a7d40 .extend/s 16, L_0x96c55e4e0;
L_0x96d2a7de0 .arith/mult 16, L_0x96d2a7ca0, L_0x96d2a7d40;
L_0x96c55e3a0 .part L_0x96d2a7de0, 15, 1;
L_0x96d2a7e80 .repeat 16, 16, L_0x96c55e3a0;
L_0x96c47a440 .concat [ 16 16 0 0], L_0x96d2a7de0, L_0x96d2a7e80;
L_0x96c47a4e0 .arith/sum 32, L_0x96c854640, L_0x96c47a440;
S_0x96d24eb80 .scope generate, "GEN_MAC[17]" "GEN_MAC[17]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584180 .param/l "i" 1 6 17, +C4<010001>;
S_0x96d24ed00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24eb80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57c940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57c980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d252e40_0 .net/s *"_ivl_0", 15 0, L_0x96d2a7f20;  1 drivers
v0x96d252ee0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8000;  1 drivers
v0x96d252f80_0 .net *"_ivl_7", 0 0, L_0x96c55e580;  1 drivers
v0x96d253020_0 .net *"_ivl_9", 15 0, L_0x96d2a8140;  1 drivers
L_0x96c854688 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2530c0_0 .net/s "acc_in", 31 0, L_0x96c854688;  1 drivers
v0x96d253160_0 .net/s "acc_out", 31 0, L_0x96c47a620;  alias, 1 drivers
v0x96d253200_0 .net/s "product", 15 0, L_0x96d2a80a0;  1 drivers
v0x96d2532a0_0 .net/s "product_ext", 31 0, L_0x96c47a580;  1 drivers
v0x96d253340_0 .net/s "w", 7 0, L_0x96c55e6c0;  1 drivers
v0x96d2533e0_0 .net/s "x", 7 0, L_0x96c55e620;  1 drivers
L_0x96d2a7f20 .extend/s 16, L_0x96c55e620;
L_0x96d2a8000 .extend/s 16, L_0x96c55e6c0;
L_0x96d2a80a0 .arith/mult 16, L_0x96d2a7f20, L_0x96d2a8000;
L_0x96c55e580 .part L_0x96d2a80a0, 15, 1;
L_0x96d2a8140 .repeat 16, 16, L_0x96c55e580;
L_0x96c47a580 .concat [ 16 16 0 0], L_0x96d2a80a0, L_0x96d2a8140;
L_0x96c47a620 .arith/sum 32, L_0x96c854688, L_0x96c47a580;
S_0x96d24ee80 .scope generate, "GEN_MAC[18]" "GEN_MAC[18]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c5841c0 .param/l "i" 1 6 17, +C4<010010>;
S_0x96d24f000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24ee80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57c9c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ca00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ca40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d253480_0 .net/s *"_ivl_0", 15 0, L_0x96d2a81e0;  1 drivers
v0x96d253520_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8280;  1 drivers
v0x96d2535c0_0 .net *"_ivl_7", 0 0, L_0x96c55e760;  1 drivers
v0x96d253660_0 .net *"_ivl_9", 15 0, L_0x96d2a83c0;  1 drivers
L_0x96c8546d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d253700_0 .net/s "acc_in", 31 0, L_0x96c8546d0;  1 drivers
v0x96d2537a0_0 .net/s "acc_out", 31 0, L_0x96c47a760;  alias, 1 drivers
v0x96d253840_0 .net/s "product", 15 0, L_0x96d2a8320;  1 drivers
v0x96d2538e0_0 .net/s "product_ext", 31 0, L_0x96c47a6c0;  1 drivers
v0x96d253980_0 .net/s "w", 7 0, L_0x96c55e8a0;  1 drivers
v0x96d253a20_0 .net/s "x", 7 0, L_0x96c55e800;  1 drivers
L_0x96d2a81e0 .extend/s 16, L_0x96c55e800;
L_0x96d2a8280 .extend/s 16, L_0x96c55e8a0;
L_0x96d2a8320 .arith/mult 16, L_0x96d2a81e0, L_0x96d2a8280;
L_0x96c55e760 .part L_0x96d2a8320, 15, 1;
L_0x96d2a83c0 .repeat 16, 16, L_0x96c55e760;
L_0x96c47a6c0 .concat [ 16 16 0 0], L_0x96d2a8320, L_0x96d2a83c0;
L_0x96c47a760 .arith/sum 32, L_0x96c8546d0, L_0x96c47a6c0;
S_0x96d24f180 .scope generate, "GEN_MAC[19]" "GEN_MAC[19]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584200 .param/l "i" 1 6 17, +C4<010011>;
S_0x96d24f300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24f180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ca80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cb00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d253ac0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a8460;  1 drivers
v0x96d253b60_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8500;  1 drivers
v0x96d253c00_0 .net *"_ivl_7", 0 0, L_0x96c55e940;  1 drivers
v0x96d253ca0_0 .net *"_ivl_9", 15 0, L_0x96d2a8640;  1 drivers
L_0x96c854718 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d253d40_0 .net/s "acc_in", 31 0, L_0x96c854718;  1 drivers
v0x96d253de0_0 .net/s "acc_out", 31 0, L_0x96c47a8a0;  alias, 1 drivers
v0x96d253e80_0 .net/s "product", 15 0, L_0x96d2a85a0;  1 drivers
v0x96d253f20_0 .net/s "product_ext", 31 0, L_0x96c47a800;  1 drivers
v0x96d254000_0 .net/s "w", 7 0, L_0x96c55ea80;  1 drivers
v0x96d2540a0_0 .net/s "x", 7 0, L_0x96c55e9e0;  1 drivers
L_0x96d2a8460 .extend/s 16, L_0x96c55e9e0;
L_0x96d2a8500 .extend/s 16, L_0x96c55ea80;
L_0x96d2a85a0 .arith/mult 16, L_0x96d2a8460, L_0x96d2a8500;
L_0x96c55e940 .part L_0x96d2a85a0, 15, 1;
L_0x96d2a8640 .repeat 16, 16, L_0x96c55e940;
L_0x96c47a800 .concat [ 16 16 0 0], L_0x96d2a85a0, L_0x96d2a8640;
L_0x96c47a8a0 .arith/sum 32, L_0x96c854718, L_0x96c47a800;
S_0x96d24f480 .scope generate, "GEN_MAC[20]" "GEN_MAC[20]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584240 .param/l "i" 1 6 17, +C4<010100>;
S_0x96d24f600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24f480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57cb40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cb80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cbc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d254140_0 .net/s *"_ivl_0", 15 0, L_0x96d2a86e0;  1 drivers
v0x96d2541e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8780;  1 drivers
v0x96d254280_0 .net *"_ivl_7", 0 0, L_0x96c55eb20;  1 drivers
v0x96d254320_0 .net *"_ivl_9", 15 0, L_0x96d2a88c0;  1 drivers
L_0x96c854760 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2543c0_0 .net/s "acc_in", 31 0, L_0x96c854760;  1 drivers
v0x96d254460_0 .net/s "acc_out", 31 0, L_0x96c47a9e0;  alias, 1 drivers
v0x96d254500_0 .net/s "product", 15 0, L_0x96d2a8820;  1 drivers
v0x96d2545a0_0 .net/s "product_ext", 31 0, L_0x96c47a940;  1 drivers
v0x96d254640_0 .net/s "w", 7 0, L_0x96c55ec60;  1 drivers
v0x96d2546e0_0 .net/s "x", 7 0, L_0x96c55ebc0;  1 drivers
L_0x96d2a86e0 .extend/s 16, L_0x96c55ebc0;
L_0x96d2a8780 .extend/s 16, L_0x96c55ec60;
L_0x96d2a8820 .arith/mult 16, L_0x96d2a86e0, L_0x96d2a8780;
L_0x96c55eb20 .part L_0x96d2a8820, 15, 1;
L_0x96d2a88c0 .repeat 16, 16, L_0x96c55eb20;
L_0x96c47a940 .concat [ 16 16 0 0], L_0x96d2a8820, L_0x96d2a88c0;
L_0x96c47a9e0 .arith/sum 32, L_0x96c854760, L_0x96c47a940;
S_0x96d24f780 .scope generate, "GEN_MAC[21]" "GEN_MAC[21]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584280 .param/l "i" 1 6 17, +C4<010101>;
S_0x96d24f900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24f780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57cc00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cc40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cc80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d254780_0 .net/s *"_ivl_0", 15 0, L_0x96d2a8960;  1 drivers
v0x96d254820_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8a00;  1 drivers
v0x96d2548c0_0 .net *"_ivl_7", 0 0, L_0x96c55ed00;  1 drivers
v0x96d254960_0 .net *"_ivl_9", 15 0, L_0x96d2a8b40;  1 drivers
L_0x96c8547a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d254a00_0 .net/s "acc_in", 31 0, L_0x96c8547a8;  1 drivers
v0x96d254aa0_0 .net/s "acc_out", 31 0, L_0x96c47ab20;  alias, 1 drivers
v0x96d254b40_0 .net/s "product", 15 0, L_0x96d2a8aa0;  1 drivers
v0x96d254be0_0 .net/s "product_ext", 31 0, L_0x96c47aa80;  1 drivers
v0x96d254c80_0 .net/s "w", 7 0, L_0x96c55ee40;  1 drivers
v0x96d254d20_0 .net/s "x", 7 0, L_0x96c55eda0;  1 drivers
L_0x96d2a8960 .extend/s 16, L_0x96c55eda0;
L_0x96d2a8a00 .extend/s 16, L_0x96c55ee40;
L_0x96d2a8aa0 .arith/mult 16, L_0x96d2a8960, L_0x96d2a8a00;
L_0x96c55ed00 .part L_0x96d2a8aa0, 15, 1;
L_0x96d2a8b40 .repeat 16, 16, L_0x96c55ed00;
L_0x96c47aa80 .concat [ 16 16 0 0], L_0x96d2a8aa0, L_0x96d2a8b40;
L_0x96c47ab20 .arith/sum 32, L_0x96c8547a8, L_0x96c47aa80;
S_0x96d24fa80 .scope generate, "GEN_MAC[22]" "GEN_MAC[22]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c5842c0 .param/l "i" 1 6 17, +C4<010110>;
S_0x96d24fc00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24fa80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ccc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cd00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cd40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d254dc0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a8be0;  1 drivers
v0x96d254e60_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8c80;  1 drivers
v0x96d254f00_0 .net *"_ivl_7", 0 0, L_0x96c55eee0;  1 drivers
v0x96d254fa0_0 .net *"_ivl_9", 15 0, L_0x96d2a8dc0;  1 drivers
L_0x96c8547f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d255040_0 .net/s "acc_in", 31 0, L_0x96c8547f0;  1 drivers
v0x96d2550e0_0 .net/s "acc_out", 31 0, L_0x96c47ac60;  alias, 1 drivers
v0x96d255180_0 .net/s "product", 15 0, L_0x96d2a8d20;  1 drivers
v0x96d255220_0 .net/s "product_ext", 31 0, L_0x96c47abc0;  1 drivers
v0x96d2552c0_0 .net/s "w", 7 0, L_0x96c55f020;  1 drivers
v0x96d255360_0 .net/s "x", 7 0, L_0x96c55ef80;  1 drivers
L_0x96d2a8be0 .extend/s 16, L_0x96c55ef80;
L_0x96d2a8c80 .extend/s 16, L_0x96c55f020;
L_0x96d2a8d20 .arith/mult 16, L_0x96d2a8be0, L_0x96d2a8c80;
L_0x96c55eee0 .part L_0x96d2a8d20, 15, 1;
L_0x96d2a8dc0 .repeat 16, 16, L_0x96c55eee0;
L_0x96c47abc0 .concat [ 16 16 0 0], L_0x96d2a8d20, L_0x96d2a8dc0;
L_0x96c47ac60 .arith/sum 32, L_0x96c8547f0, L_0x96c47abc0;
S_0x96d24fd80 .scope generate, "GEN_MAC[23]" "GEN_MAC[23]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584300 .param/l "i" 1 6 17, +C4<010111>;
S_0x96d258000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d24fd80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57cd80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cdc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ce00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d255400_0 .net/s *"_ivl_0", 15 0, L_0x96d2a8e60;  1 drivers
v0x96d2554a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a8f00;  1 drivers
v0x96d255540_0 .net *"_ivl_7", 0 0, L_0x96c55f0c0;  1 drivers
v0x96d2555e0_0 .net *"_ivl_9", 15 0, L_0x96d2a9040;  1 drivers
L_0x96c854838 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d255680_0 .net/s "acc_in", 31 0, L_0x96c854838;  1 drivers
v0x96d255720_0 .net/s "acc_out", 31 0, L_0x96c47ada0;  alias, 1 drivers
v0x96d2557c0_0 .net/s "product", 15 0, L_0x96d2a8fa0;  1 drivers
v0x96d255860_0 .net/s "product_ext", 31 0, L_0x96c47ad00;  1 drivers
v0x96d255900_0 .net/s "w", 7 0, L_0x96c55f200;  1 drivers
v0x96d2559a0_0 .net/s "x", 7 0, L_0x96c55f160;  1 drivers
L_0x96d2a8e60 .extend/s 16, L_0x96c55f160;
L_0x96d2a8f00 .extend/s 16, L_0x96c55f200;
L_0x96d2a8fa0 .arith/mult 16, L_0x96d2a8e60, L_0x96d2a8f00;
L_0x96c55f0c0 .part L_0x96d2a8fa0, 15, 1;
L_0x96d2a9040 .repeat 16, 16, L_0x96c55f0c0;
L_0x96c47ad00 .concat [ 16 16 0 0], L_0x96d2a8fa0, L_0x96d2a9040;
L_0x96c47ada0 .arith/sum 32, L_0x96c854838, L_0x96c47ad00;
S_0x96d258180 .scope generate, "GEN_MAC[24]" "GEN_MAC[24]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584340 .param/l "i" 1 6 17, +C4<011000>;
S_0x96d258300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d258180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ce40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ce80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d255a40_0 .net/s *"_ivl_0", 15 0, L_0x96d2a90e0;  1 drivers
v0x96d255ae0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9180;  1 drivers
v0x96d255b80_0 .net *"_ivl_7", 0 0, L_0x96c55f2a0;  1 drivers
v0x96d255c20_0 .net *"_ivl_9", 15 0, L_0x96d2a92c0;  1 drivers
L_0x96c854880 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d255cc0_0 .net/s "acc_in", 31 0, L_0x96c854880;  1 drivers
v0x96d255d60_0 .net/s "acc_out", 31 0, L_0x96c47aee0;  alias, 1 drivers
v0x96d255e00_0 .net/s "product", 15 0, L_0x96d2a9220;  1 drivers
v0x96d255ea0_0 .net/s "product_ext", 31 0, L_0x96c47ae40;  1 drivers
v0x96d255f40_0 .net/s "w", 7 0, L_0x96c55f3e0;  1 drivers
v0x96d255fe0_0 .net/s "x", 7 0, L_0x96c55f340;  1 drivers
L_0x96d2a90e0 .extend/s 16, L_0x96c55f340;
L_0x96d2a9180 .extend/s 16, L_0x96c55f3e0;
L_0x96d2a9220 .arith/mult 16, L_0x96d2a90e0, L_0x96d2a9180;
L_0x96c55f2a0 .part L_0x96d2a9220, 15, 1;
L_0x96d2a92c0 .repeat 16, 16, L_0x96c55f2a0;
L_0x96c47ae40 .concat [ 16 16 0 0], L_0x96d2a9220, L_0x96d2a92c0;
L_0x96c47aee0 .arith/sum 32, L_0x96c854880, L_0x96c47ae40;
S_0x96d258480 .scope generate, "GEN_MAC[25]" "GEN_MAC[25]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584380 .param/l "i" 1 6 17, +C4<011001>;
S_0x96d258600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d258480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57cf00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57cf40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57cf80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d256080_0 .net/s *"_ivl_0", 15 0, L_0x96d2a9360;  1 drivers
v0x96d256120_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9400;  1 drivers
v0x96d2561c0_0 .net *"_ivl_7", 0 0, L_0x96c55f480;  1 drivers
v0x96d256260_0 .net *"_ivl_9", 15 0, L_0x96d2a9540;  1 drivers
L_0x96c8548c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d256300_0 .net/s "acc_in", 31 0, L_0x96c8548c8;  1 drivers
v0x96d2563a0_0 .net/s "acc_out", 31 0, L_0x96c47b020;  alias, 1 drivers
v0x96d256440_0 .net/s "product", 15 0, L_0x96d2a94a0;  1 drivers
v0x96d2564e0_0 .net/s "product_ext", 31 0, L_0x96c47af80;  1 drivers
v0x96d256580_0 .net/s "w", 7 0, L_0x96c55f5c0;  1 drivers
v0x96d256620_0 .net/s "x", 7 0, L_0x96c55f520;  1 drivers
L_0x96d2a9360 .extend/s 16, L_0x96c55f520;
L_0x96d2a9400 .extend/s 16, L_0x96c55f5c0;
L_0x96d2a94a0 .arith/mult 16, L_0x96d2a9360, L_0x96d2a9400;
L_0x96c55f480 .part L_0x96d2a94a0, 15, 1;
L_0x96d2a9540 .repeat 16, 16, L_0x96c55f480;
L_0x96c47af80 .concat [ 16 16 0 0], L_0x96d2a94a0, L_0x96d2a9540;
L_0x96c47b020 .arith/sum 32, L_0x96c8548c8, L_0x96c47af80;
S_0x96d258780 .scope generate, "GEN_MAC[26]" "GEN_MAC[26]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c5843c0 .param/l "i" 1 6 17, +C4<011010>;
S_0x96d258900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d258780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57cfc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d000 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d040 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2566c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2a95e0;  1 drivers
v0x96d256760_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9680;  1 drivers
v0x96d256800_0 .net *"_ivl_7", 0 0, L_0x96c55f660;  1 drivers
v0x96d2568a0_0 .net *"_ivl_9", 15 0, L_0x96d2a97c0;  1 drivers
L_0x96c854910 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d256940_0 .net/s "acc_in", 31 0, L_0x96c854910;  1 drivers
v0x96d2569e0_0 .net/s "acc_out", 31 0, L_0x96c47b160;  alias, 1 drivers
v0x96d256a80_0 .net/s "product", 15 0, L_0x96d2a9720;  1 drivers
v0x96d256b20_0 .net/s "product_ext", 31 0, L_0x96c47b0c0;  1 drivers
v0x96d256bc0_0 .net/s "w", 7 0, L_0x96c55f7a0;  1 drivers
v0x96d256c60_0 .net/s "x", 7 0, L_0x96c55f700;  1 drivers
L_0x96d2a95e0 .extend/s 16, L_0x96c55f700;
L_0x96d2a9680 .extend/s 16, L_0x96c55f7a0;
L_0x96d2a9720 .arith/mult 16, L_0x96d2a95e0, L_0x96d2a9680;
L_0x96c55f660 .part L_0x96d2a9720, 15, 1;
L_0x96d2a97c0 .repeat 16, 16, L_0x96c55f660;
L_0x96c47b0c0 .concat [ 16 16 0 0], L_0x96d2a9720, L_0x96d2a97c0;
L_0x96c47b160 .arith/sum 32, L_0x96c854910, L_0x96c47b0c0;
S_0x96d258a80 .scope generate, "GEN_MAC[27]" "GEN_MAC[27]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584400 .param/l "i" 1 6 17, +C4<011011>;
S_0x96d258c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d258a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d080 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d0c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d100 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d256d00_0 .net/s *"_ivl_0", 15 0, L_0x96d2a9860;  1 drivers
v0x96d256da0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9900;  1 drivers
v0x96d256e40_0 .net *"_ivl_7", 0 0, L_0x96c55f840;  1 drivers
v0x96d256ee0_0 .net *"_ivl_9", 15 0, L_0x96d2a9a40;  1 drivers
L_0x96c854958 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d256f80_0 .net/s "acc_in", 31 0, L_0x96c854958;  1 drivers
v0x96d257020_0 .net/s "acc_out", 31 0, L_0x96c47b2a0;  alias, 1 drivers
v0x96d2570c0_0 .net/s "product", 15 0, L_0x96d2a99a0;  1 drivers
v0x96d257160_0 .net/s "product_ext", 31 0, L_0x96c47b200;  1 drivers
v0x96d257200_0 .net/s "w", 7 0, L_0x96c55f980;  1 drivers
v0x96d2572a0_0 .net/s "x", 7 0, L_0x96c55f8e0;  1 drivers
L_0x96d2a9860 .extend/s 16, L_0x96c55f8e0;
L_0x96d2a9900 .extend/s 16, L_0x96c55f980;
L_0x96d2a99a0 .arith/mult 16, L_0x96d2a9860, L_0x96d2a9900;
L_0x96c55f840 .part L_0x96d2a99a0, 15, 1;
L_0x96d2a9a40 .repeat 16, 16, L_0x96c55f840;
L_0x96c47b200 .concat [ 16 16 0 0], L_0x96d2a99a0, L_0x96d2a9a40;
L_0x96c47b2a0 .arith/sum 32, L_0x96c854958, L_0x96c47b200;
S_0x96d258d80 .scope generate, "GEN_MAC[28]" "GEN_MAC[28]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584440 .param/l "i" 1 6 17, +C4<011100>;
S_0x96d258f00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d258d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d140 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d180 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d1c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d257340_0 .net/s *"_ivl_0", 15 0, L_0x96d2a9ae0;  1 drivers
v0x96d2573e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9b80;  1 drivers
v0x96d257480_0 .net *"_ivl_7", 0 0, L_0x96c55fa20;  1 drivers
v0x96d257520_0 .net *"_ivl_9", 15 0, L_0x96d2a9cc0;  1 drivers
L_0x96c8549a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2575c0_0 .net/s "acc_in", 31 0, L_0x96c8549a0;  1 drivers
v0x96d257660_0 .net/s "acc_out", 31 0, L_0x96c47b3e0;  alias, 1 drivers
v0x96d257700_0 .net/s "product", 15 0, L_0x96d2a9c20;  1 drivers
v0x96d2577a0_0 .net/s "product_ext", 31 0, L_0x96c47b340;  1 drivers
v0x96d257840_0 .net/s "w", 7 0, L_0x96c55fb60;  1 drivers
v0x96d2578e0_0 .net/s "x", 7 0, L_0x96c55fac0;  1 drivers
L_0x96d2a9ae0 .extend/s 16, L_0x96c55fac0;
L_0x96d2a9b80 .extend/s 16, L_0x96c55fb60;
L_0x96d2a9c20 .arith/mult 16, L_0x96d2a9ae0, L_0x96d2a9b80;
L_0x96c55fa20 .part L_0x96d2a9c20, 15, 1;
L_0x96d2a9cc0 .repeat 16, 16, L_0x96c55fa20;
L_0x96c47b340 .concat [ 16 16 0 0], L_0x96d2a9c20, L_0x96d2a9cc0;
L_0x96c47b3e0 .arith/sum 32, L_0x96c8549a0, L_0x96c47b340;
S_0x96d259080 .scope generate, "GEN_MAC[29]" "GEN_MAC[29]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584480 .param/l "i" 1 6 17, +C4<011101>;
S_0x96d259200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d259080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d200 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d240 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d280 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d257980_0 .net/s *"_ivl_0", 15 0, L_0x96d2a9d60;  1 drivers
v0x96d257a20_0 .net/s *"_ivl_2", 15 0, L_0x96d2a9e00;  1 drivers
v0x96d257ac0_0 .net *"_ivl_7", 0 0, L_0x96c55fc00;  1 drivers
v0x96d257b60_0 .net *"_ivl_9", 15 0, L_0x96d2a9f40;  1 drivers
L_0x96c8549e8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d257c00_0 .net/s "acc_in", 31 0, L_0x96c8549e8;  1 drivers
v0x96d257ca0_0 .net/s "acc_out", 31 0, L_0x96c47b520;  alias, 1 drivers
v0x96d257d40_0 .net/s "product", 15 0, L_0x96d2a9ea0;  1 drivers
v0x96d257de0_0 .net/s "product_ext", 31 0, L_0x96c47b480;  1 drivers
v0x96d257e80_0 .net/s "w", 7 0, L_0x96c55fd40;  1 drivers
v0x96d257f20_0 .net/s "x", 7 0, L_0x96c55fca0;  1 drivers
L_0x96d2a9d60 .extend/s 16, L_0x96c55fca0;
L_0x96d2a9e00 .extend/s 16, L_0x96c55fd40;
L_0x96d2a9ea0 .arith/mult 16, L_0x96d2a9d60, L_0x96d2a9e00;
L_0x96c55fc00 .part L_0x96d2a9ea0, 15, 1;
L_0x96d2a9f40 .repeat 16, 16, L_0x96c55fc00;
L_0x96c47b480 .concat [ 16 16 0 0], L_0x96d2a9ea0, L_0x96d2a9f40;
L_0x96c47b520 .arith/sum 32, L_0x96c8549e8, L_0x96c47b480;
S_0x96d259380 .scope generate, "GEN_MAC[30]" "GEN_MAC[30]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c5844c0 .param/l "i" 1 6 17, +C4<011110>;
S_0x96d259500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d259380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d2c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d300 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d340 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25c000_0 .net/s *"_ivl_0", 15 0, L_0x96d2a9fe0;  1 drivers
v0x96d25c0a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aa080;  1 drivers
v0x96d25c140_0 .net *"_ivl_7", 0 0, L_0x96c55fde0;  1 drivers
v0x96d25c1e0_0 .net *"_ivl_9", 15 0, L_0x96d2aa1c0;  1 drivers
L_0x96c854a30 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25c280_0 .net/s "acc_in", 31 0, L_0x96c854a30;  1 drivers
v0x96d25c320_0 .net/s "acc_out", 31 0, L_0x96c47b660;  alias, 1 drivers
v0x96d25c3c0_0 .net/s "product", 15 0, L_0x96d2aa120;  1 drivers
v0x96d25c460_0 .net/s "product_ext", 31 0, L_0x96c47b5c0;  1 drivers
v0x96d25c500_0 .net/s "w", 7 0, L_0x96c55ff20;  1 drivers
v0x96d25c5a0_0 .net/s "x", 7 0, L_0x96c55fe80;  1 drivers
L_0x96d2a9fe0 .extend/s 16, L_0x96c55fe80;
L_0x96d2aa080 .extend/s 16, L_0x96c55ff20;
L_0x96d2aa120 .arith/mult 16, L_0x96d2a9fe0, L_0x96d2aa080;
L_0x96c55fde0 .part L_0x96d2aa120, 15, 1;
L_0x96d2aa1c0 .repeat 16, 16, L_0x96c55fde0;
L_0x96c47b5c0 .concat [ 16 16 0 0], L_0x96d2aa120, L_0x96d2aa1c0;
L_0x96c47b660 .arith/sum 32, L_0x96c854a30, L_0x96c47b5c0;
S_0x96d259680 .scope generate, "GEN_MAC[31]" "GEN_MAC[31]" 6 17, 6 17 0, S_0x100fc6560;
 .timescale 0 0;
P_0x96c584500 .param/l "i" 1 6 17, +C4<011111>;
S_0x96d259800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d259680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d380 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d3c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d400 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25c640_0 .net/s *"_ivl_0", 15 0, L_0x96d2aa260;  1 drivers
v0x96d25c6e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aa300;  1 drivers
v0x96d25c780_0 .net *"_ivl_7", 0 0, L_0x96c4940a0;  1 drivers
v0x96d25c820_0 .net *"_ivl_9", 15 0, L_0x96d2aa440;  1 drivers
L_0x96c854a78 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25c8c0_0 .net/s "acc_in", 31 0, L_0x96c854a78;  1 drivers
v0x96d25c960_0 .net/s "acc_out", 31 0, L_0x96c47b7a0;  alias, 1 drivers
v0x96d25ca00_0 .net/s "product", 15 0, L_0x96d2aa3a0;  1 drivers
v0x96d25caa0_0 .net/s "product_ext", 31 0, L_0x96c47b700;  1 drivers
v0x96d25cb40_0 .net/s "w", 7 0, L_0x96c5000a0;  1 drivers
v0x96d25cbe0_0 .net/s "x", 7 0, L_0x96c528140;  1 drivers
L_0x96d2aa260 .extend/s 16, L_0x96c528140;
L_0x96d2aa300 .extend/s 16, L_0x96c5000a0;
L_0x96d2aa3a0 .arith/mult 16, L_0x96d2aa260, L_0x96d2aa300;
L_0x96c4940a0 .part L_0x96d2aa3a0, 15, 1;
L_0x96d2aa440 .repeat 16, 16, L_0x96c4940a0;
L_0x96c47b700 .concat [ 16 16 0 0], L_0x96d2aa3a0, L_0x96d2aa440;
L_0x96c47b7a0 .arith/sum 32, L_0x96c854a78, L_0x96c47b700;
S_0x96d259980 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 4 34, 4 34 0, S_0x100fcf810;
 .timescale 0 0;
P_0x96c584540 .param/l "n" 1 4 34, +C4<01>;
S_0x96d259b00 .scope module, "u_neuron" "neuron_parallel" 4 41, 5 1 0, S_0x96d259980;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "start";
    .port_info 3 /INPUT 2048 "x_bus";
    .port_info 4 /INPUT 2048 "w_bus";
    .port_info 5 /INPUT 8 "bias";
    .port_info 6 /OUTPUT 8 "y";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "done";
P_0x96d259c80 .param/l "ACC_WIDTH" 0 5 5, +C4<00000000000000000000000000100000>;
P_0x96d259cc0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
P_0x96d259d00 .param/l "GROUPS" 1 5 20, +C4<00000000000000000000000000001000>;
P_0x96d259d40 .param/l "GROUP_INDEX_WIDTH" 1 5 21, +C4<00000000000000000000000000000011>;
P_0x96d259d80 .param/l "N_INPUTS" 0 5 3, +C4<00000000000000000000000100000000>;
P_0x96d259dc0 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000100000>;
v0x96d26f0c0_0 .net *"_ivl_0", 31 0, L_0x96c47ba20;  1 drivers
v0x96d26f160_0 .net *"_ivl_11", 31 0, L_0x96d2aa620;  1 drivers
v0x96d26f200_0 .net *"_ivl_14", 31 0, L_0x96c47bac0;  1 drivers
L_0x96c854b98 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26f2a0_0 .net *"_ivl_17", 28 0, L_0x96c854b98;  1 drivers
L_0x96c854be0 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d26f340_0 .net/2u *"_ivl_18", 31 0, L_0x96c854be0;  1 drivers
v0x96d26f3e0_0 .net *"_ivl_21", 31 0, L_0x96d2aa6c0;  1 drivers
L_0x96c854c28 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d26f480_0 .net/2u *"_ivl_22", 31 0, L_0x96c854c28;  1 drivers
v0x96d26f520_0 .net *"_ivl_25", 31 0, L_0x96d2aa760;  1 drivers
v0x96d26f5c0_0 .net *"_ivl_29", 0 0, L_0x96c5b3f20;  1 drivers
L_0x96c854ac0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26f660_0 .net *"_ivl_3", 28 0, L_0x96c854ac0;  1 drivers
v0x96d26f700_0 .net *"_ivl_31", 23 0, L_0x96d2af8e0;  1 drivers
L_0x96c854b08 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d26f7a0_0 .net/2u *"_ivl_4", 31 0, L_0x96c854b08;  1 drivers
v0x96d26f840_0 .net *"_ivl_7", 31 0, L_0x96d2aa580;  1 drivers
L_0x96c854b50 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d26f8e0_0 .net/2u *"_ivl_8", 31 0, L_0x96c854b50;  1 drivers
v0x96d26f980_0 .var/s "acc", 31 0;
v0x96d26fa20_0 .net/s "acc_next", 31 0, L_0x96c5b63a0;  1 drivers
v0x96d26fac0_0 .net/s "bias", 7 0, L_0x96c5bc0a0;  1 drivers
v0x96d26fb60_0 .net/s "bias_ext", 31 0, L_0x96c5b6440;  1 drivers
v0x96d26fc00_0 .var "busy", 0 0;
v0x96d26fca0_0 .net "clk", 0 0, v0x96d2a4be0_0;  alias, 1 drivers
v0x96d26fd40_0 .var "done", 0 0;
v0x96d26fde0_0 .net/s "final_acc", 31 0, L_0x96c5b64e0;  1 drivers
v0x96d26fe80_0 .var "group_index", 2 0;
v0x96d26ff20_0 .net "rst", 0 0, v0x96d2a4f00_0;  alias, 1 drivers
v0x96d274000_0 .net "start", 0 0, v0x96d2a4fa0_0;  alias, 1 drivers
v0x96d2740a0_0 .net/s "w_bus", 2047 0, L_0x96c5bc000;  1 drivers
v0x96d274140_0 .net/s "w_group", 255 0, L_0x96c5b0280;  1 drivers
v0x96d2741e0_0 .net/s "x_bus", 2047 0, v0x96d2a50e0_0;  alias, 1 drivers
v0x96d274280_0 .net/s "x_group", 255 0, L_0x96c5b01e0;  1 drivers
v0x96d274320_0 .var/s "y", 7 0;
L_0x96c47ba20 .concat [ 3 29 0 0], v0x96d26fe80_0, L_0x96c854ac0;
L_0x96d2aa580 .arith/mult 32, L_0x96c47ba20, L_0x96c854b08;
L_0x96d2aa620 .arith/mult 32, L_0x96d2aa580, L_0x96c854b50;
L_0x96c5b01e0 .part/v v0x96d2a50e0_0, L_0x96d2aa620, 256;
L_0x96c47bac0 .concat [ 3 29 0 0], v0x96d26fe80_0, L_0x96c854b98;
L_0x96d2aa6c0 .arith/mult 32, L_0x96c47bac0, L_0x96c854be0;
L_0x96d2aa760 .arith/mult 32, L_0x96d2aa6c0, L_0x96c854c28;
L_0x96c5b0280 .part/v L_0x96c5bc000, L_0x96d2aa760, 256;
L_0x96c5b3f20 .part L_0x96c5bc0a0, 7, 1;
L_0x96d2af8e0 .repeat 24, 24, L_0x96c5b3f20;
L_0x96c5b6440 .concat [ 8 24 0 0], L_0x96c5bc0a0, L_0x96d2af8e0;
L_0x96c5b64e0 .arith/sum 32, L_0x96c5b63a0, L_0x96c5b6440;
S_0x96d259e00 .scope module, "u_mac8" "mac8" 5 52, 6 1 0, S_0x96d259b00;
 .timescale 0 0;
    .port_info 0 /INPUT 256 "x_bus";
    .port_info 1 /INPUT 256 "w_bus";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d440 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
P_0x96c57d480 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
P_0x96c57d4c0 .param/l "PARALLEL" 0 6 4, +C4<00000000000000000000000000100000>;
v0x96d26ec60_0 .net/s "acc_in", 31 0, v0x96d26f980_0;  1 drivers
v0x96d26ed00_0 .net/s "acc_out", 31 0, L_0x96c5b63a0;  alias, 1 drivers
v0x96d26eda0_0 .var/i "j", 31 0;
v0x96d26ee40 .array "products", 31 0;
v0x96d26ee40_0 .net/s v0x96d26ee40 0, 31 0, L_0x96c47bc00; 1 drivers
v0x96d26ee40_1 .net/s v0x96d26ee40 1, 31 0, L_0x96c47bd40; 1 drivers
v0x96d26ee40_2 .net/s v0x96d26ee40 2, 31 0, L_0x96c47be80; 1 drivers
v0x96d26ee40_3 .net/s v0x96d26ee40 3, 31 0, L_0x96c5b4000; 1 drivers
v0x96d26ee40_4 .net/s v0x96d26ee40 4, 31 0, L_0x96c5b4140; 1 drivers
v0x96d26ee40_5 .net/s v0x96d26ee40 5, 31 0, L_0x96c5b4280; 1 drivers
v0x96d26ee40_6 .net/s v0x96d26ee40 6, 31 0, L_0x96c5b43c0; 1 drivers
v0x96d26ee40_7 .net/s v0x96d26ee40 7, 31 0, L_0x96c5b4500; 1 drivers
v0x96d26ee40_8 .net/s v0x96d26ee40 8, 31 0, L_0x96c5b4640; 1 drivers
v0x96d26ee40_9 .net/s v0x96d26ee40 9, 31 0, L_0x96c5b4780; 1 drivers
v0x96d26ee40_10 .net/s v0x96d26ee40 10, 31 0, L_0x96c5b48c0; 1 drivers
v0x96d26ee40_11 .net/s v0x96d26ee40 11, 31 0, L_0x96c5b4a00; 1 drivers
v0x96d26ee40_12 .net/s v0x96d26ee40 12, 31 0, L_0x96c5b4b40; 1 drivers
v0x96d26ee40_13 .net/s v0x96d26ee40 13, 31 0, L_0x96c5b4c80; 1 drivers
v0x96d26ee40_14 .net/s v0x96d26ee40 14, 31 0, L_0x96c5b4dc0; 1 drivers
v0x96d26ee40_15 .net/s v0x96d26ee40 15, 31 0, L_0x96c5b4f00; 1 drivers
v0x96d26ee40_16 .net/s v0x96d26ee40 16, 31 0, L_0x96c5b5040; 1 drivers
v0x96d26ee40_17 .net/s v0x96d26ee40 17, 31 0, L_0x96c5b5180; 1 drivers
v0x96d26ee40_18 .net/s v0x96d26ee40 18, 31 0, L_0x96c5b52c0; 1 drivers
v0x96d26ee40_19 .net/s v0x96d26ee40 19, 31 0, L_0x96c5b5400; 1 drivers
v0x96d26ee40_20 .net/s v0x96d26ee40 20, 31 0, L_0x96c5b5540; 1 drivers
v0x96d26ee40_21 .net/s v0x96d26ee40 21, 31 0, L_0x96c5b5680; 1 drivers
v0x96d26ee40_22 .net/s v0x96d26ee40 22, 31 0, L_0x96c5b57c0; 1 drivers
v0x96d26ee40_23 .net/s v0x96d26ee40 23, 31 0, L_0x96c5b5900; 1 drivers
v0x96d26ee40_24 .net/s v0x96d26ee40 24, 31 0, L_0x96c5b5a40; 1 drivers
v0x96d26ee40_25 .net/s v0x96d26ee40 25, 31 0, L_0x96c5b5b80; 1 drivers
v0x96d26ee40_26 .net/s v0x96d26ee40 26, 31 0, L_0x96c5b5cc0; 1 drivers
v0x96d26ee40_27 .net/s v0x96d26ee40 27, 31 0, L_0x96c5b5e00; 1 drivers
v0x96d26ee40_28 .net/s v0x96d26ee40 28, 31 0, L_0x96c5b5f40; 1 drivers
v0x96d26ee40_29 .net/s v0x96d26ee40 29, 31 0, L_0x96c5b6080; 1 drivers
v0x96d26ee40_30 .net/s v0x96d26ee40 30, 31 0, L_0x96c5b61c0; 1 drivers
v0x96d26ee40_31 .net/s v0x96d26ee40 31, 31 0, L_0x96c5b6300; 1 drivers
v0x96d26eee0_0 .var/s "sum", 31 0;
v0x96d26ef80_0 .net/s "w_bus", 255 0, L_0x96c5b0280;  alias, 1 drivers
v0x96d26f020_0 .net/s "x_bus", 255 0, L_0x96c5b01e0;  alias, 1 drivers
E_0x96d18bcc0/0 .event anyedge, v0x96d26eee0_0, v0x96d25e6c0_0, v0x96d25ed00_0, v0x96d25f340_0;
E_0x96d18bcc0/1 .event anyedge, v0x96d25f980_0, v0x96d260000_0, v0x96d260640_0, v0x96d260c80_0;
E_0x96d18bcc0/2 .event anyedge, v0x96d2612c0_0, v0x96d261900_0, v0x96d261f40_0, v0x96d262580_0;
E_0x96d18bcc0/3 .event anyedge, v0x96d262bc0_0, v0x96d263200_0, v0x96d263840_0, v0x96d263e80_0;
E_0x96d18bcc0/4 .event anyedge, v0x96d268500_0, v0x96d268b40_0, v0x96d269180_0, v0x96d2697c0_0;
E_0x96d18bcc0/5 .event anyedge, v0x96d269e00_0, v0x96d26a440_0, v0x96d26aa80_0, v0x96d26b0c0_0;
E_0x96d18bcc0/6 .event anyedge, v0x96d26b700_0, v0x96d26bd40_0, v0x96d26c3c0_0, v0x96d26ca00_0;
E_0x96d18bcc0/7 .event anyedge, v0x96d26d040_0, v0x96d26d680_0, v0x96d26dcc0_0, v0x96d26e300_0;
E_0x96d18bcc0/8 .event anyedge, v0x96d26e940_0;
E_0x96d18bcc0 .event/or E_0x96d18bcc0/0, E_0x96d18bcc0/1, E_0x96d18bcc0/2, E_0x96d18bcc0/3, E_0x96d18bcc0/4, E_0x96d18bcc0/5, E_0x96d18bcc0/6, E_0x96d18bcc0/7, E_0x96d18bcc0/8;
L_0x96c5b03c0 .part L_0x96c5b01e0, 0, 8;
L_0x96c5b0460 .part L_0x96c5b0280, 0, 8;
L_0x96c5b05a0 .part L_0x96c5b01e0, 8, 8;
L_0x96c5b0640 .part L_0x96c5b0280, 8, 8;
L_0x96c5b0780 .part L_0x96c5b01e0, 16, 8;
L_0x96c5b0820 .part L_0x96c5b0280, 16, 8;
L_0x96c5b0960 .part L_0x96c5b01e0, 24, 8;
L_0x96c5b0a00 .part L_0x96c5b0280, 24, 8;
L_0x96c5b0b40 .part L_0x96c5b01e0, 32, 8;
L_0x96c5b0be0 .part L_0x96c5b0280, 32, 8;
L_0x96c5b0d20 .part L_0x96c5b01e0, 40, 8;
L_0x96c5b0dc0 .part L_0x96c5b0280, 40, 8;
L_0x96c5b0f00 .part L_0x96c5b01e0, 48, 8;
L_0x96c5b0fa0 .part L_0x96c5b0280, 48, 8;
L_0x96c5b10e0 .part L_0x96c5b01e0, 56, 8;
L_0x96c5b1180 .part L_0x96c5b0280, 56, 8;
L_0x96c5b12c0 .part L_0x96c5b01e0, 64, 8;
L_0x96c5b1360 .part L_0x96c5b0280, 64, 8;
L_0x96c5b14a0 .part L_0x96c5b01e0, 72, 8;
L_0x96c5b1540 .part L_0x96c5b0280, 72, 8;
L_0x96c5b1680 .part L_0x96c5b01e0, 80, 8;
L_0x96c5b1720 .part L_0x96c5b0280, 80, 8;
L_0x96c5b1860 .part L_0x96c5b01e0, 88, 8;
L_0x96c5b1900 .part L_0x96c5b0280, 88, 8;
L_0x96c5b1a40 .part L_0x96c5b01e0, 96, 8;
L_0x96c5b1ae0 .part L_0x96c5b0280, 96, 8;
L_0x96c5b1c20 .part L_0x96c5b01e0, 104, 8;
L_0x96c5b1cc0 .part L_0x96c5b0280, 104, 8;
L_0x96c5b1e00 .part L_0x96c5b01e0, 112, 8;
L_0x96c5b1ea0 .part L_0x96c5b0280, 112, 8;
L_0x96c5b1fe0 .part L_0x96c5b01e0, 120, 8;
L_0x96c5b2080 .part L_0x96c5b0280, 120, 8;
L_0x96c5b21c0 .part L_0x96c5b01e0, 128, 8;
L_0x96c5b2260 .part L_0x96c5b0280, 128, 8;
L_0x96c5b23a0 .part L_0x96c5b01e0, 136, 8;
L_0x96c5b2440 .part L_0x96c5b0280, 136, 8;
L_0x96c5b2580 .part L_0x96c5b01e0, 144, 8;
L_0x96c5b2620 .part L_0x96c5b0280, 144, 8;
L_0x96c5b2760 .part L_0x96c5b01e0, 152, 8;
L_0x96c5b2800 .part L_0x96c5b0280, 152, 8;
L_0x96c5b2940 .part L_0x96c5b01e0, 160, 8;
L_0x96c5b29e0 .part L_0x96c5b0280, 160, 8;
L_0x96c5b2b20 .part L_0x96c5b01e0, 168, 8;
L_0x96c5b2bc0 .part L_0x96c5b0280, 168, 8;
L_0x96c5b2d00 .part L_0x96c5b01e0, 176, 8;
L_0x96c5b2da0 .part L_0x96c5b0280, 176, 8;
L_0x96c5b2ee0 .part L_0x96c5b01e0, 184, 8;
L_0x96c5b2f80 .part L_0x96c5b0280, 184, 8;
L_0x96c5b30c0 .part L_0x96c5b01e0, 192, 8;
L_0x96c5b3160 .part L_0x96c5b0280, 192, 8;
L_0x96c5b32a0 .part L_0x96c5b01e0, 200, 8;
L_0x96c5b3340 .part L_0x96c5b0280, 200, 8;
L_0x96c5b3480 .part L_0x96c5b01e0, 208, 8;
L_0x96c5b3520 .part L_0x96c5b0280, 208, 8;
L_0x96c5b3660 .part L_0x96c5b01e0, 216, 8;
L_0x96c5b3700 .part L_0x96c5b0280, 216, 8;
L_0x96c5b3840 .part L_0x96c5b01e0, 224, 8;
L_0x96c5b38e0 .part L_0x96c5b0280, 224, 8;
L_0x96c5b3a20 .part L_0x96c5b01e0, 232, 8;
L_0x96c5b3ac0 .part L_0x96c5b0280, 232, 8;
L_0x96c5b3c00 .part L_0x96c5b01e0, 240, 8;
L_0x96c5b3ca0 .part L_0x96c5b0280, 240, 8;
L_0x96c5b3de0 .part L_0x96c5b01e0, 248, 8;
L_0x96c5b3e80 .part L_0x96c5b0280, 248, 8;
L_0x96c5b63a0 .arith/sum 32, v0x96d26f980_0, v0x96d26eee0_0;
S_0x96d259f80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584580 .param/l "i" 1 6 17, +C4<00>;
S_0x96d25a100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d259f80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d500 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d540 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d580 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25e3a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2aa800;  1 drivers
v0x96d25e440_0 .net/s *"_ivl_2", 15 0, L_0x96d2aa8a0;  1 drivers
v0x96d25e4e0_0 .net *"_ivl_7", 0 0, L_0x96c5b0320;  1 drivers
v0x96d25e580_0 .net *"_ivl_9", 15 0, L_0x96d2aa9e0;  1 drivers
L_0x96c854c70 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25e620_0 .net/s "acc_in", 31 0, L_0x96c854c70;  1 drivers
v0x96d25e6c0_0 .net/s "acc_out", 31 0, L_0x96c47bc00;  alias, 1 drivers
v0x96d25e760_0 .net/s "product", 15 0, L_0x96d2aa940;  1 drivers
v0x96d25e800_0 .net/s "product_ext", 31 0, L_0x96c47bb60;  1 drivers
v0x96d25e8a0_0 .net/s "w", 7 0, L_0x96c5b0460;  1 drivers
v0x96d25e940_0 .net/s "x", 7 0, L_0x96c5b03c0;  1 drivers
L_0x96d2aa800 .extend/s 16, L_0x96c5b03c0;
L_0x96d2aa8a0 .extend/s 16, L_0x96c5b0460;
L_0x96d2aa940 .arith/mult 16, L_0x96d2aa800, L_0x96d2aa8a0;
L_0x96c5b0320 .part L_0x96d2aa940, 15, 1;
L_0x96d2aa9e0 .repeat 16, 16, L_0x96c5b0320;
L_0x96c47bb60 .concat [ 16 16 0 0], L_0x96d2aa940, L_0x96d2aa9e0;
L_0x96c47bc00 .arith/sum 32, L_0x96c854c70, L_0x96c47bb60;
S_0x96d25a280 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c5845c0 .param/l "i" 1 6 17, +C4<01>;
S_0x96d25a400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25a280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d5c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d600 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d640 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25e9e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2aaa80;  1 drivers
v0x96d25ea80_0 .net/s *"_ivl_2", 15 0, L_0x96d2aab20;  1 drivers
v0x96d25eb20_0 .net *"_ivl_7", 0 0, L_0x96c5b0500;  1 drivers
v0x96d25ebc0_0 .net *"_ivl_9", 15 0, L_0x96d2aac60;  1 drivers
L_0x96c854cb8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25ec60_0 .net/s "acc_in", 31 0, L_0x96c854cb8;  1 drivers
v0x96d25ed00_0 .net/s "acc_out", 31 0, L_0x96c47bd40;  alias, 1 drivers
v0x96d25eda0_0 .net/s "product", 15 0, L_0x96d2aabc0;  1 drivers
v0x96d25ee40_0 .net/s "product_ext", 31 0, L_0x96c47bca0;  1 drivers
v0x96d25eee0_0 .net/s "w", 7 0, L_0x96c5b0640;  1 drivers
v0x96d25ef80_0 .net/s "x", 7 0, L_0x96c5b05a0;  1 drivers
L_0x96d2aaa80 .extend/s 16, L_0x96c5b05a0;
L_0x96d2aab20 .extend/s 16, L_0x96c5b0640;
L_0x96d2aabc0 .arith/mult 16, L_0x96d2aaa80, L_0x96d2aab20;
L_0x96c5b0500 .part L_0x96d2aabc0, 15, 1;
L_0x96d2aac60 .repeat 16, 16, L_0x96c5b0500;
L_0x96c47bca0 .concat [ 16 16 0 0], L_0x96d2aabc0, L_0x96d2aac60;
L_0x96c47bd40 .arith/sum 32, L_0x96c854cb8, L_0x96c47bca0;
S_0x96d25a580 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584600 .param/l "i" 1 6 17, +C4<010>;
S_0x96d25a700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25a580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d680 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d6c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d700 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25f020_0 .net/s *"_ivl_0", 15 0, L_0x96d2aad00;  1 drivers
v0x96d25f0c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aada0;  1 drivers
v0x96d25f160_0 .net *"_ivl_7", 0 0, L_0x96c5b06e0;  1 drivers
v0x96d25f200_0 .net *"_ivl_9", 15 0, L_0x96d2aaee0;  1 drivers
L_0x96c854d00 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25f2a0_0 .net/s "acc_in", 31 0, L_0x96c854d00;  1 drivers
v0x96d25f340_0 .net/s "acc_out", 31 0, L_0x96c47be80;  alias, 1 drivers
v0x96d25f3e0_0 .net/s "product", 15 0, L_0x96d2aae40;  1 drivers
v0x96d25f480_0 .net/s "product_ext", 31 0, L_0x96c47bde0;  1 drivers
v0x96d25f520_0 .net/s "w", 7 0, L_0x96c5b0820;  1 drivers
v0x96d25f5c0_0 .net/s "x", 7 0, L_0x96c5b0780;  1 drivers
L_0x96d2aad00 .extend/s 16, L_0x96c5b0780;
L_0x96d2aada0 .extend/s 16, L_0x96c5b0820;
L_0x96d2aae40 .arith/mult 16, L_0x96d2aad00, L_0x96d2aada0;
L_0x96c5b06e0 .part L_0x96d2aae40, 15, 1;
L_0x96d2aaee0 .repeat 16, 16, L_0x96c5b06e0;
L_0x96c47bde0 .concat [ 16 16 0 0], L_0x96d2aae40, L_0x96d2aaee0;
L_0x96c47be80 .arith/sum 32, L_0x96c854d00, L_0x96c47bde0;
S_0x96d25a880 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584640 .param/l "i" 1 6 17, +C4<011>;
S_0x96d25aa00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25a880;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d740 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d780 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d7c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25f660_0 .net/s *"_ivl_0", 15 0, L_0x96d2aaf80;  1 drivers
v0x96d25f700_0 .net/s *"_ivl_2", 15 0, L_0x96d2ab020;  1 drivers
v0x96d25f7a0_0 .net *"_ivl_7", 0 0, L_0x96c5b08c0;  1 drivers
v0x96d25f840_0 .net *"_ivl_9", 15 0, L_0x96d2ab160;  1 drivers
L_0x96c854d48 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25f8e0_0 .net/s "acc_in", 31 0, L_0x96c854d48;  1 drivers
v0x96d25f980_0 .net/s "acc_out", 31 0, L_0x96c5b4000;  alias, 1 drivers
v0x96d25fa20_0 .net/s "product", 15 0, L_0x96d2ab0c0;  1 drivers
v0x96d25fac0_0 .net/s "product_ext", 31 0, L_0x96c47bf20;  1 drivers
v0x96d25fb60_0 .net/s "w", 7 0, L_0x96c5b0a00;  1 drivers
v0x96d25fc00_0 .net/s "x", 7 0, L_0x96c5b0960;  1 drivers
L_0x96d2aaf80 .extend/s 16, L_0x96c5b0960;
L_0x96d2ab020 .extend/s 16, L_0x96c5b0a00;
L_0x96d2ab0c0 .arith/mult 16, L_0x96d2aaf80, L_0x96d2ab020;
L_0x96c5b08c0 .part L_0x96d2ab0c0, 15, 1;
L_0x96d2ab160 .repeat 16, 16, L_0x96c5b08c0;
L_0x96c47bf20 .concat [ 16 16 0 0], L_0x96d2ab0c0, L_0x96d2ab160;
L_0x96c5b4000 .arith/sum 32, L_0x96c854d48, L_0x96c47bf20;
S_0x96d25ab80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584680 .param/l "i" 1 6 17, +C4<0100>;
S_0x96d25ad00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25ab80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d800 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d840 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d880 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d25fca0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ab200;  1 drivers
v0x96d25fd40_0 .net/s *"_ivl_2", 15 0, L_0x96d2ab2a0;  1 drivers
v0x96d25fde0_0 .net *"_ivl_7", 0 0, L_0x96c5b0aa0;  1 drivers
v0x96d25fe80_0 .net *"_ivl_9", 15 0, L_0x96d2ab3e0;  1 drivers
L_0x96c854d90 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d25ff20_0 .net/s "acc_in", 31 0, L_0x96c854d90;  1 drivers
v0x96d260000_0 .net/s "acc_out", 31 0, L_0x96c5b4140;  alias, 1 drivers
v0x96d2600a0_0 .net/s "product", 15 0, L_0x96d2ab340;  1 drivers
v0x96d260140_0 .net/s "product_ext", 31 0, L_0x96c5b40a0;  1 drivers
v0x96d2601e0_0 .net/s "w", 7 0, L_0x96c5b0be0;  1 drivers
v0x96d260280_0 .net/s "x", 7 0, L_0x96c5b0b40;  1 drivers
L_0x96d2ab200 .extend/s 16, L_0x96c5b0b40;
L_0x96d2ab2a0 .extend/s 16, L_0x96c5b0be0;
L_0x96d2ab340 .arith/mult 16, L_0x96d2ab200, L_0x96d2ab2a0;
L_0x96c5b0aa0 .part L_0x96d2ab340, 15, 1;
L_0x96d2ab3e0 .repeat 16, 16, L_0x96c5b0aa0;
L_0x96c5b40a0 .concat [ 16 16 0 0], L_0x96d2ab340, L_0x96d2ab3e0;
L_0x96c5b4140 .arith/sum 32, L_0x96c854d90, L_0x96c5b40a0;
S_0x96d25ae80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c5846c0 .param/l "i" 1 6 17, +C4<0101>;
S_0x96d25b000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25ae80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d8c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d900 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57d940 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d260320_0 .net/s *"_ivl_0", 15 0, L_0x96d2ab480;  1 drivers
v0x96d2603c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2ab520;  1 drivers
v0x96d260460_0 .net *"_ivl_7", 0 0, L_0x96c5b0c80;  1 drivers
v0x96d260500_0 .net *"_ivl_9", 15 0, L_0x96d2ab660;  1 drivers
L_0x96c854dd8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2605a0_0 .net/s "acc_in", 31 0, L_0x96c854dd8;  1 drivers
v0x96d260640_0 .net/s "acc_out", 31 0, L_0x96c5b4280;  alias, 1 drivers
v0x96d2606e0_0 .net/s "product", 15 0, L_0x96d2ab5c0;  1 drivers
v0x96d260780_0 .net/s "product_ext", 31 0, L_0x96c5b41e0;  1 drivers
v0x96d260820_0 .net/s "w", 7 0, L_0x96c5b0dc0;  1 drivers
v0x96d2608c0_0 .net/s "x", 7 0, L_0x96c5b0d20;  1 drivers
L_0x96d2ab480 .extend/s 16, L_0x96c5b0d20;
L_0x96d2ab520 .extend/s 16, L_0x96c5b0dc0;
L_0x96d2ab5c0 .arith/mult 16, L_0x96d2ab480, L_0x96d2ab520;
L_0x96c5b0c80 .part L_0x96d2ab5c0, 15, 1;
L_0x96d2ab660 .repeat 16, 16, L_0x96c5b0c80;
L_0x96c5b41e0 .concat [ 16 16 0 0], L_0x96d2ab5c0, L_0x96d2ab660;
L_0x96c5b4280 .arith/sum 32, L_0x96c854dd8, L_0x96c5b41e0;
S_0x96d25b180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584700 .param/l "i" 1 6 17, +C4<0110>;
S_0x96d25b300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25b180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57d980 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57d9c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57da00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d260960_0 .net/s *"_ivl_0", 15 0, L_0x96d2ab700;  1 drivers
v0x96d260a00_0 .net/s *"_ivl_2", 15 0, L_0x96d2ab7a0;  1 drivers
v0x96d260aa0_0 .net *"_ivl_7", 0 0, L_0x96c5b0e60;  1 drivers
v0x96d260b40_0 .net *"_ivl_9", 15 0, L_0x96d2ab8e0;  1 drivers
L_0x96c854e20 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d260be0_0 .net/s "acc_in", 31 0, L_0x96c854e20;  1 drivers
v0x96d260c80_0 .net/s "acc_out", 31 0, L_0x96c5b43c0;  alias, 1 drivers
v0x96d260d20_0 .net/s "product", 15 0, L_0x96d2ab840;  1 drivers
v0x96d260dc0_0 .net/s "product_ext", 31 0, L_0x96c5b4320;  1 drivers
v0x96d260e60_0 .net/s "w", 7 0, L_0x96c5b0fa0;  1 drivers
v0x96d260f00_0 .net/s "x", 7 0, L_0x96c5b0f00;  1 drivers
L_0x96d2ab700 .extend/s 16, L_0x96c5b0f00;
L_0x96d2ab7a0 .extend/s 16, L_0x96c5b0fa0;
L_0x96d2ab840 .arith/mult 16, L_0x96d2ab700, L_0x96d2ab7a0;
L_0x96c5b0e60 .part L_0x96d2ab840, 15, 1;
L_0x96d2ab8e0 .repeat 16, 16, L_0x96c5b0e60;
L_0x96c5b4320 .concat [ 16 16 0 0], L_0x96d2ab840, L_0x96d2ab8e0;
L_0x96c5b43c0 .arith/sum 32, L_0x96c854e20, L_0x96c5b4320;
S_0x96d25b480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584740 .param/l "i" 1 6 17, +C4<0111>;
S_0x96d25b600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25b480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57da40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57da80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57dac0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d260fa0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ab980;  1 drivers
v0x96d261040_0 .net/s *"_ivl_2", 15 0, L_0x96d2aba20;  1 drivers
v0x96d2610e0_0 .net *"_ivl_7", 0 0, L_0x96c5b1040;  1 drivers
v0x96d261180_0 .net *"_ivl_9", 15 0, L_0x96d2abb60;  1 drivers
L_0x96c854e68 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d261220_0 .net/s "acc_in", 31 0, L_0x96c854e68;  1 drivers
v0x96d2612c0_0 .net/s "acc_out", 31 0, L_0x96c5b4500;  alias, 1 drivers
v0x96d261360_0 .net/s "product", 15 0, L_0x96d2abac0;  1 drivers
v0x96d261400_0 .net/s "product_ext", 31 0, L_0x96c5b4460;  1 drivers
v0x96d2614a0_0 .net/s "w", 7 0, L_0x96c5b1180;  1 drivers
v0x96d261540_0 .net/s "x", 7 0, L_0x96c5b10e0;  1 drivers
L_0x96d2ab980 .extend/s 16, L_0x96c5b10e0;
L_0x96d2aba20 .extend/s 16, L_0x96c5b1180;
L_0x96d2abac0 .arith/mult 16, L_0x96d2ab980, L_0x96d2aba20;
L_0x96c5b1040 .part L_0x96d2abac0, 15, 1;
L_0x96d2abb60 .repeat 16, 16, L_0x96c5b1040;
L_0x96c5b4460 .concat [ 16 16 0 0], L_0x96d2abac0, L_0x96d2abb60;
L_0x96c5b4500 .arith/sum 32, L_0x96c854e68, L_0x96c5b4460;
S_0x96d25b780 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584780 .param/l "i" 1 6 17, +C4<01000>;
S_0x96d25b900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25b780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57db00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57db40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57db80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2615e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2abc00;  1 drivers
v0x96d261680_0 .net/s *"_ivl_2", 15 0, L_0x96d2abca0;  1 drivers
v0x96d261720_0 .net *"_ivl_7", 0 0, L_0x96c5b1220;  1 drivers
v0x96d2617c0_0 .net *"_ivl_9", 15 0, L_0x96d2abde0;  1 drivers
L_0x96c854eb0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d261860_0 .net/s "acc_in", 31 0, L_0x96c854eb0;  1 drivers
v0x96d261900_0 .net/s "acc_out", 31 0, L_0x96c5b4640;  alias, 1 drivers
v0x96d2619a0_0 .net/s "product", 15 0, L_0x96d2abd40;  1 drivers
v0x96d261a40_0 .net/s "product_ext", 31 0, L_0x96c5b45a0;  1 drivers
v0x96d261ae0_0 .net/s "w", 7 0, L_0x96c5b1360;  1 drivers
v0x96d261b80_0 .net/s "x", 7 0, L_0x96c5b12c0;  1 drivers
L_0x96d2abc00 .extend/s 16, L_0x96c5b12c0;
L_0x96d2abca0 .extend/s 16, L_0x96c5b1360;
L_0x96d2abd40 .arith/mult 16, L_0x96d2abc00, L_0x96d2abca0;
L_0x96c5b1220 .part L_0x96d2abd40, 15, 1;
L_0x96d2abde0 .repeat 16, 16, L_0x96c5b1220;
L_0x96c5b45a0 .concat [ 16 16 0 0], L_0x96d2abd40, L_0x96d2abde0;
L_0x96c5b4640 .arith/sum 32, L_0x96c854eb0, L_0x96c5b45a0;
S_0x96d25ba80 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c5847c0 .param/l "i" 1 6 17, +C4<01001>;
S_0x96d25bc00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25ba80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57dbc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57dc00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57dc40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d261c20_0 .net/s *"_ivl_0", 15 0, L_0x96d2abf20;  1 drivers
v0x96d261cc0_0 .net/s *"_ivl_2", 15 0, L_0x96d2ac000;  1 drivers
v0x96d261d60_0 .net *"_ivl_7", 0 0, L_0x96c5b1400;  1 drivers
v0x96d261e00_0 .net *"_ivl_9", 15 0, L_0x96d2ac140;  1 drivers
L_0x96c854ef8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d261ea0_0 .net/s "acc_in", 31 0, L_0x96c854ef8;  1 drivers
v0x96d261f40_0 .net/s "acc_out", 31 0, L_0x96c5b4780;  alias, 1 drivers
v0x96d261fe0_0 .net/s "product", 15 0, L_0x96d2ac0a0;  1 drivers
v0x96d262080_0 .net/s "product_ext", 31 0, L_0x96c5b46e0;  1 drivers
v0x96d262120_0 .net/s "w", 7 0, L_0x96c5b1540;  1 drivers
v0x96d2621c0_0 .net/s "x", 7 0, L_0x96c5b14a0;  1 drivers
L_0x96d2abf20 .extend/s 16, L_0x96c5b14a0;
L_0x96d2ac000 .extend/s 16, L_0x96c5b1540;
L_0x96d2ac0a0 .arith/mult 16, L_0x96d2abf20, L_0x96d2ac000;
L_0x96c5b1400 .part L_0x96d2ac0a0, 15, 1;
L_0x96d2ac140 .repeat 16, 16, L_0x96c5b1400;
L_0x96c5b46e0 .concat [ 16 16 0 0], L_0x96d2ac0a0, L_0x96d2ac140;
L_0x96c5b4780 .arith/sum 32, L_0x96c854ef8, L_0x96c5b46e0;
S_0x96d25bd80 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584800 .param/l "i" 1 6 17, +C4<01010>;
S_0x96d264000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d25bd80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57dc80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57dcc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57dd00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d262260_0 .net/s *"_ivl_0", 15 0, L_0x96d2ac1e0;  1 drivers
v0x96d262300_0 .net/s *"_ivl_2", 15 0, L_0x96d2ac280;  1 drivers
v0x96d2623a0_0 .net *"_ivl_7", 0 0, L_0x96c5b15e0;  1 drivers
v0x96d262440_0 .net *"_ivl_9", 15 0, L_0x96d2ac3c0;  1 drivers
L_0x96c854f40 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2624e0_0 .net/s "acc_in", 31 0, L_0x96c854f40;  1 drivers
v0x96d262580_0 .net/s "acc_out", 31 0, L_0x96c5b48c0;  alias, 1 drivers
v0x96d262620_0 .net/s "product", 15 0, L_0x96d2ac320;  1 drivers
v0x96d2626c0_0 .net/s "product_ext", 31 0, L_0x96c5b4820;  1 drivers
v0x96d262760_0 .net/s "w", 7 0, L_0x96c5b1720;  1 drivers
v0x96d262800_0 .net/s "x", 7 0, L_0x96c5b1680;  1 drivers
L_0x96d2ac1e0 .extend/s 16, L_0x96c5b1680;
L_0x96d2ac280 .extend/s 16, L_0x96c5b1720;
L_0x96d2ac320 .arith/mult 16, L_0x96d2ac1e0, L_0x96d2ac280;
L_0x96c5b15e0 .part L_0x96d2ac320, 15, 1;
L_0x96d2ac3c0 .repeat 16, 16, L_0x96c5b15e0;
L_0x96c5b4820 .concat [ 16 16 0 0], L_0x96d2ac320, L_0x96d2ac3c0;
L_0x96c5b48c0 .arith/sum 32, L_0x96c854f40, L_0x96c5b4820;
S_0x96d264180 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584840 .param/l "i" 1 6 17, +C4<01011>;
S_0x96d264300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d264180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57dd40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57dd80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ddc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2628a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ac460;  1 drivers
v0x96d262940_0 .net/s *"_ivl_2", 15 0, L_0x96d2ac500;  1 drivers
v0x96d2629e0_0 .net *"_ivl_7", 0 0, L_0x96c5b17c0;  1 drivers
v0x96d262a80_0 .net *"_ivl_9", 15 0, L_0x96d2ac640;  1 drivers
L_0x96c854f88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d262b20_0 .net/s "acc_in", 31 0, L_0x96c854f88;  1 drivers
v0x96d262bc0_0 .net/s "acc_out", 31 0, L_0x96c5b4a00;  alias, 1 drivers
v0x96d262c60_0 .net/s "product", 15 0, L_0x96d2ac5a0;  1 drivers
v0x96d262d00_0 .net/s "product_ext", 31 0, L_0x96c5b4960;  1 drivers
v0x96d262da0_0 .net/s "w", 7 0, L_0x96c5b1900;  1 drivers
v0x96d262e40_0 .net/s "x", 7 0, L_0x96c5b1860;  1 drivers
L_0x96d2ac460 .extend/s 16, L_0x96c5b1860;
L_0x96d2ac500 .extend/s 16, L_0x96c5b1900;
L_0x96d2ac5a0 .arith/mult 16, L_0x96d2ac460, L_0x96d2ac500;
L_0x96c5b17c0 .part L_0x96d2ac5a0, 15, 1;
L_0x96d2ac640 .repeat 16, 16, L_0x96c5b17c0;
L_0x96c5b4960 .concat [ 16 16 0 0], L_0x96d2ac5a0, L_0x96d2ac640;
L_0x96c5b4a00 .arith/sum 32, L_0x96c854f88, L_0x96c5b4960;
S_0x96d264480 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584880 .param/l "i" 1 6 17, +C4<01100>;
S_0x96d264600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d264480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57de00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57de40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57de80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d262ee0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ac6e0;  1 drivers
v0x96d262f80_0 .net/s *"_ivl_2", 15 0, L_0x96d2ac780;  1 drivers
v0x96d263020_0 .net *"_ivl_7", 0 0, L_0x96c5b19a0;  1 drivers
v0x96d2630c0_0 .net *"_ivl_9", 15 0, L_0x96d2ac8c0;  1 drivers
L_0x96c854fd0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d263160_0 .net/s "acc_in", 31 0, L_0x96c854fd0;  1 drivers
v0x96d263200_0 .net/s "acc_out", 31 0, L_0x96c5b4b40;  alias, 1 drivers
v0x96d2632a0_0 .net/s "product", 15 0, L_0x96d2ac820;  1 drivers
v0x96d263340_0 .net/s "product_ext", 31 0, L_0x96c5b4aa0;  1 drivers
v0x96d2633e0_0 .net/s "w", 7 0, L_0x96c5b1ae0;  1 drivers
v0x96d263480_0 .net/s "x", 7 0, L_0x96c5b1a40;  1 drivers
L_0x96d2ac6e0 .extend/s 16, L_0x96c5b1a40;
L_0x96d2ac780 .extend/s 16, L_0x96c5b1ae0;
L_0x96d2ac820 .arith/mult 16, L_0x96d2ac6e0, L_0x96d2ac780;
L_0x96c5b19a0 .part L_0x96d2ac820, 15, 1;
L_0x96d2ac8c0 .repeat 16, 16, L_0x96c5b19a0;
L_0x96c5b4aa0 .concat [ 16 16 0 0], L_0x96d2ac820, L_0x96d2ac8c0;
L_0x96c5b4b40 .arith/sum 32, L_0x96c854fd0, L_0x96c5b4aa0;
S_0x96d264780 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c5848c0 .param/l "i" 1 6 17, +C4<01101>;
S_0x96d264900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d264780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57dec0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57df00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57df40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d263520_0 .net/s *"_ivl_0", 15 0, L_0x96d2ac960;  1 drivers
v0x96d2635c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aca00;  1 drivers
v0x96d263660_0 .net *"_ivl_7", 0 0, L_0x96c5b1b80;  1 drivers
v0x96d263700_0 .net *"_ivl_9", 15 0, L_0x96d2acb40;  1 drivers
L_0x96c855018 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2637a0_0 .net/s "acc_in", 31 0, L_0x96c855018;  1 drivers
v0x96d263840_0 .net/s "acc_out", 31 0, L_0x96c5b4c80;  alias, 1 drivers
v0x96d2638e0_0 .net/s "product", 15 0, L_0x96d2acaa0;  1 drivers
v0x96d263980_0 .net/s "product_ext", 31 0, L_0x96c5b4be0;  1 drivers
v0x96d263a20_0 .net/s "w", 7 0, L_0x96c5b1cc0;  1 drivers
v0x96d263ac0_0 .net/s "x", 7 0, L_0x96c5b1c20;  1 drivers
L_0x96d2ac960 .extend/s 16, L_0x96c5b1c20;
L_0x96d2aca00 .extend/s 16, L_0x96c5b1cc0;
L_0x96d2acaa0 .arith/mult 16, L_0x96d2ac960, L_0x96d2aca00;
L_0x96c5b1b80 .part L_0x96d2acaa0, 15, 1;
L_0x96d2acb40 .repeat 16, 16, L_0x96c5b1b80;
L_0x96c5b4be0 .concat [ 16 16 0 0], L_0x96d2acaa0, L_0x96d2acb40;
L_0x96c5b4c80 .arith/sum 32, L_0x96c855018, L_0x96c5b4be0;
S_0x96d264a80 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584900 .param/l "i" 1 6 17, +C4<01110>;
S_0x96d264c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d264a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57df80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57dfc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e000 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d263b60_0 .net/s *"_ivl_0", 15 0, L_0x96d2acbe0;  1 drivers
v0x96d263c00_0 .net/s *"_ivl_2", 15 0, L_0x96d2acc80;  1 drivers
v0x96d263ca0_0 .net *"_ivl_7", 0 0, L_0x96c5b1d60;  1 drivers
v0x96d263d40_0 .net *"_ivl_9", 15 0, L_0x96d2acdc0;  1 drivers
L_0x96c855060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d263de0_0 .net/s "acc_in", 31 0, L_0x96c855060;  1 drivers
v0x96d263e80_0 .net/s "acc_out", 31 0, L_0x96c5b4dc0;  alias, 1 drivers
v0x96d263f20_0 .net/s "product", 15 0, L_0x96d2acd20;  1 drivers
v0x96d268000_0 .net/s "product_ext", 31 0, L_0x96c5b4d20;  1 drivers
v0x96d2680a0_0 .net/s "w", 7 0, L_0x96c5b1ea0;  1 drivers
v0x96d268140_0 .net/s "x", 7 0, L_0x96c5b1e00;  1 drivers
L_0x96d2acbe0 .extend/s 16, L_0x96c5b1e00;
L_0x96d2acc80 .extend/s 16, L_0x96c5b1ea0;
L_0x96d2acd20 .arith/mult 16, L_0x96d2acbe0, L_0x96d2acc80;
L_0x96c5b1d60 .part L_0x96d2acd20, 15, 1;
L_0x96d2acdc0 .repeat 16, 16, L_0x96c5b1d60;
L_0x96c5b4d20 .concat [ 16 16 0 0], L_0x96d2acd20, L_0x96d2acdc0;
L_0x96c5b4dc0 .arith/sum 32, L_0x96c855060, L_0x96c5b4d20;
S_0x96d264d80 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584940 .param/l "i" 1 6 17, +C4<01111>;
S_0x96d264f00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d264d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e040 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e080 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e0c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2681e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ace60;  1 drivers
v0x96d268280_0 .net/s *"_ivl_2", 15 0, L_0x96d2acf00;  1 drivers
v0x96d268320_0 .net *"_ivl_7", 0 0, L_0x96c5b1f40;  1 drivers
v0x96d2683c0_0 .net *"_ivl_9", 15 0, L_0x96d2ad040;  1 drivers
L_0x96c8550a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d268460_0 .net/s "acc_in", 31 0, L_0x96c8550a8;  1 drivers
v0x96d268500_0 .net/s "acc_out", 31 0, L_0x96c5b4f00;  alias, 1 drivers
v0x96d2685a0_0 .net/s "product", 15 0, L_0x96d2acfa0;  1 drivers
v0x96d268640_0 .net/s "product_ext", 31 0, L_0x96c5b4e60;  1 drivers
v0x96d2686e0_0 .net/s "w", 7 0, L_0x96c5b2080;  1 drivers
v0x96d268780_0 .net/s "x", 7 0, L_0x96c5b1fe0;  1 drivers
L_0x96d2ace60 .extend/s 16, L_0x96c5b1fe0;
L_0x96d2acf00 .extend/s 16, L_0x96c5b2080;
L_0x96d2acfa0 .arith/mult 16, L_0x96d2ace60, L_0x96d2acf00;
L_0x96c5b1f40 .part L_0x96d2acfa0, 15, 1;
L_0x96d2ad040 .repeat 16, 16, L_0x96c5b1f40;
L_0x96c5b4e60 .concat [ 16 16 0 0], L_0x96d2acfa0, L_0x96d2ad040;
L_0x96c5b4f00 .arith/sum 32, L_0x96c8550a8, L_0x96c5b4e60;
S_0x96d265080 .scope generate, "GEN_MAC[16]" "GEN_MAC[16]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584980 .param/l "i" 1 6 17, +C4<010000>;
S_0x96d265200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e100 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e140 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e180 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d268820_0 .net/s *"_ivl_0", 15 0, L_0x96d2ad0e0;  1 drivers
v0x96d2688c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2ad180;  1 drivers
v0x96d268960_0 .net *"_ivl_7", 0 0, L_0x96c5b2120;  1 drivers
v0x96d268a00_0 .net *"_ivl_9", 15 0, L_0x96d2ad2c0;  1 drivers
L_0x96c8550f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d268aa0_0 .net/s "acc_in", 31 0, L_0x96c8550f0;  1 drivers
v0x96d268b40_0 .net/s "acc_out", 31 0, L_0x96c5b5040;  alias, 1 drivers
v0x96d268be0_0 .net/s "product", 15 0, L_0x96d2ad220;  1 drivers
v0x96d268c80_0 .net/s "product_ext", 31 0, L_0x96c5b4fa0;  1 drivers
v0x96d268d20_0 .net/s "w", 7 0, L_0x96c5b2260;  1 drivers
v0x96d268dc0_0 .net/s "x", 7 0, L_0x96c5b21c0;  1 drivers
L_0x96d2ad0e0 .extend/s 16, L_0x96c5b21c0;
L_0x96d2ad180 .extend/s 16, L_0x96c5b2260;
L_0x96d2ad220 .arith/mult 16, L_0x96d2ad0e0, L_0x96d2ad180;
L_0x96c5b2120 .part L_0x96d2ad220, 15, 1;
L_0x96d2ad2c0 .repeat 16, 16, L_0x96c5b2120;
L_0x96c5b4fa0 .concat [ 16 16 0 0], L_0x96d2ad220, L_0x96d2ad2c0;
L_0x96c5b5040 .arith/sum 32, L_0x96c8550f0, L_0x96c5b4fa0;
S_0x96d265380 .scope generate, "GEN_MAC[17]" "GEN_MAC[17]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c5849c0 .param/l "i" 1 6 17, +C4<010001>;
S_0x96d265500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e1c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e200 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e240 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d268e60_0 .net/s *"_ivl_0", 15 0, L_0x96d2ad360;  1 drivers
v0x96d268f00_0 .net/s *"_ivl_2", 15 0, L_0x96d2ad400;  1 drivers
v0x96d268fa0_0 .net *"_ivl_7", 0 0, L_0x96c5b2300;  1 drivers
v0x96d269040_0 .net *"_ivl_9", 15 0, L_0x96d2ad540;  1 drivers
L_0x96c855138 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2690e0_0 .net/s "acc_in", 31 0, L_0x96c855138;  1 drivers
v0x96d269180_0 .net/s "acc_out", 31 0, L_0x96c5b5180;  alias, 1 drivers
v0x96d269220_0 .net/s "product", 15 0, L_0x96d2ad4a0;  1 drivers
v0x96d2692c0_0 .net/s "product_ext", 31 0, L_0x96c5b50e0;  1 drivers
v0x96d269360_0 .net/s "w", 7 0, L_0x96c5b2440;  1 drivers
v0x96d269400_0 .net/s "x", 7 0, L_0x96c5b23a0;  1 drivers
L_0x96d2ad360 .extend/s 16, L_0x96c5b23a0;
L_0x96d2ad400 .extend/s 16, L_0x96c5b2440;
L_0x96d2ad4a0 .arith/mult 16, L_0x96d2ad360, L_0x96d2ad400;
L_0x96c5b2300 .part L_0x96d2ad4a0, 15, 1;
L_0x96d2ad540 .repeat 16, 16, L_0x96c5b2300;
L_0x96c5b50e0 .concat [ 16 16 0 0], L_0x96d2ad4a0, L_0x96d2ad540;
L_0x96c5b5180 .arith/sum 32, L_0x96c855138, L_0x96c5b50e0;
S_0x96d265680 .scope generate, "GEN_MAC[18]" "GEN_MAC[18]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584a00 .param/l "i" 1 6 17, +C4<010010>;
S_0x96d265800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e280 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e2c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e300 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2694a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ad5e0;  1 drivers
v0x96d269540_0 .net/s *"_ivl_2", 15 0, L_0x96d2ad680;  1 drivers
v0x96d2695e0_0 .net *"_ivl_7", 0 0, L_0x96c5b24e0;  1 drivers
v0x96d269680_0 .net *"_ivl_9", 15 0, L_0x96d2ad7c0;  1 drivers
L_0x96c855180 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d269720_0 .net/s "acc_in", 31 0, L_0x96c855180;  1 drivers
v0x96d2697c0_0 .net/s "acc_out", 31 0, L_0x96c5b52c0;  alias, 1 drivers
v0x96d269860_0 .net/s "product", 15 0, L_0x96d2ad720;  1 drivers
v0x96d269900_0 .net/s "product_ext", 31 0, L_0x96c5b5220;  1 drivers
v0x96d2699a0_0 .net/s "w", 7 0, L_0x96c5b2620;  1 drivers
v0x96d269a40_0 .net/s "x", 7 0, L_0x96c5b2580;  1 drivers
L_0x96d2ad5e0 .extend/s 16, L_0x96c5b2580;
L_0x96d2ad680 .extend/s 16, L_0x96c5b2620;
L_0x96d2ad720 .arith/mult 16, L_0x96d2ad5e0, L_0x96d2ad680;
L_0x96c5b24e0 .part L_0x96d2ad720, 15, 1;
L_0x96d2ad7c0 .repeat 16, 16, L_0x96c5b24e0;
L_0x96c5b5220 .concat [ 16 16 0 0], L_0x96d2ad720, L_0x96d2ad7c0;
L_0x96c5b52c0 .arith/sum 32, L_0x96c855180, L_0x96c5b5220;
S_0x96d265980 .scope generate, "GEN_MAC[19]" "GEN_MAC[19]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584a40 .param/l "i" 1 6 17, +C4<010011>;
S_0x96d265b00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265980;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e340 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e380 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e3c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d269ae0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ad860;  1 drivers
v0x96d269b80_0 .net/s *"_ivl_2", 15 0, L_0x96d2ad900;  1 drivers
v0x96d269c20_0 .net *"_ivl_7", 0 0, L_0x96c5b26c0;  1 drivers
v0x96d269cc0_0 .net *"_ivl_9", 15 0, L_0x96d2ada40;  1 drivers
L_0x96c8551c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d269d60_0 .net/s "acc_in", 31 0, L_0x96c8551c8;  1 drivers
v0x96d269e00_0 .net/s "acc_out", 31 0, L_0x96c5b5400;  alias, 1 drivers
v0x96d269ea0_0 .net/s "product", 15 0, L_0x96d2ad9a0;  1 drivers
v0x96d269f40_0 .net/s "product_ext", 31 0, L_0x96c5b5360;  1 drivers
v0x96d269fe0_0 .net/s "w", 7 0, L_0x96c5b2800;  1 drivers
v0x96d26a080_0 .net/s "x", 7 0, L_0x96c5b2760;  1 drivers
L_0x96d2ad860 .extend/s 16, L_0x96c5b2760;
L_0x96d2ad900 .extend/s 16, L_0x96c5b2800;
L_0x96d2ad9a0 .arith/mult 16, L_0x96d2ad860, L_0x96d2ad900;
L_0x96c5b26c0 .part L_0x96d2ad9a0, 15, 1;
L_0x96d2ada40 .repeat 16, 16, L_0x96c5b26c0;
L_0x96c5b5360 .concat [ 16 16 0 0], L_0x96d2ad9a0, L_0x96d2ada40;
L_0x96c5b5400 .arith/sum 32, L_0x96c8551c8, L_0x96c5b5360;
S_0x96d265c80 .scope generate, "GEN_MAC[20]" "GEN_MAC[20]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584a80 .param/l "i" 1 6 17, +C4<010100>;
S_0x96d265e00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265c80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e400 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e440 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e480 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26a120_0 .net/s *"_ivl_0", 15 0, L_0x96d2adae0;  1 drivers
v0x96d26a1c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2adb80;  1 drivers
v0x96d26a260_0 .net *"_ivl_7", 0 0, L_0x96c5b28a0;  1 drivers
v0x96d26a300_0 .net *"_ivl_9", 15 0, L_0x96d2adcc0;  1 drivers
L_0x96c855210 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26a3a0_0 .net/s "acc_in", 31 0, L_0x96c855210;  1 drivers
v0x96d26a440_0 .net/s "acc_out", 31 0, L_0x96c5b5540;  alias, 1 drivers
v0x96d26a4e0_0 .net/s "product", 15 0, L_0x96d2adc20;  1 drivers
v0x96d26a580_0 .net/s "product_ext", 31 0, L_0x96c5b54a0;  1 drivers
v0x96d26a620_0 .net/s "w", 7 0, L_0x96c5b29e0;  1 drivers
v0x96d26a6c0_0 .net/s "x", 7 0, L_0x96c5b2940;  1 drivers
L_0x96d2adae0 .extend/s 16, L_0x96c5b2940;
L_0x96d2adb80 .extend/s 16, L_0x96c5b29e0;
L_0x96d2adc20 .arith/mult 16, L_0x96d2adae0, L_0x96d2adb80;
L_0x96c5b28a0 .part L_0x96d2adc20, 15, 1;
L_0x96d2adcc0 .repeat 16, 16, L_0x96c5b28a0;
L_0x96c5b54a0 .concat [ 16 16 0 0], L_0x96d2adc20, L_0x96d2adcc0;
L_0x96c5b5540 .arith/sum 32, L_0x96c855210, L_0x96c5b54a0;
S_0x96d265f80 .scope generate, "GEN_MAC[21]" "GEN_MAC[21]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584ac0 .param/l "i" 1 6 17, +C4<010101>;
S_0x96d266100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d265f80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e4c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e500 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e540 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26a760_0 .net/s *"_ivl_0", 15 0, L_0x96d2add60;  1 drivers
v0x96d26a800_0 .net/s *"_ivl_2", 15 0, L_0x96d2ade00;  1 drivers
v0x96d26a8a0_0 .net *"_ivl_7", 0 0, L_0x96c5b2a80;  1 drivers
v0x96d26a940_0 .net *"_ivl_9", 15 0, L_0x96d2adf40;  1 drivers
L_0x96c855258 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26a9e0_0 .net/s "acc_in", 31 0, L_0x96c855258;  1 drivers
v0x96d26aa80_0 .net/s "acc_out", 31 0, L_0x96c5b5680;  alias, 1 drivers
v0x96d26ab20_0 .net/s "product", 15 0, L_0x96d2adea0;  1 drivers
v0x96d26abc0_0 .net/s "product_ext", 31 0, L_0x96c5b55e0;  1 drivers
v0x96d26ac60_0 .net/s "w", 7 0, L_0x96c5b2bc0;  1 drivers
v0x96d26ad00_0 .net/s "x", 7 0, L_0x96c5b2b20;  1 drivers
L_0x96d2add60 .extend/s 16, L_0x96c5b2b20;
L_0x96d2ade00 .extend/s 16, L_0x96c5b2bc0;
L_0x96d2adea0 .arith/mult 16, L_0x96d2add60, L_0x96d2ade00;
L_0x96c5b2a80 .part L_0x96d2adea0, 15, 1;
L_0x96d2adf40 .repeat 16, 16, L_0x96c5b2a80;
L_0x96c5b55e0 .concat [ 16 16 0 0], L_0x96d2adea0, L_0x96d2adf40;
L_0x96c5b5680 .arith/sum 32, L_0x96c855258, L_0x96c5b55e0;
S_0x96d266280 .scope generate, "GEN_MAC[22]" "GEN_MAC[22]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584b00 .param/l "i" 1 6 17, +C4<010110>;
S_0x96d266400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d266280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e580 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e5c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e600 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26ada0_0 .net/s *"_ivl_0", 15 0, L_0x96d2adfe0;  1 drivers
v0x96d26ae40_0 .net/s *"_ivl_2", 15 0, L_0x96d2ae080;  1 drivers
v0x96d26aee0_0 .net *"_ivl_7", 0 0, L_0x96c5b2c60;  1 drivers
v0x96d26af80_0 .net *"_ivl_9", 15 0, L_0x96d2ae1c0;  1 drivers
L_0x96c8552a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26b020_0 .net/s "acc_in", 31 0, L_0x96c8552a0;  1 drivers
v0x96d26b0c0_0 .net/s "acc_out", 31 0, L_0x96c5b57c0;  alias, 1 drivers
v0x96d26b160_0 .net/s "product", 15 0, L_0x96d2ae120;  1 drivers
v0x96d26b200_0 .net/s "product_ext", 31 0, L_0x96c5b5720;  1 drivers
v0x96d26b2a0_0 .net/s "w", 7 0, L_0x96c5b2da0;  1 drivers
v0x96d26b340_0 .net/s "x", 7 0, L_0x96c5b2d00;  1 drivers
L_0x96d2adfe0 .extend/s 16, L_0x96c5b2d00;
L_0x96d2ae080 .extend/s 16, L_0x96c5b2da0;
L_0x96d2ae120 .arith/mult 16, L_0x96d2adfe0, L_0x96d2ae080;
L_0x96c5b2c60 .part L_0x96d2ae120, 15, 1;
L_0x96d2ae1c0 .repeat 16, 16, L_0x96c5b2c60;
L_0x96c5b5720 .concat [ 16 16 0 0], L_0x96d2ae120, L_0x96d2ae1c0;
L_0x96c5b57c0 .arith/sum 32, L_0x96c8552a0, L_0x96c5b5720;
S_0x96d266580 .scope generate, "GEN_MAC[23]" "GEN_MAC[23]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584b40 .param/l "i" 1 6 17, +C4<010111>;
S_0x96d266700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d266580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e640 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e680 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e6c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26b3e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ae260;  1 drivers
v0x96d26b480_0 .net/s *"_ivl_2", 15 0, L_0x96d2ae300;  1 drivers
v0x96d26b520_0 .net *"_ivl_7", 0 0, L_0x96c5b2e40;  1 drivers
v0x96d26b5c0_0 .net *"_ivl_9", 15 0, L_0x96d2ae440;  1 drivers
L_0x96c8552e8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26b660_0 .net/s "acc_in", 31 0, L_0x96c8552e8;  1 drivers
v0x96d26b700_0 .net/s "acc_out", 31 0, L_0x96c5b5900;  alias, 1 drivers
v0x96d26b7a0_0 .net/s "product", 15 0, L_0x96d2ae3a0;  1 drivers
v0x96d26b840_0 .net/s "product_ext", 31 0, L_0x96c5b5860;  1 drivers
v0x96d26b8e0_0 .net/s "w", 7 0, L_0x96c5b2f80;  1 drivers
v0x96d26b980_0 .net/s "x", 7 0, L_0x96c5b2ee0;  1 drivers
L_0x96d2ae260 .extend/s 16, L_0x96c5b2ee0;
L_0x96d2ae300 .extend/s 16, L_0x96c5b2f80;
L_0x96d2ae3a0 .arith/mult 16, L_0x96d2ae260, L_0x96d2ae300;
L_0x96c5b2e40 .part L_0x96d2ae3a0, 15, 1;
L_0x96d2ae440 .repeat 16, 16, L_0x96c5b2e40;
L_0x96c5b5860 .concat [ 16 16 0 0], L_0x96d2ae3a0, L_0x96d2ae440;
L_0x96c5b5900 .arith/sum 32, L_0x96c8552e8, L_0x96c5b5860;
S_0x96d266880 .scope generate, "GEN_MAC[24]" "GEN_MAC[24]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584b80 .param/l "i" 1 6 17, +C4<011000>;
S_0x96d266a00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d266880;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e700 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e740 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e780 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26ba20_0 .net/s *"_ivl_0", 15 0, L_0x96d2ae4e0;  1 drivers
v0x96d26bac0_0 .net/s *"_ivl_2", 15 0, L_0x96d2ae580;  1 drivers
v0x96d26bb60_0 .net *"_ivl_7", 0 0, L_0x96c5b3020;  1 drivers
v0x96d26bc00_0 .net *"_ivl_9", 15 0, L_0x96d2ae6c0;  1 drivers
L_0x96c855330 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26bca0_0 .net/s "acc_in", 31 0, L_0x96c855330;  1 drivers
v0x96d26bd40_0 .net/s "acc_out", 31 0, L_0x96c5b5a40;  alias, 1 drivers
v0x96d26bde0_0 .net/s "product", 15 0, L_0x96d2ae620;  1 drivers
v0x96d26be80_0 .net/s "product_ext", 31 0, L_0x96c5b59a0;  1 drivers
v0x96d26bf20_0 .net/s "w", 7 0, L_0x96c5b3160;  1 drivers
v0x96d26c000_0 .net/s "x", 7 0, L_0x96c5b30c0;  1 drivers
L_0x96d2ae4e0 .extend/s 16, L_0x96c5b30c0;
L_0x96d2ae580 .extend/s 16, L_0x96c5b3160;
L_0x96d2ae620 .arith/mult 16, L_0x96d2ae4e0, L_0x96d2ae580;
L_0x96c5b3020 .part L_0x96d2ae620, 15, 1;
L_0x96d2ae6c0 .repeat 16, 16, L_0x96c5b3020;
L_0x96c5b59a0 .concat [ 16 16 0 0], L_0x96d2ae620, L_0x96d2ae6c0;
L_0x96c5b5a40 .arith/sum 32, L_0x96c855330, L_0x96c5b59a0;
S_0x96d266b80 .scope generate, "GEN_MAC[25]" "GEN_MAC[25]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584bc0 .param/l "i" 1 6 17, +C4<011001>;
S_0x96d266d00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d266b80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e7c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e800 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e840 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26c0a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ae760;  1 drivers
v0x96d26c140_0 .net/s *"_ivl_2", 15 0, L_0x96d2ae800;  1 drivers
v0x96d26c1e0_0 .net *"_ivl_7", 0 0, L_0x96c5b3200;  1 drivers
v0x96d26c280_0 .net *"_ivl_9", 15 0, L_0x96d2ae940;  1 drivers
L_0x96c855378 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26c320_0 .net/s "acc_in", 31 0, L_0x96c855378;  1 drivers
v0x96d26c3c0_0 .net/s "acc_out", 31 0, L_0x96c5b5b80;  alias, 1 drivers
v0x96d26c460_0 .net/s "product", 15 0, L_0x96d2ae8a0;  1 drivers
v0x96d26c500_0 .net/s "product_ext", 31 0, L_0x96c5b5ae0;  1 drivers
v0x96d26c5a0_0 .net/s "w", 7 0, L_0x96c5b3340;  1 drivers
v0x96d26c640_0 .net/s "x", 7 0, L_0x96c5b32a0;  1 drivers
L_0x96d2ae760 .extend/s 16, L_0x96c5b32a0;
L_0x96d2ae800 .extend/s 16, L_0x96c5b3340;
L_0x96d2ae8a0 .arith/mult 16, L_0x96d2ae760, L_0x96d2ae800;
L_0x96c5b3200 .part L_0x96d2ae8a0, 15, 1;
L_0x96d2ae940 .repeat 16, 16, L_0x96c5b3200;
L_0x96c5b5ae0 .concat [ 16 16 0 0], L_0x96d2ae8a0, L_0x96d2ae940;
L_0x96c5b5b80 .arith/sum 32, L_0x96c855378, L_0x96c5b5ae0;
S_0x96d266e80 .scope generate, "GEN_MAC[26]" "GEN_MAC[26]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584c00 .param/l "i" 1 6 17, +C4<011010>;
S_0x96d267000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d266e80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e880 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e8c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e900 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26c6e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2ae9e0;  1 drivers
v0x96d26c780_0 .net/s *"_ivl_2", 15 0, L_0x96d2aea80;  1 drivers
v0x96d26c820_0 .net *"_ivl_7", 0 0, L_0x96c5b33e0;  1 drivers
v0x96d26c8c0_0 .net *"_ivl_9", 15 0, L_0x96d2aebc0;  1 drivers
L_0x96c8553c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26c960_0 .net/s "acc_in", 31 0, L_0x96c8553c0;  1 drivers
v0x96d26ca00_0 .net/s "acc_out", 31 0, L_0x96c5b5cc0;  alias, 1 drivers
v0x96d26caa0_0 .net/s "product", 15 0, L_0x96d2aeb20;  1 drivers
v0x96d26cb40_0 .net/s "product_ext", 31 0, L_0x96c5b5c20;  1 drivers
v0x96d26cbe0_0 .net/s "w", 7 0, L_0x96c5b3520;  1 drivers
v0x96d26cc80_0 .net/s "x", 7 0, L_0x96c5b3480;  1 drivers
L_0x96d2ae9e0 .extend/s 16, L_0x96c5b3480;
L_0x96d2aea80 .extend/s 16, L_0x96c5b3520;
L_0x96d2aeb20 .arith/mult 16, L_0x96d2ae9e0, L_0x96d2aea80;
L_0x96c5b33e0 .part L_0x96d2aeb20, 15, 1;
L_0x96d2aebc0 .repeat 16, 16, L_0x96c5b33e0;
L_0x96c5b5c20 .concat [ 16 16 0 0], L_0x96d2aeb20, L_0x96d2aebc0;
L_0x96c5b5cc0 .arith/sum 32, L_0x96c8553c0, L_0x96c5b5c20;
S_0x96d267180 .scope generate, "GEN_MAC[27]" "GEN_MAC[27]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584c40 .param/l "i" 1 6 17, +C4<011011>;
S_0x96d267300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d267180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57e940 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57e980 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57e9c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26cd20_0 .net/s *"_ivl_0", 15 0, L_0x96d2aec60;  1 drivers
v0x96d26cdc0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aed00;  1 drivers
v0x96d26ce60_0 .net *"_ivl_7", 0 0, L_0x96c5b35c0;  1 drivers
v0x96d26cf00_0 .net *"_ivl_9", 15 0, L_0x96d2aee40;  1 drivers
L_0x96c855408 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26cfa0_0 .net/s "acc_in", 31 0, L_0x96c855408;  1 drivers
v0x96d26d040_0 .net/s "acc_out", 31 0, L_0x96c5b5e00;  alias, 1 drivers
v0x96d26d0e0_0 .net/s "product", 15 0, L_0x96d2aeda0;  1 drivers
v0x96d26d180_0 .net/s "product_ext", 31 0, L_0x96c5b5d60;  1 drivers
v0x96d26d220_0 .net/s "w", 7 0, L_0x96c5b3700;  1 drivers
v0x96d26d2c0_0 .net/s "x", 7 0, L_0x96c5b3660;  1 drivers
L_0x96d2aec60 .extend/s 16, L_0x96c5b3660;
L_0x96d2aed00 .extend/s 16, L_0x96c5b3700;
L_0x96d2aeda0 .arith/mult 16, L_0x96d2aec60, L_0x96d2aed00;
L_0x96c5b35c0 .part L_0x96d2aeda0, 15, 1;
L_0x96d2aee40 .repeat 16, 16, L_0x96c5b35c0;
L_0x96c5b5d60 .concat [ 16 16 0 0], L_0x96d2aeda0, L_0x96d2aee40;
L_0x96c5b5e00 .arith/sum 32, L_0x96c855408, L_0x96c5b5d60;
S_0x96d267480 .scope generate, "GEN_MAC[28]" "GEN_MAC[28]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584c80 .param/l "i" 1 6 17, +C4<011100>;
S_0x96d267600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d267480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ea00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ea40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ea80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26d360_0 .net/s *"_ivl_0", 15 0, L_0x96d2aeee0;  1 drivers
v0x96d26d400_0 .net/s *"_ivl_2", 15 0, L_0x96d2aef80;  1 drivers
v0x96d26d4a0_0 .net *"_ivl_7", 0 0, L_0x96c5b37a0;  1 drivers
v0x96d26d540_0 .net *"_ivl_9", 15 0, L_0x96d2af0c0;  1 drivers
L_0x96c855450 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26d5e0_0 .net/s "acc_in", 31 0, L_0x96c855450;  1 drivers
v0x96d26d680_0 .net/s "acc_out", 31 0, L_0x96c5b5f40;  alias, 1 drivers
v0x96d26d720_0 .net/s "product", 15 0, L_0x96d2af020;  1 drivers
v0x96d26d7c0_0 .net/s "product_ext", 31 0, L_0x96c5b5ea0;  1 drivers
v0x96d26d860_0 .net/s "w", 7 0, L_0x96c5b38e0;  1 drivers
v0x96d26d900_0 .net/s "x", 7 0, L_0x96c5b3840;  1 drivers
L_0x96d2aeee0 .extend/s 16, L_0x96c5b3840;
L_0x96d2aef80 .extend/s 16, L_0x96c5b38e0;
L_0x96d2af020 .arith/mult 16, L_0x96d2aeee0, L_0x96d2aef80;
L_0x96c5b37a0 .part L_0x96d2af020, 15, 1;
L_0x96d2af0c0 .repeat 16, 16, L_0x96c5b37a0;
L_0x96c5b5ea0 .concat [ 16 16 0 0], L_0x96d2af020, L_0x96d2af0c0;
L_0x96c5b5f40 .arith/sum 32, L_0x96c855450, L_0x96c5b5ea0;
S_0x96d267780 .scope generate, "GEN_MAC[29]" "GEN_MAC[29]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584cc0 .param/l "i" 1 6 17, +C4<011101>;
S_0x96d267900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d267780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57eac0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57eb00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57eb40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26d9a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2af160;  1 drivers
v0x96d26da40_0 .net/s *"_ivl_2", 15 0, L_0x96d2af200;  1 drivers
v0x96d26dae0_0 .net *"_ivl_7", 0 0, L_0x96c5b3980;  1 drivers
v0x96d26db80_0 .net *"_ivl_9", 15 0, L_0x96d2af340;  1 drivers
L_0x96c855498 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26dc20_0 .net/s "acc_in", 31 0, L_0x96c855498;  1 drivers
v0x96d26dcc0_0 .net/s "acc_out", 31 0, L_0x96c5b6080;  alias, 1 drivers
v0x96d26dd60_0 .net/s "product", 15 0, L_0x96d2af2a0;  1 drivers
v0x96d26de00_0 .net/s "product_ext", 31 0, L_0x96c5b5fe0;  1 drivers
v0x96d26dea0_0 .net/s "w", 7 0, L_0x96c5b3ac0;  1 drivers
v0x96d26df40_0 .net/s "x", 7 0, L_0x96c5b3a20;  1 drivers
L_0x96d2af160 .extend/s 16, L_0x96c5b3a20;
L_0x96d2af200 .extend/s 16, L_0x96c5b3ac0;
L_0x96d2af2a0 .arith/mult 16, L_0x96d2af160, L_0x96d2af200;
L_0x96c5b3980 .part L_0x96d2af2a0, 15, 1;
L_0x96d2af340 .repeat 16, 16, L_0x96c5b3980;
L_0x96c5b5fe0 .concat [ 16 16 0 0], L_0x96d2af2a0, L_0x96d2af340;
L_0x96c5b6080 .arith/sum 32, L_0x96c855498, L_0x96c5b5fe0;
S_0x96d267a80 .scope generate, "GEN_MAC[30]" "GEN_MAC[30]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584d00 .param/l "i" 1 6 17, +C4<011110>;
S_0x96d267c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d267a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57eb80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ebc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ec00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26dfe0_0 .net/s *"_ivl_0", 15 0, L_0x96d2af3e0;  1 drivers
v0x96d26e080_0 .net/s *"_ivl_2", 15 0, L_0x96d2af480;  1 drivers
v0x96d26e120_0 .net *"_ivl_7", 0 0, L_0x96c5b3b60;  1 drivers
v0x96d26e1c0_0 .net *"_ivl_9", 15 0, L_0x96d2af5c0;  1 drivers
L_0x96c8554e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26e260_0 .net/s "acc_in", 31 0, L_0x96c8554e0;  1 drivers
v0x96d26e300_0 .net/s "acc_out", 31 0, L_0x96c5b61c0;  alias, 1 drivers
v0x96d26e3a0_0 .net/s "product", 15 0, L_0x96d2af520;  1 drivers
v0x96d26e440_0 .net/s "product_ext", 31 0, L_0x96c5b6120;  1 drivers
v0x96d26e4e0_0 .net/s "w", 7 0, L_0x96c5b3ca0;  1 drivers
v0x96d26e580_0 .net/s "x", 7 0, L_0x96c5b3c00;  1 drivers
L_0x96d2af3e0 .extend/s 16, L_0x96c5b3c00;
L_0x96d2af480 .extend/s 16, L_0x96c5b3ca0;
L_0x96d2af520 .arith/mult 16, L_0x96d2af3e0, L_0x96d2af480;
L_0x96c5b3b60 .part L_0x96d2af520, 15, 1;
L_0x96d2af5c0 .repeat 16, 16, L_0x96c5b3b60;
L_0x96c5b6120 .concat [ 16 16 0 0], L_0x96d2af520, L_0x96d2af5c0;
L_0x96c5b61c0 .arith/sum 32, L_0x96c8554e0, L_0x96c5b6120;
S_0x96d267d80 .scope generate, "GEN_MAC[31]" "GEN_MAC[31]" 6 17, 6 17 0, S_0x96d259e00;
 .timescale 0 0;
P_0x96c584d40 .param/l "i" 1 6 17, +C4<011111>;
S_0x96d270000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d267d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ec40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ec80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ecc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d26e620_0 .net/s *"_ivl_0", 15 0, L_0x96d2af660;  1 drivers
v0x96d26e6c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2af700;  1 drivers
v0x96d26e760_0 .net *"_ivl_7", 0 0, L_0x96c5b3d40;  1 drivers
v0x96d26e800_0 .net *"_ivl_9", 15 0, L_0x96d2af840;  1 drivers
L_0x96c855528 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d26e8a0_0 .net/s "acc_in", 31 0, L_0x96c855528;  1 drivers
v0x96d26e940_0 .net/s "acc_out", 31 0, L_0x96c5b6300;  alias, 1 drivers
v0x96d26e9e0_0 .net/s "product", 15 0, L_0x96d2af7a0;  1 drivers
v0x96d26ea80_0 .net/s "product_ext", 31 0, L_0x96c5b6260;  1 drivers
v0x96d26eb20_0 .net/s "w", 7 0, L_0x96c5b3e80;  1 drivers
v0x96d26ebc0_0 .net/s "x", 7 0, L_0x96c5b3de0;  1 drivers
L_0x96d2af660 .extend/s 16, L_0x96c5b3de0;
L_0x96d2af700 .extend/s 16, L_0x96c5b3e80;
L_0x96d2af7a0 .arith/mult 16, L_0x96d2af660, L_0x96d2af700;
L_0x96c5b3d40 .part L_0x96d2af7a0, 15, 1;
L_0x96d2af840 .repeat 16, 16, L_0x96c5b3d40;
L_0x96c5b6260 .concat [ 16 16 0 0], L_0x96d2af7a0, L_0x96d2af840;
L_0x96c5b6300 .arith/sum 32, L_0x96c855528, L_0x96c5b6260;
S_0x96d270180 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 4 34, 4 34 0, S_0x100fcf810;
 .timescale 0 0;
P_0x96c584d80 .param/l "n" 1 4 34, +C4<010>;
S_0x96d270300 .scope module, "u_neuron" "neuron_parallel" 4 41, 5 1 0, S_0x96d270180;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "start";
    .port_info 3 /INPUT 2048 "x_bus";
    .port_info 4 /INPUT 2048 "w_bus";
    .port_info 5 /INPUT 8 "bias";
    .port_info 6 /OUTPUT 8 "y";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "done";
P_0x96d270480 .param/l "ACC_WIDTH" 0 5 5, +C4<00000000000000000000000000100000>;
P_0x96d2704c0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
P_0x96d270500 .param/l "GROUPS" 1 5 20, +C4<00000000000000000000000000001000>;
P_0x96d270540 .param/l "GROUP_INDEX_WIDTH" 1 5 21, +C4<00000000000000000000000000000011>;
P_0x96d270580 .param/l "N_INPUTS" 0 5 3, +C4<00000000000000000000000100000000>;
P_0x96d2705c0 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000100000>;
v0x96d2890e0_0 .net *"_ivl_0", 31 0, L_0x96c5b6580;  1 drivers
v0x96d289180_0 .net *"_ivl_11", 31 0, L_0x96d2afa20;  1 drivers
v0x96d289220_0 .net *"_ivl_14", 31 0, L_0x96c5b6620;  1 drivers
L_0x96c855648 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2892c0_0 .net *"_ivl_17", 28 0, L_0x96c855648;  1 drivers
L_0x96c855690 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d289360_0 .net/2u *"_ivl_18", 31 0, L_0x96c855690;  1 drivers
v0x96d289400_0 .net *"_ivl_21", 31 0, L_0x96d2afac0;  1 drivers
L_0x96c8556d8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d2894a0_0 .net/2u *"_ivl_22", 31 0, L_0x96c8556d8;  1 drivers
v0x96d289540_0 .net *"_ivl_25", 31 0, L_0x96d2afb60;  1 drivers
v0x96d2895e0_0 .net *"_ivl_29", 0 0, L_0x96c5bfe80;  1 drivers
L_0x96c855570 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d289680_0 .net *"_ivl_3", 28 0, L_0x96c855570;  1 drivers
v0x96d289720_0 .net *"_ivl_31", 23 0, L_0x96d2b4be0;  1 drivers
L_0x96c8555b8 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d2897c0_0 .net/2u *"_ivl_4", 31 0, L_0x96c8555b8;  1 drivers
v0x96d289860_0 .net *"_ivl_7", 31 0, L_0x96d2af980;  1 drivers
L_0x96c855600 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d289900_0 .net/2u *"_ivl_8", 31 0, L_0x96c855600;  1 drivers
v0x96d2899a0_0 .var/s "acc", 31 0;
v0x96d289a40_0 .net/s "acc_next", 31 0, L_0x96c5c4f00;  1 drivers
v0x96d289ae0_0 .net/s "bias", 7 0, L_0x96c5cc000;  1 drivers
v0x96d289b80_0 .net/s "bias_ext", 31 0, L_0x96c5c4fa0;  1 drivers
v0x96d289c20_0 .var "busy", 0 0;
v0x96d289cc0_0 .net "clk", 0 0, v0x96d2a4be0_0;  alias, 1 drivers
v0x96d289d60_0 .var "done", 0 0;
v0x96d289e00_0 .net/s "final_acc", 31 0, L_0x96c5c5040;  1 drivers
v0x96d289ea0_0 .var "group_index", 2 0;
v0x96d289f40_0 .net "rst", 0 0, v0x96d2a4f00_0;  alias, 1 drivers
v0x96d289fe0_0 .net "start", 0 0, v0x96d2a4fa0_0;  alias, 1 drivers
v0x96d28a080_0 .net/s "w_bus", 2047 0, L_0x96c5bff20;  1 drivers
v0x96d28a120_0 .net/s "w_group", 255 0, L_0x96c5bc1e0;  1 drivers
v0x96d28a1c0_0 .net/s "x_bus", 2047 0, v0x96d2a50e0_0;  alias, 1 drivers
v0x96d28a260_0 .net/s "x_group", 255 0, L_0x96c5bc140;  1 drivers
v0x96d28a300_0 .var/s "y", 7 0;
L_0x96c5b6580 .concat [ 3 29 0 0], v0x96d289ea0_0, L_0x96c855570;
L_0x96d2af980 .arith/mult 32, L_0x96c5b6580, L_0x96c8555b8;
L_0x96d2afa20 .arith/mult 32, L_0x96d2af980, L_0x96c855600;
L_0x96c5bc140 .part/v v0x96d2a50e0_0, L_0x96d2afa20, 256;
L_0x96c5b6620 .concat [ 3 29 0 0], v0x96d289ea0_0, L_0x96c855648;
L_0x96d2afac0 .arith/mult 32, L_0x96c5b6620, L_0x96c855690;
L_0x96d2afb60 .arith/mult 32, L_0x96d2afac0, L_0x96c8556d8;
L_0x96c5bc1e0 .part/v L_0x96c5bff20, L_0x96d2afb60, 256;
L_0x96c5bfe80 .part L_0x96c5cc000, 7, 1;
L_0x96d2b4be0 .repeat 24, 24, L_0x96c5bfe80;
L_0x96c5c4fa0 .concat [ 8 24 0 0], L_0x96c5cc000, L_0x96d2b4be0;
L_0x96c5c5040 .arith/sum 32, L_0x96c5c4f00, L_0x96c5c4fa0;
S_0x96d270600 .scope module, "u_mac8" "mac8" 5 52, 6 1 0, S_0x96d270300;
 .timescale 0 0;
    .port_info 0 /INPUT 256 "x_bus";
    .port_info 1 /INPUT 256 "w_bus";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ed00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
P_0x96c57ed40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
P_0x96c57ed80 .param/l "PARALLEL" 0 6 4, +C4<00000000000000000000000000100000>;
v0x96d288c80_0 .net/s "acc_in", 31 0, v0x96d2899a0_0;  1 drivers
v0x96d288d20_0 .net/s "acc_out", 31 0, L_0x96c5c4f00;  alias, 1 drivers
v0x96d288dc0_0 .var/i "j", 31 0;
v0x96d288e60 .array "products", 31 0;
v0x96d288e60_0 .net/s v0x96d288e60 0, 31 0, L_0x96c5b6760; 1 drivers
v0x96d288e60_1 .net/s v0x96d288e60 1, 31 0, L_0x96c5b68a0; 1 drivers
v0x96d288e60_2 .net/s v0x96d288e60 2, 31 0, L_0x96c5b69e0; 1 drivers
v0x96d288e60_3 .net/s v0x96d288e60 3, 31 0, L_0x96c5b6b20; 1 drivers
v0x96d288e60_4 .net/s v0x96d288e60 4, 31 0, L_0x96c5b6c60; 1 drivers
v0x96d288e60_5 .net/s v0x96d288e60 5, 31 0, L_0x96c5b6da0; 1 drivers
v0x96d288e60_6 .net/s v0x96d288e60 6, 31 0, L_0x96c5b6ee0; 1 drivers
v0x96d288e60_7 .net/s v0x96d288e60 7, 31 0, L_0x96c5b7020; 1 drivers
v0x96d288e60_8 .net/s v0x96d288e60 8, 31 0, L_0x96c5b7160; 1 drivers
v0x96d288e60_9 .net/s v0x96d288e60 9, 31 0, L_0x96c5b72a0; 1 drivers
v0x96d288e60_10 .net/s v0x96d288e60 10, 31 0, L_0x96c5b73e0; 1 drivers
v0x96d288e60_11 .net/s v0x96d288e60 11, 31 0, L_0x96c5b7520; 1 drivers
v0x96d288e60_12 .net/s v0x96d288e60 12, 31 0, L_0x96c5b7660; 1 drivers
v0x96d288e60_13 .net/s v0x96d288e60 13, 31 0, L_0x96c5b77a0; 1 drivers
v0x96d288e60_14 .net/s v0x96d288e60 14, 31 0, L_0x96c5b78e0; 1 drivers
v0x96d288e60_15 .net/s v0x96d288e60 15, 31 0, L_0x96c5b7a20; 1 drivers
v0x96d288e60_16 .net/s v0x96d288e60 16, 31 0, L_0x96c5b7b60; 1 drivers
v0x96d288e60_17 .net/s v0x96d288e60 17, 31 0, L_0x96c5b7ca0; 1 drivers
v0x96d288e60_18 .net/s v0x96d288e60 18, 31 0, L_0x96c5b7de0; 1 drivers
v0x96d288e60_19 .net/s v0x96d288e60 19, 31 0, L_0x96c5b7f20; 1 drivers
v0x96d288e60_20 .net/s v0x96d288e60 20, 31 0, L_0x96c5c40a0; 1 drivers
v0x96d288e60_21 .net/s v0x96d288e60 21, 31 0, L_0x96c5c41e0; 1 drivers
v0x96d288e60_22 .net/s v0x96d288e60 22, 31 0, L_0x96c5c4320; 1 drivers
v0x96d288e60_23 .net/s v0x96d288e60 23, 31 0, L_0x96c5c4460; 1 drivers
v0x96d288e60_24 .net/s v0x96d288e60 24, 31 0, L_0x96c5c45a0; 1 drivers
v0x96d288e60_25 .net/s v0x96d288e60 25, 31 0, L_0x96c5c46e0; 1 drivers
v0x96d288e60_26 .net/s v0x96d288e60 26, 31 0, L_0x96c5c4820; 1 drivers
v0x96d288e60_27 .net/s v0x96d288e60 27, 31 0, L_0x96c5c4960; 1 drivers
v0x96d288e60_28 .net/s v0x96d288e60 28, 31 0, L_0x96c5c4aa0; 1 drivers
v0x96d288e60_29 .net/s v0x96d288e60 29, 31 0, L_0x96c5c4be0; 1 drivers
v0x96d288e60_30 .net/s v0x96d288e60 30, 31 0, L_0x96c5c4d20; 1 drivers
v0x96d288e60_31 .net/s v0x96d288e60 31, 31 0, L_0x96c5c4e60; 1 drivers
v0x96d288f00_0 .var/s "sum", 31 0;
v0x96d288fa0_0 .net/s "w_bus", 255 0, L_0x96c5bc1e0;  alias, 1 drivers
v0x96d289040_0 .net/s "x_bus", 255 0, L_0x96c5bc140;  alias, 1 drivers
E_0x96d18bd00/0 .event anyedge, v0x96d288f00_0, v0x96d2746e0_0, v0x96d274d20_0, v0x96d275360_0;
E_0x96d18bd00/1 .event anyedge, v0x96d2759a0_0, v0x96d275fe0_0, v0x96d276620_0, v0x96d276c60_0;
E_0x96d18bd00/2 .event anyedge, v0x96d2772a0_0, v0x96d2778e0_0, v0x96d277f20_0, v0x96d2785a0_0;
E_0x96d18bd00/3 .event anyedge, v0x96d278be0_0, v0x96d279220_0, v0x96d279860_0, v0x96d279ea0_0;
E_0x96d18bd00/4 .event anyedge, v0x96d27a4e0_0, v0x96d27ab20_0, v0x96d27b160_0, v0x96d27b7a0_0;
E_0x96d18bd00/5 .event anyedge, v0x96d27bde0_0, v0x96d280460_0, v0x96d280aa0_0, v0x96d2810e0_0;
E_0x96d18bd00/6 .event anyedge, v0x96d281720_0, v0x96d281d60_0, v0x96d2823a0_0, v0x96d2829e0_0;
E_0x96d18bd00/7 .event anyedge, v0x96d283020_0, v0x96d283660_0, v0x96d283ca0_0, v0x96d288320_0;
E_0x96d18bd00/8 .event anyedge, v0x96d288960_0;
E_0x96d18bd00 .event/or E_0x96d18bd00/0, E_0x96d18bd00/1, E_0x96d18bd00/2, E_0x96d18bd00/3, E_0x96d18bd00/4, E_0x96d18bd00/5, E_0x96d18bd00/6, E_0x96d18bd00/7, E_0x96d18bd00/8;
L_0x96c5bc320 .part L_0x96c5bc140, 0, 8;
L_0x96c5bc3c0 .part L_0x96c5bc1e0, 0, 8;
L_0x96c5bc500 .part L_0x96c5bc140, 8, 8;
L_0x96c5bc5a0 .part L_0x96c5bc1e0, 8, 8;
L_0x96c5bc6e0 .part L_0x96c5bc140, 16, 8;
L_0x96c5bc780 .part L_0x96c5bc1e0, 16, 8;
L_0x96c5bc8c0 .part L_0x96c5bc140, 24, 8;
L_0x96c5bc960 .part L_0x96c5bc1e0, 24, 8;
L_0x96c5bcaa0 .part L_0x96c5bc140, 32, 8;
L_0x96c5bcb40 .part L_0x96c5bc1e0, 32, 8;
L_0x96c5bcc80 .part L_0x96c5bc140, 40, 8;
L_0x96c5bcd20 .part L_0x96c5bc1e0, 40, 8;
L_0x96c5bce60 .part L_0x96c5bc140, 48, 8;
L_0x96c5bcf00 .part L_0x96c5bc1e0, 48, 8;
L_0x96c5bd040 .part L_0x96c5bc140, 56, 8;
L_0x96c5bd0e0 .part L_0x96c5bc1e0, 56, 8;
L_0x96c5bd220 .part L_0x96c5bc140, 64, 8;
L_0x96c5bd2c0 .part L_0x96c5bc1e0, 64, 8;
L_0x96c5bd400 .part L_0x96c5bc140, 72, 8;
L_0x96c5bd4a0 .part L_0x96c5bc1e0, 72, 8;
L_0x96c5bd5e0 .part L_0x96c5bc140, 80, 8;
L_0x96c5bd680 .part L_0x96c5bc1e0, 80, 8;
L_0x96c5bd7c0 .part L_0x96c5bc140, 88, 8;
L_0x96c5bd860 .part L_0x96c5bc1e0, 88, 8;
L_0x96c5bd9a0 .part L_0x96c5bc140, 96, 8;
L_0x96c5bda40 .part L_0x96c5bc1e0, 96, 8;
L_0x96c5bdb80 .part L_0x96c5bc140, 104, 8;
L_0x96c5bdc20 .part L_0x96c5bc1e0, 104, 8;
L_0x96c5bdd60 .part L_0x96c5bc140, 112, 8;
L_0x96c5bde00 .part L_0x96c5bc1e0, 112, 8;
L_0x96c5bdf40 .part L_0x96c5bc140, 120, 8;
L_0x96c5bdfe0 .part L_0x96c5bc1e0, 120, 8;
L_0x96c5be120 .part L_0x96c5bc140, 128, 8;
L_0x96c5be1c0 .part L_0x96c5bc1e0, 128, 8;
L_0x96c5be300 .part L_0x96c5bc140, 136, 8;
L_0x96c5be3a0 .part L_0x96c5bc1e0, 136, 8;
L_0x96c5be4e0 .part L_0x96c5bc140, 144, 8;
L_0x96c5be580 .part L_0x96c5bc1e0, 144, 8;
L_0x96c5be6c0 .part L_0x96c5bc140, 152, 8;
L_0x96c5be760 .part L_0x96c5bc1e0, 152, 8;
L_0x96c5be8a0 .part L_0x96c5bc140, 160, 8;
L_0x96c5be940 .part L_0x96c5bc1e0, 160, 8;
L_0x96c5bea80 .part L_0x96c5bc140, 168, 8;
L_0x96c5beb20 .part L_0x96c5bc1e0, 168, 8;
L_0x96c5bec60 .part L_0x96c5bc140, 176, 8;
L_0x96c5bed00 .part L_0x96c5bc1e0, 176, 8;
L_0x96c5bee40 .part L_0x96c5bc140, 184, 8;
L_0x96c5beee0 .part L_0x96c5bc1e0, 184, 8;
L_0x96c5bf020 .part L_0x96c5bc140, 192, 8;
L_0x96c5bf0c0 .part L_0x96c5bc1e0, 192, 8;
L_0x96c5bf200 .part L_0x96c5bc140, 200, 8;
L_0x96c5bf2a0 .part L_0x96c5bc1e0, 200, 8;
L_0x96c5bf3e0 .part L_0x96c5bc140, 208, 8;
L_0x96c5bf480 .part L_0x96c5bc1e0, 208, 8;
L_0x96c5bf5c0 .part L_0x96c5bc140, 216, 8;
L_0x96c5bf660 .part L_0x96c5bc1e0, 216, 8;
L_0x96c5bf7a0 .part L_0x96c5bc140, 224, 8;
L_0x96c5bf840 .part L_0x96c5bc1e0, 224, 8;
L_0x96c5bf980 .part L_0x96c5bc140, 232, 8;
L_0x96c5bfa20 .part L_0x96c5bc1e0, 232, 8;
L_0x96c5bfb60 .part L_0x96c5bc140, 240, 8;
L_0x96c5bfc00 .part L_0x96c5bc1e0, 240, 8;
L_0x96c5bfd40 .part L_0x96c5bc140, 248, 8;
L_0x96c5bfde0 .part L_0x96c5bc1e0, 248, 8;
L_0x96c5c4f00 .arith/sum 32, v0x96d2899a0_0, v0x96d288f00_0;
S_0x96d270780 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584dc0 .param/l "i" 1 6 17, +C4<00>;
S_0x96d270900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d270780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57edc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ee00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ee40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2743c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2afc00;  1 drivers
v0x96d274460_0 .net/s *"_ivl_2", 15 0, L_0x96d2afca0;  1 drivers
v0x96d274500_0 .net *"_ivl_7", 0 0, L_0x96c5bc280;  1 drivers
v0x96d2745a0_0 .net *"_ivl_9", 15 0, L_0x96d2afde0;  1 drivers
L_0x96c855720 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d274640_0 .net/s "acc_in", 31 0, L_0x96c855720;  1 drivers
v0x96d2746e0_0 .net/s "acc_out", 31 0, L_0x96c5b6760;  alias, 1 drivers
v0x96d274780_0 .net/s "product", 15 0, L_0x96d2afd40;  1 drivers
v0x96d274820_0 .net/s "product_ext", 31 0, L_0x96c5b66c0;  1 drivers
v0x96d2748c0_0 .net/s "w", 7 0, L_0x96c5bc3c0;  1 drivers
v0x96d274960_0 .net/s "x", 7 0, L_0x96c5bc320;  1 drivers
L_0x96d2afc00 .extend/s 16, L_0x96c5bc320;
L_0x96d2afca0 .extend/s 16, L_0x96c5bc3c0;
L_0x96d2afd40 .arith/mult 16, L_0x96d2afc00, L_0x96d2afca0;
L_0x96c5bc280 .part L_0x96d2afd40, 15, 1;
L_0x96d2afde0 .repeat 16, 16, L_0x96c5bc280;
L_0x96c5b66c0 .concat [ 16 16 0 0], L_0x96d2afd40, L_0x96d2afde0;
L_0x96c5b6760 .arith/sum 32, L_0x96c855720, L_0x96c5b66c0;
S_0x96d270a80 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584e00 .param/l "i" 1 6 17, +C4<01>;
S_0x96d270c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d270a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ee80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57eec0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ef00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d274a00_0 .net/s *"_ivl_0", 15 0, L_0x96d2afe80;  1 drivers
v0x96d274aa0_0 .net/s *"_ivl_2", 15 0, L_0x96d2aff20;  1 drivers
v0x96d274b40_0 .net *"_ivl_7", 0 0, L_0x96c5bc460;  1 drivers
v0x96d274be0_0 .net *"_ivl_9", 15 0, L_0x96d2b0000;  1 drivers
L_0x96c855768 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d274c80_0 .net/s "acc_in", 31 0, L_0x96c855768;  1 drivers
v0x96d274d20_0 .net/s "acc_out", 31 0, L_0x96c5b68a0;  alias, 1 drivers
v0x96d274dc0_0 .net/s "product", 15 0, L_0x96d2abe80;  1 drivers
v0x96d274e60_0 .net/s "product_ext", 31 0, L_0x96c5b6800;  1 drivers
v0x96d274f00_0 .net/s "w", 7 0, L_0x96c5bc5a0;  1 drivers
v0x96d274fa0_0 .net/s "x", 7 0, L_0x96c5bc500;  1 drivers
L_0x96d2afe80 .extend/s 16, L_0x96c5bc500;
L_0x96d2aff20 .extend/s 16, L_0x96c5bc5a0;
L_0x96d2abe80 .arith/mult 16, L_0x96d2afe80, L_0x96d2aff20;
L_0x96c5bc460 .part L_0x96d2abe80, 15, 1;
L_0x96d2b0000 .repeat 16, 16, L_0x96c5bc460;
L_0x96c5b6800 .concat [ 16 16 0 0], L_0x96d2abe80, L_0x96d2b0000;
L_0x96c5b68a0 .arith/sum 32, L_0x96c855768, L_0x96c5b6800;
S_0x96d270d80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584e40 .param/l "i" 1 6 17, +C4<010>;
S_0x96d270f00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d270d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ef40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ef80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57efc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d275040_0 .net/s *"_ivl_0", 15 0, L_0x96d2b00a0;  1 drivers
v0x96d2750e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b0140;  1 drivers
v0x96d275180_0 .net *"_ivl_7", 0 0, L_0x96c5bc640;  1 drivers
v0x96d275220_0 .net *"_ivl_9", 15 0, L_0x96d2b0280;  1 drivers
L_0x96c8557b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2752c0_0 .net/s "acc_in", 31 0, L_0x96c8557b0;  1 drivers
v0x96d275360_0 .net/s "acc_out", 31 0, L_0x96c5b69e0;  alias, 1 drivers
v0x96d275400_0 .net/s "product", 15 0, L_0x96d2b01e0;  1 drivers
v0x96d2754a0_0 .net/s "product_ext", 31 0, L_0x96c5b6940;  1 drivers
v0x96d275540_0 .net/s "w", 7 0, L_0x96c5bc780;  1 drivers
v0x96d2755e0_0 .net/s "x", 7 0, L_0x96c5bc6e0;  1 drivers
L_0x96d2b00a0 .extend/s 16, L_0x96c5bc6e0;
L_0x96d2b0140 .extend/s 16, L_0x96c5bc780;
L_0x96d2b01e0 .arith/mult 16, L_0x96d2b00a0, L_0x96d2b0140;
L_0x96c5bc640 .part L_0x96d2b01e0, 15, 1;
L_0x96d2b0280 .repeat 16, 16, L_0x96c5bc640;
L_0x96c5b6940 .concat [ 16 16 0 0], L_0x96d2b01e0, L_0x96d2b0280;
L_0x96c5b69e0 .arith/sum 32, L_0x96c8557b0, L_0x96c5b6940;
S_0x96d271080 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584e80 .param/l "i" 1 6 17, +C4<011>;
S_0x96d271200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f000 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f040 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f080 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d275680_0 .net/s *"_ivl_0", 15 0, L_0x96d2b0320;  1 drivers
v0x96d275720_0 .net/s *"_ivl_2", 15 0, L_0x96d2b03c0;  1 drivers
v0x96d2757c0_0 .net *"_ivl_7", 0 0, L_0x96c5bc820;  1 drivers
v0x96d275860_0 .net *"_ivl_9", 15 0, L_0x96d2b0500;  1 drivers
L_0x96c8557f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d275900_0 .net/s "acc_in", 31 0, L_0x96c8557f8;  1 drivers
v0x96d2759a0_0 .net/s "acc_out", 31 0, L_0x96c5b6b20;  alias, 1 drivers
v0x96d275a40_0 .net/s "product", 15 0, L_0x96d2b0460;  1 drivers
v0x96d275ae0_0 .net/s "product_ext", 31 0, L_0x96c5b6a80;  1 drivers
v0x96d275b80_0 .net/s "w", 7 0, L_0x96c5bc960;  1 drivers
v0x96d275c20_0 .net/s "x", 7 0, L_0x96c5bc8c0;  1 drivers
L_0x96d2b0320 .extend/s 16, L_0x96c5bc8c0;
L_0x96d2b03c0 .extend/s 16, L_0x96c5bc960;
L_0x96d2b0460 .arith/mult 16, L_0x96d2b0320, L_0x96d2b03c0;
L_0x96c5bc820 .part L_0x96d2b0460, 15, 1;
L_0x96d2b0500 .repeat 16, 16, L_0x96c5bc820;
L_0x96c5b6a80 .concat [ 16 16 0 0], L_0x96d2b0460, L_0x96d2b0500;
L_0x96c5b6b20 .arith/sum 32, L_0x96c8557f8, L_0x96c5b6a80;
S_0x96d271380 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584ec0 .param/l "i" 1 6 17, +C4<0100>;
S_0x96d271500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f0c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d275cc0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b05a0;  1 drivers
v0x96d275d60_0 .net/s *"_ivl_2", 15 0, L_0x96d2b0640;  1 drivers
v0x96d275e00_0 .net *"_ivl_7", 0 0, L_0x96c5bca00;  1 drivers
v0x96d275ea0_0 .net *"_ivl_9", 15 0, L_0x96d2b0780;  1 drivers
L_0x96c855840 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d275f40_0 .net/s "acc_in", 31 0, L_0x96c855840;  1 drivers
v0x96d275fe0_0 .net/s "acc_out", 31 0, L_0x96c5b6c60;  alias, 1 drivers
v0x96d276080_0 .net/s "product", 15 0, L_0x96d2b06e0;  1 drivers
v0x96d276120_0 .net/s "product_ext", 31 0, L_0x96c5b6bc0;  1 drivers
v0x96d2761c0_0 .net/s "w", 7 0, L_0x96c5bcb40;  1 drivers
v0x96d276260_0 .net/s "x", 7 0, L_0x96c5bcaa0;  1 drivers
L_0x96d2b05a0 .extend/s 16, L_0x96c5bcaa0;
L_0x96d2b0640 .extend/s 16, L_0x96c5bcb40;
L_0x96d2b06e0 .arith/mult 16, L_0x96d2b05a0, L_0x96d2b0640;
L_0x96c5bca00 .part L_0x96d2b06e0, 15, 1;
L_0x96d2b0780 .repeat 16, 16, L_0x96c5bca00;
L_0x96c5b6bc0 .concat [ 16 16 0 0], L_0x96d2b06e0, L_0x96d2b0780;
L_0x96c5b6c60 .arith/sum 32, L_0x96c855840, L_0x96c5b6bc0;
S_0x96d271680 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584f00 .param/l "i" 1 6 17, +C4<0101>;
S_0x96d271800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f1c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d276300_0 .net/s *"_ivl_0", 15 0, L_0x96d2b0820;  1 drivers
v0x96d2763a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b08c0;  1 drivers
v0x96d276440_0 .net *"_ivl_7", 0 0, L_0x96c5bcbe0;  1 drivers
v0x96d2764e0_0 .net *"_ivl_9", 15 0, L_0x96d2b0a00;  1 drivers
L_0x96c855888 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d276580_0 .net/s "acc_in", 31 0, L_0x96c855888;  1 drivers
v0x96d276620_0 .net/s "acc_out", 31 0, L_0x96c5b6da0;  alias, 1 drivers
v0x96d2766c0_0 .net/s "product", 15 0, L_0x96d2b0960;  1 drivers
v0x96d276760_0 .net/s "product_ext", 31 0, L_0x96c5b6d00;  1 drivers
v0x96d276800_0 .net/s "w", 7 0, L_0x96c5bcd20;  1 drivers
v0x96d2768a0_0 .net/s "x", 7 0, L_0x96c5bcc80;  1 drivers
L_0x96d2b0820 .extend/s 16, L_0x96c5bcc80;
L_0x96d2b08c0 .extend/s 16, L_0x96c5bcd20;
L_0x96d2b0960 .arith/mult 16, L_0x96d2b0820, L_0x96d2b08c0;
L_0x96c5bcbe0 .part L_0x96d2b0960, 15, 1;
L_0x96d2b0a00 .repeat 16, 16, L_0x96c5bcbe0;
L_0x96c5b6d00 .concat [ 16 16 0 0], L_0x96d2b0960, L_0x96d2b0a00;
L_0x96c5b6da0 .arith/sum 32, L_0x96c855888, L_0x96c5b6d00;
S_0x96d271980 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584f40 .param/l "i" 1 6 17, +C4<0110>;
S_0x96d271b00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271980;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f2c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d276940_0 .net/s *"_ivl_0", 15 0, L_0x96d2b0aa0;  1 drivers
v0x96d2769e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b0b40;  1 drivers
v0x96d276a80_0 .net *"_ivl_7", 0 0, L_0x96c5bcdc0;  1 drivers
v0x96d276b20_0 .net *"_ivl_9", 15 0, L_0x96d2b0c80;  1 drivers
L_0x96c8558d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d276bc0_0 .net/s "acc_in", 31 0, L_0x96c8558d0;  1 drivers
v0x96d276c60_0 .net/s "acc_out", 31 0, L_0x96c5b6ee0;  alias, 1 drivers
v0x96d276d00_0 .net/s "product", 15 0, L_0x96d2b0be0;  1 drivers
v0x96d276da0_0 .net/s "product_ext", 31 0, L_0x96c5b6e40;  1 drivers
v0x96d276e40_0 .net/s "w", 7 0, L_0x96c5bcf00;  1 drivers
v0x96d276ee0_0 .net/s "x", 7 0, L_0x96c5bce60;  1 drivers
L_0x96d2b0aa0 .extend/s 16, L_0x96c5bce60;
L_0x96d2b0b40 .extend/s 16, L_0x96c5bcf00;
L_0x96d2b0be0 .arith/mult 16, L_0x96d2b0aa0, L_0x96d2b0b40;
L_0x96c5bcdc0 .part L_0x96d2b0be0, 15, 1;
L_0x96d2b0c80 .repeat 16, 16, L_0x96c5bcdc0;
L_0x96c5b6e40 .concat [ 16 16 0 0], L_0x96d2b0be0, L_0x96d2b0c80;
L_0x96c5b6ee0 .arith/sum 32, L_0x96c8558d0, L_0x96c5b6e40;
S_0x96d271c80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584f80 .param/l "i" 1 6 17, +C4<0111>;
S_0x96d271e00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271c80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d276f80_0 .net/s *"_ivl_0", 15 0, L_0x96d2b0d20;  1 drivers
v0x96d277020_0 .net/s *"_ivl_2", 15 0, L_0x96d2b0dc0;  1 drivers
v0x96d2770c0_0 .net *"_ivl_7", 0 0, L_0x96c5bcfa0;  1 drivers
v0x96d277160_0 .net *"_ivl_9", 15 0, L_0x96d2b0f00;  1 drivers
L_0x96c855918 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d277200_0 .net/s "acc_in", 31 0, L_0x96c855918;  1 drivers
v0x96d2772a0_0 .net/s "acc_out", 31 0, L_0x96c5b7020;  alias, 1 drivers
v0x96d277340_0 .net/s "product", 15 0, L_0x96d2b0e60;  1 drivers
v0x96d2773e0_0 .net/s "product_ext", 31 0, L_0x96c5b6f80;  1 drivers
v0x96d277480_0 .net/s "w", 7 0, L_0x96c5bd0e0;  1 drivers
v0x96d277520_0 .net/s "x", 7 0, L_0x96c5bd040;  1 drivers
L_0x96d2b0d20 .extend/s 16, L_0x96c5bd040;
L_0x96d2b0dc0 .extend/s 16, L_0x96c5bd0e0;
L_0x96d2b0e60 .arith/mult 16, L_0x96d2b0d20, L_0x96d2b0dc0;
L_0x96c5bcfa0 .part L_0x96d2b0e60, 15, 1;
L_0x96d2b0f00 .repeat 16, 16, L_0x96c5bcfa0;
L_0x96c5b6f80 .concat [ 16 16 0 0], L_0x96d2b0e60, L_0x96d2b0f00;
L_0x96c5b7020 .arith/sum 32, L_0x96c855918, L_0x96c5b6f80;
S_0x96d271f80 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c584fc0 .param/l "i" 1 6 17, +C4<01000>;
S_0x96d272100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d271f80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f3c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2775c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b0fa0;  1 drivers
v0x96d277660_0 .net/s *"_ivl_2", 15 0, L_0x96d2b1040;  1 drivers
v0x96d277700_0 .net *"_ivl_7", 0 0, L_0x96c5bd180;  1 drivers
v0x96d2777a0_0 .net *"_ivl_9", 15 0, L_0x96d2b1180;  1 drivers
L_0x96c855960 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d277840_0 .net/s "acc_in", 31 0, L_0x96c855960;  1 drivers
v0x96d2778e0_0 .net/s "acc_out", 31 0, L_0x96c5b7160;  alias, 1 drivers
v0x96d277980_0 .net/s "product", 15 0, L_0x96d2b10e0;  1 drivers
v0x96d277a20_0 .net/s "product_ext", 31 0, L_0x96c5b70c0;  1 drivers
v0x96d277ac0_0 .net/s "w", 7 0, L_0x96c5bd2c0;  1 drivers
v0x96d277b60_0 .net/s "x", 7 0, L_0x96c5bd220;  1 drivers
L_0x96d2b0fa0 .extend/s 16, L_0x96c5bd220;
L_0x96d2b1040 .extend/s 16, L_0x96c5bd2c0;
L_0x96d2b10e0 .arith/mult 16, L_0x96d2b0fa0, L_0x96d2b1040;
L_0x96c5bd180 .part L_0x96d2b10e0, 15, 1;
L_0x96d2b1180 .repeat 16, 16, L_0x96c5bd180;
L_0x96c5b70c0 .concat [ 16 16 0 0], L_0x96d2b10e0, L_0x96d2b1180;
L_0x96c5b7160 .arith/sum 32, L_0x96c855960, L_0x96c5b70c0;
S_0x96d272280 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585000 .param/l "i" 1 6 17, +C4<01001>;
S_0x96d272400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d272280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f4c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d277c00_0 .net/s *"_ivl_0", 15 0, L_0x96d2b12c0;  1 drivers
v0x96d277ca0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b1360;  1 drivers
v0x96d277d40_0 .net *"_ivl_7", 0 0, L_0x96c5bd360;  1 drivers
v0x96d277de0_0 .net *"_ivl_9", 15 0, L_0x96d2b14a0;  1 drivers
L_0x96c8559a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d277e80_0 .net/s "acc_in", 31 0, L_0x96c8559a8;  1 drivers
v0x96d277f20_0 .net/s "acc_out", 31 0, L_0x96c5b72a0;  alias, 1 drivers
v0x96d278000_0 .net/s "product", 15 0, L_0x96d2b1400;  1 drivers
v0x96d2780a0_0 .net/s "product_ext", 31 0, L_0x96c5b7200;  1 drivers
v0x96d278140_0 .net/s "w", 7 0, L_0x96c5bd4a0;  1 drivers
v0x96d2781e0_0 .net/s "x", 7 0, L_0x96c5bd400;  1 drivers
L_0x96d2b12c0 .extend/s 16, L_0x96c5bd400;
L_0x96d2b1360 .extend/s 16, L_0x96c5bd4a0;
L_0x96d2b1400 .arith/mult 16, L_0x96d2b12c0, L_0x96d2b1360;
L_0x96c5bd360 .part L_0x96d2b1400, 15, 1;
L_0x96d2b14a0 .repeat 16, 16, L_0x96c5bd360;
L_0x96c5b7200 .concat [ 16 16 0 0], L_0x96d2b1400, L_0x96d2b14a0;
L_0x96c5b72a0 .arith/sum 32, L_0x96c8559a8, L_0x96c5b7200;
S_0x96d272580 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585040 .param/l "i" 1 6 17, +C4<01010>;
S_0x96d272700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d272580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f5c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d278280_0 .net/s *"_ivl_0", 15 0, L_0x96d2b1540;  1 drivers
v0x96d278320_0 .net/s *"_ivl_2", 15 0, L_0x96d2b15e0;  1 drivers
v0x96d2783c0_0 .net *"_ivl_7", 0 0, L_0x96c5bd540;  1 drivers
v0x96d278460_0 .net *"_ivl_9", 15 0, L_0x96d2b1720;  1 drivers
L_0x96c8559f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d278500_0 .net/s "acc_in", 31 0, L_0x96c8559f0;  1 drivers
v0x96d2785a0_0 .net/s "acc_out", 31 0, L_0x96c5b73e0;  alias, 1 drivers
v0x96d278640_0 .net/s "product", 15 0, L_0x96d2b1680;  1 drivers
v0x96d2786e0_0 .net/s "product_ext", 31 0, L_0x96c5b7340;  1 drivers
v0x96d278780_0 .net/s "w", 7 0, L_0x96c5bd680;  1 drivers
v0x96d278820_0 .net/s "x", 7 0, L_0x96c5bd5e0;  1 drivers
L_0x96d2b1540 .extend/s 16, L_0x96c5bd5e0;
L_0x96d2b15e0 .extend/s 16, L_0x96c5bd680;
L_0x96d2b1680 .arith/mult 16, L_0x96d2b1540, L_0x96d2b15e0;
L_0x96c5bd540 .part L_0x96d2b1680, 15, 1;
L_0x96d2b1720 .repeat 16, 16, L_0x96c5bd540;
L_0x96c5b7340 .concat [ 16 16 0 0], L_0x96d2b1680, L_0x96d2b1720;
L_0x96c5b73e0 .arith/sum 32, L_0x96c8559f0, L_0x96c5b7340;
S_0x96d272880 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585080 .param/l "i" 1 6 17, +C4<01011>;
S_0x96d272a00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d272880;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f600 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f640 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f680 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2788c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b1220;  1 drivers
v0x96d278960_0 .net/s *"_ivl_2", 15 0, L_0x96d2b17c0;  1 drivers
v0x96d278a00_0 .net *"_ivl_7", 0 0, L_0x96c5bd720;  1 drivers
v0x96d278aa0_0 .net *"_ivl_9", 15 0, L_0x96d2b1900;  1 drivers
L_0x96c855a38 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d278b40_0 .net/s "acc_in", 31 0, L_0x96c855a38;  1 drivers
v0x96d278be0_0 .net/s "acc_out", 31 0, L_0x96c5b7520;  alias, 1 drivers
v0x96d278c80_0 .net/s "product", 15 0, L_0x96d2b1860;  1 drivers
v0x96d278d20_0 .net/s "product_ext", 31 0, L_0x96c5b7480;  1 drivers
v0x96d278dc0_0 .net/s "w", 7 0, L_0x96c5bd860;  1 drivers
v0x96d278e60_0 .net/s "x", 7 0, L_0x96c5bd7c0;  1 drivers
L_0x96d2b1220 .extend/s 16, L_0x96c5bd7c0;
L_0x96d2b17c0 .extend/s 16, L_0x96c5bd860;
L_0x96d2b1860 .arith/mult 16, L_0x96d2b1220, L_0x96d2b17c0;
L_0x96c5bd720 .part L_0x96d2b1860, 15, 1;
L_0x96d2b1900 .repeat 16, 16, L_0x96c5bd720;
L_0x96c5b7480 .concat [ 16 16 0 0], L_0x96d2b1860, L_0x96d2b1900;
L_0x96c5b7520 .arith/sum 32, L_0x96c855a38, L_0x96c5b7480;
S_0x96d272b80 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c5850c0 .param/l "i" 1 6 17, +C4<01100>;
S_0x96d272d00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d272b80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f6c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d278f00_0 .net/s *"_ivl_0", 15 0, L_0x96d2b19a0;  1 drivers
v0x96d278fa0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b1a40;  1 drivers
v0x96d279040_0 .net *"_ivl_7", 0 0, L_0x96c5bd900;  1 drivers
v0x96d2790e0_0 .net *"_ivl_9", 15 0, L_0x96d2b1b80;  1 drivers
L_0x96c855a80 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d279180_0 .net/s "acc_in", 31 0, L_0x96c855a80;  1 drivers
v0x96d279220_0 .net/s "acc_out", 31 0, L_0x96c5b7660;  alias, 1 drivers
v0x96d2792c0_0 .net/s "product", 15 0, L_0x96d2b1ae0;  1 drivers
v0x96d279360_0 .net/s "product_ext", 31 0, L_0x96c5b75c0;  1 drivers
v0x96d279400_0 .net/s "w", 7 0, L_0x96c5bda40;  1 drivers
v0x96d2794a0_0 .net/s "x", 7 0, L_0x96c5bd9a0;  1 drivers
L_0x96d2b19a0 .extend/s 16, L_0x96c5bd9a0;
L_0x96d2b1a40 .extend/s 16, L_0x96c5bda40;
L_0x96d2b1ae0 .arith/mult 16, L_0x96d2b19a0, L_0x96d2b1a40;
L_0x96c5bd900 .part L_0x96d2b1ae0, 15, 1;
L_0x96d2b1b80 .repeat 16, 16, L_0x96c5bd900;
L_0x96c5b75c0 .concat [ 16 16 0 0], L_0x96d2b1ae0, L_0x96d2b1b80;
L_0x96c5b7660 .arith/sum 32, L_0x96c855a80, L_0x96c5b75c0;
S_0x96d272e80 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585100 .param/l "i" 1 6 17, +C4<01101>;
S_0x96d273000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d272e80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f7c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d279540_0 .net/s *"_ivl_0", 15 0, L_0x96d2b1c20;  1 drivers
v0x96d2795e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b1cc0;  1 drivers
v0x96d279680_0 .net *"_ivl_7", 0 0, L_0x96c5bdae0;  1 drivers
v0x96d279720_0 .net *"_ivl_9", 15 0, L_0x96d2b1e00;  1 drivers
L_0x96c855ac8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2797c0_0 .net/s "acc_in", 31 0, L_0x96c855ac8;  1 drivers
v0x96d279860_0 .net/s "acc_out", 31 0, L_0x96c5b77a0;  alias, 1 drivers
v0x96d279900_0 .net/s "product", 15 0, L_0x96d2b1d60;  1 drivers
v0x96d2799a0_0 .net/s "product_ext", 31 0, L_0x96c5b7700;  1 drivers
v0x96d279a40_0 .net/s "w", 7 0, L_0x96c5bdc20;  1 drivers
v0x96d279ae0_0 .net/s "x", 7 0, L_0x96c5bdb80;  1 drivers
L_0x96d2b1c20 .extend/s 16, L_0x96c5bdb80;
L_0x96d2b1cc0 .extend/s 16, L_0x96c5bdc20;
L_0x96d2b1d60 .arith/mult 16, L_0x96d2b1c20, L_0x96d2b1cc0;
L_0x96c5bdae0 .part L_0x96d2b1d60, 15, 1;
L_0x96d2b1e00 .repeat 16, 16, L_0x96c5bdae0;
L_0x96c5b7700 .concat [ 16 16 0 0], L_0x96d2b1d60, L_0x96d2b1e00;
L_0x96c5b77a0 .arith/sum 32, L_0x96c855ac8, L_0x96c5b7700;
S_0x96d273180 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585140 .param/l "i" 1 6 17, +C4<01110>;
S_0x96d273300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d273180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f8c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d279b80_0 .net/s *"_ivl_0", 15 0, L_0x96d2b1ea0;  1 drivers
v0x96d279c20_0 .net/s *"_ivl_2", 15 0, L_0x96d2b1f40;  1 drivers
v0x96d279cc0_0 .net *"_ivl_7", 0 0, L_0x96c5bdcc0;  1 drivers
v0x96d279d60_0 .net *"_ivl_9", 15 0, L_0x96d2b2080;  1 drivers
L_0x96c855b10 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d279e00_0 .net/s "acc_in", 31 0, L_0x96c855b10;  1 drivers
v0x96d279ea0_0 .net/s "acc_out", 31 0, L_0x96c5b78e0;  alias, 1 drivers
v0x96d279f40_0 .net/s "product", 15 0, L_0x96d2b1fe0;  1 drivers
v0x96d279fe0_0 .net/s "product_ext", 31 0, L_0x96c5b7840;  1 drivers
v0x96d27a080_0 .net/s "w", 7 0, L_0x96c5bde00;  1 drivers
v0x96d27a120_0 .net/s "x", 7 0, L_0x96c5bdd60;  1 drivers
L_0x96d2b1ea0 .extend/s 16, L_0x96c5bdd60;
L_0x96d2b1f40 .extend/s 16, L_0x96c5bde00;
L_0x96d2b1fe0 .arith/mult 16, L_0x96d2b1ea0, L_0x96d2b1f40;
L_0x96c5bdcc0 .part L_0x96d2b1fe0, 15, 1;
L_0x96d2b2080 .repeat 16, 16, L_0x96c5bdcc0;
L_0x96c5b7840 .concat [ 16 16 0 0], L_0x96d2b1fe0, L_0x96d2b2080;
L_0x96c5b78e0 .arith/sum 32, L_0x96c855b10, L_0x96c5b7840;
S_0x96d273480 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585180 .param/l "i" 1 6 17, +C4<01111>;
S_0x96d273600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d273480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57f940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57f980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d27a1c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b2120;  1 drivers
v0x96d27a260_0 .net/s *"_ivl_2", 15 0, L_0x96d2b21c0;  1 drivers
v0x96d27a300_0 .net *"_ivl_7", 0 0, L_0x96c5bdea0;  1 drivers
v0x96d27a3a0_0 .net *"_ivl_9", 15 0, L_0x96d2b2300;  1 drivers
L_0x96c855b58 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d27a440_0 .net/s "acc_in", 31 0, L_0x96c855b58;  1 drivers
v0x96d27a4e0_0 .net/s "acc_out", 31 0, L_0x96c5b7a20;  alias, 1 drivers
v0x96d27a580_0 .net/s "product", 15 0, L_0x96d2b2260;  1 drivers
v0x96d27a620_0 .net/s "product_ext", 31 0, L_0x96c5b7980;  1 drivers
v0x96d27a6c0_0 .net/s "w", 7 0, L_0x96c5bdfe0;  1 drivers
v0x96d27a760_0 .net/s "x", 7 0, L_0x96c5bdf40;  1 drivers
L_0x96d2b2120 .extend/s 16, L_0x96c5bdf40;
L_0x96d2b21c0 .extend/s 16, L_0x96c5bdfe0;
L_0x96d2b2260 .arith/mult 16, L_0x96d2b2120, L_0x96d2b21c0;
L_0x96c5bdea0 .part L_0x96d2b2260, 15, 1;
L_0x96d2b2300 .repeat 16, 16, L_0x96c5bdea0;
L_0x96c5b7980 .concat [ 16 16 0 0], L_0x96d2b2260, L_0x96d2b2300;
L_0x96c5b7a20 .arith/sum 32, L_0x96c855b58, L_0x96c5b7980;
S_0x96d273780 .scope generate, "GEN_MAC[16]" "GEN_MAC[16]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c5851c0 .param/l "i" 1 6 17, +C4<010000>;
S_0x96d273900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d273780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57f9c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fa00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fa40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d27a800_0 .net/s *"_ivl_0", 15 0, L_0x96d2b23a0;  1 drivers
v0x96d27a8a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b2440;  1 drivers
v0x96d27a940_0 .net *"_ivl_7", 0 0, L_0x96c5be080;  1 drivers
v0x96d27a9e0_0 .net *"_ivl_9", 15 0, L_0x96d2b2580;  1 drivers
L_0x96c855ba0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d27aa80_0 .net/s "acc_in", 31 0, L_0x96c855ba0;  1 drivers
v0x96d27ab20_0 .net/s "acc_out", 31 0, L_0x96c5b7b60;  alias, 1 drivers
v0x96d27abc0_0 .net/s "product", 15 0, L_0x96d2b24e0;  1 drivers
v0x96d27ac60_0 .net/s "product_ext", 31 0, L_0x96c5b7ac0;  1 drivers
v0x96d27ad00_0 .net/s "w", 7 0, L_0x96c5be1c0;  1 drivers
v0x96d27ada0_0 .net/s "x", 7 0, L_0x96c5be120;  1 drivers
L_0x96d2b23a0 .extend/s 16, L_0x96c5be120;
L_0x96d2b2440 .extend/s 16, L_0x96c5be1c0;
L_0x96d2b24e0 .arith/mult 16, L_0x96d2b23a0, L_0x96d2b2440;
L_0x96c5be080 .part L_0x96d2b24e0, 15, 1;
L_0x96d2b2580 .repeat 16, 16, L_0x96c5be080;
L_0x96c5b7ac0 .concat [ 16 16 0 0], L_0x96d2b24e0, L_0x96d2b2580;
L_0x96c5b7b60 .arith/sum 32, L_0x96c855ba0, L_0x96c5b7ac0;
S_0x96d273a80 .scope generate, "GEN_MAC[17]" "GEN_MAC[17]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585200 .param/l "i" 1 6 17, +C4<010001>;
S_0x96d273c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d273a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fa80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fb00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d27ae40_0 .net/s *"_ivl_0", 15 0, L_0x96d2b2620;  1 drivers
v0x96d27aee0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b26c0;  1 drivers
v0x96d27af80_0 .net *"_ivl_7", 0 0, L_0x96c5be260;  1 drivers
v0x96d27b020_0 .net *"_ivl_9", 15 0, L_0x96d2b2800;  1 drivers
L_0x96c855be8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d27b0c0_0 .net/s "acc_in", 31 0, L_0x96c855be8;  1 drivers
v0x96d27b160_0 .net/s "acc_out", 31 0, L_0x96c5b7ca0;  alias, 1 drivers
v0x96d27b200_0 .net/s "product", 15 0, L_0x96d2b2760;  1 drivers
v0x96d27b2a0_0 .net/s "product_ext", 31 0, L_0x96c5b7c00;  1 drivers
v0x96d27b340_0 .net/s "w", 7 0, L_0x96c5be3a0;  1 drivers
v0x96d27b3e0_0 .net/s "x", 7 0, L_0x96c5be300;  1 drivers
L_0x96d2b2620 .extend/s 16, L_0x96c5be300;
L_0x96d2b26c0 .extend/s 16, L_0x96c5be3a0;
L_0x96d2b2760 .arith/mult 16, L_0x96d2b2620, L_0x96d2b26c0;
L_0x96c5be260 .part L_0x96d2b2760, 15, 1;
L_0x96d2b2800 .repeat 16, 16, L_0x96c5be260;
L_0x96c5b7c00 .concat [ 16 16 0 0], L_0x96d2b2760, L_0x96d2b2800;
L_0x96c5b7ca0 .arith/sum 32, L_0x96c855be8, L_0x96c5b7c00;
S_0x96d273d80 .scope generate, "GEN_MAC[18]" "GEN_MAC[18]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585240 .param/l "i" 1 6 17, +C4<010010>;
S_0x96d27c000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d273d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fb40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fb80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fbc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d27b480_0 .net/s *"_ivl_0", 15 0, L_0x96d2b28a0;  1 drivers
v0x96d27b520_0 .net/s *"_ivl_2", 15 0, L_0x96d2b2940;  1 drivers
v0x96d27b5c0_0 .net *"_ivl_7", 0 0, L_0x96c5be440;  1 drivers
v0x96d27b660_0 .net *"_ivl_9", 15 0, L_0x96d2b2a80;  1 drivers
L_0x96c855c30 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d27b700_0 .net/s "acc_in", 31 0, L_0x96c855c30;  1 drivers
v0x96d27b7a0_0 .net/s "acc_out", 31 0, L_0x96c5b7de0;  alias, 1 drivers
v0x96d27b840_0 .net/s "product", 15 0, L_0x96d2b29e0;  1 drivers
v0x96d27b8e0_0 .net/s "product_ext", 31 0, L_0x96c5b7d40;  1 drivers
v0x96d27b980_0 .net/s "w", 7 0, L_0x96c5be580;  1 drivers
v0x96d27ba20_0 .net/s "x", 7 0, L_0x96c5be4e0;  1 drivers
L_0x96d2b28a0 .extend/s 16, L_0x96c5be4e0;
L_0x96d2b2940 .extend/s 16, L_0x96c5be580;
L_0x96d2b29e0 .arith/mult 16, L_0x96d2b28a0, L_0x96d2b2940;
L_0x96c5be440 .part L_0x96d2b29e0, 15, 1;
L_0x96d2b2a80 .repeat 16, 16, L_0x96c5be440;
L_0x96c5b7d40 .concat [ 16 16 0 0], L_0x96d2b29e0, L_0x96d2b2a80;
L_0x96c5b7de0 .arith/sum 32, L_0x96c855c30, L_0x96c5b7d40;
S_0x96d27c180 .scope generate, "GEN_MAC[19]" "GEN_MAC[19]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585280 .param/l "i" 1 6 17, +C4<010011>;
S_0x96d27c300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27c180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fc00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fc40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fc80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d27bac0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b2b20;  1 drivers
v0x96d27bb60_0 .net/s *"_ivl_2", 15 0, L_0x96d2b2bc0;  1 drivers
v0x96d27bc00_0 .net *"_ivl_7", 0 0, L_0x96c5be620;  1 drivers
v0x96d27bca0_0 .net *"_ivl_9", 15 0, L_0x96d2b2d00;  1 drivers
L_0x96c855c78 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d27bd40_0 .net/s "acc_in", 31 0, L_0x96c855c78;  1 drivers
v0x96d27bde0_0 .net/s "acc_out", 31 0, L_0x96c5b7f20;  alias, 1 drivers
v0x96d27be80_0 .net/s "product", 15 0, L_0x96d2b2c60;  1 drivers
v0x96d27bf20_0 .net/s "product_ext", 31 0, L_0x96c5b7e80;  1 drivers
v0x96d280000_0 .net/s "w", 7 0, L_0x96c5be760;  1 drivers
v0x96d2800a0_0 .net/s "x", 7 0, L_0x96c5be6c0;  1 drivers
L_0x96d2b2b20 .extend/s 16, L_0x96c5be6c0;
L_0x96d2b2bc0 .extend/s 16, L_0x96c5be760;
L_0x96d2b2c60 .arith/mult 16, L_0x96d2b2b20, L_0x96d2b2bc0;
L_0x96c5be620 .part L_0x96d2b2c60, 15, 1;
L_0x96d2b2d00 .repeat 16, 16, L_0x96c5be620;
L_0x96c5b7e80 .concat [ 16 16 0 0], L_0x96d2b2c60, L_0x96d2b2d00;
L_0x96c5b7f20 .arith/sum 32, L_0x96c855c78, L_0x96c5b7e80;
S_0x96d27c480 .scope generate, "GEN_MAC[20]" "GEN_MAC[20]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c5852c0 .param/l "i" 1 6 17, +C4<010100>;
S_0x96d27c600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27c480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fcc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fd00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fd40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d280140_0 .net/s *"_ivl_0", 15 0, L_0x96d2b2da0;  1 drivers
v0x96d2801e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b2e40;  1 drivers
v0x96d280280_0 .net *"_ivl_7", 0 0, L_0x96c5be800;  1 drivers
v0x96d280320_0 .net *"_ivl_9", 15 0, L_0x96d2b2f80;  1 drivers
L_0x96c855cc0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2803c0_0 .net/s "acc_in", 31 0, L_0x96c855cc0;  1 drivers
v0x96d280460_0 .net/s "acc_out", 31 0, L_0x96c5c40a0;  alias, 1 drivers
v0x96d280500_0 .net/s "product", 15 0, L_0x96d2b2ee0;  1 drivers
v0x96d2805a0_0 .net/s "product_ext", 31 0, L_0x96c5c4000;  1 drivers
v0x96d280640_0 .net/s "w", 7 0, L_0x96c5be940;  1 drivers
v0x96d2806e0_0 .net/s "x", 7 0, L_0x96c5be8a0;  1 drivers
L_0x96d2b2da0 .extend/s 16, L_0x96c5be8a0;
L_0x96d2b2e40 .extend/s 16, L_0x96c5be940;
L_0x96d2b2ee0 .arith/mult 16, L_0x96d2b2da0, L_0x96d2b2e40;
L_0x96c5be800 .part L_0x96d2b2ee0, 15, 1;
L_0x96d2b2f80 .repeat 16, 16, L_0x96c5be800;
L_0x96c5c4000 .concat [ 16 16 0 0], L_0x96d2b2ee0, L_0x96d2b2f80;
L_0x96c5c40a0 .arith/sum 32, L_0x96c855cc0, L_0x96c5c4000;
S_0x96d27c780 .scope generate, "GEN_MAC[21]" "GEN_MAC[21]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585300 .param/l "i" 1 6 17, +C4<010101>;
S_0x96d27c900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27c780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fd80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fdc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fe00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d280780_0 .net/s *"_ivl_0", 15 0, L_0x96d2b3020;  1 drivers
v0x96d280820_0 .net/s *"_ivl_2", 15 0, L_0x96d2b30c0;  1 drivers
v0x96d2808c0_0 .net *"_ivl_7", 0 0, L_0x96c5be9e0;  1 drivers
v0x96d280960_0 .net *"_ivl_9", 15 0, L_0x96d2b3200;  1 drivers
L_0x96c855d08 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d280a00_0 .net/s "acc_in", 31 0, L_0x96c855d08;  1 drivers
v0x96d280aa0_0 .net/s "acc_out", 31 0, L_0x96c5c41e0;  alias, 1 drivers
v0x96d280b40_0 .net/s "product", 15 0, L_0x96d2b3160;  1 drivers
v0x96d280be0_0 .net/s "product_ext", 31 0, L_0x96c5c4140;  1 drivers
v0x96d280c80_0 .net/s "w", 7 0, L_0x96c5beb20;  1 drivers
v0x96d280d20_0 .net/s "x", 7 0, L_0x96c5bea80;  1 drivers
L_0x96d2b3020 .extend/s 16, L_0x96c5bea80;
L_0x96d2b30c0 .extend/s 16, L_0x96c5beb20;
L_0x96d2b3160 .arith/mult 16, L_0x96d2b3020, L_0x96d2b30c0;
L_0x96c5be9e0 .part L_0x96d2b3160, 15, 1;
L_0x96d2b3200 .repeat 16, 16, L_0x96c5be9e0;
L_0x96c5c4140 .concat [ 16 16 0 0], L_0x96d2b3160, L_0x96d2b3200;
L_0x96c5c41e0 .arith/sum 32, L_0x96c855d08, L_0x96c5c4140;
S_0x96d27ca80 .scope generate, "GEN_MAC[22]" "GEN_MAC[22]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585340 .param/l "i" 1 6 17, +C4<010110>;
S_0x96d27cc00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27ca80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57fe40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57fe80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57fec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d280dc0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b32a0;  1 drivers
v0x96d280e60_0 .net/s *"_ivl_2", 15 0, L_0x96d2b3340;  1 drivers
v0x96d280f00_0 .net *"_ivl_7", 0 0, L_0x96c5bebc0;  1 drivers
v0x96d280fa0_0 .net *"_ivl_9", 15 0, L_0x96d2b3480;  1 drivers
L_0x96c855d50 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d281040_0 .net/s "acc_in", 31 0, L_0x96c855d50;  1 drivers
v0x96d2810e0_0 .net/s "acc_out", 31 0, L_0x96c5c4320;  alias, 1 drivers
v0x96d281180_0 .net/s "product", 15 0, L_0x96d2b33e0;  1 drivers
v0x96d281220_0 .net/s "product_ext", 31 0, L_0x96c5c4280;  1 drivers
v0x96d2812c0_0 .net/s "w", 7 0, L_0x96c5bed00;  1 drivers
v0x96d281360_0 .net/s "x", 7 0, L_0x96c5bec60;  1 drivers
L_0x96d2b32a0 .extend/s 16, L_0x96c5bec60;
L_0x96d2b3340 .extend/s 16, L_0x96c5bed00;
L_0x96d2b33e0 .arith/mult 16, L_0x96d2b32a0, L_0x96d2b3340;
L_0x96c5bebc0 .part L_0x96d2b33e0, 15, 1;
L_0x96d2b3480 .repeat 16, 16, L_0x96c5bebc0;
L_0x96c5c4280 .concat [ 16 16 0 0], L_0x96d2b33e0, L_0x96d2b3480;
L_0x96c5c4320 .arith/sum 32, L_0x96c855d50, L_0x96c5c4280;
S_0x96d27cd80 .scope generate, "GEN_MAC[23]" "GEN_MAC[23]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585380 .param/l "i" 1 6 17, +C4<010111>;
S_0x96d27cf00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27cd80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c57ff00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c57ff40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c57ff80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d281400_0 .net/s *"_ivl_0", 15 0, L_0x96d2b3520;  1 drivers
v0x96d2814a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b35c0;  1 drivers
v0x96d281540_0 .net *"_ivl_7", 0 0, L_0x96c5beda0;  1 drivers
v0x96d2815e0_0 .net *"_ivl_9", 15 0, L_0x96d2b3700;  1 drivers
L_0x96c855d98 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d281680_0 .net/s "acc_in", 31 0, L_0x96c855d98;  1 drivers
v0x96d281720_0 .net/s "acc_out", 31 0, L_0x96c5c4460;  alias, 1 drivers
v0x96d2817c0_0 .net/s "product", 15 0, L_0x96d2b3660;  1 drivers
v0x96d281860_0 .net/s "product_ext", 31 0, L_0x96c5c43c0;  1 drivers
v0x96d281900_0 .net/s "w", 7 0, L_0x96c5beee0;  1 drivers
v0x96d2819a0_0 .net/s "x", 7 0, L_0x96c5bee40;  1 drivers
L_0x96d2b3520 .extend/s 16, L_0x96c5bee40;
L_0x96d2b35c0 .extend/s 16, L_0x96c5beee0;
L_0x96d2b3660 .arith/mult 16, L_0x96d2b3520, L_0x96d2b35c0;
L_0x96c5beda0 .part L_0x96d2b3660, 15, 1;
L_0x96d2b3700 .repeat 16, 16, L_0x96c5beda0;
L_0x96c5c43c0 .concat [ 16 16 0 0], L_0x96d2b3660, L_0x96d2b3700;
L_0x96c5c4460 .arith/sum 32, L_0x96c855d98, L_0x96c5c43c0;
S_0x96d27d080 .scope generate, "GEN_MAC[24]" "GEN_MAC[24]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c5853c0 .param/l "i" 1 6 17, +C4<011000>;
S_0x96d27d200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27d080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0000 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0040 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0080 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d281a40_0 .net/s *"_ivl_0", 15 0, L_0x96d2b37a0;  1 drivers
v0x96d281ae0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b3840;  1 drivers
v0x96d281b80_0 .net *"_ivl_7", 0 0, L_0x96c5bef80;  1 drivers
v0x96d281c20_0 .net *"_ivl_9", 15 0, L_0x96d2b3980;  1 drivers
L_0x96c855de0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d281cc0_0 .net/s "acc_in", 31 0, L_0x96c855de0;  1 drivers
v0x96d281d60_0 .net/s "acc_out", 31 0, L_0x96c5c45a0;  alias, 1 drivers
v0x96d281e00_0 .net/s "product", 15 0, L_0x96d2b38e0;  1 drivers
v0x96d281ea0_0 .net/s "product_ext", 31 0, L_0x96c5c4500;  1 drivers
v0x96d281f40_0 .net/s "w", 7 0, L_0x96c5bf0c0;  1 drivers
v0x96d281fe0_0 .net/s "x", 7 0, L_0x96c5bf020;  1 drivers
L_0x96d2b37a0 .extend/s 16, L_0x96c5bf020;
L_0x96d2b3840 .extend/s 16, L_0x96c5bf0c0;
L_0x96d2b38e0 .arith/mult 16, L_0x96d2b37a0, L_0x96d2b3840;
L_0x96c5bef80 .part L_0x96d2b38e0, 15, 1;
L_0x96d2b3980 .repeat 16, 16, L_0x96c5bef80;
L_0x96c5c4500 .concat [ 16 16 0 0], L_0x96d2b38e0, L_0x96d2b3980;
L_0x96c5c45a0 .arith/sum 32, L_0x96c855de0, L_0x96c5c4500;
S_0x96d27d380 .scope generate, "GEN_MAC[25]" "GEN_MAC[25]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585400 .param/l "i" 1 6 17, +C4<011001>;
S_0x96d27d500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27d380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a00c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d282080_0 .net/s *"_ivl_0", 15 0, L_0x96d2b3a20;  1 drivers
v0x96d282120_0 .net/s *"_ivl_2", 15 0, L_0x96d2b3ac0;  1 drivers
v0x96d2821c0_0 .net *"_ivl_7", 0 0, L_0x96c5bf160;  1 drivers
v0x96d282260_0 .net *"_ivl_9", 15 0, L_0x96d2b3c00;  1 drivers
L_0x96c855e28 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d282300_0 .net/s "acc_in", 31 0, L_0x96c855e28;  1 drivers
v0x96d2823a0_0 .net/s "acc_out", 31 0, L_0x96c5c46e0;  alias, 1 drivers
v0x96d282440_0 .net/s "product", 15 0, L_0x96d2b3b60;  1 drivers
v0x96d2824e0_0 .net/s "product_ext", 31 0, L_0x96c5c4640;  1 drivers
v0x96d282580_0 .net/s "w", 7 0, L_0x96c5bf2a0;  1 drivers
v0x96d282620_0 .net/s "x", 7 0, L_0x96c5bf200;  1 drivers
L_0x96d2b3a20 .extend/s 16, L_0x96c5bf200;
L_0x96d2b3ac0 .extend/s 16, L_0x96c5bf2a0;
L_0x96d2b3b60 .arith/mult 16, L_0x96d2b3a20, L_0x96d2b3ac0;
L_0x96c5bf160 .part L_0x96d2b3b60, 15, 1;
L_0x96d2b3c00 .repeat 16, 16, L_0x96c5bf160;
L_0x96c5c4640 .concat [ 16 16 0 0], L_0x96d2b3b60, L_0x96d2b3c00;
L_0x96c5c46e0 .arith/sum 32, L_0x96c855e28, L_0x96c5c4640;
S_0x96d27d680 .scope generate, "GEN_MAC[26]" "GEN_MAC[26]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585440 .param/l "i" 1 6 17, +C4<011010>;
S_0x96d27d800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27d680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a01c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2826c0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b3ca0;  1 drivers
v0x96d282760_0 .net/s *"_ivl_2", 15 0, L_0x96d2b3d40;  1 drivers
v0x96d282800_0 .net *"_ivl_7", 0 0, L_0x96c5bf340;  1 drivers
v0x96d2828a0_0 .net *"_ivl_9", 15 0, L_0x96d2b3e80;  1 drivers
L_0x96c855e70 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d282940_0 .net/s "acc_in", 31 0, L_0x96c855e70;  1 drivers
v0x96d2829e0_0 .net/s "acc_out", 31 0, L_0x96c5c4820;  alias, 1 drivers
v0x96d282a80_0 .net/s "product", 15 0, L_0x96d2b3de0;  1 drivers
v0x96d282b20_0 .net/s "product_ext", 31 0, L_0x96c5c4780;  1 drivers
v0x96d282bc0_0 .net/s "w", 7 0, L_0x96c5bf480;  1 drivers
v0x96d282c60_0 .net/s "x", 7 0, L_0x96c5bf3e0;  1 drivers
L_0x96d2b3ca0 .extend/s 16, L_0x96c5bf3e0;
L_0x96d2b3d40 .extend/s 16, L_0x96c5bf480;
L_0x96d2b3de0 .arith/mult 16, L_0x96d2b3ca0, L_0x96d2b3d40;
L_0x96c5bf340 .part L_0x96d2b3de0, 15, 1;
L_0x96d2b3e80 .repeat 16, 16, L_0x96c5bf340;
L_0x96c5c4780 .concat [ 16 16 0 0], L_0x96d2b3de0, L_0x96d2b3e80;
L_0x96c5c4820 .arith/sum 32, L_0x96c855e70, L_0x96c5c4780;
S_0x96d27d980 .scope generate, "GEN_MAC[27]" "GEN_MAC[27]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585480 .param/l "i" 1 6 17, +C4<011011>;
S_0x96d27db00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27d980;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a02c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d282d00_0 .net/s *"_ivl_0", 15 0, L_0x96d2b3f20;  1 drivers
v0x96d282da0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4000;  1 drivers
v0x96d282e40_0 .net *"_ivl_7", 0 0, L_0x96c5bf520;  1 drivers
v0x96d282ee0_0 .net *"_ivl_9", 15 0, L_0x96d2b4140;  1 drivers
L_0x96c855eb8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d282f80_0 .net/s "acc_in", 31 0, L_0x96c855eb8;  1 drivers
v0x96d283020_0 .net/s "acc_out", 31 0, L_0x96c5c4960;  alias, 1 drivers
v0x96d2830c0_0 .net/s "product", 15 0, L_0x96d2b40a0;  1 drivers
v0x96d283160_0 .net/s "product_ext", 31 0, L_0x96c5c48c0;  1 drivers
v0x96d283200_0 .net/s "w", 7 0, L_0x96c5bf660;  1 drivers
v0x96d2832a0_0 .net/s "x", 7 0, L_0x96c5bf5c0;  1 drivers
L_0x96d2b3f20 .extend/s 16, L_0x96c5bf5c0;
L_0x96d2b4000 .extend/s 16, L_0x96c5bf660;
L_0x96d2b40a0 .arith/mult 16, L_0x96d2b3f20, L_0x96d2b4000;
L_0x96c5bf520 .part L_0x96d2b40a0, 15, 1;
L_0x96d2b4140 .repeat 16, 16, L_0x96c5bf520;
L_0x96c5c48c0 .concat [ 16 16 0 0], L_0x96d2b40a0, L_0x96d2b4140;
L_0x96c5c4960 .arith/sum 32, L_0x96c855eb8, L_0x96c5c48c0;
S_0x96d27dc80 .scope generate, "GEN_MAC[28]" "GEN_MAC[28]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c5854c0 .param/l "i" 1 6 17, +C4<011100>;
S_0x96d27de00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27dc80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d283340_0 .net/s *"_ivl_0", 15 0, L_0x96d2b41e0;  1 drivers
v0x96d2833e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4280;  1 drivers
v0x96d283480_0 .net *"_ivl_7", 0 0, L_0x96c5bf700;  1 drivers
v0x96d283520_0 .net *"_ivl_9", 15 0, L_0x96d2b43c0;  1 drivers
L_0x96c855f00 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2835c0_0 .net/s "acc_in", 31 0, L_0x96c855f00;  1 drivers
v0x96d283660_0 .net/s "acc_out", 31 0, L_0x96c5c4aa0;  alias, 1 drivers
v0x96d283700_0 .net/s "product", 15 0, L_0x96d2b4320;  1 drivers
v0x96d2837a0_0 .net/s "product_ext", 31 0, L_0x96c5c4a00;  1 drivers
v0x96d283840_0 .net/s "w", 7 0, L_0x96c5bf840;  1 drivers
v0x96d2838e0_0 .net/s "x", 7 0, L_0x96c5bf7a0;  1 drivers
L_0x96d2b41e0 .extend/s 16, L_0x96c5bf7a0;
L_0x96d2b4280 .extend/s 16, L_0x96c5bf840;
L_0x96d2b4320 .arith/mult 16, L_0x96d2b41e0, L_0x96d2b4280;
L_0x96c5bf700 .part L_0x96d2b4320, 15, 1;
L_0x96d2b43c0 .repeat 16, 16, L_0x96c5bf700;
L_0x96c5c4a00 .concat [ 16 16 0 0], L_0x96d2b4320, L_0x96d2b43c0;
L_0x96c5c4aa0 .arith/sum 32, L_0x96c855f00, L_0x96c5c4a00;
S_0x96d27df80 .scope generate, "GEN_MAC[29]" "GEN_MAC[29]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585500 .param/l "i" 1 6 17, +C4<011101>;
S_0x96d27e100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27df80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a03c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d283980_0 .net/s *"_ivl_0", 15 0, L_0x96d2b4460;  1 drivers
v0x96d283a20_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4500;  1 drivers
v0x96d283ac0_0 .net *"_ivl_7", 0 0, L_0x96c5bf8e0;  1 drivers
v0x96d283b60_0 .net *"_ivl_9", 15 0, L_0x96d2b4640;  1 drivers
L_0x96c855f48 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d283c00_0 .net/s "acc_in", 31 0, L_0x96c855f48;  1 drivers
v0x96d283ca0_0 .net/s "acc_out", 31 0, L_0x96c5c4be0;  alias, 1 drivers
v0x96d283d40_0 .net/s "product", 15 0, L_0x96d2b45a0;  1 drivers
v0x96d283de0_0 .net/s "product_ext", 31 0, L_0x96c5c4b40;  1 drivers
v0x96d283e80_0 .net/s "w", 7 0, L_0x96c5bfa20;  1 drivers
v0x96d283f20_0 .net/s "x", 7 0, L_0x96c5bf980;  1 drivers
L_0x96d2b4460 .extend/s 16, L_0x96c5bf980;
L_0x96d2b4500 .extend/s 16, L_0x96c5bfa20;
L_0x96d2b45a0 .arith/mult 16, L_0x96d2b4460, L_0x96d2b4500;
L_0x96c5bf8e0 .part L_0x96d2b45a0, 15, 1;
L_0x96d2b4640 .repeat 16, 16, L_0x96c5bf8e0;
L_0x96c5c4b40 .concat [ 16 16 0 0], L_0x96d2b45a0, L_0x96d2b4640;
L_0x96c5c4be0 .arith/sum 32, L_0x96c855f48, L_0x96c5c4b40;
S_0x96d27e280 .scope generate, "GEN_MAC[30]" "GEN_MAC[30]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585540 .param/l "i" 1 6 17, +C4<011110>;
S_0x96d27e400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27e280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a04c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d288000_0 .net/s *"_ivl_0", 15 0, L_0x96d2b46e0;  1 drivers
v0x96d2880a0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4780;  1 drivers
v0x96d288140_0 .net *"_ivl_7", 0 0, L_0x96c5bfac0;  1 drivers
v0x96d2881e0_0 .net *"_ivl_9", 15 0, L_0x96d2b48c0;  1 drivers
L_0x96c855f90 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d288280_0 .net/s "acc_in", 31 0, L_0x96c855f90;  1 drivers
v0x96d288320_0 .net/s "acc_out", 31 0, L_0x96c5c4d20;  alias, 1 drivers
v0x96d2883c0_0 .net/s "product", 15 0, L_0x96d2b4820;  1 drivers
v0x96d288460_0 .net/s "product_ext", 31 0, L_0x96c5c4c80;  1 drivers
v0x96d288500_0 .net/s "w", 7 0, L_0x96c5bfc00;  1 drivers
v0x96d2885a0_0 .net/s "x", 7 0, L_0x96c5bfb60;  1 drivers
L_0x96d2b46e0 .extend/s 16, L_0x96c5bfb60;
L_0x96d2b4780 .extend/s 16, L_0x96c5bfc00;
L_0x96d2b4820 .arith/mult 16, L_0x96d2b46e0, L_0x96d2b4780;
L_0x96c5bfac0 .part L_0x96d2b4820, 15, 1;
L_0x96d2b48c0 .repeat 16, 16, L_0x96c5bfac0;
L_0x96c5c4c80 .concat [ 16 16 0 0], L_0x96d2b4820, L_0x96d2b48c0;
L_0x96c5c4d20 .arith/sum 32, L_0x96c855f90, L_0x96c5c4c80;
S_0x96d27e580 .scope generate, "GEN_MAC[31]" "GEN_MAC[31]" 6 17, 6 17 0, S_0x96d270600;
 .timescale 0 0;
P_0x96c585580 .param/l "i" 1 6 17, +C4<011111>;
S_0x96d27e700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27e580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a05c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d288640_0 .net/s *"_ivl_0", 15 0, L_0x96d2b4960;  1 drivers
v0x96d2886e0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4a00;  1 drivers
v0x96d288780_0 .net *"_ivl_7", 0 0, L_0x96c5bfca0;  1 drivers
v0x96d288820_0 .net *"_ivl_9", 15 0, L_0x96d2b4b40;  1 drivers
L_0x96c855fd8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2888c0_0 .net/s "acc_in", 31 0, L_0x96c855fd8;  1 drivers
v0x96d288960_0 .net/s "acc_out", 31 0, L_0x96c5c4e60;  alias, 1 drivers
v0x96d288a00_0 .net/s "product", 15 0, L_0x96d2b4aa0;  1 drivers
v0x96d288aa0_0 .net/s "product_ext", 31 0, L_0x96c5c4dc0;  1 drivers
v0x96d288b40_0 .net/s "w", 7 0, L_0x96c5bfde0;  1 drivers
v0x96d288be0_0 .net/s "x", 7 0, L_0x96c5bfd40;  1 drivers
L_0x96d2b4960 .extend/s 16, L_0x96c5bfd40;
L_0x96d2b4a00 .extend/s 16, L_0x96c5bfde0;
L_0x96d2b4aa0 .arith/mult 16, L_0x96d2b4960, L_0x96d2b4a00;
L_0x96c5bfca0 .part L_0x96d2b4aa0, 15, 1;
L_0x96d2b4b40 .repeat 16, 16, L_0x96c5bfca0;
L_0x96c5c4dc0 .concat [ 16 16 0 0], L_0x96d2b4aa0, L_0x96d2b4b40;
L_0x96c5c4e60 .arith/sum 32, L_0x96c855fd8, L_0x96c5c4dc0;
S_0x96d27e880 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 4 34, 4 34 0, S_0x100fcf810;
 .timescale 0 0;
P_0x96c5855c0 .param/l "n" 1 4 34, +C4<011>;
S_0x96d27ea00 .scope module, "u_neuron" "neuron_parallel" 4 41, 5 1 0, S_0x96d27e880;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "start";
    .port_info 3 /INPUT 2048 "x_bus";
    .port_info 4 /INPUT 2048 "w_bus";
    .port_info 5 /INPUT 8 "bias";
    .port_info 6 /OUTPUT 8 "y";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "done";
P_0x96d27eb80 .param/l "ACC_WIDTH" 0 5 5, +C4<00000000000000000000000000100000>;
P_0x96d27ebc0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
P_0x96d27ec00 .param/l "GROUPS" 1 5 20, +C4<00000000000000000000000000001000>;
P_0x96d27ec40 .param/l "GROUP_INDEX_WIDTH" 1 5 21, +C4<00000000000000000000000000000011>;
P_0x96d27ec80 .param/l "N_INPUTS" 0 5 3, +C4<00000000000000000000000100000000>;
P_0x96d27ecc0 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000100000>;
v0x96d29f0c0_0 .net *"_ivl_0", 31 0, L_0x96c5c50e0;  1 drivers
v0x96d29f160_0 .net *"_ivl_11", 31 0, L_0x96d2b4d20;  1 drivers
v0x96d29f200_0 .net *"_ivl_14", 31 0, L_0x96c5c5180;  1 drivers
L_0x96c8560f8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29f2a0_0 .net *"_ivl_17", 28 0, L_0x96c8560f8;  1 drivers
L_0x96c856140 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d29f340_0 .net/2u *"_ivl_18", 31 0, L_0x96c856140;  1 drivers
v0x96d29f3e0_0 .net *"_ivl_21", 31 0, L_0x96d2b4dc0;  1 drivers
L_0x96c856188 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d29f480_0 .net/2u *"_ivl_22", 31 0, L_0x96c856188;  1 drivers
v0x96d29f520_0 .net *"_ivl_25", 31 0, L_0x96d2b4e60;  1 drivers
v0x96d29f5c0_0 .net *"_ivl_29", 0 0, L_0x96c5cfde0;  1 drivers
L_0x96c856020 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29f660_0 .net *"_ivl_3", 28 0, L_0x96c856020;  1 drivers
v0x96d29f700_0 .net *"_ivl_31", 23 0, L_0x96d2bdf40;  1 drivers
L_0x96c856068 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
v0x96d29f7a0_0 .net/2u *"_ivl_4", 31 0, L_0x96c856068;  1 drivers
v0x96d29f840_0 .net *"_ivl_7", 31 0, L_0x96d2b4c80;  1 drivers
L_0x96c8560b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
v0x96d29f8e0_0 .net/2u *"_ivl_8", 31 0, L_0x96c8560b0;  1 drivers
v0x96d29f980_0 .var/s "acc", 31 0;
v0x96d29fa20_0 .net/s "acc_next", 31 0, L_0x96c5c7a20;  1 drivers
v0x96d29fac0_0 .net/s "bias", 7 0, L_0x96c5cff20;  1 drivers
v0x96d29fb60_0 .net/s "bias_ext", 31 0, L_0x96c5c7ac0;  1 drivers
v0x96d29fc00_0 .var "busy", 0 0;
v0x96d29fca0_0 .net "clk", 0 0, v0x96d2a4be0_0;  alias, 1 drivers
v0x96d29fd40_0 .var "done", 0 0;
v0x96d29fde0_0 .net/s "final_acc", 31 0, L_0x96c5c7b60;  1 drivers
v0x96d29fe80_0 .var "group_index", 2 0;
v0x96d29ff20_0 .net "rst", 0 0, v0x96d2a4f00_0;  alias, 1 drivers
v0x96d2a4000_0 .net "start", 0 0, v0x96d2a4fa0_0;  alias, 1 drivers
v0x96d2a40a0_0 .net/s "w_bus", 2047 0, L_0x96c5cfe80;  1 drivers
v0x96d2a4140_0 .net/s "w_group", 255 0, L_0x96c5cc140;  1 drivers
v0x96d2a41e0_0 .net/s "x_bus", 2047 0, v0x96d2a50e0_0;  alias, 1 drivers
v0x96d2a4280_0 .net/s "x_group", 255 0, L_0x96c5cc0a0;  1 drivers
v0x96d2a4320_0 .var/s "y", 7 0;
L_0x96c5c50e0 .concat [ 3 29 0 0], v0x96d29fe80_0, L_0x96c856020;
L_0x96d2b4c80 .arith/mult 32, L_0x96c5c50e0, L_0x96c856068;
L_0x96d2b4d20 .arith/mult 32, L_0x96d2b4c80, L_0x96c8560b0;
L_0x96c5cc0a0 .part/v v0x96d2a50e0_0, L_0x96d2b4d20, 256;
L_0x96c5c5180 .concat [ 3 29 0 0], v0x96d29fe80_0, L_0x96c8560f8;
L_0x96d2b4dc0 .arith/mult 32, L_0x96c5c5180, L_0x96c856140;
L_0x96d2b4e60 .arith/mult 32, L_0x96d2b4dc0, L_0x96c856188;
L_0x96c5cc140 .part/v L_0x96c5cfe80, L_0x96d2b4e60, 256;
L_0x96c5cfde0 .part L_0x96c5cff20, 7, 1;
L_0x96d2bdf40 .repeat 24, 24, L_0x96c5cfde0;
L_0x96c5c7ac0 .concat [ 8 24 0 0], L_0x96c5cff20, L_0x96d2bdf40;
L_0x96c5c7b60 .arith/sum 32, L_0x96c5c7a20, L_0x96c5c7ac0;
S_0x96d27ed00 .scope module, "u_mac8" "mac8" 5 52, 6 1 0, S_0x96d27ea00;
 .timescale 0 0;
    .port_info 0 /INPUT 256 "x_bus";
    .port_info 1 /INPUT 256 "w_bus";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0680 .param/l "PARALLEL" 0 6 4, +C4<00000000000000000000000000100000>;
v0x96d29ec60_0 .net/s "acc_in", 31 0, v0x96d29f980_0;  1 drivers
v0x96d29ed00_0 .net/s "acc_out", 31 0, L_0x96c5c7a20;  alias, 1 drivers
v0x96d29eda0_0 .var/i "j", 31 0;
v0x96d29ee40 .array "products", 31 0;
v0x96d29ee40_0 .net/s v0x96d29ee40 0, 31 0, L_0x96c5c52c0; 1 drivers
v0x96d29ee40_1 .net/s v0x96d29ee40 1, 31 0, L_0x96c5c5400; 1 drivers
v0x96d29ee40_2 .net/s v0x96d29ee40 2, 31 0, L_0x96c5c5540; 1 drivers
v0x96d29ee40_3 .net/s v0x96d29ee40 3, 31 0, L_0x96c5c5680; 1 drivers
v0x96d29ee40_4 .net/s v0x96d29ee40 4, 31 0, L_0x96c5c57c0; 1 drivers
v0x96d29ee40_5 .net/s v0x96d29ee40 5, 31 0, L_0x96c5c5900; 1 drivers
v0x96d29ee40_6 .net/s v0x96d29ee40 6, 31 0, L_0x96c5c5a40; 1 drivers
v0x96d29ee40_7 .net/s v0x96d29ee40 7, 31 0, L_0x96c5c5b80; 1 drivers
v0x96d29ee40_8 .net/s v0x96d29ee40 8, 31 0, L_0x96c5c5cc0; 1 drivers
v0x96d29ee40_9 .net/s v0x96d29ee40 9, 31 0, L_0x96c5c5e00; 1 drivers
v0x96d29ee40_10 .net/s v0x96d29ee40 10, 31 0, L_0x96c5c5f40; 1 drivers
v0x96d29ee40_11 .net/s v0x96d29ee40 11, 31 0, L_0x96c5c6080; 1 drivers
v0x96d29ee40_12 .net/s v0x96d29ee40 12, 31 0, L_0x96c5c61c0; 1 drivers
v0x96d29ee40_13 .net/s v0x96d29ee40 13, 31 0, L_0x96c5c6300; 1 drivers
v0x96d29ee40_14 .net/s v0x96d29ee40 14, 31 0, L_0x96c5c6440; 1 drivers
v0x96d29ee40_15 .net/s v0x96d29ee40 15, 31 0, L_0x96c5c6580; 1 drivers
v0x96d29ee40_16 .net/s v0x96d29ee40 16, 31 0, L_0x96c5c66c0; 1 drivers
v0x96d29ee40_17 .net/s v0x96d29ee40 17, 31 0, L_0x96c5c6800; 1 drivers
v0x96d29ee40_18 .net/s v0x96d29ee40 18, 31 0, L_0x96c5c6940; 1 drivers
v0x96d29ee40_19 .net/s v0x96d29ee40 19, 31 0, L_0x96c5c6a80; 1 drivers
v0x96d29ee40_20 .net/s v0x96d29ee40 20, 31 0, L_0x96c5c6bc0; 1 drivers
v0x96d29ee40_21 .net/s v0x96d29ee40 21, 31 0, L_0x96c5c6d00; 1 drivers
v0x96d29ee40_22 .net/s v0x96d29ee40 22, 31 0, L_0x96c5c6e40; 1 drivers
v0x96d29ee40_23 .net/s v0x96d29ee40 23, 31 0, L_0x96c5c6f80; 1 drivers
v0x96d29ee40_24 .net/s v0x96d29ee40 24, 31 0, L_0x96c5c70c0; 1 drivers
v0x96d29ee40_25 .net/s v0x96d29ee40 25, 31 0, L_0x96c5c7200; 1 drivers
v0x96d29ee40_26 .net/s v0x96d29ee40 26, 31 0, L_0x96c5c7340; 1 drivers
v0x96d29ee40_27 .net/s v0x96d29ee40 27, 31 0, L_0x96c5c7480; 1 drivers
v0x96d29ee40_28 .net/s v0x96d29ee40 28, 31 0, L_0x96c5c75c0; 1 drivers
v0x96d29ee40_29 .net/s v0x96d29ee40 29, 31 0, L_0x96c5c7700; 1 drivers
v0x96d29ee40_30 .net/s v0x96d29ee40 30, 31 0, L_0x96c5c7840; 1 drivers
v0x96d29ee40_31 .net/s v0x96d29ee40 31, 31 0, L_0x96c5c7980; 1 drivers
v0x96d29eee0_0 .var/s "sum", 31 0;
v0x96d29ef80_0 .net/s "w_bus", 255 0, L_0x96c5cc140;  alias, 1 drivers
v0x96d29f020_0 .net/s "x_bus", 255 0, L_0x96c5cc0a0;  alias, 1 drivers
E_0x96d18bd40/0 .event anyedge, v0x96d29eee0_0, v0x96d28a6c0_0, v0x96d28ad00_0, v0x96d28b340_0;
E_0x96d18bd40/1 .event anyedge, v0x96d28b980_0, v0x96d28c000_0, v0x96d28c640_0, v0x96d28cc80_0;
E_0x96d18bd40/2 .event anyedge, v0x96d28d2c0_0, v0x96d28d900_0, v0x96d28df40_0, v0x96d28e580_0;
E_0x96d18bd40/3 .event anyedge, v0x96d28ebc0_0, v0x96d28f200_0, v0x96d28f840_0, v0x96d28fe80_0;
E_0x96d18bd40/4 .event anyedge, v0x96d294500_0, v0x96d294b40_0, v0x96d295180_0, v0x96d2957c0_0;
E_0x96d18bd40/5 .event anyedge, v0x96d295e00_0, v0x96d296440_0, v0x96d296a80_0, v0x96d2970c0_0;
E_0x96d18bd40/6 .event anyedge, v0x96d297700_0, v0x96d297d40_0, v0x96d29c3c0_0, v0x96d29ca00_0;
E_0x96d18bd40/7 .event anyedge, v0x96d29d040_0, v0x96d29d680_0, v0x96d29dcc0_0, v0x96d29e300_0;
E_0x96d18bd40/8 .event anyedge, v0x96d29e940_0;
E_0x96d18bd40 .event/or E_0x96d18bd40/0, E_0x96d18bd40/1, E_0x96d18bd40/2, E_0x96d18bd40/3, E_0x96d18bd40/4, E_0x96d18bd40/5, E_0x96d18bd40/6, E_0x96d18bd40/7, E_0x96d18bd40/8;
L_0x96c5cc280 .part L_0x96c5cc0a0, 0, 8;
L_0x96c5cc320 .part L_0x96c5cc140, 0, 8;
L_0x96c5cc460 .part L_0x96c5cc0a0, 8, 8;
L_0x96c5cc500 .part L_0x96c5cc140, 8, 8;
L_0x96c5cc640 .part L_0x96c5cc0a0, 16, 8;
L_0x96c5cc6e0 .part L_0x96c5cc140, 16, 8;
L_0x96c5cc820 .part L_0x96c5cc0a0, 24, 8;
L_0x96c5cc8c0 .part L_0x96c5cc140, 24, 8;
L_0x96c5cca00 .part L_0x96c5cc0a0, 32, 8;
L_0x96c5ccaa0 .part L_0x96c5cc140, 32, 8;
L_0x96c5ccbe0 .part L_0x96c5cc0a0, 40, 8;
L_0x96c5ccc80 .part L_0x96c5cc140, 40, 8;
L_0x96c5ccdc0 .part L_0x96c5cc0a0, 48, 8;
L_0x96c5cce60 .part L_0x96c5cc140, 48, 8;
L_0x96c5ccfa0 .part L_0x96c5cc0a0, 56, 8;
L_0x96c5cd040 .part L_0x96c5cc140, 56, 8;
L_0x96c5cd180 .part L_0x96c5cc0a0, 64, 8;
L_0x96c5cd220 .part L_0x96c5cc140, 64, 8;
L_0x96c5cd360 .part L_0x96c5cc0a0, 72, 8;
L_0x96c5cd400 .part L_0x96c5cc140, 72, 8;
L_0x96c5cd540 .part L_0x96c5cc0a0, 80, 8;
L_0x96c5cd5e0 .part L_0x96c5cc140, 80, 8;
L_0x96c5cd720 .part L_0x96c5cc0a0, 88, 8;
L_0x96c5cd7c0 .part L_0x96c5cc140, 88, 8;
L_0x96c5cd900 .part L_0x96c5cc0a0, 96, 8;
L_0x96c5cd9a0 .part L_0x96c5cc140, 96, 8;
L_0x96c5cdae0 .part L_0x96c5cc0a0, 104, 8;
L_0x96c5cdb80 .part L_0x96c5cc140, 104, 8;
L_0x96c5cdcc0 .part L_0x96c5cc0a0, 112, 8;
L_0x96c5cdd60 .part L_0x96c5cc140, 112, 8;
L_0x96c5cdea0 .part L_0x96c5cc0a0, 120, 8;
L_0x96c5cdf40 .part L_0x96c5cc140, 120, 8;
L_0x96c5ce080 .part L_0x96c5cc0a0, 128, 8;
L_0x96c5ce120 .part L_0x96c5cc140, 128, 8;
L_0x96c5ce260 .part L_0x96c5cc0a0, 136, 8;
L_0x96c5ce300 .part L_0x96c5cc140, 136, 8;
L_0x96c5ce440 .part L_0x96c5cc0a0, 144, 8;
L_0x96c5ce4e0 .part L_0x96c5cc140, 144, 8;
L_0x96c5ce620 .part L_0x96c5cc0a0, 152, 8;
L_0x96c5ce6c0 .part L_0x96c5cc140, 152, 8;
L_0x96c5ce800 .part L_0x96c5cc0a0, 160, 8;
L_0x96c5ce8a0 .part L_0x96c5cc140, 160, 8;
L_0x96c5ce9e0 .part L_0x96c5cc0a0, 168, 8;
L_0x96c5cea80 .part L_0x96c5cc140, 168, 8;
L_0x96c5cebc0 .part L_0x96c5cc0a0, 176, 8;
L_0x96c5cec60 .part L_0x96c5cc140, 176, 8;
L_0x96c5ceda0 .part L_0x96c5cc0a0, 184, 8;
L_0x96c5cee40 .part L_0x96c5cc140, 184, 8;
L_0x96c5cef80 .part L_0x96c5cc0a0, 192, 8;
L_0x96c5cf020 .part L_0x96c5cc140, 192, 8;
L_0x96c5cf160 .part L_0x96c5cc0a0, 200, 8;
L_0x96c5cf200 .part L_0x96c5cc140, 200, 8;
L_0x96c5cf340 .part L_0x96c5cc0a0, 208, 8;
L_0x96c5cf3e0 .part L_0x96c5cc140, 208, 8;
L_0x96c5cf520 .part L_0x96c5cc0a0, 216, 8;
L_0x96c5cf5c0 .part L_0x96c5cc140, 216, 8;
L_0x96c5cf700 .part L_0x96c5cc0a0, 224, 8;
L_0x96c5cf7a0 .part L_0x96c5cc140, 224, 8;
L_0x96c5cf8e0 .part L_0x96c5cc0a0, 232, 8;
L_0x96c5cf980 .part L_0x96c5cc140, 232, 8;
L_0x96c5cfac0 .part L_0x96c5cc0a0, 240, 8;
L_0x96c5cfb60 .part L_0x96c5cc140, 240, 8;
L_0x96c5cfca0 .part L_0x96c5cc0a0, 248, 8;
L_0x96c5cfd40 .part L_0x96c5cc140, 248, 8;
L_0x96c5c7a20 .arith/sum 32, v0x96d29f980_0, v0x96d29eee0_0;
S_0x96d27ee80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585600 .param/l "i" 1 6 17, +C4<00>;
S_0x96d27f000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27ee80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a06c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28a3a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b4f00;  1 drivers
v0x96d28a440_0 .net/s *"_ivl_2", 15 0, L_0x96d2b4fa0;  1 drivers
v0x96d28a4e0_0 .net *"_ivl_7", 0 0, L_0x96c5cc1e0;  1 drivers
v0x96d28a580_0 .net *"_ivl_9", 15 0, L_0x96d2b50e0;  1 drivers
L_0x96c8561d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28a620_0 .net/s "acc_in", 31 0, L_0x96c8561d0;  1 drivers
v0x96d28a6c0_0 .net/s "acc_out", 31 0, L_0x96c5c52c0;  alias, 1 drivers
v0x96d28a760_0 .net/s "product", 15 0, L_0x96d2b5040;  1 drivers
v0x96d28a800_0 .net/s "product_ext", 31 0, L_0x96c5c5220;  1 drivers
v0x96d28a8a0_0 .net/s "w", 7 0, L_0x96c5cc320;  1 drivers
v0x96d28a940_0 .net/s "x", 7 0, L_0x96c5cc280;  1 drivers
L_0x96d2b4f00 .extend/s 16, L_0x96c5cc280;
L_0x96d2b4fa0 .extend/s 16, L_0x96c5cc320;
L_0x96d2b5040 .arith/mult 16, L_0x96d2b4f00, L_0x96d2b4fa0;
L_0x96c5cc1e0 .part L_0x96d2b5040, 15, 1;
L_0x96d2b50e0 .repeat 16, 16, L_0x96c5cc1e0;
L_0x96c5c5220 .concat [ 16 16 0 0], L_0x96d2b5040, L_0x96d2b50e0;
L_0x96c5c52c0 .arith/sum 32, L_0x96c8561d0, L_0x96c5c5220;
S_0x96d27f180 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585640 .param/l "i" 1 6 17, +C4<01>;
S_0x96d27f300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27f180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a07c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28a9e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5180;  1 drivers
v0x96d28aa80_0 .net/s *"_ivl_2", 15 0, L_0x96d2b5220;  1 drivers
v0x96d28ab20_0 .net *"_ivl_7", 0 0, L_0x96c5cc3c0;  1 drivers
v0x96d28abc0_0 .net *"_ivl_9", 15 0, L_0x96d2b5360;  1 drivers
L_0x96c856218 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28ac60_0 .net/s "acc_in", 31 0, L_0x96c856218;  1 drivers
v0x96d28ad00_0 .net/s "acc_out", 31 0, L_0x96c5c5400;  alias, 1 drivers
v0x96d28ada0_0 .net/s "product", 15 0, L_0x96d2b52c0;  1 drivers
v0x96d28ae40_0 .net/s "product_ext", 31 0, L_0x96c5c5360;  1 drivers
v0x96d28aee0_0 .net/s "w", 7 0, L_0x96c5cc500;  1 drivers
v0x96d28af80_0 .net/s "x", 7 0, L_0x96c5cc460;  1 drivers
L_0x96d2b5180 .extend/s 16, L_0x96c5cc460;
L_0x96d2b5220 .extend/s 16, L_0x96c5cc500;
L_0x96d2b52c0 .arith/mult 16, L_0x96d2b5180, L_0x96d2b5220;
L_0x96c5cc3c0 .part L_0x96d2b52c0, 15, 1;
L_0x96d2b5360 .repeat 16, 16, L_0x96c5cc3c0;
L_0x96c5c5360 .concat [ 16 16 0 0], L_0x96d2b52c0, L_0x96d2b5360;
L_0x96c5c5400 .arith/sum 32, L_0x96c856218, L_0x96c5c5360;
S_0x96d27f480 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585680 .param/l "i" 1 6 17, +C4<010>;
S_0x96d27f600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27f480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a08c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28b020_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5400;  1 drivers
v0x96d28b0c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b54a0;  1 drivers
v0x96d28b160_0 .net *"_ivl_7", 0 0, L_0x96c5cc5a0;  1 drivers
v0x96d28b200_0 .net *"_ivl_9", 15 0, L_0x96d2b55e0;  1 drivers
L_0x96c856260 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28b2a0_0 .net/s "acc_in", 31 0, L_0x96c856260;  1 drivers
v0x96d28b340_0 .net/s "acc_out", 31 0, L_0x96c5c5540;  alias, 1 drivers
v0x96d28b3e0_0 .net/s "product", 15 0, L_0x96d2b5540;  1 drivers
v0x96d28b480_0 .net/s "product_ext", 31 0, L_0x96c5c54a0;  1 drivers
v0x96d28b520_0 .net/s "w", 7 0, L_0x96c5cc6e0;  1 drivers
v0x96d28b5c0_0 .net/s "x", 7 0, L_0x96c5cc640;  1 drivers
L_0x96d2b5400 .extend/s 16, L_0x96c5cc640;
L_0x96d2b54a0 .extend/s 16, L_0x96c5cc6e0;
L_0x96d2b5540 .arith/mult 16, L_0x96d2b5400, L_0x96d2b54a0;
L_0x96c5cc5a0 .part L_0x96d2b5540, 15, 1;
L_0x96d2b55e0 .repeat 16, 16, L_0x96c5cc5a0;
L_0x96c5c54a0 .concat [ 16 16 0 0], L_0x96d2b5540, L_0x96d2b55e0;
L_0x96c5c5540 .arith/sum 32, L_0x96c856260, L_0x96c5c54a0;
S_0x96d27f780 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c5856c0 .param/l "i" 1 6 17, +C4<011>;
S_0x96d27f900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27f780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28b660_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5680;  1 drivers
v0x96d28b700_0 .net/s *"_ivl_2", 15 0, L_0x96d2b5720;  1 drivers
v0x96d28b7a0_0 .net *"_ivl_7", 0 0, L_0x96c5cc780;  1 drivers
v0x96d28b840_0 .net *"_ivl_9", 15 0, L_0x96d2b5860;  1 drivers
L_0x96c8562a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28b8e0_0 .net/s "acc_in", 31 0, L_0x96c8562a8;  1 drivers
v0x96d28b980_0 .net/s "acc_out", 31 0, L_0x96c5c5680;  alias, 1 drivers
v0x96d28ba20_0 .net/s "product", 15 0, L_0x96d2b57c0;  1 drivers
v0x96d28bac0_0 .net/s "product_ext", 31 0, L_0x96c5c55e0;  1 drivers
v0x96d28bb60_0 .net/s "w", 7 0, L_0x96c5cc8c0;  1 drivers
v0x96d28bc00_0 .net/s "x", 7 0, L_0x96c5cc820;  1 drivers
L_0x96d2b5680 .extend/s 16, L_0x96c5cc820;
L_0x96d2b5720 .extend/s 16, L_0x96c5cc8c0;
L_0x96d2b57c0 .arith/mult 16, L_0x96d2b5680, L_0x96d2b5720;
L_0x96c5cc780 .part L_0x96d2b57c0, 15, 1;
L_0x96d2b5860 .repeat 16, 16, L_0x96c5cc780;
L_0x96c5c55e0 .concat [ 16 16 0 0], L_0x96d2b57c0, L_0x96d2b5860;
L_0x96c5c5680 .arith/sum 32, L_0x96c8562a8, L_0x96c5c55e0;
S_0x96d27fa80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585700 .param/l "i" 1 6 17, +C4<0100>;
S_0x96d27fc00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27fa80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a09c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0a00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0a40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28bca0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5900;  1 drivers
v0x96d28bd40_0 .net/s *"_ivl_2", 15 0, L_0x96d2b59a0;  1 drivers
v0x96d28bde0_0 .net *"_ivl_7", 0 0, L_0x96c5cc960;  1 drivers
v0x96d28be80_0 .net *"_ivl_9", 15 0, L_0x96d2b5ae0;  1 drivers
L_0x96c8562f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28bf20_0 .net/s "acc_in", 31 0, L_0x96c8562f0;  1 drivers
v0x96d28c000_0 .net/s "acc_out", 31 0, L_0x96c5c57c0;  alias, 1 drivers
v0x96d28c0a0_0 .net/s "product", 15 0, L_0x96d2b5a40;  1 drivers
v0x96d28c140_0 .net/s "product_ext", 31 0, L_0x96c5c5720;  1 drivers
v0x96d28c1e0_0 .net/s "w", 7 0, L_0x96c5ccaa0;  1 drivers
v0x96d28c280_0 .net/s "x", 7 0, L_0x96c5cca00;  1 drivers
L_0x96d2b5900 .extend/s 16, L_0x96c5cca00;
L_0x96d2b59a0 .extend/s 16, L_0x96c5ccaa0;
L_0x96d2b5a40 .arith/mult 16, L_0x96d2b5900, L_0x96d2b59a0;
L_0x96c5cc960 .part L_0x96d2b5a40, 15, 1;
L_0x96d2b5ae0 .repeat 16, 16, L_0x96c5cc960;
L_0x96c5c5720 .concat [ 16 16 0 0], L_0x96d2b5a40, L_0x96d2b5ae0;
L_0x96c5c57c0 .arith/sum 32, L_0x96c8562f0, L_0x96c5c5720;
S_0x96d27fd80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585740 .param/l "i" 1 6 17, +C4<0101>;
S_0x96d290000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d27fd80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0a80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0ac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0b00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28c320_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5b80;  1 drivers
v0x96d28c3c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b5c20;  1 drivers
v0x96d28c460_0 .net *"_ivl_7", 0 0, L_0x96c5ccb40;  1 drivers
v0x96d28c500_0 .net *"_ivl_9", 15 0, L_0x96d2b5d60;  1 drivers
L_0x96c856338 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28c5a0_0 .net/s "acc_in", 31 0, L_0x96c856338;  1 drivers
v0x96d28c640_0 .net/s "acc_out", 31 0, L_0x96c5c5900;  alias, 1 drivers
v0x96d28c6e0_0 .net/s "product", 15 0, L_0x96d2b5cc0;  1 drivers
v0x96d28c780_0 .net/s "product_ext", 31 0, L_0x96c5c5860;  1 drivers
v0x96d28c820_0 .net/s "w", 7 0, L_0x96c5ccc80;  1 drivers
v0x96d28c8c0_0 .net/s "x", 7 0, L_0x96c5ccbe0;  1 drivers
L_0x96d2b5b80 .extend/s 16, L_0x96c5ccbe0;
L_0x96d2b5c20 .extend/s 16, L_0x96c5ccc80;
L_0x96d2b5cc0 .arith/mult 16, L_0x96d2b5b80, L_0x96d2b5c20;
L_0x96c5ccb40 .part L_0x96d2b5cc0, 15, 1;
L_0x96d2b5d60 .repeat 16, 16, L_0x96c5ccb40;
L_0x96c5c5860 .concat [ 16 16 0 0], L_0x96d2b5cc0, L_0x96d2b5d60;
L_0x96c5c5900 .arith/sum 32, L_0x96c856338, L_0x96c5c5860;
S_0x96d290180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585780 .param/l "i" 1 6 17, +C4<0110>;
S_0x96d290300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d290180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0b40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0b80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0bc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28c960_0 .net/s *"_ivl_0", 15 0, L_0x96d2b5e00;  1 drivers
v0x96d28ca00_0 .net/s *"_ivl_2", 15 0, L_0x96d2b5ea0;  1 drivers
v0x96d28caa0_0 .net *"_ivl_7", 0 0, L_0x96c5ccd20;  1 drivers
v0x96d28cb40_0 .net *"_ivl_9", 15 0, L_0x96d2b5fe0;  1 drivers
L_0x96c856380 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28cbe0_0 .net/s "acc_in", 31 0, L_0x96c856380;  1 drivers
v0x96d28cc80_0 .net/s "acc_out", 31 0, L_0x96c5c5a40;  alias, 1 drivers
v0x96d28cd20_0 .net/s "product", 15 0, L_0x96d2b5f40;  1 drivers
v0x96d28cdc0_0 .net/s "product_ext", 31 0, L_0x96c5c59a0;  1 drivers
v0x96d28ce60_0 .net/s "w", 7 0, L_0x96c5cce60;  1 drivers
v0x96d28cf00_0 .net/s "x", 7 0, L_0x96c5ccdc0;  1 drivers
L_0x96d2b5e00 .extend/s 16, L_0x96c5ccdc0;
L_0x96d2b5ea0 .extend/s 16, L_0x96c5cce60;
L_0x96d2b5f40 .arith/mult 16, L_0x96d2b5e00, L_0x96d2b5ea0;
L_0x96c5ccd20 .part L_0x96d2b5f40, 15, 1;
L_0x96d2b5fe0 .repeat 16, 16, L_0x96c5ccd20;
L_0x96c5c59a0 .concat [ 16 16 0 0], L_0x96d2b5f40, L_0x96d2b5fe0;
L_0x96c5c5a40 .arith/sum 32, L_0x96c856380, L_0x96c5c59a0;
S_0x96d290480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c5857c0 .param/l "i" 1 6 17, +C4<0111>;
S_0x96d290600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d290480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0c00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0c40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0c80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28cfa0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6080;  1 drivers
v0x96d28d040_0 .net/s *"_ivl_2", 15 0, L_0x96d2b6120;  1 drivers
v0x96d28d0e0_0 .net *"_ivl_7", 0 0, L_0x96c5ccf00;  1 drivers
v0x96d28d180_0 .net *"_ivl_9", 15 0, L_0x96d2b6260;  1 drivers
L_0x96c8563c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28d220_0 .net/s "acc_in", 31 0, L_0x96c8563c8;  1 drivers
v0x96d28d2c0_0 .net/s "acc_out", 31 0, L_0x96c5c5b80;  alias, 1 drivers
v0x96d28d360_0 .net/s "product", 15 0, L_0x96d2b61c0;  1 drivers
v0x96d28d400_0 .net/s "product_ext", 31 0, L_0x96c5c5ae0;  1 drivers
v0x96d28d4a0_0 .net/s "w", 7 0, L_0x96c5cd040;  1 drivers
v0x96d28d540_0 .net/s "x", 7 0, L_0x96c5ccfa0;  1 drivers
L_0x96d2b6080 .extend/s 16, L_0x96c5ccfa0;
L_0x96d2b6120 .extend/s 16, L_0x96c5cd040;
L_0x96d2b61c0 .arith/mult 16, L_0x96d2b6080, L_0x96d2b6120;
L_0x96c5ccf00 .part L_0x96d2b61c0, 15, 1;
L_0x96d2b6260 .repeat 16, 16, L_0x96c5ccf00;
L_0x96c5c5ae0 .concat [ 16 16 0 0], L_0x96d2b61c0, L_0x96d2b6260;
L_0x96c5c5b80 .arith/sum 32, L_0x96c8563c8, L_0x96c5c5ae0;
S_0x96d290780 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585800 .param/l "i" 1 6 17, +C4<01000>;
S_0x96d290900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d290780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0cc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0d00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0d40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28d5e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6300;  1 drivers
v0x96d28d680_0 .net/s *"_ivl_2", 15 0, L_0x96d2b63a0;  1 drivers
v0x96d28d720_0 .net *"_ivl_7", 0 0, L_0x96c5cd0e0;  1 drivers
v0x96d28d7c0_0 .net *"_ivl_9", 15 0, L_0x96d2b64e0;  1 drivers
L_0x96c856410 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28d860_0 .net/s "acc_in", 31 0, L_0x96c856410;  1 drivers
v0x96d28d900_0 .net/s "acc_out", 31 0, L_0x96c5c5cc0;  alias, 1 drivers
v0x96d28d9a0_0 .net/s "product", 15 0, L_0x96d2b6440;  1 drivers
v0x96d28da40_0 .net/s "product_ext", 31 0, L_0x96c5c5c20;  1 drivers
v0x96d28dae0_0 .net/s "w", 7 0, L_0x96c5cd220;  1 drivers
v0x96d28db80_0 .net/s "x", 7 0, L_0x96c5cd180;  1 drivers
L_0x96d2b6300 .extend/s 16, L_0x96c5cd180;
L_0x96d2b63a0 .extend/s 16, L_0x96c5cd220;
L_0x96d2b6440 .arith/mult 16, L_0x96d2b6300, L_0x96d2b63a0;
L_0x96c5cd0e0 .part L_0x96d2b6440, 15, 1;
L_0x96d2b64e0 .repeat 16, 16, L_0x96c5cd0e0;
L_0x96c5c5c20 .concat [ 16 16 0 0], L_0x96d2b6440, L_0x96d2b64e0;
L_0x96c5c5cc0 .arith/sum 32, L_0x96c856410, L_0x96c5c5c20;
S_0x96d290a80 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585840 .param/l "i" 1 6 17, +C4<01001>;
S_0x96d290c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d290a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0d80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0dc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0e00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28dc20_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6620;  1 drivers
v0x96d28dcc0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b66c0;  1 drivers
v0x96d28dd60_0 .net *"_ivl_7", 0 0, L_0x96c5cd2c0;  1 drivers
v0x96d28de00_0 .net *"_ivl_9", 15 0, L_0x96d2b6800;  1 drivers
L_0x96c856458 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28dea0_0 .net/s "acc_in", 31 0, L_0x96c856458;  1 drivers
v0x96d28df40_0 .net/s "acc_out", 31 0, L_0x96c5c5e00;  alias, 1 drivers
v0x96d28dfe0_0 .net/s "product", 15 0, L_0x96d2b6760;  1 drivers
v0x96d28e080_0 .net/s "product_ext", 31 0, L_0x96c5c5d60;  1 drivers
v0x96d28e120_0 .net/s "w", 7 0, L_0x96c5cd400;  1 drivers
v0x96d28e1c0_0 .net/s "x", 7 0, L_0x96c5cd360;  1 drivers
L_0x96d2b6620 .extend/s 16, L_0x96c5cd360;
L_0x96d2b66c0 .extend/s 16, L_0x96c5cd400;
L_0x96d2b6760 .arith/mult 16, L_0x96d2b6620, L_0x96d2b66c0;
L_0x96c5cd2c0 .part L_0x96d2b6760, 15, 1;
L_0x96d2b6800 .repeat 16, 16, L_0x96c5cd2c0;
L_0x96c5c5d60 .concat [ 16 16 0 0], L_0x96d2b6760, L_0x96d2b6800;
L_0x96c5c5e00 .arith/sum 32, L_0x96c856458, L_0x96c5c5d60;
S_0x96d290d80 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585880 .param/l "i" 1 6 17, +C4<01010>;
S_0x96d290f00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d290d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0e40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0e80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0ec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28e260_0 .net/s *"_ivl_0", 15 0, L_0x96d2b68a0;  1 drivers
v0x96d28e300_0 .net/s *"_ivl_2", 15 0, L_0x96d2b6940;  1 drivers
v0x96d28e3a0_0 .net *"_ivl_7", 0 0, L_0x96c5cd4a0;  1 drivers
v0x96d28e440_0 .net *"_ivl_9", 15 0, L_0x96d2b6a80;  1 drivers
L_0x96c8564a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28e4e0_0 .net/s "acc_in", 31 0, L_0x96c8564a0;  1 drivers
v0x96d28e580_0 .net/s "acc_out", 31 0, L_0x96c5c5f40;  alias, 1 drivers
v0x96d28e620_0 .net/s "product", 15 0, L_0x96d2b69e0;  1 drivers
v0x96d28e6c0_0 .net/s "product_ext", 31 0, L_0x96c5c5ea0;  1 drivers
v0x96d28e760_0 .net/s "w", 7 0, L_0x96c5cd5e0;  1 drivers
v0x96d28e800_0 .net/s "x", 7 0, L_0x96c5cd540;  1 drivers
L_0x96d2b68a0 .extend/s 16, L_0x96c5cd540;
L_0x96d2b6940 .extend/s 16, L_0x96c5cd5e0;
L_0x96d2b69e0 .arith/mult 16, L_0x96d2b68a0, L_0x96d2b6940;
L_0x96c5cd4a0 .part L_0x96d2b69e0, 15, 1;
L_0x96d2b6a80 .repeat 16, 16, L_0x96c5cd4a0;
L_0x96c5c5ea0 .concat [ 16 16 0 0], L_0x96d2b69e0, L_0x96d2b6a80;
L_0x96c5c5f40 .arith/sum 32, L_0x96c8564a0, L_0x96c5c5ea0;
S_0x96d291080 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c5858c0 .param/l "i" 1 6 17, +C4<01011>;
S_0x96d291200 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291080;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0f00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a0f40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a0f80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28e8a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6580;  1 drivers
v0x96d28e940_0 .net/s *"_ivl_2", 15 0, L_0x96d2b6b20;  1 drivers
v0x96d28e9e0_0 .net *"_ivl_7", 0 0, L_0x96c5cd680;  1 drivers
v0x96d28ea80_0 .net *"_ivl_9", 15 0, L_0x96d2b6c60;  1 drivers
L_0x96c8564e8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28eb20_0 .net/s "acc_in", 31 0, L_0x96c8564e8;  1 drivers
v0x96d28ebc0_0 .net/s "acc_out", 31 0, L_0x96c5c6080;  alias, 1 drivers
v0x96d28ec60_0 .net/s "product", 15 0, L_0x96d2b6bc0;  1 drivers
v0x96d28ed00_0 .net/s "product_ext", 31 0, L_0x96c5c5fe0;  1 drivers
v0x96d28eda0_0 .net/s "w", 7 0, L_0x96c5cd7c0;  1 drivers
v0x96d28ee40_0 .net/s "x", 7 0, L_0x96c5cd720;  1 drivers
L_0x96d2b6580 .extend/s 16, L_0x96c5cd720;
L_0x96d2b6b20 .extend/s 16, L_0x96c5cd7c0;
L_0x96d2b6bc0 .arith/mult 16, L_0x96d2b6580, L_0x96d2b6b20;
L_0x96c5cd680 .part L_0x96d2b6bc0, 15, 1;
L_0x96d2b6c60 .repeat 16, 16, L_0x96c5cd680;
L_0x96c5c5fe0 .concat [ 16 16 0 0], L_0x96d2b6bc0, L_0x96d2b6c60;
L_0x96c5c6080 .arith/sum 32, L_0x96c8564e8, L_0x96c5c5fe0;
S_0x96d291380 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585900 .param/l "i" 1 6 17, +C4<01100>;
S_0x96d291500 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291380;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a0fc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1000 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1040 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28eee0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6d00;  1 drivers
v0x96d28ef80_0 .net/s *"_ivl_2", 15 0, L_0x96d2b6da0;  1 drivers
v0x96d28f020_0 .net *"_ivl_7", 0 0, L_0x96c5cd860;  1 drivers
v0x96d28f0c0_0 .net *"_ivl_9", 15 0, L_0x96d2b6ee0;  1 drivers
L_0x96c856530 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28f160_0 .net/s "acc_in", 31 0, L_0x96c856530;  1 drivers
v0x96d28f200_0 .net/s "acc_out", 31 0, L_0x96c5c61c0;  alias, 1 drivers
v0x96d28f2a0_0 .net/s "product", 15 0, L_0x96d2b6e40;  1 drivers
v0x96d28f340_0 .net/s "product_ext", 31 0, L_0x96c5c6120;  1 drivers
v0x96d28f3e0_0 .net/s "w", 7 0, L_0x96c5cd9a0;  1 drivers
v0x96d28f480_0 .net/s "x", 7 0, L_0x96c5cd900;  1 drivers
L_0x96d2b6d00 .extend/s 16, L_0x96c5cd900;
L_0x96d2b6da0 .extend/s 16, L_0x96c5cd9a0;
L_0x96d2b6e40 .arith/mult 16, L_0x96d2b6d00, L_0x96d2b6da0;
L_0x96c5cd860 .part L_0x96d2b6e40, 15, 1;
L_0x96d2b6ee0 .repeat 16, 16, L_0x96c5cd860;
L_0x96c5c6120 .concat [ 16 16 0 0], L_0x96d2b6e40, L_0x96d2b6ee0;
L_0x96c5c61c0 .arith/sum 32, L_0x96c856530, L_0x96c5c6120;
S_0x96d291680 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585940 .param/l "i" 1 6 17, +C4<01101>;
S_0x96d291800 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291680;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1080 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a10c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1100 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28f520_0 .net/s *"_ivl_0", 15 0, L_0x96d2b6f80;  1 drivers
v0x96d28f5c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b7020;  1 drivers
v0x96d28f660_0 .net *"_ivl_7", 0 0, L_0x96c5cda40;  1 drivers
v0x96d28f700_0 .net *"_ivl_9", 15 0, L_0x96d2b7160;  1 drivers
L_0x96c856578 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28f7a0_0 .net/s "acc_in", 31 0, L_0x96c856578;  1 drivers
v0x96d28f840_0 .net/s "acc_out", 31 0, L_0x96c5c6300;  alias, 1 drivers
v0x96d28f8e0_0 .net/s "product", 15 0, L_0x96d2b70c0;  1 drivers
v0x96d28f980_0 .net/s "product_ext", 31 0, L_0x96c5c6260;  1 drivers
v0x96d28fa20_0 .net/s "w", 7 0, L_0x96c5cdb80;  1 drivers
v0x96d28fac0_0 .net/s "x", 7 0, L_0x96c5cdae0;  1 drivers
L_0x96d2b6f80 .extend/s 16, L_0x96c5cdae0;
L_0x96d2b7020 .extend/s 16, L_0x96c5cdb80;
L_0x96d2b70c0 .arith/mult 16, L_0x96d2b6f80, L_0x96d2b7020;
L_0x96c5cda40 .part L_0x96d2b70c0, 15, 1;
L_0x96d2b7160 .repeat 16, 16, L_0x96c5cda40;
L_0x96c5c6260 .concat [ 16 16 0 0], L_0x96d2b70c0, L_0x96d2b7160;
L_0x96c5c6300 .arith/sum 32, L_0x96c856578, L_0x96c5c6260;
S_0x96d291980 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585980 .param/l "i" 1 6 17, +C4<01110>;
S_0x96d291b00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291980;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1140 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1180 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a11c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d28fb60_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7200;  1 drivers
v0x96d28fc00_0 .net/s *"_ivl_2", 15 0, L_0x96d2b72a0;  1 drivers
v0x96d28fca0_0 .net *"_ivl_7", 0 0, L_0x96c5cdc20;  1 drivers
v0x96d28fd40_0 .net *"_ivl_9", 15 0, L_0x96d2b73e0;  1 drivers
L_0x96c8565c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d28fde0_0 .net/s "acc_in", 31 0, L_0x96c8565c0;  1 drivers
v0x96d28fe80_0 .net/s "acc_out", 31 0, L_0x96c5c6440;  alias, 1 drivers
v0x96d28ff20_0 .net/s "product", 15 0, L_0x96d2b7340;  1 drivers
v0x96d294000_0 .net/s "product_ext", 31 0, L_0x96c5c63a0;  1 drivers
v0x96d2940a0_0 .net/s "w", 7 0, L_0x96c5cdd60;  1 drivers
v0x96d294140_0 .net/s "x", 7 0, L_0x96c5cdcc0;  1 drivers
L_0x96d2b7200 .extend/s 16, L_0x96c5cdcc0;
L_0x96d2b72a0 .extend/s 16, L_0x96c5cdd60;
L_0x96d2b7340 .arith/mult 16, L_0x96d2b7200, L_0x96d2b72a0;
L_0x96c5cdc20 .part L_0x96d2b7340, 15, 1;
L_0x96d2b73e0 .repeat 16, 16, L_0x96c5cdc20;
L_0x96c5c63a0 .concat [ 16 16 0 0], L_0x96d2b7340, L_0x96d2b73e0;
L_0x96c5c6440 .arith/sum 32, L_0x96c8565c0, L_0x96c5c63a0;
S_0x96d291c80 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c5859c0 .param/l "i" 1 6 17, +C4<01111>;
S_0x96d291e00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291c80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1200 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1240 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1280 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2941e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7480;  1 drivers
v0x96d294280_0 .net/s *"_ivl_2", 15 0, L_0x96d2b7520;  1 drivers
v0x96d294320_0 .net *"_ivl_7", 0 0, L_0x96c5cde00;  1 drivers
v0x96d2943c0_0 .net *"_ivl_9", 15 0, L_0x96d2b7660;  1 drivers
L_0x96c856608 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d294460_0 .net/s "acc_in", 31 0, L_0x96c856608;  1 drivers
v0x96d294500_0 .net/s "acc_out", 31 0, L_0x96c5c6580;  alias, 1 drivers
v0x96d2945a0_0 .net/s "product", 15 0, L_0x96d2b75c0;  1 drivers
v0x96d294640_0 .net/s "product_ext", 31 0, L_0x96c5c64e0;  1 drivers
v0x96d2946e0_0 .net/s "w", 7 0, L_0x96c5cdf40;  1 drivers
v0x96d294780_0 .net/s "x", 7 0, L_0x96c5cdea0;  1 drivers
L_0x96d2b7480 .extend/s 16, L_0x96c5cdea0;
L_0x96d2b7520 .extend/s 16, L_0x96c5cdf40;
L_0x96d2b75c0 .arith/mult 16, L_0x96d2b7480, L_0x96d2b7520;
L_0x96c5cde00 .part L_0x96d2b75c0, 15, 1;
L_0x96d2b7660 .repeat 16, 16, L_0x96c5cde00;
L_0x96c5c64e0 .concat [ 16 16 0 0], L_0x96d2b75c0, L_0x96d2b7660;
L_0x96c5c6580 .arith/sum 32, L_0x96c856608, L_0x96c5c64e0;
S_0x96d291f80 .scope generate, "GEN_MAC[16]" "GEN_MAC[16]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585a00 .param/l "i" 1 6 17, +C4<010000>;
S_0x96d292100 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d291f80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a12c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1300 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1340 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d294820_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7700;  1 drivers
v0x96d2948c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2b77a0;  1 drivers
v0x96d294960_0 .net *"_ivl_7", 0 0, L_0x96c5cdfe0;  1 drivers
v0x96d294a00_0 .net *"_ivl_9", 15 0, L_0x96d2b78e0;  1 drivers
L_0x96c856650 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d294aa0_0 .net/s "acc_in", 31 0, L_0x96c856650;  1 drivers
v0x96d294b40_0 .net/s "acc_out", 31 0, L_0x96c5c66c0;  alias, 1 drivers
v0x96d294be0_0 .net/s "product", 15 0, L_0x96d2b7840;  1 drivers
v0x96d294c80_0 .net/s "product_ext", 31 0, L_0x96c5c6620;  1 drivers
v0x96d294d20_0 .net/s "w", 7 0, L_0x96c5ce120;  1 drivers
v0x96d294dc0_0 .net/s "x", 7 0, L_0x96c5ce080;  1 drivers
L_0x96d2b7700 .extend/s 16, L_0x96c5ce080;
L_0x96d2b77a0 .extend/s 16, L_0x96c5ce120;
L_0x96d2b7840 .arith/mult 16, L_0x96d2b7700, L_0x96d2b77a0;
L_0x96c5cdfe0 .part L_0x96d2b7840, 15, 1;
L_0x96d2b78e0 .repeat 16, 16, L_0x96c5cdfe0;
L_0x96c5c6620 .concat [ 16 16 0 0], L_0x96d2b7840, L_0x96d2b78e0;
L_0x96c5c66c0 .arith/sum 32, L_0x96c856650, L_0x96c5c6620;
S_0x96d292280 .scope generate, "GEN_MAC[17]" "GEN_MAC[17]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585a40 .param/l "i" 1 6 17, +C4<010001>;
S_0x96d292400 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d292280;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1380 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a13c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1400 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d294e60_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7980;  1 drivers
v0x96d294f00_0 .net/s *"_ivl_2", 15 0, L_0x96d2b7a20;  1 drivers
v0x96d294fa0_0 .net *"_ivl_7", 0 0, L_0x96c5ce1c0;  1 drivers
v0x96d295040_0 .net *"_ivl_9", 15 0, L_0x96d2b7b60;  1 drivers
L_0x96c856698 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2950e0_0 .net/s "acc_in", 31 0, L_0x96c856698;  1 drivers
v0x96d295180_0 .net/s "acc_out", 31 0, L_0x96c5c6800;  alias, 1 drivers
v0x96d295220_0 .net/s "product", 15 0, L_0x96d2b7ac0;  1 drivers
v0x96d2952c0_0 .net/s "product_ext", 31 0, L_0x96c5c6760;  1 drivers
v0x96d295360_0 .net/s "w", 7 0, L_0x96c5ce300;  1 drivers
v0x96d295400_0 .net/s "x", 7 0, L_0x96c5ce260;  1 drivers
L_0x96d2b7980 .extend/s 16, L_0x96c5ce260;
L_0x96d2b7a20 .extend/s 16, L_0x96c5ce300;
L_0x96d2b7ac0 .arith/mult 16, L_0x96d2b7980, L_0x96d2b7a20;
L_0x96c5ce1c0 .part L_0x96d2b7ac0, 15, 1;
L_0x96d2b7b60 .repeat 16, 16, L_0x96c5ce1c0;
L_0x96c5c6760 .concat [ 16 16 0 0], L_0x96d2b7ac0, L_0x96d2b7b60;
L_0x96c5c6800 .arith/sum 32, L_0x96c856698, L_0x96c5c6760;
S_0x96d292580 .scope generate, "GEN_MAC[18]" "GEN_MAC[18]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585a80 .param/l "i" 1 6 17, +C4<010010>;
S_0x96d292700 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d292580;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1440 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1480 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a14c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2954a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7c00;  1 drivers
v0x96d295540_0 .net/s *"_ivl_2", 15 0, L_0x96d2b7ca0;  1 drivers
v0x96d2955e0_0 .net *"_ivl_7", 0 0, L_0x96c5ce3a0;  1 drivers
v0x96d295680_0 .net *"_ivl_9", 15 0, L_0x96d2b7de0;  1 drivers
L_0x96c8566e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d295720_0 .net/s "acc_in", 31 0, L_0x96c8566e0;  1 drivers
v0x96d2957c0_0 .net/s "acc_out", 31 0, L_0x96c5c6940;  alias, 1 drivers
v0x96d295860_0 .net/s "product", 15 0, L_0x96d2b7d40;  1 drivers
v0x96d295900_0 .net/s "product_ext", 31 0, L_0x96c5c68a0;  1 drivers
v0x96d2959a0_0 .net/s "w", 7 0, L_0x96c5ce4e0;  1 drivers
v0x96d295a40_0 .net/s "x", 7 0, L_0x96c5ce440;  1 drivers
L_0x96d2b7c00 .extend/s 16, L_0x96c5ce440;
L_0x96d2b7ca0 .extend/s 16, L_0x96c5ce4e0;
L_0x96d2b7d40 .arith/mult 16, L_0x96d2b7c00, L_0x96d2b7ca0;
L_0x96c5ce3a0 .part L_0x96d2b7d40, 15, 1;
L_0x96d2b7de0 .repeat 16, 16, L_0x96c5ce3a0;
L_0x96c5c68a0 .concat [ 16 16 0 0], L_0x96d2b7d40, L_0x96d2b7de0;
L_0x96c5c6940 .arith/sum 32, L_0x96c8566e0, L_0x96c5c68a0;
S_0x96d292880 .scope generate, "GEN_MAC[19]" "GEN_MAC[19]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585ac0 .param/l "i" 1 6 17, +C4<010011>;
S_0x96d292a00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d292880;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1500 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1540 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1580 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d295ae0_0 .net/s *"_ivl_0", 15 0, L_0x96d2b7e80;  1 drivers
v0x96d295b80_0 .net/s *"_ivl_2", 15 0, L_0x96d2b7f20;  1 drivers
v0x96d295c20_0 .net *"_ivl_7", 0 0, L_0x96c5ce580;  1 drivers
v0x96d295cc0_0 .net *"_ivl_9", 15 0, L_0x96d2bc0a0;  1 drivers
L_0x96c856728 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d295d60_0 .net/s "acc_in", 31 0, L_0x96c856728;  1 drivers
v0x96d295e00_0 .net/s "acc_out", 31 0, L_0x96c5c6a80;  alias, 1 drivers
v0x96d295ea0_0 .net/s "product", 15 0, L_0x96d2bc000;  1 drivers
v0x96d295f40_0 .net/s "product_ext", 31 0, L_0x96c5c69e0;  1 drivers
v0x96d295fe0_0 .net/s "w", 7 0, L_0x96c5ce6c0;  1 drivers
v0x96d296080_0 .net/s "x", 7 0, L_0x96c5ce620;  1 drivers
L_0x96d2b7e80 .extend/s 16, L_0x96c5ce620;
L_0x96d2b7f20 .extend/s 16, L_0x96c5ce6c0;
L_0x96d2bc000 .arith/mult 16, L_0x96d2b7e80, L_0x96d2b7f20;
L_0x96c5ce580 .part L_0x96d2bc000, 15, 1;
L_0x96d2bc0a0 .repeat 16, 16, L_0x96c5ce580;
L_0x96c5c69e0 .concat [ 16 16 0 0], L_0x96d2bc000, L_0x96d2bc0a0;
L_0x96c5c6a80 .arith/sum 32, L_0x96c856728, L_0x96c5c69e0;
S_0x96d292b80 .scope generate, "GEN_MAC[20]" "GEN_MAC[20]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585b00 .param/l "i" 1 6 17, +C4<010100>;
S_0x96d292d00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d292b80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a15c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1600 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1640 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d296120_0 .net/s *"_ivl_0", 15 0, L_0x96d2bc140;  1 drivers
v0x96d2961c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2bc1e0;  1 drivers
v0x96d296260_0 .net *"_ivl_7", 0 0, L_0x96c5ce760;  1 drivers
v0x96d296300_0 .net *"_ivl_9", 15 0, L_0x96d2bc320;  1 drivers
L_0x96c856770 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2963a0_0 .net/s "acc_in", 31 0, L_0x96c856770;  1 drivers
v0x96d296440_0 .net/s "acc_out", 31 0, L_0x96c5c6bc0;  alias, 1 drivers
v0x96d2964e0_0 .net/s "product", 15 0, L_0x96d2bc280;  1 drivers
v0x96d296580_0 .net/s "product_ext", 31 0, L_0x96c5c6b20;  1 drivers
v0x96d296620_0 .net/s "w", 7 0, L_0x96c5ce8a0;  1 drivers
v0x96d2966c0_0 .net/s "x", 7 0, L_0x96c5ce800;  1 drivers
L_0x96d2bc140 .extend/s 16, L_0x96c5ce800;
L_0x96d2bc1e0 .extend/s 16, L_0x96c5ce8a0;
L_0x96d2bc280 .arith/mult 16, L_0x96d2bc140, L_0x96d2bc1e0;
L_0x96c5ce760 .part L_0x96d2bc280, 15, 1;
L_0x96d2bc320 .repeat 16, 16, L_0x96c5ce760;
L_0x96c5c6b20 .concat [ 16 16 0 0], L_0x96d2bc280, L_0x96d2bc320;
L_0x96c5c6bc0 .arith/sum 32, L_0x96c856770, L_0x96c5c6b20;
S_0x96d292e80 .scope generate, "GEN_MAC[21]" "GEN_MAC[21]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585b40 .param/l "i" 1 6 17, +C4<010101>;
S_0x96d293000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d292e80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1680 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a16c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1700 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d296760_0 .net/s *"_ivl_0", 15 0, L_0x96d2bc3c0;  1 drivers
v0x96d296800_0 .net/s *"_ivl_2", 15 0, L_0x96d2bc460;  1 drivers
v0x96d2968a0_0 .net *"_ivl_7", 0 0, L_0x96c5ce940;  1 drivers
v0x96d296940_0 .net *"_ivl_9", 15 0, L_0x96d2bc5a0;  1 drivers
L_0x96c8567b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d2969e0_0 .net/s "acc_in", 31 0, L_0x96c8567b8;  1 drivers
v0x96d296a80_0 .net/s "acc_out", 31 0, L_0x96c5c6d00;  alias, 1 drivers
v0x96d296b20_0 .net/s "product", 15 0, L_0x96d2bc500;  1 drivers
v0x96d296bc0_0 .net/s "product_ext", 31 0, L_0x96c5c6c60;  1 drivers
v0x96d296c60_0 .net/s "w", 7 0, L_0x96c5cea80;  1 drivers
v0x96d296d00_0 .net/s "x", 7 0, L_0x96c5ce9e0;  1 drivers
L_0x96d2bc3c0 .extend/s 16, L_0x96c5ce9e0;
L_0x96d2bc460 .extend/s 16, L_0x96c5cea80;
L_0x96d2bc500 .arith/mult 16, L_0x96d2bc3c0, L_0x96d2bc460;
L_0x96c5ce940 .part L_0x96d2bc500, 15, 1;
L_0x96d2bc5a0 .repeat 16, 16, L_0x96c5ce940;
L_0x96c5c6c60 .concat [ 16 16 0 0], L_0x96d2bc500, L_0x96d2bc5a0;
L_0x96c5c6d00 .arith/sum 32, L_0x96c8567b8, L_0x96c5c6c60;
S_0x96d293180 .scope generate, "GEN_MAC[22]" "GEN_MAC[22]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585b80 .param/l "i" 1 6 17, +C4<010110>;
S_0x96d293300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d293180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1740 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1780 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a17c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d296da0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bc640;  1 drivers
v0x96d296e40_0 .net/s *"_ivl_2", 15 0, L_0x96d2bc6e0;  1 drivers
v0x96d296ee0_0 .net *"_ivl_7", 0 0, L_0x96c5ceb20;  1 drivers
v0x96d296f80_0 .net *"_ivl_9", 15 0, L_0x96d2bc820;  1 drivers
L_0x96c856800 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d297020_0 .net/s "acc_in", 31 0, L_0x96c856800;  1 drivers
v0x96d2970c0_0 .net/s "acc_out", 31 0, L_0x96c5c6e40;  alias, 1 drivers
v0x96d297160_0 .net/s "product", 15 0, L_0x96d2bc780;  1 drivers
v0x96d297200_0 .net/s "product_ext", 31 0, L_0x96c5c6da0;  1 drivers
v0x96d2972a0_0 .net/s "w", 7 0, L_0x96c5cec60;  1 drivers
v0x96d297340_0 .net/s "x", 7 0, L_0x96c5cebc0;  1 drivers
L_0x96d2bc640 .extend/s 16, L_0x96c5cebc0;
L_0x96d2bc6e0 .extend/s 16, L_0x96c5cec60;
L_0x96d2bc780 .arith/mult 16, L_0x96d2bc640, L_0x96d2bc6e0;
L_0x96c5ceb20 .part L_0x96d2bc780, 15, 1;
L_0x96d2bc820 .repeat 16, 16, L_0x96c5ceb20;
L_0x96c5c6da0 .concat [ 16 16 0 0], L_0x96d2bc780, L_0x96d2bc820;
L_0x96c5c6e40 .arith/sum 32, L_0x96c856800, L_0x96c5c6da0;
S_0x96d293480 .scope generate, "GEN_MAC[23]" "GEN_MAC[23]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585bc0 .param/l "i" 1 6 17, +C4<010111>;
S_0x96d293600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d293480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1800 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1840 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1880 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d2973e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bc8c0;  1 drivers
v0x96d297480_0 .net/s *"_ivl_2", 15 0, L_0x96d2bc960;  1 drivers
v0x96d297520_0 .net *"_ivl_7", 0 0, L_0x96c5ced00;  1 drivers
v0x96d2975c0_0 .net *"_ivl_9", 15 0, L_0x96d2bcaa0;  1 drivers
L_0x96c856848 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d297660_0 .net/s "acc_in", 31 0, L_0x96c856848;  1 drivers
v0x96d297700_0 .net/s "acc_out", 31 0, L_0x96c5c6f80;  alias, 1 drivers
v0x96d2977a0_0 .net/s "product", 15 0, L_0x96d2bca00;  1 drivers
v0x96d297840_0 .net/s "product_ext", 31 0, L_0x96c5c6ee0;  1 drivers
v0x96d2978e0_0 .net/s "w", 7 0, L_0x96c5cee40;  1 drivers
v0x96d297980_0 .net/s "x", 7 0, L_0x96c5ceda0;  1 drivers
L_0x96d2bc8c0 .extend/s 16, L_0x96c5ceda0;
L_0x96d2bc960 .extend/s 16, L_0x96c5cee40;
L_0x96d2bca00 .arith/mult 16, L_0x96d2bc8c0, L_0x96d2bc960;
L_0x96c5ced00 .part L_0x96d2bca00, 15, 1;
L_0x96d2bcaa0 .repeat 16, 16, L_0x96c5ced00;
L_0x96c5c6ee0 .concat [ 16 16 0 0], L_0x96d2bca00, L_0x96d2bcaa0;
L_0x96c5c6f80 .arith/sum 32, L_0x96c856848, L_0x96c5c6ee0;
S_0x96d293780 .scope generate, "GEN_MAC[24]" "GEN_MAC[24]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585c00 .param/l "i" 1 6 17, +C4<011000>;
S_0x96d293900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d293780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a18c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1900 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1940 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d297a20_0 .net/s *"_ivl_0", 15 0, L_0x96d2bcb40;  1 drivers
v0x96d297ac0_0 .net/s *"_ivl_2", 15 0, L_0x96d2bcbe0;  1 drivers
v0x96d297b60_0 .net *"_ivl_7", 0 0, L_0x96c5ceee0;  1 drivers
v0x96d297c00_0 .net *"_ivl_9", 15 0, L_0x96d2bcd20;  1 drivers
L_0x96c856890 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d297ca0_0 .net/s "acc_in", 31 0, L_0x96c856890;  1 drivers
v0x96d297d40_0 .net/s "acc_out", 31 0, L_0x96c5c70c0;  alias, 1 drivers
v0x96d297de0_0 .net/s "product", 15 0, L_0x96d2bcc80;  1 drivers
v0x96d297e80_0 .net/s "product_ext", 31 0, L_0x96c5c7020;  1 drivers
v0x96d297f20_0 .net/s "w", 7 0, L_0x96c5cf020;  1 drivers
v0x96d29c000_0 .net/s "x", 7 0, L_0x96c5cef80;  1 drivers
L_0x96d2bcb40 .extend/s 16, L_0x96c5cef80;
L_0x96d2bcbe0 .extend/s 16, L_0x96c5cf020;
L_0x96d2bcc80 .arith/mult 16, L_0x96d2bcb40, L_0x96d2bcbe0;
L_0x96c5ceee0 .part L_0x96d2bcc80, 15, 1;
L_0x96d2bcd20 .repeat 16, 16, L_0x96c5ceee0;
L_0x96c5c7020 .concat [ 16 16 0 0], L_0x96d2bcc80, L_0x96d2bcd20;
L_0x96c5c70c0 .arith/sum 32, L_0x96c856890, L_0x96c5c7020;
S_0x96d293a80 .scope generate, "GEN_MAC[25]" "GEN_MAC[25]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585c40 .param/l "i" 1 6 17, +C4<011001>;
S_0x96d293c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d293a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1980 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a19c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1a00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29c0a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bcdc0;  1 drivers
v0x96d29c140_0 .net/s *"_ivl_2", 15 0, L_0x96d2bce60;  1 drivers
v0x96d29c1e0_0 .net *"_ivl_7", 0 0, L_0x96c5cf0c0;  1 drivers
v0x96d29c280_0 .net *"_ivl_9", 15 0, L_0x96d2bcfa0;  1 drivers
L_0x96c8568d8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29c320_0 .net/s "acc_in", 31 0, L_0x96c8568d8;  1 drivers
v0x96d29c3c0_0 .net/s "acc_out", 31 0, L_0x96c5c7200;  alias, 1 drivers
v0x96d29c460_0 .net/s "product", 15 0, L_0x96d2bcf00;  1 drivers
v0x96d29c500_0 .net/s "product_ext", 31 0, L_0x96c5c7160;  1 drivers
v0x96d29c5a0_0 .net/s "w", 7 0, L_0x96c5cf200;  1 drivers
v0x96d29c640_0 .net/s "x", 7 0, L_0x96c5cf160;  1 drivers
L_0x96d2bcdc0 .extend/s 16, L_0x96c5cf160;
L_0x96d2bce60 .extend/s 16, L_0x96c5cf200;
L_0x96d2bcf00 .arith/mult 16, L_0x96d2bcdc0, L_0x96d2bce60;
L_0x96c5cf0c0 .part L_0x96d2bcf00, 15, 1;
L_0x96d2bcfa0 .repeat 16, 16, L_0x96c5cf0c0;
L_0x96c5c7160 .concat [ 16 16 0 0], L_0x96d2bcf00, L_0x96d2bcfa0;
L_0x96c5c7200 .arith/sum 32, L_0x96c8568d8, L_0x96c5c7160;
S_0x96d293d80 .scope generate, "GEN_MAC[26]" "GEN_MAC[26]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585c80 .param/l "i" 1 6 17, +C4<011010>;
S_0x96d2a0000 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d293d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1a40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1a80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1ac0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29c6e0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bd040;  1 drivers
v0x96d29c780_0 .net/s *"_ivl_2", 15 0, L_0x96d2bd0e0;  1 drivers
v0x96d29c820_0 .net *"_ivl_7", 0 0, L_0x96c5cf2a0;  1 drivers
v0x96d29c8c0_0 .net *"_ivl_9", 15 0, L_0x96d2bd220;  1 drivers
L_0x96c856920 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29c960_0 .net/s "acc_in", 31 0, L_0x96c856920;  1 drivers
v0x96d29ca00_0 .net/s "acc_out", 31 0, L_0x96c5c7340;  alias, 1 drivers
v0x96d29caa0_0 .net/s "product", 15 0, L_0x96d2bd180;  1 drivers
v0x96d29cb40_0 .net/s "product_ext", 31 0, L_0x96c5c72a0;  1 drivers
v0x96d29cbe0_0 .net/s "w", 7 0, L_0x96c5cf3e0;  1 drivers
v0x96d29cc80_0 .net/s "x", 7 0, L_0x96c5cf340;  1 drivers
L_0x96d2bd040 .extend/s 16, L_0x96c5cf340;
L_0x96d2bd0e0 .extend/s 16, L_0x96c5cf3e0;
L_0x96d2bd180 .arith/mult 16, L_0x96d2bd040, L_0x96d2bd0e0;
L_0x96c5cf2a0 .part L_0x96d2bd180, 15, 1;
L_0x96d2bd220 .repeat 16, 16, L_0x96c5cf2a0;
L_0x96c5c72a0 .concat [ 16 16 0 0], L_0x96d2bd180, L_0x96d2bd220;
L_0x96c5c7340 .arith/sum 32, L_0x96c856920, L_0x96c5c72a0;
S_0x96d2a0180 .scope generate, "GEN_MAC[27]" "GEN_MAC[27]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585cc0 .param/l "i" 1 6 17, +C4<011011>;
S_0x96d2a0300 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d2a0180;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1b00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1b40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1b80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29cd20_0 .net/s *"_ivl_0", 15 0, L_0x96d2bd2c0;  1 drivers
v0x96d29cdc0_0 .net/s *"_ivl_2", 15 0, L_0x96d2bd360;  1 drivers
v0x96d29ce60_0 .net *"_ivl_7", 0 0, L_0x96c5cf480;  1 drivers
v0x96d29cf00_0 .net *"_ivl_9", 15 0, L_0x96d2bd4a0;  1 drivers
L_0x96c856968 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29cfa0_0 .net/s "acc_in", 31 0, L_0x96c856968;  1 drivers
v0x96d29d040_0 .net/s "acc_out", 31 0, L_0x96c5c7480;  alias, 1 drivers
v0x96d29d0e0_0 .net/s "product", 15 0, L_0x96d2bd400;  1 drivers
v0x96d29d180_0 .net/s "product_ext", 31 0, L_0x96c5c73e0;  1 drivers
v0x96d29d220_0 .net/s "w", 7 0, L_0x96c5cf5c0;  1 drivers
v0x96d29d2c0_0 .net/s "x", 7 0, L_0x96c5cf520;  1 drivers
L_0x96d2bd2c0 .extend/s 16, L_0x96c5cf520;
L_0x96d2bd360 .extend/s 16, L_0x96c5cf5c0;
L_0x96d2bd400 .arith/mult 16, L_0x96d2bd2c0, L_0x96d2bd360;
L_0x96c5cf480 .part L_0x96d2bd400, 15, 1;
L_0x96d2bd4a0 .repeat 16, 16, L_0x96c5cf480;
L_0x96c5c73e0 .concat [ 16 16 0 0], L_0x96d2bd400, L_0x96d2bd4a0;
L_0x96c5c7480 .arith/sum 32, L_0x96c856968, L_0x96c5c73e0;
S_0x96d2a0480 .scope generate, "GEN_MAC[28]" "GEN_MAC[28]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585d00 .param/l "i" 1 6 17, +C4<011100>;
S_0x96d2a0600 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d2a0480;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1bc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1c00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1c40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29d360_0 .net/s *"_ivl_0", 15 0, L_0x96d2bd540;  1 drivers
v0x96d29d400_0 .net/s *"_ivl_2", 15 0, L_0x96d2bd5e0;  1 drivers
v0x96d29d4a0_0 .net *"_ivl_7", 0 0, L_0x96c5cf660;  1 drivers
v0x96d29d540_0 .net *"_ivl_9", 15 0, L_0x96d2bd720;  1 drivers
L_0x96c8569b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29d5e0_0 .net/s "acc_in", 31 0, L_0x96c8569b0;  1 drivers
v0x96d29d680_0 .net/s "acc_out", 31 0, L_0x96c5c75c0;  alias, 1 drivers
v0x96d29d720_0 .net/s "product", 15 0, L_0x96d2bd680;  1 drivers
v0x96d29d7c0_0 .net/s "product_ext", 31 0, L_0x96c5c7520;  1 drivers
v0x96d29d860_0 .net/s "w", 7 0, L_0x96c5cf7a0;  1 drivers
v0x96d29d900_0 .net/s "x", 7 0, L_0x96c5cf700;  1 drivers
L_0x96d2bd540 .extend/s 16, L_0x96c5cf700;
L_0x96d2bd5e0 .extend/s 16, L_0x96c5cf7a0;
L_0x96d2bd680 .arith/mult 16, L_0x96d2bd540, L_0x96d2bd5e0;
L_0x96c5cf660 .part L_0x96d2bd680, 15, 1;
L_0x96d2bd720 .repeat 16, 16, L_0x96c5cf660;
L_0x96c5c7520 .concat [ 16 16 0 0], L_0x96d2bd680, L_0x96d2bd720;
L_0x96c5c75c0 .arith/sum 32, L_0x96c8569b0, L_0x96c5c7520;
S_0x96d2a0780 .scope generate, "GEN_MAC[29]" "GEN_MAC[29]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585d40 .param/l "i" 1 6 17, +C4<011101>;
S_0x96d2a0900 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d2a0780;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1c80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1cc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1d00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29d9a0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bd7c0;  1 drivers
v0x96d29da40_0 .net/s *"_ivl_2", 15 0, L_0x96d2bd860;  1 drivers
v0x96d29dae0_0 .net *"_ivl_7", 0 0, L_0x96c5cf840;  1 drivers
v0x96d29db80_0 .net *"_ivl_9", 15 0, L_0x96d2bd9a0;  1 drivers
L_0x96c8569f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29dc20_0 .net/s "acc_in", 31 0, L_0x96c8569f8;  1 drivers
v0x96d29dcc0_0 .net/s "acc_out", 31 0, L_0x96c5c7700;  alias, 1 drivers
v0x96d29dd60_0 .net/s "product", 15 0, L_0x96d2bd900;  1 drivers
v0x96d29de00_0 .net/s "product_ext", 31 0, L_0x96c5c7660;  1 drivers
v0x96d29dea0_0 .net/s "w", 7 0, L_0x96c5cf980;  1 drivers
v0x96d29df40_0 .net/s "x", 7 0, L_0x96c5cf8e0;  1 drivers
L_0x96d2bd7c0 .extend/s 16, L_0x96c5cf8e0;
L_0x96d2bd860 .extend/s 16, L_0x96c5cf980;
L_0x96d2bd900 .arith/mult 16, L_0x96d2bd7c0, L_0x96d2bd860;
L_0x96c5cf840 .part L_0x96d2bd900, 15, 1;
L_0x96d2bd9a0 .repeat 16, 16, L_0x96c5cf840;
L_0x96c5c7660 .concat [ 16 16 0 0], L_0x96d2bd900, L_0x96d2bd9a0;
L_0x96c5c7700 .arith/sum 32, L_0x96c8569f8, L_0x96c5c7660;
S_0x96d2a0a80 .scope generate, "GEN_MAC[30]" "GEN_MAC[30]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585d80 .param/l "i" 1 6 17, +C4<011110>;
S_0x96d2a0c00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d2a0a80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1d40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1d80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1dc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29dfe0_0 .net/s *"_ivl_0", 15 0, L_0x96d2bda40;  1 drivers
v0x96d29e080_0 .net/s *"_ivl_2", 15 0, L_0x96d2bdae0;  1 drivers
v0x96d29e120_0 .net *"_ivl_7", 0 0, L_0x96c5cfa20;  1 drivers
v0x96d29e1c0_0 .net *"_ivl_9", 15 0, L_0x96d2bdc20;  1 drivers
L_0x96c856a40 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29e260_0 .net/s "acc_in", 31 0, L_0x96c856a40;  1 drivers
v0x96d29e300_0 .net/s "acc_out", 31 0, L_0x96c5c7840;  alias, 1 drivers
v0x96d29e3a0_0 .net/s "product", 15 0, L_0x96d2bdb80;  1 drivers
v0x96d29e440_0 .net/s "product_ext", 31 0, L_0x96c5c77a0;  1 drivers
v0x96d29e4e0_0 .net/s "w", 7 0, L_0x96c5cfb60;  1 drivers
v0x96d29e580_0 .net/s "x", 7 0, L_0x96c5cfac0;  1 drivers
L_0x96d2bda40 .extend/s 16, L_0x96c5cfac0;
L_0x96d2bdae0 .extend/s 16, L_0x96c5cfb60;
L_0x96d2bdb80 .arith/mult 16, L_0x96d2bda40, L_0x96d2bdae0;
L_0x96c5cfa20 .part L_0x96d2bdb80, 15, 1;
L_0x96d2bdc20 .repeat 16, 16, L_0x96c5cfa20;
L_0x96c5c77a0 .concat [ 16 16 0 0], L_0x96d2bdb80, L_0x96d2bdc20;
L_0x96c5c7840 .arith/sum 32, L_0x96c856a40, L_0x96c5c77a0;
S_0x96d2a0d80 .scope generate, "GEN_MAC[31]" "GEN_MAC[31]" 6 17, 6 17 0, S_0x96d27ed00;
 .timescale 0 0;
P_0x96c585dc0 .param/l "i" 1 6 17, +C4<011111>;
S_0x96d2a0f00 .scope module, "u_mac" "mac_unit" 6 22, 7 1 0, S_0x96d2a0d80;
 .timescale 0 0;
    .port_info 0 /INPUT 8 "x";
    .port_info 1 /INPUT 8 "w";
    .port_info 2 /INPUT 32 "acc_in";
    .port_info 3 /OUTPUT 32 "acc_out";
P_0x96c5a1e00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000100000>;
P_0x96c5a1e40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000001000>;
P_0x96c5a1e80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
v0x96d29e620_0 .net/s *"_ivl_0", 15 0, L_0x96d2bdcc0;  1 drivers
v0x96d29e6c0_0 .net/s *"_ivl_2", 15 0, L_0x96d2bdd60;  1 drivers
v0x96d29e760_0 .net *"_ivl_7", 0 0, L_0x96c5cfc00;  1 drivers
v0x96d29e800_0 .net *"_ivl_9", 15 0, L_0x96d2bdea0;  1 drivers
L_0x96c856a88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x96d29e8a0_0 .net/s "acc_in", 31 0, L_0x96c856a88;  1 drivers
v0x96d29e940_0 .net/s "acc_out", 31 0, L_0x96c5c7980;  alias, 1 drivers
v0x96d29e9e0_0 .net/s "product", 15 0, L_0x96d2bde00;  1 drivers
v0x96d29ea80_0 .net/s "product_ext", 31 0, L_0x96c5c78e0;  1 drivers
v0x96d29eb20_0 .net/s "w", 7 0, L_0x96c5cfd40;  1 drivers
v0x96d29ebc0_0 .net/s "x", 7 0, L_0x96c5cfca0;  1 drivers
L_0x96d2bdcc0 .extend/s 16, L_0x96c5cfca0;
L_0x96d2bdd60 .extend/s 16, L_0x96c5cfd40;
L_0x96d2bde00 .arith/mult 16, L_0x96d2bdcc0, L_0x96d2bdd60;
L_0x96c5cfc00 .part L_0x96d2bde00, 15, 1;
L_0x96d2bdea0 .repeat 16, 16, L_0x96c5cfc00;
L_0x96c5c78e0 .concat [ 16 16 0 0], L_0x96d2bde00, L_0x96d2bdea0;
L_0x96c5c7980 .arith/sum 32, L_0x96c856a88, L_0x96c5c78e0;
S_0x96d2a1080 .scope task, "run_layer" "run_layer" 3 55, 3 55 0, S_0x100fce6d0;
 .timescale -9 -12;
E_0x96d18bd80 .event anyedge, v0x96d2a45a0_0;
TD_tb.run_layer ;
    %wait E_0x96d18bc40;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x96d2a4fa0_0, 0, 1;
    %wait E_0x96d18bc40;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x96d2a4fa0_0, 0, 1;
T_0.0 ;
    %load/vec4 v0x96d2a4c80_0;
    %pad/u 32;
    %pushi/vec4 1, 0, 32;
    %cmp/e;
    %flag_get/vec4 4;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_0.1, 6;
    %wait E_0x96d18bd80;
    %jmp T_0.0;
T_0.1 ;
    %wait E_0x96d18bc40;
    %end;
    .scope S_0x100fc6560;
T_1 ;
    %wait E_0x96d18bc80;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d25cf00_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d25cdc0_0, 0, 32;
T_1.0 ; Top of for-loop
    %load/vec4 v0x96d25cdc0_0;
    %cmpi/s 32, 0, 32;
	  %jmp/0xz T_1.1, 5;
    %load/vec4 v0x96d25cf00_0;
    %ix/getv/s 4, v0x96d25cdc0_0;
    %load/vec4a v0x96d25ce60, 4;
    %add;
    %store/vec4 v0x96d25cf00_0, 0, 32;
T_1.2 ; for-loop step statement
    %load/vec4 v0x96d25cdc0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d25cdc0_0, 0, 32;
    %jmp T_1.0;
T_1.1 ; for-loop exit label
    %jmp T_1;
    .thread T_1, $push;
    .scope S_0x100fcec90;
T_2 ;
    %wait E_0x96d18bc40;
    %load/vec4 v0x96d25df40_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d25dea0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d25d9a0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d25e300_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d25dc20_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d25dd60_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d25dd60_0, 0;
    %load/vec4 v0x96d25dfe0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_2.4, 9;
    %load/vec4 v0x96d25dc20_0;
    %nor/r;
    %and;
T_2.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.2, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d25dea0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d25d9a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d25dc20_0, 0;
    %jmp T_2.3;
T_2.2 ;
    %load/vec4 v0x96d25dc20_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.5, 8;
    %load/vec4 v0x96d25dea0_0;
    %pad/u 32;
    %cmpi/e 7, 0, 32;
    %jmp/0xz  T_2.7, 4;
    %load/vec4 v0x96d25de00_0;
    %assign/vec4 v0x96d25d9a0_0, 0;
    %load/vec4 v0x96d25de00_0;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz  T_2.9, 5;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d25e300_0, 0;
    %jmp T_2.10;
T_2.9 ;
    %load/vec4 v0x96d25de00_0;
    %cmpi/s 127, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_2.11, 5;
    %pushi/vec4 127, 0, 8;
    %assign/vec4 v0x96d25e300_0, 0;
    %jmp T_2.12;
T_2.11 ;
    %load/vec4 v0x96d25de00_0;
    %parti/s 8, 0, 2;
    %assign/vec4 v0x96d25e300_0, 0;
T_2.12 ;
T_2.10 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d25dc20_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d25dd60_0, 0;
    %jmp T_2.8;
T_2.7 ;
    %load/vec4 v0x96d25da40_0;
    %assign/vec4 v0x96d25d9a0_0, 0;
    %load/vec4 v0x96d25dea0_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x96d25dea0_0, 0;
T_2.8 ;
T_2.5 ;
T_2.3 ;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_0x96d259e00;
T_3 ;
    %wait E_0x96d18bcc0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d26eee0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d26eda0_0, 0, 32;
T_3.0 ; Top of for-loop
    %load/vec4 v0x96d26eda0_0;
    %cmpi/s 32, 0, 32;
	  %jmp/0xz T_3.1, 5;
    %load/vec4 v0x96d26eee0_0;
    %ix/getv/s 4, v0x96d26eda0_0;
    %load/vec4a v0x96d26ee40, 4;
    %add;
    %store/vec4 v0x96d26eee0_0, 0, 32;
T_3.2 ; for-loop step statement
    %load/vec4 v0x96d26eda0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d26eda0_0, 0, 32;
    %jmp T_3.0;
T_3.1 ; for-loop exit label
    %jmp T_3;
    .thread T_3, $push;
    .scope S_0x96d259b00;
T_4 ;
    %wait E_0x96d18bc40;
    %load/vec4 v0x96d26ff20_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d26fe80_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d26f980_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d274320_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d26fc00_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d26fd40_0, 0;
    %jmp T_4.1;
T_4.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d26fd40_0, 0;
    %load/vec4 v0x96d274000_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_4.4, 9;
    %load/vec4 v0x96d26fc00_0;
    %nor/r;
    %and;
T_4.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.2, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d26fe80_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d26f980_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d26fc00_0, 0;
    %jmp T_4.3;
T_4.2 ;
    %load/vec4 v0x96d26fc00_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.5, 8;
    %load/vec4 v0x96d26fe80_0;
    %pad/u 32;
    %cmpi/e 7, 0, 32;
    %jmp/0xz  T_4.7, 4;
    %load/vec4 v0x96d26fde0_0;
    %assign/vec4 v0x96d26f980_0, 0;
    %load/vec4 v0x96d26fde0_0;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz  T_4.9, 5;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d274320_0, 0;
    %jmp T_4.10;
T_4.9 ;
    %load/vec4 v0x96d26fde0_0;
    %cmpi/s 127, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_4.11, 5;
    %pushi/vec4 127, 0, 8;
    %assign/vec4 v0x96d274320_0, 0;
    %jmp T_4.12;
T_4.11 ;
    %load/vec4 v0x96d26fde0_0;
    %parti/s 8, 0, 2;
    %assign/vec4 v0x96d274320_0, 0;
T_4.12 ;
T_4.10 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d26fc00_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d26fd40_0, 0;
    %jmp T_4.8;
T_4.7 ;
    %load/vec4 v0x96d26fa20_0;
    %assign/vec4 v0x96d26f980_0, 0;
    %load/vec4 v0x96d26fe80_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x96d26fe80_0, 0;
T_4.8 ;
T_4.5 ;
T_4.3 ;
T_4.1 ;
    %jmp T_4;
    .thread T_4;
    .scope S_0x96d270600;
T_5 ;
    %wait E_0x96d18bd00;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d288f00_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d288dc0_0, 0, 32;
T_5.0 ; Top of for-loop
    %load/vec4 v0x96d288dc0_0;
    %cmpi/s 32, 0, 32;
	  %jmp/0xz T_5.1, 5;
    %load/vec4 v0x96d288f00_0;
    %ix/getv/s 4, v0x96d288dc0_0;
    %load/vec4a v0x96d288e60, 4;
    %add;
    %store/vec4 v0x96d288f00_0, 0, 32;
T_5.2 ; for-loop step statement
    %load/vec4 v0x96d288dc0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d288dc0_0, 0, 32;
    %jmp T_5.0;
T_5.1 ; for-loop exit label
    %jmp T_5;
    .thread T_5, $push;
    .scope S_0x96d270300;
T_6 ;
    %wait E_0x96d18bc40;
    %load/vec4 v0x96d289f40_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d289ea0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d2899a0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d28a300_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d289c20_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d289d60_0, 0;
    %jmp T_6.1;
T_6.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d289d60_0, 0;
    %load/vec4 v0x96d289fe0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_6.4, 9;
    %load/vec4 v0x96d289c20_0;
    %nor/r;
    %and;
T_6.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.2, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d289ea0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d2899a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d289c20_0, 0;
    %jmp T_6.3;
T_6.2 ;
    %load/vec4 v0x96d289c20_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.5, 8;
    %load/vec4 v0x96d289ea0_0;
    %pad/u 32;
    %cmpi/e 7, 0, 32;
    %jmp/0xz  T_6.7, 4;
    %load/vec4 v0x96d289e00_0;
    %assign/vec4 v0x96d2899a0_0, 0;
    %load/vec4 v0x96d289e00_0;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz  T_6.9, 5;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d28a300_0, 0;
    %jmp T_6.10;
T_6.9 ;
    %load/vec4 v0x96d289e00_0;
    %cmpi/s 127, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_6.11, 5;
    %pushi/vec4 127, 0, 8;
    %assign/vec4 v0x96d28a300_0, 0;
    %jmp T_6.12;
T_6.11 ;
    %load/vec4 v0x96d289e00_0;
    %parti/s 8, 0, 2;
    %assign/vec4 v0x96d28a300_0, 0;
T_6.12 ;
T_6.10 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d289c20_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d289d60_0, 0;
    %jmp T_6.8;
T_6.7 ;
    %load/vec4 v0x96d289a40_0;
    %assign/vec4 v0x96d2899a0_0, 0;
    %load/vec4 v0x96d289ea0_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x96d289ea0_0, 0;
T_6.8 ;
T_6.5 ;
T_6.3 ;
T_6.1 ;
    %jmp T_6;
    .thread T_6;
    .scope S_0x96d27ed00;
T_7 ;
    %wait E_0x96d18bd40;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d29eee0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d29eda0_0, 0, 32;
T_7.0 ; Top of for-loop
    %load/vec4 v0x96d29eda0_0;
    %cmpi/s 32, 0, 32;
	  %jmp/0xz T_7.1, 5;
    %load/vec4 v0x96d29eee0_0;
    %ix/getv/s 4, v0x96d29eda0_0;
    %load/vec4a v0x96d29ee40, 4;
    %add;
    %store/vec4 v0x96d29eee0_0, 0, 32;
T_7.2 ; for-loop step statement
    %load/vec4 v0x96d29eda0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d29eda0_0, 0, 32;
    %jmp T_7.0;
T_7.1 ; for-loop exit label
    %jmp T_7;
    .thread T_7, $push;
    .scope S_0x96d27ea00;
T_8 ;
    %wait E_0x96d18bc40;
    %load/vec4 v0x96d29ff20_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d29fe80_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d29f980_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d2a4320_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d29fc00_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d29fd40_0, 0;
    %jmp T_8.1;
T_8.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d29fd40_0, 0;
    %load/vec4 v0x96d2a4000_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_8.4, 9;
    %load/vec4 v0x96d29fc00_0;
    %nor/r;
    %and;
T_8.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.2, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x96d29fe80_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x96d29f980_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d29fc00_0, 0;
    %jmp T_8.3;
T_8.2 ;
    %load/vec4 v0x96d29fc00_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.5, 8;
    %load/vec4 v0x96d29fe80_0;
    %pad/u 32;
    %cmpi/e 7, 0, 32;
    %jmp/0xz  T_8.7, 4;
    %load/vec4 v0x96d29fde0_0;
    %assign/vec4 v0x96d29f980_0, 0;
    %load/vec4 v0x96d29fde0_0;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz  T_8.9, 5;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x96d2a4320_0, 0;
    %jmp T_8.10;
T_8.9 ;
    %load/vec4 v0x96d29fde0_0;
    %cmpi/s 127, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_8.11, 5;
    %pushi/vec4 127, 0, 8;
    %assign/vec4 v0x96d2a4320_0, 0;
    %jmp T_8.12;
T_8.11 ;
    %load/vec4 v0x96d29fde0_0;
    %parti/s 8, 0, 2;
    %assign/vec4 v0x96d2a4320_0, 0;
T_8.12 ;
T_8.10 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x96d29fc00_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x96d29fd40_0, 0;
    %jmp T_8.8;
T_8.7 ;
    %load/vec4 v0x96d29fa20_0;
    %assign/vec4 v0x96d29f980_0, 0;
    %load/vec4 v0x96d29fe80_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x96d29fe80_0, 0;
T_8.8 ;
T_8.5 ;
T_8.3 ;
T_8.1 ;
    %jmp T_8;
    .thread T_8;
    .scope S_0x100fce6d0;
T_9 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x96d2a4be0_0, 0, 1;
T_9.0 ;
    %delay 5000, 0;
    %load/vec4 v0x96d2a4be0_0;
    %inv;
    %store/vec4 v0x96d2a4be0_0, 0, 1;
    %jmp T_9.0;
T_9.1 ;
    %end;
    .thread T_9;
    .scope S_0x100fce6d0;
T_10 ;
    %vpi_call/w 3 71 "$dumpfile", "sim/parametric.vcd" {0 0 0};
    %vpi_call/w 3 72 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x100fce6d0 {0 0 0};
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x96d2a4f00_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x96d2a4fa0_0, 0, 1;
    %pushi/vec4 0, 0, 2048;
    %store/vec4 v0x96d2a50e0_0, 0, 2048;
    %pushi/vec4 0, 0, 8192;
    %store/vec4 v0x96d2a5040_0, 0, 8192;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4aa0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
    %pushi/vec4 2, 0, 32;
T_10.0 %dup/vec4;
    %cmpi/s 0, 0, 32;
    %jmp/1xz T_10.1, 5;
    %jmp/1 T_10.1, 4;
    %subi 1, 0, 32;
    %wait E_0x96d18bc40;
    %jmp T_10.0;
T_10.1 ;
    %pop/vec4 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x96d2a4f00_0, 0, 1;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
T_10.2 ; Top of for-loop
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 256, 0, 32;
	  %jmp/0xz T_10.3, 5;
    %pushi/vec4 1, 0, 8;
    %load/vec4 v0x96d2a4e60_0;
    %muli 8, 0, 32;
    %ix/vec4/s 4;
    %store/vec4 v0x96d2a50e0_0, 4, 8;
T_10.4 ; for-loop step statement
    %load/vec4 v0x96d2a4e60_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
    %jmp T_10.2;
T_10.3 ; for-loop exit label
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
T_10.5 ; Top of for-loop
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 256, 0, 32;
	  %jmp/0xz T_10.6, 5;
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 32, 0, 32;
    %flag_mov 8, 5;
    %jmp/0 T_10.8, 8;
    %pushi/vec4 1, 0, 8;
    %jmp/1 T_10.9, 8;
T_10.8 ; End of true expr.
    %pushi/vec4 0, 0, 8;
    %jmp/0 T_10.9, 8;
 ; End of false expr.
    %blend;
T_10.9;
    %pushi/vec4 0, 0, 32;
    %load/vec4 v0x96d2a4e60_0;
    %muli 8, 0, 32;
    %add;
    %ix/vec4/s 4;
    %store/vec4 v0x96d2a5040_0, 4, 8;
T_10.7 ; for-loop step statement
    %load/vec4 v0x96d2a4e60_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
    %jmp T_10.5;
T_10.6 ; for-loop exit label
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
T_10.10 ; Top of for-loop
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 256, 0, 32;
	  %jmp/0xz T_10.11, 5;
    %pushi/vec4 0, 0, 8;
    %pushi/vec4 2048, 0, 32;
    %load/vec4 v0x96d2a4e60_0;
    %muli 8, 0, 32;
    %add;
    %ix/vec4/s 4;
    %store/vec4 v0x96d2a5040_0, 4, 8;
T_10.12 ; for-loop step statement
    %load/vec4 v0x96d2a4e60_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
    %jmp T_10.10;
T_10.11 ; for-loop exit label
    %pushi/vec4 10, 0, 8;
    %ix/load 4, 8, 0;
    %flag_set/imm 4, 0;
    %store/vec4 v0x96d2a4aa0_0, 4, 8;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
T_10.13 ; Top of for-loop
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 256, 0, 32;
	  %jmp/0xz T_10.14, 5;
    %pushi/vec4 255, 0, 8;
    %pushi/vec4 4096, 0, 32;
    %load/vec4 v0x96d2a4e60_0;
    %muli 8, 0, 32;
    %add;
    %ix/vec4/s 4;
    %store/vec4 v0x96d2a5040_0, 4, 8;
T_10.15 ; for-loop step statement
    %load/vec4 v0x96d2a4e60_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
    %jmp T_10.13;
T_10.14 ; for-loop exit label
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
T_10.16 ; Top of for-loop
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 256, 0, 32;
	  %jmp/0xz T_10.17, 5;
    %load/vec4 v0x96d2a4e60_0;
    %cmpi/s 32, 0, 32;
    %flag_mov 8, 5;
    %jmp/0 T_10.19, 8;
    %pushi/vec4 4, 0, 8;
    %jmp/1 T_10.20, 8;
T_10.19 ; End of true expr.
    %pushi/vec4 0, 0, 8;
    %jmp/0 T_10.20, 8;
 ; End of false expr.
    %blend;
T_10.20;
    %pushi/vec4 6144, 0, 32;
    %load/vec4 v0x96d2a4e60_0;
    %muli 8, 0, 32;
    %add;
    %ix/vec4/s 4;
    %store/vec4 v0x96d2a5040_0, 4, 8;
T_10.18 ; for-loop step statement
    %load/vec4 v0x96d2a4e60_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4e60_0, 0, 32;
    %jmp T_10.16;
T_10.17 ; for-loop exit label
    %vpi_call/w 3 153 "$display", "\000" {0 0 0};
    %vpi_call/w 3 154 "$display", "========================================" {0 0 0};
    %vpi_call/w 3 155 "$display", "INT8 / INT32 PARAMETRIC LAYER TEST" {0 0 0};
    %vpi_call/w 3 156 "$display", "N_INPUTS  = %0d", P_0x96c5178c0 {0 0 0};
    %vpi_call/w 3 157 "$display", "N_NEURONS = %0d", P_0x96c517900 {0 0 0};
    %vpi_call/w 3 158 "$display", "PARALLEL  = %0d", P_0x96c517940 {0 0 0};
    %vpi_call/w 3 159 "$display", "DATA_WIDTH = %0d", P_0x96c517880 {0 0 0};
    %vpi_call/w 3 160 "$display", "ACC_WIDTH  = %0d", P_0x96c517840 {0 0 0};
    %vpi_call/w 3 161 "$display", "========================================" {0 0 0};
    %fork TD_tb.run_layer, S_0x96d2a1080;
    %join;
    %pushi/vec4 32, 0, 32;
    %store/vec4 v0x96d2a4dc0_0, 0, 32;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 0, 2;
    %pad/s 32;
    %load/vec4 v0x96d2a4dc0_0;
    %cmp/ne;
    %jmp/0xz  T_10.21, 6;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 0, 2;
    %vpi_call/w 3 171 "$display", "FAIL N0: got %0d expected %0d", S<0,vec4,s8>, v0x96d2a4dc0_0 {1 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
    %jmp T_10.22;
T_10.21 ;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 0, 2;
    %vpi_call/w 3 177 "$display", "PASS N0: %0d", S<0,vec4,s8> {1 0 0};
T_10.22 ;
    %pushi/vec4 10, 0, 32;
    %store/vec4 v0x96d2a4dc0_0, 0, 32;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 8, 5;
    %pad/s 32;
    %load/vec4 v0x96d2a4dc0_0;
    %cmp/ne;
    %jmp/0xz  T_10.23, 6;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 8, 5;
    %vpi_call/w 3 187 "$display", "FAIL N1: got %0d expected %0d", S<0,vec4,s8>, v0x96d2a4dc0_0 {1 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
    %jmp T_10.24;
T_10.23 ;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 8, 5;
    %vpi_call/w 3 193 "$display", "PASS N1: %0d", S<0,vec4,s8> {1 0 0};
T_10.24 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x96d2a4dc0_0, 0, 32;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 16, 6;
    %pad/s 32;
    %cmpi/ne 0, 0, 32;
    %jmp/0xz  T_10.25, 6;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 16, 6;
    %vpi_call/w 3 205 "$display", "FAIL N2: got %0d expected 0", S<0,vec4,s8> {1 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
    %jmp T_10.26;
T_10.25 ;
    %vpi_call/w 3 210 "$display", "PASS N2: 0 (ReLU)" {0 0 0};
T_10.26 ;
    %pushi/vec4 127, 0, 32;
    %store/vec4 v0x96d2a4dc0_0, 0, 32;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 24, 6;
    %pad/s 32;
    %load/vec4 v0x96d2a4dc0_0;
    %cmp/ne;
    %jmp/0xz  T_10.27, 6;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 24, 6;
    %vpi_call/w 3 224 "$display", "FAIL N3: got %0d expected %0d", S<0,vec4,s8>, v0x96d2a4dc0_0 {1 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
    %jmp T_10.28;
T_10.27 ;
    %load/vec4 v0x96d2a5180_0;
    %parti/s 8, 24, 6;
    %vpi_call/w 3 230 "$display", "PASS N3: %0d (saturation)", S<0,vec4,s8> {1 0 0};
T_10.28 ;
    %load/vec4 v0x96d2a4b40_0;
    %pad/u 32;
    %cmpi/ne 0, 0, 32;
    %jmp/0xz  T_10.29, 6;
    %vpi_call/w 3 235 "$display", "FAIL: busy still active" {0 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
T_10.29 ;
    %load/vec4 v0x96d2a4c80_0;
    %pad/u 32;
    %cmpi/ne 1, 0, 32;
    %jmp/0xz  T_10.31, 6;
    %vpi_call/w 3 240 "$display", "FAIL: done not asserted" {0 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %addi 1, 0, 32;
    %store/vec4 v0x96d2a4d20_0, 0, 32;
T_10.31 ;
    %vpi_call/w 3 244 "$display", "\000" {0 0 0};
    %vpi_call/w 3 245 "$display", "========================================" {0 0 0};
    %load/vec4 v0x96d2a4d20_0;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_10.33, 4;
    %vpi_call/w 3 248 "$display", "INT8 PARAMETRIC TEST PASSED" {0 0 0};
    %jmp T_10.34;
T_10.33 ;
    %vpi_call/w 3 250 "$display", "INT8 PARAMETRIC TEST FAILED: %0d errors", v0x96d2a4d20_0 {0 0 0};
T_10.34 ;
    %vpi_call/w 3 252 "$display", "========================================" {0 0 0};
    %vpi_call/w 3 253 "$display", "\000" {0 0 0};
    %vpi_call/w 3 255 "$finish" {0 0 0};
    %end;
    .thread T_10;
# The file index is used to find the file name in the following table.
:file_names 8;
    "N/A";
    "<interactive>";
    "-";
    "sim/parametric_tb.v";
    "rtl/layer.v";
    "rtl/neuron_parallel.v";
    "rtl/mac8.v";
    "rtl/mac_unit.v";
