micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
83 lines
4.4 KiB
TeX
83 lines
4.4 KiB
TeX
\chapter{Overview and design philosophy}
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\label{ch:overview}
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\section{From sequential accelerator to dataflow machine}
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V1 is, structurally, a single pipeline: one neuron computes at a time,
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driven by the host over SPI, one MAC group at a time, one layer at a
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time. It is fast for what it is (the V1 datasheet's own ``ECP5
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implementation'' chapter documents its real Fmax/timing-closure history),
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but it cannot keep
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more than one computational unit genuinely busy at once, and it has no
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notion of a dependency graph --- the host sequences everything.
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V2 keeps V1's own proven INT8 datapath (bit-exact, byte-for-byte reused
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math) but wraps it in a fundamentally different control architecture:
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a \textbf{Dependency Manager} tracks a graph of neuron ``jobs'', each
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with an explicit list of producer nodes it depends on; a \textbf{Neural
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Director} dispatches every node whose dependencies have resolved to
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whichever of \code{N\_SLOTS} concurrent (Memory Manager $+$ Neural
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Processor) pairs is free; a slot's completion feeds back to wake up any
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node that was waiting on it. Once a graph is loaded, the whole system
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runs autonomously --- no per-neuron host intervention.
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\section{What did NOT change}
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\begin{itemize}
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\item The INT8$\times$INT8$\to$INT32 MAC math, the balanced adder tree,
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ReLU/linear activation with saturation --- \code{neural\_processor.v}
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is a direct, bit-exact-verified port of V1's own
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\code{neuron\_parallel.v}/\code{mac8.v}/\code{mac\_unit.v}.
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\item The real PSRAM backend: \code{memory\_interface.v} and
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\code{psram\_controller.v} are reused \textbf{byte-for-byte,
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unmodified} from V1 throughout every V2 milestone --- including
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the two post-campaign optimizations (ch.~\ref{ch:mem}). V1 itself,
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as a tree (\code{hardware/v1/}), is frozen and was never touched.
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\item The target device (Lattice ECP5 \code{LFE5U-45F-8BG381C}) and the
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real-toolchain-only measurement discipline: every number in this
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datasheet is labelled \textsc{Theoretical}, \textsc{Simulated},
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\textsc{Post-P\&R measured}, or \textsc{Derived}, and no result was
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invented to make V2 look better than it measured (§\ref{ch:impl2}).
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\end{itemize}
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\section{What DID change}
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\begin{itemize}
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\item \textbf{Concurrency}: from one active neuron to \code{N\_SLOTS}
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independent Neural Processor instances, each fed by its own Memory
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Manager.
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\item \textbf{Scheduling}: from host-sequenced SPI opcodes to an on-chip
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dependency graph, resolved autonomously.
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\item \textbf{Memory backend granularity}: from byte-at-a-time fetches
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(through \code{int8\_memory\_access.v}, still frozen V1 but no
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longer instantiated in V2's own datapath) to word-level bursts
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talking to \code{memory\_interface.v} directly --- a real, measured
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2.24--2.37$\times$ speedup (ch.~\ref{ch:mem}).
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\item \textbf{Memory traffic pattern}: a new shared on-chip
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\textbf{activation cache} eliminates redundant re-fetching of an
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input vector shared by many neurons of the same layer --- a
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further real 1.66--2.00$\times$ cycle reduction, at a real, honestly
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reported Fmax cost (ch.~\ref{ch:mem}).
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\end{itemize}
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\section{The central, measured finding}
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The single most important result of this project's own benchmark
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campaign is that \textbf{V2 is memory-bound, not compute-bound}: the
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real compute-to-memory-wait ratio is on the order of 1:170--1:220, and
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the one physical PSRAM port saturates at $\approx$90\% utilization
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regardless of \code{N\_SLOTS}$\ge$2. Real parallel scaling from
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\code{N\_SLOTS}=1 to \code{N\_SLOTS}=8 is essentially flat for
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large/sustained workloads (1.05--1.06$\times$), and once real,
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place\&route-measured Fmax degradation from added routing congestion is
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also accounted for, \code{N\_SLOTS}=4 measures as \emph{slower} in real
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wall-clock time than \code{N\_SLOTS}=1 for the largest workload tested
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--- more hardware parallelism made that specific configuration worse,
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not better, because the bottleneck was never compute. This finding
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directly shaped both post-campaign optimizations in ch.~\ref{ch:mem} and
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the \code{N\_SLOTS}=2 recommendation carried throughout this datasheet.
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\begin{fnnote}[Reproducibility]
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Every real number in this datasheet traces to a specific, append-only
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log entry (\code{EXP-\textit{NNNN}}, \code{DEC-\textit{NNNN}},
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\code{ERR-\textit{NNNN}}) in \code{hardware/v2/logs/}, a specific git
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commit, and an exact toolchain command --- the same discipline applied
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throughout V1's own development.
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\end{fnnote}
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