Files

T

micheleandClaude Sonnet 5 a3ba8f93ac docs: resolve the +1V1 label mystery and close remaining schematic open items

User confirmed TLV62568 (U1) outputs 1.1V, explaining the +1V1 label
found near the VCCAUX ferrite (L2) during the schematic review: it
belongs to U1's own real output net, merely nearby on the page layout,
not routed through the ferrite. VCCAUX remains 2.5V as required by the
real Lattice datasheet.

All three schematic "open items" from the earlier review are now
resolved: TLV62568 EN (R3=499k, confirmed via BOM), the +1V1 label
(false alarm, explained above), and the JTAG pull-up array (confirmed
8 discrete 0402 parts via BOM, not a bussed package -- no polarity
limitation). Only the boot-flash net-name typo (FGPA/FPGA + SCLK/CLK)
remains as a real, open schematic fix, and the FPGA grade discrepancy
(8BG381I vs 8BG381C) remains to be confirmed.

Compiled clean (47 pages, 0 errors).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-07 19:42:46 +02:00

chapters

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

v2-en

docs: resolve the +1V1 label mystery and close remaining schematic open items

2026-09-07 19:42:46 +02:00

FPGA-Neural-Datasheet.pdf

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

FPGA-Neural-Datasheet.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

preamble.tex

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

docs: bring datasheet/ into the main repo under hardware/v2/docs

2026-09-07 05:09:14 +02:00

README.md

FPGA-Neural — Datasheet

Datasheet tecnico multicapitolo dell'engine FPGA-Neural, in italiano e inglese. Ricostruito a partire dal codice RTL, dalla documentazione e dai benchmark presenti nella repository (revisione A1, settembre 2026).

Struttura

docs/datasheet/
├── FPGA-Neural-Datasheet.pdf        ← PDF italiano (36 pagine)
├── FPGA-Neural-Datasheet.tex        ← sorgente principale (IT)
├── preamble.tex                     ← stili, palette, box, TikZ
├── chapters/                        ← 14 capitoli (IT)
└── en/
    ├── FPGA-Neural-Datasheet-EN.pdf ← PDF inglese (36 pagine)
    ├── FPGA-Neural-Datasheet-EN.tex ← sorgente principale (EN)
    ├── preamble.tex                 ← stili (EN)
    └── chapters/                    ← 14 capitoli (EN)

Compilazione

Serve una distribuzione LaTeX con pgfplots, tikz-timing, tcolorbox, ltablex, listings, babel.

# Italiano
cd docs/datasheet
pdflatex FPGA-Neural-Datasheet.tex
pdflatex FPGA-Neural-Datasheet.tex   # 2ª passata per indice e riferimenti

# Inglese
cd docs/datasheet/en
pdflatex FPGA-Neural-Datasheet-EN.tex
pdflatex FPGA-Neural-Datasheet-EN.tex

Nota sul pinout

Il capitolo Progetto hardware e mappa dei segnali riporta l'analisi completa segnale-per-segnale del top-level spi_neuron_top, con la colonna Ball compilata con assegnazioni CABGA381 reali (53 segnali, .lpf reale in synth/) e verificata da un place&route reale (nextpnr-ecp5, 0 errori di vincolo, Program finished normally) — non più auto-piazzate.