micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
63 lines
4.2 KiB
TeX
63 lines
4.2 KiB
TeX
\chapter{Roadmap and development status}
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\label{ch:roadmap}
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\section{Milestones M1--M10}
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\begin{tabularx}{\textwidth}{C{1.0cm} L{3.6cm} C{1.3cm} Y}
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\toprule
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\rowh \thd{M} & \thd{Title} & \thd{Status} & \thd{Content} \\
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\midrule
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1 & Neural Processor & \OK & Bit-exact 8-stage pipeline vs.\ V1, 7/7 tests; 183.12~MHz isolated. \\
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\rowa 2 & Processor Array & \OK & 1/2/4/8 processors, real concurrent-slot simulation; DSP (not LUT/FF) found to saturate first. \\
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3 & Buffers & \OK & \code{activation\_buffer}/\code{weight\_buffer}/\code{result\_buffer}, real \code{DP16KD} inference --- superseded in the real datapath by the Activation Cache (\S\ref{sec:roadmapcache}). \\
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\rowa 4 & Memory Manager & \OK & Double-buffered prefetch, real V1 PSRAM chain, 3 real RTL bugs found/fixed. \\
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5 & Neural Director & \OK & First-free dispatch, real backpressure, 4/4 tests. \\
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\rowa 6 & Dependency Manager & \OK & Multi-dependency/shared-producer wake-up, 4/4 tests. \\
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7 & Dataflow Core & \OK & Full M1--M6 integration, wake-up loop closed end-to-end. \\
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\rowa 8 & PSRAM integration & \OK & Real, shared PSRAM across concurrent slots; 1 real arbiter bug found/fixed (dropped request under contention). \\
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9 & Full benchmark & \OK & V1 vs.\ V2 comparison, every number classified. \\
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\rowa 10 & Optimization & \OK & N\_SLOTS ceiling (DSP), ACC\_WIDTH 6-seed sweep, real stall/utilization instrumentation. \\
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\bottomrule
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\end{tabularx}
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\section{Post-campaign: user-requested optimizations}
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\label{sec:roadmapcache}
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Following M9/M10's own final benchmark campaign
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(\code{hardware/v2/docs/benchmarks/final-benchmark.md}), two concrete
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optimizations were implemented and measured against the real toolchain:
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\begin{enumerate}
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\item \textbf{Word-level burst reads} (ch.~\ref{ch:mem}, \S\ref{sec:burst}):
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real 2.24--2.37$\times$ wall-clock speedup, negligible Fmax cost.
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\item \textbf{Shared activation cache} (ch.~\ref{ch:mem},
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\S\ref{sec:cache}): a further real 1.66--2.00$\times$ cycle
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reduction, at a real, steep Fmax cost that makes
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\code{N\_SLOTS}=4 fail 80\,MHz outright.
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\end{enumerate}
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Combined: \textbf{2.45$\times$} real wall-clock speedup at
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\code{N\_SLOTS}=2 (recommended) over the pre-optimization baseline, which
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was itself already 2.6$\times$ faster than V1.
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\section{Open work items (real, not hidden)}
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\begin{tabularx}{\textwidth}{L{3.6cm} Y}
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\toprule
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\rowh \thd{Item} & \thd{Why it is open} \\
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\midrule
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Activation cache pipelining & The concrete fix for \code{N\_SLOTS}=4's Fmax failure: register the hit-detection/broadcast logic to break its single-cycle combinational path. Not attempted this round --- \code{N\_SLOTS}=4 delivers no real throughput benefit anyway (memory-bound), so this protects \code{N\_SLOTS}=2's own margin rather than making 4 useful. \\
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\rowa Dependency Manager node-slot reclamation & \code{ST\_DISPATCHED} is terminal; a real long-running system will eventually exhaust \code{N\_NODES}. \\
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Scheduler fairness & Fixed lowest-index priority shows real, measured per-slot imbalance under sustained contention (ch.~\ref{ch:sched}); no fairness-aware alternative has been measured yet. \\
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\rowa Second physical PSRAM bank & The only real way to raise the memory-bandwidth ceiling itself, rather than use existing bandwidth more efficiently --- a board-level change, not attempted this round. \\
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Real host driver \& pinout & No physical transport or placed pin assignment exists for the node-registration bus (ch.~\ref{ch:host}, ch.~\ref{ch:hw}). \\
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\rowa Per-node bias/activation & Every job currently hardcodes \code{bias=0}/\code{ACT\_RELU}; not yet exposed by the Dependency Manager's own job descriptor. \\
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Power/energy characterization & No ECP5 power estimator available in this toolchain; honestly reported as \textsc{Not measured}, not invented. \\
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\bottomrule
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\end{tabularx}
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\begin{fnnote}[Every claim in this datasheet traces to a log entry]
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\code{hardware/v2/logs/}: \code{development.log}, \code{simulation.log},
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\code{synthesis.log}, \code{timing.log}, \code{benchmark.log},
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\code{decisions.log} (\code{DEC-\textit{NNNN}}), \code{experiments.log}
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(\code{EXP-\textit{NNNN}}), \code{errors.log} (\code{ERR-\textit{NNNN}}).
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IDs are never reused, past results are never overwritten, even failed
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ones --- the same discipline V1's own \code{docs/validation/} campaign
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followed.
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\end{fnnote}
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