micheleandClaude Sonnet 5
7728a6c796
Establishes the real ESP32<->ECP5 programming architecture: flash #1 (neural-network data, existing V1 subsystem, ball reserved not yet wired into V2) stays separate from flash #2 (boot bitstream, MSPI auto-boot, CFG[2:0]=[0,1,0]); ESP32 talks JTAG only (bit-banged, no hardware JTAG-master peripheral on S3/C6), updating flash #2 through the ECP5's own internal sysCONFIG-to-SPI bridge, never driving the flash pins directly -- zero bus contention, confirmed against the real Lattice hardware checklist and sysCONFIG user guide. Adds real, verified ball assignments (official Lattice CABGA381 CSV + Project Trellis iodb.json) for JTAG, PROGRAMN/INITN/DONE, CFG[2:0], and the MSPI dedicated pins -- all written to docs/pinouts.md. Implements FPGA_DATA_READY as real RTL: a system-idle detector (dependency_manager's any_pending OR neural_director's !queue_empty OR any active slot), sticky on the busy->idle edge, self-clearing on new work -- not a per-neuron completion pulse, which was confirmed too fine-grained. Bit-exact regression re-verified at N_SLOTS=4 and 8 (zero cycle-count change), new explicit data_ready assertion check added to the D-Stress testbench (PASS both configs), and a fresh Yosys+nextpnr-ecp5 placement check (0 errors, data_ready placed at G3). Also fixes a real, independently-found bug while editing an adjacent file: nms_neural_multiprocessor_sdram_unified.v's own sdram_a port was still [11:0] (12 bits), stale from before the 64MB/13-bit memory upgrade. Not exercised by the real board-level top (which wires SDRAM directly, bypassing this wrapper) but WAS silently truncating A12 in every D-Stress simulation this session, including today's earlier ERR-0029 verification runs. Assessed impact: all D-Stress test addresses used this session decode to rows under 4096 (bit 12 never actually needed), so no false-positive PASS is believed to have resulted -- but the full 64MB space was never actually exercised through this wrapper. Fixed; re-verified bit-exact with identical cycle counts. See decisions.log DEC-0041 for full detail. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
FPGA-Neural — Datasheet
Datasheet tecnico multicapitolo dell'engine FPGA-Neural, in italiano e inglese. Ricostruito a partire dal codice RTL, dalla documentazione e dai benchmark presenti nella repository (revisione A1, settembre 2026).
Struttura
docs/datasheet/
├── FPGA-Neural-Datasheet.pdf ← PDF italiano (36 pagine)
├── FPGA-Neural-Datasheet.tex ← sorgente principale (IT)
├── preamble.tex ← stili, palette, box, TikZ
├── chapters/ ← 14 capitoli (IT)
└── en/
├── FPGA-Neural-Datasheet-EN.pdf ← PDF inglese (36 pagine)
├── FPGA-Neural-Datasheet-EN.tex ← sorgente principale (EN)
├── preamble.tex ← stili (EN)
└── chapters/ ← 14 capitoli (EN)
Compilazione
Serve una distribuzione LaTeX con pgfplots, tikz-timing, tcolorbox,
ltablex, listings, babel.
# Italiano
cd docs/datasheet
pdflatex FPGA-Neural-Datasheet.tex
pdflatex FPGA-Neural-Datasheet.tex # 2ª passata per indice e riferimenti
# Inglese
cd docs/datasheet/en
pdflatex FPGA-Neural-Datasheet-EN.tex
pdflatex FPGA-Neural-Datasheet-EN.tex
Nota sul pinout
Il capitolo Progetto hardware e mappa dei segnali riporta l'analisi completa
segnale-per-segnale del top-level spi_neuron_top, con la colonna Ball
compilata con assegnazioni CABGA381 reali (53 segnali, .lpf reale in
synth/) e verificata da un place&route reale (nextpnr-ecp5, 0 errori di
vincolo, Program finished normally) — non più auto-piazzate.