micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
78 lines
4.0 KiB
TeX
78 lines
4.0 KiB
TeX
\chapter{Register-level interface \& internal state encodings}
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\label{ch:regs}
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\begin{fnwarn}[No SPI register map in this revision]
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V1's own quick-reference chapter documents a real SPI opcode/register
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map (\code{STATUS}, \code{SET\_BASE}, \code{READ\_CONFIG}, \ldots). V2 has
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no equivalent yet (ch.~\ref{ch:host}) --- this chapter instead documents
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the \textbf{node-registration field layout} (repeated here for quick
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reference) and the \textbf{internal FSM state encodings} exposed by each
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module, useful for simulation-level debug and for a future host driver.
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\end{fnwarn}
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\section{Node registration fields (quick reference)}
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See ch.~\ref{ch:host} for the full field-level description.
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\code{reg\_node\_id}, \code{reg\_required}, \code{reg\_producer\_ids},
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\code{reg\_x\_base}, \code{reg\_w\_base}, \code{reg\_n\_tiles},
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\code{reg\_result\_addr} --- valid/ready handshake, \code{reg\_ready}
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gated on the target node id's table slot being \code{EMPTY}.
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\section{Dependency Manager node state (\texttt{node\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.6cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{2'd0} & \code{ST\_EMPTY} & Table slot free; \code{reg\_ready} asserted for this node id. \\
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\rowa \op{2'd1} & \code{ST\_WAITING} & Registered, at least one producer not yet resolved. \\
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\op{2'd2} & \code{ST\_READY} & All producers resolved; eligible for dispatch. \\
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\rowa \op{2'd3} & \code{ST\_DISPATCHED} & Handed to the Director; \textbf{terminal} (\S\ref{ch:sched}). \\
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\bottomrule
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\end{tabularx}
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\section{Neural Director state (\texttt{dir\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.6cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{4'd0} & \code{DIR\_IDLE} & Reset/startup. \\
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\rowa \op{4'd1} & \code{DIR\_SCAN\_READY} & Checking whether a queued job and a free slot both exist. \\
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\op{4'd2} & \code{DIR\_ALLOCATE} & Dispatching the head-of-queue job to the first free slot. \\
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\rowa \op{4'd3} & \code{DIR\_ERROR} & Recoverable only via reset (an isolated fault never blocks other slots). \\
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\bottomrule
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\end{tabularx}
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\section{Memory Manager state (\texttt{state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{3.0cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{3'd0} & \code{MM\_IDLE} & Waiting for \code{job\_start}. \\
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\rowa \op{3'd1} & \code{MM\_PREFETCH\_FIRST} & Waiting for tile~0's activation \emph{and} weight halves to both arrive. \\
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\op{3'd2} & \code{MM\_STREAM} & Presenting tiles to the Neural Processor, double-buffering the next one. \\
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\rowa \op{3'd3} & \code{MM\_WAIT\_RESULT} & Last tile handed off; waiting for the Neural Processor's own result. \\
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\op{3'd4} & \code{MM\_WRITE\_RESULT} & Issuing the real PSRAM word write for the INT8 result. \\
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\rowa \op{3'd5} & \code{MM\_DONE} & Waiting for the write's own \code{mem\_ready}; then pulses \code{job\_done}. \\
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\bottomrule
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\end{tabularx}
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\section{Neural Processor state (\texttt{np\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.8cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{4'd0} & \code{NP\_IDLE} & No job in flight. \\
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\rowa \op{4'd1} & \code{NP\_LOAD\_JOB} & Latching \code{job\_bias}/\code{job\_activation}, clearing the accumulator. \\
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\op{4'd2} & \code{NP\_WAIT\_OPERANDS} & Consuming tiles as they arrive (absorbs the per-tile MAC/accumulate/next-tile sequence). \\
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\rowa \op{4'd3} & \code{NP\_FINISH} & Draining the pipeline after \code{tile\_last}. \\
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\op{4'd4} & \code{NP\_WRITE\_RESULT} & Result available for the Memory Manager to consume. \\
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\rowa \op{4'd5} & \code{NP\_DONE} & Job complete. \\
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\op{4'd6} & \code{NP\_ERROR} & Reachable only via an unreachable \code{default} case --- isolated per-processor, never blocks other slots. \\
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\bottomrule
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\end{tabularx}
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\section{Slot Memory Arbiter owner encoding}
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\code{owner} is \code{0} for ``no port granted'', or (port index $+1$)
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for the currently-granted port --- indices \code{0..N\_SLOTS-1} are the
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per-slot Memory Managers' own weight/write-back traffic; index
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\code{N\_SLOTS} is the shared Activation Cache's own traffic.
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