micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
120 lines
5.8 KiB
TeX
120 lines
5.8 KiB
TeX
\chapter{Hardware and board}
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\label{ch:hw}
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\section{Unchanged from V1}
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V2 targets the identical board and component set as V1: Lattice ECP5
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\code{LFE5U-45F-8BG381C} ($-8$, CABGA381), ISSI
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\code{IS66WVE4M16EBLL-70BLI} PSRAM (64\,Mb, 4M$\times$16), same 16\,MHz
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reference oscillator. The real PSRAM controller
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(\code{psram\_controller.v}) and its byte$\leftrightarrow$word adapter
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(\code{memory\_interface.v}) are reused byte-for-byte, unmodified, from
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\code{hardware/v1/} throughout every V2 milestone --- their real,
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already-verified electrical/timing requirements and page-mode behavior
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are unchanged, because the controller itself was never touched.
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\begin{fnnote}[Real ball assignment: defer to V1's own chapter]
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V1's own hardware chapter documents a real, \code{iodb.json}-verified,
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place\&route-confirmed ball assignment for every PSRAM signal
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(\code{psram\_a}, \code{psram\_dq}, \code{psram\_ce\_n/oe\_n/we\_n/
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lb\_n/ub\_n/zz\_n}). Since V2's own \code{neural\_multiprocessor.v}
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drives these signals through the identical, unmodified controller, that
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same real ball assignment applies unchanged if V2 is deployed on the
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same physical board --- it is not repeated here to avoid maintaining two
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copies of the same real data; see the V1 datasheet directly.
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\end{fnnote}
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\section{What V2 has not yet placed on real hardware}
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As stated in ch.~\ref{ch:host}, V2's own node-registration bus has no
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physical pin assignment in this revision --- every V2 characterization
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to date used either a Verilator testbench or an unconstrained
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(\code{--lpf-allow-unconstrained}) synthesis top-level. A real deployment
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would need:
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\begin{itemize}
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\item A physical host transport for the registration bus (ch.~\ref{ch:host}).
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\item A real, constrained \code{nextpnr-ecp5} place\&route run
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producing a genuine \code{.lpf}/ball assignment for
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\code{neural\_multiprocessor.v}'s own top-level pins, analogous to
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V1's own \code{tools/pinout/gen\_lpf.py} flow.
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\item Re-verification that the real Fmax numbers in ch.~\ref{ch:impl2}
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(obtained unconstrained) hold once real pin locations are fixed ---
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pin placement can itself affect routing and therefore Fmax.
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\end{itemize}
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\section{Power supply, oscillator, configuration}
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Unchanged from V1: same board-level power sequencing, same oscillator,
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same JTAG/config-SPI boot path (fixed-function dedicated pins, outside
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RTL scope). No V2-specific hardware change was made or is required
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beyond the (not yet placed) registration-bus transport above.
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\section{SDRAM upgrade addendum (2026-09-07) --- current, authoritative
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board state}
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\label{sec:sdram-addendum}
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\begin{fnwarn}[This section supersedes the PSRAM description above for
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the current hardware baseline]
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The sections above describe an earlier V2 milestone that still reused
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V1's own PSRAM chain unconstrained. The project has since made a
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closed architectural decision (real \code{decisions.log} DEC-0034) to
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replace external memory with a single SDR SDRAM device, and has since
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upgraded that device's capacity and re-verified real, constrained
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place\&route timing. This section is the current, real, measured state
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--- see \code{hardware/v2/docs/MEMORY\_UPGRADE\_64MB\_N8.md} in the
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repository for the full investigation.
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\end{fnwarn}
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\subsection{Memory device}
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\textbf{Alliance Memory AS4C32M16SB-7BIN} --- 512\,Mbit (64\,MByte) SDR
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SDRAM, organized 4 banks $\times$ 8M words $\times$ 16 bits, 54-ball
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FBGA package (8$\times$8$\times$1.2\,mm max), $-40$ to $85^{\circ}$C
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industrial, $-7$ speed grade (143\,MHz max). VDD/VDDQ 3.3\,V $\pm$0.3\,V.
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Single-ended \code{CLK} --- \textbf{no \code{CLK\_N}}, this is SDR, not
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DDR, SDRAM. Real distributor availability confirmed: DigiKey product
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11613071, 568 units in stock, \$31.12/unit (qty 1), 16-week
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manufacturer lead time.
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\subsection{Complete AS4C32M16SB-7BIN ball assignment}
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From the manufacturer's own \code{-7BIN}-specific datasheet (Alliance
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Memory, Rev.\,1.4, June 2024, Figure~1.1 --- the real TFBGA ball
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diagram, not inferred from the TSOP-II \code{-7TIN} pinout).
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\begin{fnnote}[Address / Bank]
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A0=H7, A1=H8, A2=J8, A3=J7, A4=J3, A5=J2, A6=H3, A7=H2, A8=H1, A9=G3,
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A10/AP=H9, A11=G2, A12=G1, BA0=G7, BA1=G8.
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\end{fnnote}
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\begin{fnnote}[Data / Masks]
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DQ0=A8, DQ1=B9, DQ2=B8, DQ3=C9, DQ4=C8, DQ5=D9, DQ6=D8, DQ7=E9, DQ8=E1,
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DQ9=D2, DQ10=D1, DQ11=C2, DQ12=C1, DQ13=B2, DQ14=B1, DQ15=A2, LDQM=E8,
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UDQM=F1.
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\end{fnnote}
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\begin{fnnote}[Control / Power]
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CLK=F2, CKE=F3, CS\#=G9, RAS\#=F8, CAS\#=F7, WE\#=F9. VDD=\{A9,E7,J9\},
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VSS=\{A1,E3,J1\}, VDDQ=\{A7,B3,C7,D3\}, VSSQ=\{A3,B7,C3,D7\}, NC=E2.
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\end{fnnote}
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\subsection{FPGA $\leftrightarrow$ SDRAM mapping (real, LPF-verified)}
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From \code{hardware/v2/constraints/v2\_board\_top.lpf} (45/45 unique
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FPGA balls, no duplicates, LFE5U-45F-8BG381 rev.\,3.0 CSV-verified).
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\begin{fnnote}[FPGA ball $\to$ SDRAM ball, by signal group]
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\code{sdram\_a[0..12]}: D5,D3,F4,E5,E3,F5,A2,B1,C2,C1,D2,D1,F1 $\to$
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A0..A12 (H7,H8,J8,J7,J3,J2,H3,H2,H1,G3,H9,G2,G1). \code{sdram\_ba[0:1]}:
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E4,C3 $\to$ BA0,BA1 (G7,G8). \code{sdram\_dq[0..15]}:
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E1,G5,H3,J5,K3,K2,H1,J1,K1,K4,L4,L5,M5,M4,N4,N5 $\to$ DQ0..DQ15.
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\code{sdram\_dqm[0:1]}: P5,N3 $\to$ LDQM,UDQM. Control:
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\code{sdram\_cke/cs\_n/ras\_n/cas\_n/we\_n}: B5,C5,C4,A3,B3 $\to$
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CKE,CS\#,RAS\#,CAS\#,WE\#.
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\end{fnnote}
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\subsection{Real, measured clock closure (nextpnr-ecp5, 8 seeds/config)}
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\begin{tabularx}{\textwidth}{L{4.0cm} C{1.6cm} C{2.2cm} X}
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\toprule
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\rowh \thd{Configuration} & \thd{Pass} & \thd{Worst Fmax} & \thd{Notes} \\
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\midrule
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N\_SLOTS=4 @ 64\,MHz & 8/8 & 66.58\,MHz & Production baseline, GO \\
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\rowa N\_SLOTS=8 @ 64\,MHz & 5/8 & 60.12\,MHz & Open, not production-frozen \\
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N\_SLOTS=4/8 @ 80\,MHz & 0/8 & --- & NO-GO, genuine \code{ecppll}-regenerated PLL \\
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\bottomrule
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\end{tabularx}
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Real, measured after the ERR-0029 weight-cache hit-index optimization
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(serial priority scan $\to$ flat one-hot compare); see
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\code{hardware/v2/logs/errors.log} and \code{decisions.log} DEC-0040.
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