micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
55 lines
2.3 KiB
TeX
55 lines
2.3 KiB
TeX
\thispagestyle{plain}
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\noindent
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\begin{tikzpicture}
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\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
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minimum width=\textwidth,anchor=west]
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{\large\bfseries Pinout summary --- scope and honesty note};
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\end{tikzpicture}
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\vspace{6pt}
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\noindent
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{\footnotesize
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V2's top-level module, \code{neural\_multiprocessor.v}, has been
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synthesized and placed\&routed \textbf{unconstrained}
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(\code{nextpnr-ecp5 --lpf-allow-unconstrained}) throughout this project's
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own real-toolchain characterization: every Fmax/resource number in this
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datasheet is real and measured, but \textbf{no ball-by-ball pin
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assignment (\code{.lpf}) has been generated for V2's top level in this
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revision}. Unlike V1's own pinout chapter (which reports a real,
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\code{iodb.json}-verified ball map from a constrained place\&route run),
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this chapter reports what is \textbf{honestly known} and nothing
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invented.
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}
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\vspace{6pt}
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\begin{fnnote}[What is real and reusable]
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V2's PSRAM-facing pins (\code{psram\_a}, \code{psram\_dq},
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\code{psram\_ce\_n/oe\_n/we\_n/lb\_n/ub\_n/zz\_n}) drive the exact same,
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real, unmodified V1 backend chain (\code{memory\_interface.v} $\to$
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\code{psram\_controller.v}) as V1's own \code{spi\_neuron\_top}. If V2 is
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deployed on the same board, \textbf{V1's own real, verified ball
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assignment for these signals (ch.~10 of the V1 datasheet) applies
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unchanged} --- the controller was never touched, so its pin requirements
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did not change either.
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\end{fnnote}
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\begin{fnwarn}[What is NOT yet real]
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The node-registration bus (\code{reg\_valid}, \code{reg\_node\_id},
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\code{reg\_required}, \code{reg\_producer\_ids}, \code{reg\_x\_base},
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\code{reg\_w\_base}, \code{reg\_n\_tiles}, \code{reg\_result\_addr},
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\code{reg\_ready}) has no assigned physical pins in this revision: every
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V2 measurement to date drove this bus directly from a Verilator
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testbench or an unconstrained synthesis top-level, never through a real
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host-facing SPI (or other) interface with its own placed pinout. Framing
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this bus as a real, deployable host interface (analogous to V1's SPI
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Mode~0 slave) is explicitly \textbf{future work} --- see
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ch.~\ref{ch:roadmap}.
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\end{fnwarn}
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\vspace{4pt}
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\noindent
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{\footnotesize\color{fnGrey}
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Logical (not physical) port list and field widths: ch.~\ref{ch:regs}
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(``Register-level interface''). Real PSRAM signal reuse and board
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wiring: ch.~\ref{ch:hw}.\par}
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