micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
79 lines
4.0 KiB
TeX
79 lines
4.0 KiB
TeX
\chapter[Arbitration and top-level]{Arbitration and top-level integration}
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\label{ch:top}
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\section{\texttt{mem\_arbiter} --- three-port arbiter}
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A single byte-level memory master (which feeds the shared chain
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\code{int8\_memory\_access} $\to$ \code{memory\_interface} $\to$ \code{psram\_controller})
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is arbitrated among three requesters:
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\begin{tabularx}{\textwidth}{C{1.3cm} L{3.4cm} Y}
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\toprule
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\rowh \thd{Port} & \thd{Master} & \thd{Accesses} \\
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\midrule
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A & \code{spi\_engine} & \op{WRITE\_RAM} / \op{READ\_RAM}. \\
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\rowa B & \code{neuron\_memory} & X/W/bias reads during an execution. \\
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C & \code{layer\_sequencer} & Descriptor reads + buffer writes between layers. \\
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\bottomrule
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\end{tabularx}
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Fixed priority \textbf{B $>$ C $>$ A}: an inference in progress is more critical than the
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sequencer's bookkeeping, which in turn is more critical than a manual SPI access that has
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just arrived. In normal operation B and C are anyway temporally disjoint
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(\code{neuron\_memory} requests only during an execution, \code{layer\_sequencer} only in
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the pauses between layers), so the priority matters mostly for the corner case of a
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manual \op{WRITE\_RAM}/\op{READ\_RAM} arriving during a multi-layer execution.
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=6mm]
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\node[fnblock,minimum width=30mm](a){Port A --- \code{spi\_engine}};
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\node[fnblock,below=4mm of a,minimum width=30mm](b){Port B --- \code{neuron\_memory}};
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\node[fnblock,below=4mm of b,minimum width=30mm](c){Port C --- \code{layer\_sequencer}};
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\node[fnblockD,right=16mm of b,minimum width=26mm,minimum height=16mm](arb){\code{mem\_arbiter}\\{\scriptsize B$>$C$>$A}};
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\node[fnblockT,right=14mm of arb,minimum width=26mm](m){shared memory\\{\scriptsize chain}};
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\draw[fnarrow] (a)-|(arb.west|-a); \draw[fnarrow] (b)--(arb.west);
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\draw[fnarrow] (c)-|(arb.west|-c);
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\draw[fnbus] (arb)--(m);
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\end{tikzpicture}
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\end{center}
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Once access is granted, the arbiter retains ownership until the single transaction's
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\code{m\_ready} pulse, then releases: all three masters emit \code{req} as a clean
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one-cycle pulse, so a queue-less grant-and-forward design suffices.
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\section{\texttt{spi\_neuron\_top} --- full integration}
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The top-level connects SPI (\code{spi\_slave}+\code{spi\_engine}), the arbiter, the
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sequencer, \code{neuron\_memory} and the PSRAM chain. The reset of \code{neuron\_memory}
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is the OR of the global reset with the soft-reset pulse of the \op{RESET} opcode, so the
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host can recover the engine over SPI without a physical reset (the RAM stays intact).
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=7mm]
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\node[fnblockA,minimum width=22mm](ss){\code{spi\_slave}};
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\node[fnblockA,right=8mm of ss,minimum width=22mm](se){\code{spi\_engine}};
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\node[fnblockT,below=8mm of se,minimum width=26mm](sq){\code{layer\_sequencer}};
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\node[fnblockD,right=10mm of se,minimum width=24mm](mux){ctrl MUX\\{\scriptsize on \code{seq\_busy}}};
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\node[fnblock,below=8mm of mux,minimum width=26mm](nm){\code{neuron\_memory}};
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\node[fnblockD,right=10mm of mux,minimum width=22mm](arb){\code{mem\_arbiter}};
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\node[fnblockA,right=8mm of arb,minimum width=26mm](mem){PSRAM chain};
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\draw[fnarrow] (ss)--(se);
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\draw[fnarrow] (se)--(mux);
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\draw[fnarrow] (sq)--(mux);
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\draw[fnarrow] (mux)--(nm);
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\draw[fnarrow] (se.south) to[bend right=10] (arb.north west);
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\draw[fnarrow] (nm)--(arb);
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\draw[fnarrow] (sq.east) to[bend right=20] (arb.south west);
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\draw[fnbus] (arb)--(mem);
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\end{tikzpicture}
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\end{center}
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The multiplexer switches the control lines of \code{neuron\_memory} between the sequencer
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(while \code{seq\_busy} is high) and the direct path of \code{spi\_engine} (legacy
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single-layer mode), returning the engine to the direct path at the end of the sequence.
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\begin{fnnote}[End-to-end verification]
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\code{spi\_neuron\_top} is verified in simulation with real PSRAM
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(\code{psram\_model.v}, no mock): RESET/READ\_CONFIG/WRITE\_RAM/READ\_RAM/SET\_BASE/
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START/STATUS/READ\_OUTPUT and \op{RUN\_NETWORK} are exercised purely over simulated SPI
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(ch.~\ref{ch:impl}).
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\end{fnnote}
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