micheleandClaude Sonnet 5
0e73eb4726
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
104 lines
5.6 KiB
TeX
104 lines
5.6 KiB
TeX
\thispagestyle{plain}
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\noindent
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\begin{tikzpicture}
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\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
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minimum width=\textwidth,anchor=west]
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{\large\bfseries Pinout summary --- pin-by-pin connection};
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\end{tikzpicture}
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\vspace{6pt}
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\noindent
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{\footnotesize
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Quick-reference table: the \textbf{57 real signals} of the top-level
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\code{spi\_neuron\_top}, each with its own individual \code{CABGA381} ball
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(\textbf{not} a bus range) --- real data from Project~Trellis's device
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database (\code{iodb.json}), \textbf{verified by a complete
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\code{nextpnr-ecp5} place\&route run at 0 errors} (not a planned pinout).
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Full description, per-bank placement rationale and the pin-by-pin
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connection to the ISSI PSRAM: ch.~\ref{ch:hw}.
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}
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\vspace{4pt}
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\noindent
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\renewcommand{\arraystretch}{1.08}
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\begin{tabularx}{\textwidth}{L{2.7cm} C{1.0cm} C{1.0cm} C{0.9cm} Y}
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\toprule
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\rowh \thd{Signal} & \thd{Ball} & \thd{Bank} & \thd{Dir} & \thd{Corresponding pin / function} \\
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\midrule
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\multicolumn{5}{l}{\textit{\color{fnDark}Clock and reset}}\\
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\code{clk} & H5 & 7 & IN & System clock, pad \code{GR\_PCLK7\_0} (dedicated global clock). \\
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\rowa \code{rst} & B4 & 7 & IN & Global synchronous reset, active high. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Application SPI (host $\leftrightarrow$ FPGA, Mode~0)}}\\
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\code{sclk} & B5 & 7 & IN & SPI clock (CPOL=0, CPHA=0). \\
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\rowa \code{mosi} & C5 & 7 & IN & Master-Out Slave-In. \\
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\code{miso} & A3 & 7 & OUT & Master-In Slave-Out. \\
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\rowa \code{cs\_n} & B3 & 7 & IN & Chip-select, active low. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Host attention (active-low, level)}}\\
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\code{data\_ready\_n} & C3 & 7 & OUT & Low while a result is waiting to be read. \\
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\rowa \code{irq\_n} & C4 & 7 & OUT & Low while the graph engine's load-time guard has tripped. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}Flash subsystem --- SPI toward W25Q128JV (boot/persistence)}}\\
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\code{flash\_sclk} & E3 & 7 & OUT & SPI clock toward the flash --- ordinary GPIO, independent (Phase F7, ch.~\ref{ch:hw}). \\
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\rowa \code{flash\_mosi} & D3 & 7 & OUT & Master-Out Slave-In toward the onboard flash. \\
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\code{flash\_miso} & D5 & 7 & IN & Master-In Slave-Out from the flash. \\
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\rowa \code{flash\_cs\_n} & E4 & 7 & OUT & Flash chip-select, active low. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}PSRAM address bus \code{psram\_a[21:0]} --- 22 individual balls (bank 2)}}\\
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\code{psram\_a[0]} & E16 & 2 & OUT & PSRAM A0 \\
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\rowa \code{psram\_a[1]} & F16 & 2 & OUT & PSRAM A1 \\
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\code{psram\_a[2]} & D18 & 2 & OUT & PSRAM A2 \\
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\rowa \code{psram\_a[3]} & E17 & 2 & OUT & PSRAM A3 \\
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\code{psram\_a[4]} & E18 & 2 & OUT & PSRAM A4 \\
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\rowa \code{psram\_a[5]} & F18 & 2 & OUT & PSRAM A5 \\
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\code{psram\_a[6]} & F17 & 2 & OUT & PSRAM A6 \\
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\rowa \code{psram\_a[7]} & G16 & 2 & OUT & PSRAM A7 \\
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\code{psram\_a[8]} & G18 & 2 & OUT & PSRAM A8 \\
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\rowa \code{psram\_a[9]} & H16 & 2 & OUT & PSRAM A9 \\
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\code{psram\_a[10]} & H17 & 2 & OUT & PSRAM A10 \\
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\rowa \code{psram\_a[11]} & H18 & 2 & OUT & PSRAM A11 \\
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\code{psram\_a[12]} & J16 & 2 & OUT & PSRAM A12 \\
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\rowa \code{psram\_a[13]} & J17 & 2 & OUT & PSRAM A13 \\
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\code{psram\_a[14]} & C20 & 2 & OUT & PSRAM A14 \\
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\rowa \code{psram\_a[15]} & D19 & 2 & OUT & PSRAM A15 \\
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\code{psram\_a[16]} & E19 & 2 & OUT & PSRAM A16 \\
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\rowa \code{psram\_a[17]} & E20 & 2 & OUT & PSRAM A17 \\
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\code{psram\_a[18]} & F19 & 2 & OUT & PSRAM A18 \\
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\rowa \code{psram\_a[19]} & F20 & 2 & OUT & PSRAM A19 \\
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\code{psram\_a[20]} & G20 & 2 & OUT & PSRAM A20 \\
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\rowa \code{psram\_a[21]} & H20 & 2 & OUT & PSRAM A21 \\
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\code{psram\_a[22]} & P18 & 3 & OUT & Always 0 (byte$\to$word shift): NC on the board. \\
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\multicolumn{5}{l}{\textit{\color{fnDark}PSRAM data bus \code{psram\_dq[15:0]} --- 16 individual balls (banks 2 and 3)}}\\
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\rowa \code{psram\_dq[0]} & K18 & 2 & IO & PSRAM DQ0 \\
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\code{psram\_dq[1]} & C18 & 2 & IO & PSRAM DQ1 (dual-function ball, used as ordinary GPIO). \\
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\rowa \code{psram\_dq[2]} & D17 & 2 & IO & PSRAM DQ2 \\
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\code{psram\_dq[3]} & D20 & 2 & IO & PSRAM DQ3 \\
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\rowa \code{psram\_dq[4]} & G19 & 2 & IO & PSRAM DQ4 \\
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\code{psram\_dq[5]} & J18 & 2 & IO & PSRAM DQ5 \\
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\rowa \code{psram\_dq[6]} & J19 & 2 & IO & PSRAM DQ6 \\
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\code{psram\_dq[7]} & J20 & 2 & IO & PSRAM DQ7 \\
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\rowa \code{psram\_dq[8]} & K19 & 2 & IO & PSRAM DQ8 \\
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\code{psram\_dq[9]} & K20 & 2 & IO & PSRAM DQ9 \\
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\rowa \code{psram\_dq[10]} & L17 & 3 & IO & PSRAM DQ10 \\
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\code{psram\_dq[11]} & M18 & 3 & IO & PSRAM DQ11 \\
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\rowa \code{psram\_dq[12]} & M17 & 3 & IO & PSRAM DQ12 \\
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\code{psram\_dq[13]} & N16 & 3 & IO & PSRAM DQ13 \\
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\rowa \code{psram\_dq[14]} & N18 & 3 & IO & PSRAM DQ14 \\
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\code{psram\_dq[15]} & P17 & 3 & IO & PSRAM DQ15 \\
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\multicolumn{5}{l}{\textit{\color{fnDark}PSRAM control}}\\
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\rowa \code{psram\_ce\_n} & N17 & 3 & OUT & PSRAM CE\# --- chip enable, active low. \\
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\code{psram\_oe\_n} & R16 & 3 & OUT & PSRAM OE\# --- output enable (read). \\
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\rowa \code{psram\_we\_n} & R17 & 3 & OUT & PSRAM WE\# --- write enable. \\
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\code{psram\_lb\_n} & T16 & 3 & OUT & PSRAM LB\# --- lower-byte enable (DQ[7:0]). \\
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\rowa \code{psram\_ub\_n} & N19 & 3 & OUT & PSRAM UB\# --- upper-byte enable (DQ[15:8]). \\
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\code{psram\_zz\_n} & N20 & 3 & OUT & PSRAM ZZ\# --- sleep/snooze (high during normal operation). \\
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\bottomrule
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\end{tabularx}
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\renewcommand{\arraystretch}{1.25}
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\vspace{4pt}
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\noindent
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{\footnotesize\color{fnGrey}
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Standard I/O: LVCMOS33 on all 57 signals. Boot config-SPI and JTAG balls (fixed-function
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dedicated pins, no RTL port) do not appear in this table --- see ch.~\ref{ch:hw}
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§``Configuration and programming''. Source: \code{synth/ecp5/spi\_neuron\_top.lpf},
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generated by \code{tools/pinout/gen\_lpf.py} against Project~Trellis's
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\code{iodb.json}.\par}
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