micheleandClaude Sonnet 5
07f8ec0460
The repository had accumulated multiple, contradictory "current state" documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root (docs/DatasheetLatex/), and a second, much older documentation track (hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md, MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/ N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board. The LaTeX datasheet's own front matter (features/pinout cover pages) and chapter 9 (benchmarks) were themselves still describing that obsolete architecture, contradicting the real, current chapters 5/7/10 elsewhere in the same document. This commit: - Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting). - Removes the old V1 IT/EN LaTeX copies and the stray root-level duplicate entirely (recoverable from git history, not from disk). - Preserves the real component reference PDFs (ECP5 eval board, ISSI PSRAM, programming cables) under datasheet/references/. - Removes 13 superseded hardware/v2/docs/*.md status documents after folding every real, unique fact they contained into the datasheet: SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR), and the real FPGA<->SDRAM ball mapping cross-check. - Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8 (top-level module -- was documenting the wrong, non-physical top entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/ N_SLOTS=4 production board, while keeping the real PSRAM-era chapters as clearly-labeled history rather than deleting correctly-measured work. - Fixes a title-page tikzpicture that was clipped off the page edge (pre-existing, unrelated to this change) by scaling it to fit. Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up runbook, not a duplicate spec). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
66 lines
3.9 KiB
TeX
66 lines
3.9 KiB
TeX
\chapter{Module and file map}
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\label{ap:modules}
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\section{V2 RTL (\texttt{hardware/v2/rtl/})}
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\begin{tabularx}{\textwidth}{L{4.2cm} Y}
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\toprule
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\rowh \thd{File} & \thd{Role} \\
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\midrule
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\code{neural\_processor.v} & 8-stage INT8 pipeline (M1); bit-exact vs.\ V1. \\
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\rowa \code{neural\_processor\_array.v} & N-processor array used for the M2 concurrency sweep. \\
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\code{activation\_buffer.v}, \code{weight\_buffer.v}, \code{result\_buffer.v} & M3 BRAM-backed buffers; superseded in the real datapath by \code{activation\_cache.v}. \\
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\rowa \code{prefetch\_engine.v} & Weight-only, word-level burst fetch engine (M4, rewritten DEC-0015/DEC-0016). \\
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\code{memory\_manager.v} & Double-buffered per-slot tile manager; coordinates the Activation Cache (X) and \code{prefetch\_engine.v} (W). \\
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\rowa \code{neural\_director.v} & First-free job dispatch (M5). \\
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\code{dependency\_manager.v} & Node table, dependency counting, wake-up (M6). \\
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\rowa \code{dataflow\_core.v} & Full M1--M6 integration $+$ Activation Cache (M7, extended DEC-0016). \\
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\code{slot\_mem\_arbiter.v} & Generic N-port arbiter to the real PSRAM chain (M8). \\
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\rowa \code{activation\_cache.v} & Shared, single-tag activation cache (post-M10, DEC-0016). \\
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\code{neural\_multiprocessor.v} & Real hardware-facing top level (M8). \\
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\bottomrule
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\end{tabularx}
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\section{NMS RTL (\texttt{hardware/v2/nms/rtl/}, ch.~\ref{ch:nms})}
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\begin{tabularx}{\textwidth}{L{4.6cm} Y}
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\toprule
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\rowh \thd{File} & \thd{Role} \\
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\midrule
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\code{nms\_activation\_replicated.v} & Selected Activation SRAM: \code{N\_SLOTS} private full-vector copies, broadcast-write fill (DEC-0019). \\
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\rowa \code{nms\_activation\_fill\_ctrl.v} & Shared dedup/fetch controller backing it -- the real \code{N\_SLOTS}=4/8 Fmax bottleneck identified in ch.~\ref{ch:nms}. \\
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\code{nms\_weight\_packed.v} & Selected Weight SRAM: per-MAC-lane packed private copies (DEC-0020). \\
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\rowa \code{nms\_memory\_manager.v} & Per-slot job FSM, drop-in replacement for \code{memory\_manager.v}'s own external interface. \\
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\code{nms\_dataflow\_core.v} & Full NMS integration, mirrors \code{dataflow\_core.v}'s own scope (STEP8). \\
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\rowa \code{nms\_neural\_multiprocessor.v} & Real hardware-facing top level, mirrors \code{neural\_multiprocessor.v}'s own scope (STEP9). \\
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\bottomrule
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\end{tabularx}
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Also reused verbatim, unmodified, in the NMS datapath:
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\code{neural\_processor.v}, \code{prefetch\_engine.v} (as a generic
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P\_IN-byte-tile fetch engine, not weight-specific despite its name),
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\code{dependency\_manager.v}, \code{neural\_director.v},
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\code{slot\_mem\_arbiter.v}.
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\section{Reused, unmodified V1 (\texttt{hardware/v1/rtl/})}
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\begin{tabularx}{\textwidth}{L{4.2cm} Y}
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\toprule
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\rowh \thd{File} & \thd{Role in V2} \\
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\midrule
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\code{memory\_interface.v} & Word-level (16-bit) PSRAM backend port, now the direct target of both \code{prefetch\_engine.v} and \code{activation\_cache.v}. \\
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\rowa \code{psram\_controller.v} & Real PSRAM controller, page-mode support exploited more effectively by the word-burst rewrite. \\
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\code{int8\_memory\_access.v} & \textbf{No longer instantiated} in V2's datapath post-DEC-0015 --- file itself untouched. \\
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\bottomrule
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\end{tabularx}
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\section{Simulation (\texttt{hardware/v2/sim/})}
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\code{tb\_neural\_processor.v}, \code{tb\_dataflow\_core.v},
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\code{tb\_memory\_manager.v}, \code{tb\_neural\_director.v},
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\code{tb\_dependency\_manager.v}, \code{tb\_neural\_multiprocessor.v},
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\code{tb\_benchmark\_suite.v} (the final campaign's own testbench,
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parametric in \code{N\_SLOTS\_CFG} via Verilator's own \code{-G} override).
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\section{Documentation and logs (\texttt{hardware/v2/docs/}, \texttt{hardware/v2/logs/})}
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\code{ROADMAP.md}; \code{docs/benchmarks/final-benchmark.md} (the
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21-section pre-optimization campaign report); append-only logs
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(\code{development}, \code{simulation}, \code{synthesis}, \code{timing},
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\code{benchmark}, \code{decisions}, \code{experiments}, \code{errors})
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--- the primary source of every number in this datasheet.
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