micheleandClaude Sonnet 5
07f8ec0460
The repository had accumulated multiple, contradictory "current state" documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root (docs/DatasheetLatex/), and a second, much older documentation track (hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md, MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/ N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board. The LaTeX datasheet's own front matter (features/pinout cover pages) and chapter 9 (benchmarks) were themselves still describing that obsolete architecture, contradicting the real, current chapters 5/7/10 elsewhere in the same document. This commit: - Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting). - Removes the old V1 IT/EN LaTeX copies and the stray root-level duplicate entirely (recoverable from git history, not from disk). - Preserves the real component reference PDFs (ECP5 eval board, ISSI PSRAM, programming cables) under datasheet/references/. - Removes 13 superseded hardware/v2/docs/*.md status documents after folding every real, unique fact they contained into the datasheet: SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR), and the real FPGA<->SDRAM ball mapping cross-check. - Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8 (top-level module -- was documenting the wrong, non-physical top entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/ N_SLOTS=4 production board, while keeping the real PSRAM-era chapters as clearly-labeled history rather than deleting correctly-measured work. - Fixes a title-page tikzpicture that was clipped off the page edge (pre-existing, unrelated to this change) by scaling it to fit. Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up runbook, not a duplicate spec). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
87 lines
4.6 KiB
TeX
87 lines
4.6 KiB
TeX
\chapter{Register-level interface \& internal state encodings}
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\label{ch:regs}
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\begin{fnwarn}[Real SPI opcode map exists; state encodings below are
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per-module reference]
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Ch.~\ref{ch:host} now documents V2's real, physical SPI opcode map
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(\code{WRITE\_JOB}/\code{WRITE\_MEM}/\code{READ\_MEM}/\code{STATUS}/
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\code{RESET}) --- this chapter's own node-registration field layout
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below remains the logical field reference (repeated here for quick
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reference). The \textbf{internal FSM state encodings} below are useful
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for simulation-level debug; \S\S\ref{ch:regs}'s Dependency
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Manager/Neural Director tables are shared by every V2 architecture
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(unchanged between the PSRAM-era and current SDRAM boards). The Memory
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Manager and Neural Processor tables were captured from the PSRAM-era
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\code{memory\_manager.v}/\code{neural\_processor.v} pairing (ch.~\ref{ch:arch})
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--- the current SDRAM board's \code{nms\_memory\_manager\_stream\_wide.v}
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implements the same functional handshake (prefetch $\to$ stream $\to$
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write-back $\to$ done) against the SDRAM backend instead of PSRAM, but
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its own internal state encoding was not re-transcribed into this table.
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\end{fnwarn}
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\section{Node registration fields (quick reference)}
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See ch.~\ref{ch:host} for the full field-level description.
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\code{reg\_node\_id}, \code{reg\_required}, \code{reg\_producer\_ids},
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\code{reg\_x\_base}, \code{reg\_w\_base}, \code{reg\_n\_tiles},
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\code{reg\_result\_addr} --- valid/ready handshake, \code{reg\_ready}
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gated on the target node id's table slot being \code{EMPTY}.
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\section{Dependency Manager node state (\texttt{node\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.6cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{2'd0} & \code{ST\_EMPTY} & Table slot free; \code{reg\_ready} asserted for this node id. \\
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\rowa \op{2'd1} & \code{ST\_WAITING} & Registered, at least one producer not yet resolved. \\
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\op{2'd2} & \code{ST\_READY} & All producers resolved; eligible for dispatch. \\
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\rowa \op{2'd3} & \code{ST\_DISPATCHED} & Handed to the Director; \textbf{terminal} (\S\ref{ch:sched}). \\
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\bottomrule
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\end{tabularx}
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\section{Neural Director state (\texttt{dir\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.6cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{4'd0} & \code{DIR\_IDLE} & Reset/startup. \\
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\rowa \op{4'd1} & \code{DIR\_SCAN\_READY} & Checking whether a queued job and a free slot both exist. \\
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\op{4'd2} & \code{DIR\_ALLOCATE} & Dispatching the head-of-queue job to the first free slot. \\
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\rowa \op{4'd3} & \code{DIR\_ERROR} & Recoverable only via reset (an isolated fault never blocks other slots). \\
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\bottomrule
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\end{tabularx}
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\section{Memory Manager state (\texttt{state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{3.0cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{3'd0} & \code{MM\_IDLE} & Waiting for \code{job\_start}. \\
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\rowa \op{3'd1} & \code{MM\_PREFETCH\_FIRST} & Waiting for tile~0's activation \emph{and} weight halves to both arrive. \\
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\op{3'd2} & \code{MM\_STREAM} & Presenting tiles to the Neural Processor, double-buffering the next one. \\
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\rowa \op{3'd3} & \code{MM\_WAIT\_RESULT} & Last tile handed off; waiting for the Neural Processor's own result. \\
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\op{3'd4} & \code{MM\_WRITE\_RESULT} & Issuing the real PSRAM word write for the INT8 result. \\
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\rowa \op{3'd5} & \code{MM\_DONE} & Waiting for the write's own \code{mem\_ready}; then pulses \code{job\_done}. \\
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\bottomrule
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\end{tabularx}
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\section{Neural Processor state (\texttt{np\_state})}
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\begin{tabularx}{\textwidth}{C{1.4cm} L{2.8cm} Y}
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\toprule
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\rowh \thd{Value} & \thd{Name} & \thd{Meaning} \\
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\midrule
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\op{4'd0} & \code{NP\_IDLE} & No job in flight. \\
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\rowa \op{4'd1} & \code{NP\_LOAD\_JOB} & Latching \code{job\_bias}/\code{job\_activation}, clearing the accumulator. \\
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\op{4'd2} & \code{NP\_WAIT\_OPERANDS} & Consuming tiles as they arrive (absorbs the per-tile MAC/accumulate/next-tile sequence). \\
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\rowa \op{4'd3} & \code{NP\_FINISH} & Draining the pipeline after \code{tile\_last}. \\
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\op{4'd4} & \code{NP\_WRITE\_RESULT} & Result available for the Memory Manager to consume. \\
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\rowa \op{4'd5} & \code{NP\_DONE} & Job complete. \\
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\op{4'd6} & \code{NP\_ERROR} & Reachable only via an unreachable \code{default} case --- isolated per-processor, never blocks other slots. \\
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\bottomrule
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\end{tabularx}
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\section{Slot Memory Arbiter owner encoding}
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\code{owner} is \code{0} for ``no port granted'', or (port index $+1$)
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for the currently-granted port --- indices \code{0..N\_SLOTS-1} are the
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per-slot Memory Managers' own weight/write-back traffic; index
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\code{N\_SLOTS} is the shared Activation Cache's own traffic.
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