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• 07f8ec0460 docs: consolidate all V2 datasheets into one current, complete document main micheleandClaude Sonnet 5 2026-09-09 00:41:06 +02:00
• b7b4ada99f docs: polish V2 datasheet to professional third-person English micheleandClaude Sonnet 5 2026-09-07 20:17:09 +02:00
• 85d473a79b docs: embed real KiCad schematic export in V2 datasheet, verify BOM from source micheleandClaude Sonnet 5 2026-09-07 20:03:57 +02:00
• 86581e1521 docs: resolve FPGA grade to commercial (8BG381C), correct temp range data micheleandClaude Sonnet 5 2026-09-07 19:46:14 +02:00
• a3ba8f93ac docs: resolve the +1V1 label mystery and close remaining schematic open items micheleandClaude Sonnet 5 2026-09-07 19:42:46 +02:00
• a8b202f63d docs: clear CAS#/WE# false alarm, resolve TLV73325 EN wiring micheleandClaude Sonnet 5 2026-09-07 19:38:48 +02:00
• e7f9b9f719 docs: add real BOM, flag FPGA grade discrepancy (8BG381I vs 8BG381C) micheleandClaude Sonnet 5 2026-09-07 19:36:51 +02:00
• 58b7374106 docs: real KiCad schematic review + reserved PCB module section micheleandClaude Sonnet 5 2026-09-07 19:35:03 +02:00
• ffc1c7ccfc docs: reflect flash #1 removal and the N=4 8/8 timing recovery micheleandClaude Sonnet 5 2026-09-07 19:20:57 +02:00
• d8ccc9d494 docs: datasheet addendum for two-flash programming architecture + FPGA_DATA_READY micheleandClaude Sonnet 5 2026-09-07 13:11:12 +02:00
• 7728a6c796 feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout micheleandClaude Sonnet 5 2026-09-07 12:46:00 +02:00
• 0e73eb4726 docs: bring datasheet/ into the main repo under hardware/v2/docs micheleandClaude Sonnet 5 2026-09-07 05:09:14 +02:00