michele/FPGA-Neural-Datasheet
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

docs: clear CAS#/WE# false alarm, resolve TLV73325 EN wiring

Browse Source 
User confirmed the real schematic has SDRAM CAS#=F7/WE#=F9 -- matches
this chapter exactly. The earlier review's "appear swapped" finding
was a misread of the schematic image, not a real error; moved from
"real findings" to a cleared checked-item note.

TLV73325's EN pin resolved: direct wire to +3.3V (VIN), always-enabled
-- no soft-start timing requirement like TLV62568's own R3 pull-up (a
plain LDO, no sequencing note in TI's own datasheet), and no dynamic
enable/disable control exists elsewhere in this design.

Remaining real, open finding: the boot-flash net-name mismatch
(FGPA/FPGA typo + SCLK/CLK) still needs a schematic fix.

Compiled clean (47 pages, 0 errors).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-07 19:38:48 +02:00
co-authored by Claude Sonnet 5
parent e7f9b9f719
commit a8b202f63d
2 changed files with 14 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
files/docs/datasheet/v2-en/FPGA-Neural-V2-Datasheet-EN.pdf
BIN
View File
Binary file not shown.
files/docs/datasheet/v2-en/chapters/10-hardware.tex
+14 -8
View File
@@ -371,17 +371,19 @@ pull-up (inside the required 1--10\,k$\Omega$ range).
disconnected from the FPGA's own configuration engine --- disconnected from the FPGA's own configuration engine ---
auto-boot from flash would silently fail. \textbf{Fix}: make all auto-boot from flash would silently fail. \textbf{Fix}: make all
eight labels identical text. eight labels identical text.
\item \textbf{SDRAM CAS\#/WE\# appear swapped}: schematic shows
CAS\#=F9, WE\#=F7; the real, independently-verified assignment
(this chapter, Alliance Memory datasheet-derived) is
\textbf{CAS\#=F7, WE\#=F9}.
\end{enumerate} \end{enumerate}
\begin{fnnote}[Checked and cleared]
SDRAM CAS\#/WE\#: user confirmed CAS\#=F7, WE\#=F9 in the real
schematic --- matches this chapter exactly. The apparent swap in the
original review was a misread of the schematic image, not a real
error.
\end{fnnote}
\subsection{Open items (not resolvable from the schematic image alone)} \subsection{Open items (not resolvable from the schematic image alone)}
\begin{itemize} \begin{itemize}
\item \code{TLV62568}'s EN pin: is \code{R3}=499\,k$\Omega$ actually on \item \code{TLV62568}'s EN pin: is \code{R3}=499\,k$\Omega$ actually on
EN, and to which rail? EN, and to which rail?
\item \code{TLV73325}'s EN pin: connected to anything?
\item A \code{+1V1} label appears near the VCCAUX ferrite (L2)/its \item A \code{+1V1} label appears near the VCCAUX ferrite (L2)/its
decoupling (C8/C9) --- VCCAUX must remain 2.5\,V after the decoupling (C8/C9) --- VCCAUX must remain 2.5\,V after the
ferrite (a ferrite bead filters, it does not change DC voltage); ferrite (a ferrite bead filters, it does not change DC voltage);
@@ -442,9 +444,13 @@ apply --- each resistor can go to its own correct rail. U5 confirms
the 16\,MHz oscillator, previously missing from the capture, is now the 16\,MHz oscillator, previously missing from the capture, is now
present. present.
\subsection{Still open} \subsection{Resolved}
TLV73325's EN pin has no dedicated resistor in this BOM --- presumably TLV73325's EN pin: no dedicated resistor needed --- direct wire to
a direct wire to +3.3\,V (always-enabled); not yet confirmed. +3.3\,V (VIN), always-enabled. Unlike TLV62568's own soft-start
R3=499\,k$\Omega$ pull-up, a plain LDO has no equivalent timing
requirement (per TI's own datasheet: ``active high, do not leave
floating,'' no sequencing note); no dynamic enable/disable control
exists elsewhere in this design.
\section{PCB module form factor (reserved)} \section{PCB module form factor (reserved)}
\label{sec:pcb-module} \label{sec:pcb-module}