feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout

Establishes the real ESP32<->ECP5 programming architecture: flash #1
(neural-network data, existing V1 subsystem, ball reserved not yet
wired into V2) stays separate from flash #2 (boot bitstream, MSPI
auto-boot, CFG[2:0]=[0,1,0]); ESP32 talks JTAG only (bit-banged, no
hardware JTAG-master peripheral on S3/C6), updating flash #2 through
the ECP5's own internal sysCONFIG-to-SPI bridge, never driving the
flash pins directly -- zero bus contention, confirmed against the real
Lattice hardware checklist and sysCONFIG user guide.

Adds real, verified ball assignments (official Lattice CABGA381 CSV +
Project Trellis iodb.json) for JTAG, PROGRAMN/INITN/DONE, CFG[2:0],
and the MSPI dedicated pins -- all written to docs/pinouts.md.

Implements FPGA_DATA_READY as real RTL: a system-idle detector
(dependency_manager's any_pending OR neural_director's !queue_empty OR
any active slot), sticky on the busy->idle edge, self-clearing on new
work -- not a per-neuron completion pulse, which was confirmed too
fine-grained. Bit-exact regression re-verified at N_SLOTS=4 and 8
(zero cycle-count change), new explicit data_ready assertion check
added to the D-Stress testbench (PASS both configs), and a fresh
Yosys+nextpnr-ecp5 placement check (0 errors, data_ready placed at G3).

Also fixes a real, independently-found bug while editing an adjacent
file: nms_neural_multiprocessor_sdram_unified.v's own sdram_a port was
still [11:0] (12 bits), stale from before the 64MB/13-bit memory
upgrade. Not exercised by the real board-level top (which wires SDRAM
directly, bypassing this wrapper) but WAS silently truncating A12 in
every D-Stress simulation this session, including today's earlier
ERR-0029 verification runs. Assessed impact: all D-Stress test
addresses used this session decode to rows under 4096 (bit 12 never
actually needed), so no false-positive PASS is believed to have
resulted -- but the full 64MB space was never actually exercised
through this wrapper. Fixed; re-verified bit-exact with identical
cycle counts.

See decisions.log DEC-0041 for full detail.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

files/docs/datasheet/v2-en/chapters/10-hardware.tex

@@ -117,3 +117,131 @@ N\_SLOTS=4/8 @ 80\,MHz & 0/8 & --- & NO-GO, genuine \code{ecppll}-regenerated PL
 Real, measured after the ERR-0029 weight-cache hit-index optimization
 (serial priority scan $\to$ flat one-hot compare); see
 \code{hardware/v2/logs/errors.log} and \code{decisions.log} DEC-0040.
+
+\section{Power supply design (2026-09-07) --- verified against the real
+Lattice hardware checklist}
+\label{sec:power-addendum}
+\begin{fnwarn}[Supersedes the generic \S3 stub above]
+The ``Power supply, oscillator, configuration'' section earlier in
+this chapter only said ``unchanged from V1'' without real design data.
+This section replaces that stub with the actual rail topology, sized
+against the real, primary-source Lattice and TI documents below --- not
+estimated.
+\end{fnwarn}
+
+\subsection{Rail topology}
+Three rails, one simplification from the original V1 reference design:
+\textbf{no separate buck regulator for the 3.3\,V I/O rail} --- the
+board's own external input is specified as \textbf{3.3\,V}, so
+\code{VCCIO}, the SDRAM (VDD/VDDQ, 3.3\,V per its own datasheet), and
+the flash (3.3\,V) are fed directly from the board input. A buck
+targeting 3.3\,V output from a 3.3\,V input would run at 100\% duty
+cycle permanently --- zero regulation margin, no benefit over a direct
+connection.
+
+\begin{tabularx}{\textwidth}{L{2.6cm} L{2.0cm} L{3.2cm} X}
+\toprule
+\rowh \thd{Rail} & \thd{Value} & \thd{Source} & \thd{Feeds} \\
+\midrule
+I/O & 3.3\,V & Direct board input & FPGA \code{VCCIO0--8}, SDRAM VDD/VDDQ, SPI flash, PMOD \\
+\rowa Core & 1.1\,V & TLV62568 (buck), from the 3.3\,V rail & FPGA \code{VCC} \\
+Auxiliary & 2.5\,V & TLV73325 (LDO), from the 3.3\,V rail & FPGA \code{VCCAUX} \\
+\bottomrule
+\end{tabularx}
+
+\subsection{Power-up sequencing --- real Lattice requirement, verified
+compliant}
+Per Lattice's own \emph{ECP5 and ECP5-5G Hardware Checklist}
+(FPGA-TN-02038-2.0, July 2024), \S4: \emph{``\code{VCCIO} supplies
+should be powered up before or together with the \code{VCC} and
+\code{VCCAUX} supplies.''} The same document's \S2 adds: all three
+monitored rails must rise \textbf{monotonically}, and the on-chip
+Power-On-Reset de-asserts only once \code{VCC}$\geq$0.9\,V,
+\code{VCCAUX}$\geq$2.0\,V, and \code{VCCIO8}$\geq$0.95\,V are all
+simultaneously satisfied --- device initialization waits for whichever
+of the three is slowest.
+
+This board's topology satisfies the requirement \textbf{by construction},
+with no sequencer IC needed: \code{VCCIO} (3.3\,V) is a direct,
+unregulated connection to the board input, so it rises first/fastest,
+strictly before the two regulated rails (Core, Aux) can even begin
+their own soft-start ramps --- ``before or together with'' is met on
+every possible power-up transient, not just the typical case.
+
+\subsection{Decoupling --- real Lattice-recommended values (not a
+generic ``one cap per pin'' guess)}
+Per FPGA-TN-02038-2.0 Table~3.1 (\S3.1), applied per-rail:
+
+\begin{tabularx}{\textwidth}{L{2.0cm} L{5.0cm} X}
+\toprule
+\rowh \thd{Rail} & \thd{Filter} & \thd{Notes} \\
+\midrule
+\code{VCC} & 10\,\textmu F $\times$3 (bulk) $+$ 100\,nF per pin & Core, 1.1\,V \\
+\rowa \code{VCCAUX} & 120\,$\Omega$ ferrite bead $+$ 10\,\textmu F $+$
+  100\,nF per pin & 2.5\,V; \textbf{new part not in the earlier power
+  tree draft} --- a ferrite bead in series was missing before this
+  verification pass \\
+\code{VCCIO[0--8]} & 10\,\textmu F $+$ 100\,nF per pin (per bank in
+  use) & 1\textmu F acceptable on unused banks; 22\,\textmu F (or a
+  second 10\,\textmu F) on banks with heavy output loading \\
+\bottomrule
+\end{tabularx}
+
+Capacitor selection, also per the same document: X5R/X7R dielectric
+(avoid Y5V/Z5U), voltage rating $\geq$80\% above the rail's maximum ---
+for the 3.3\,V rail this means a \textbf{6.3\,V minimum} rating, not
+the bare 3.3\,V-rated parts sometimes used to save cost. All ground
+pins tie to the board's ground plane (no star grounding on this
+family).
+
+\subsection{Regulator component values (real, computed from datasheet
+constants)}
+\textbf{TLV62568} (core, 1.1\,V): input range 2.5--5.5\,V (3.3\,V
+input has full margin); feedback reference \code{VFB}$=0.6$\,V
+(typical, per TI SLVSD89B). Output set via
+$V_{OUT}=V_{FB}\left(1+\frac{R1}{R2}\right)$: choosing
+\textbf{R1$=$100\,k$\Omega$, R2$=$120\,k$\Omega$} gives
+$0.6\times(1+100/120)=1.1$\,V exactly. Per TI's own typical
+application circuit: C1$=$4.7\,\textmu F on \code{VIN}, L1$=$2.2\,
+\textmu H inductor, C2$=$10\,\textmu F on \code{VOUT}.
+
+\textbf{TLV73325} (auxiliary, 2.5\,V fixed-output LDO): input range
+1.4--5.5\,V (per TI SBVS221, real datasheet), dropout 125\,mV at
+300\,mA --- far above this rail's $\sim$10\,mA real load, so dropout is
+not a concern at 3.3\,V input. Capacitor-free architecture (stable
+without external caps at the regulator itself); the 10\,\textmu F$+$
+100\,nF on \code{VCCAUX} above are the FPGA-side filter from
+FPGA-TN-02038, not regulator-stability caps, and are still required.
+
+\begin{fnnote}[Open item carried from \S3 above]
+The 16\,MHz reference oscillator's exact manufacturer part number is
+not yet specified in this document (only ``16\,MHz'' as a frequency
+requirement) --- flagged, not invented, pending the schematic capture
+the user is preparing separately.
+\end{fnnote}
+
+\subsection{Power tree}
+\begin{center}
+\begin{tikzpicture}[node distance=10mm and 14mm,font=\footnotesize]
+  \node[fnblockD,minimum width=30mm,minimum height=11mm] (in){Board input\\3.3\,V};
+  \node[fnblock,below left=14mm and -6mm of in,minimum width=32mm,minimum height=13mm] (u3){TLV62568 (buck)\\R1/R2 $\to$ 1.1\,V};
+  \node[fnblockT,below right=14mm and -6mm of in,minimum width=32mm,minimum height=13mm] (u5){TLV73325 (LDO)\\fixed 2.5\,V};
+  \node[fnblockA,right=30mm of in,minimum width=26mm,minimum height=11mm] (io){\code{VCCIO0--8}\\3.3\,V direct};
+  \node[fnreg,below=8mm of io,minimum width=26mm] (sd){SDRAM VDD/VDDQ};
+  \node[fnreg,below=6mm of sd,minimum width=26mm] (fl){SPI flash \code{VCC}};
+  \node[fnblock,below=18mm of u3,minimum width=30mm,minimum height=11mm] (core){FPGA \code{VCC}\\1.1\,V core};
+  \node[fnblockT,below=18mm of u5,minimum width=30mm,minimum height=11mm] (aux){FPGA \code{VCCAUX}\\2.5\,V};
+  \draw[fnbus] (in) -- (io);
+  \draw[fnarrow] (io) -- (sd);
+  \draw[fnarrow] (io) -- (fl);
+  \draw[fnbus] (in) -- (u3);
+  \draw[fnbus] (in) -- (u5);
+  \draw[fnbus] (u3) -- node[fnlbl,right]{10\textmu F$\times$3 + 100nF/pin} (core);
+  \draw[fnbus] (u5) -- node[fnlbl,right]{120$\Omega$ FB + 10\textmu F + 100nF/pin} (aux);
+\end{tikzpicture}
+\end{center}
+\begin{center}
+{\scriptsize Power tree, direct 3.3\,V I/O rail (no redundant buck), verified against
+FPGA-TN-02038-2.0 \S3--4. Full schematic capture (BOM, connectors,
+FPGA--RAM/FLASH and PROG sections) pending separately.}
+\end{center}