docs: bring datasheet/ into the main repo under hardware/v2/docs
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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% ======================================================================
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% FPGA-Neural V2 -- Neural Multiprocessor / Dataflow Machine
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% Datasheet / Technical reference manual
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% Repository: github.com/manvalan/FPGA-Neural
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% ======================================================================
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\documentclass[11pt,a4paper,openany]{report}
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\newcommand{\datasheetrev}{B2}
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\newcommand{\datasheetdate}{September 2026}
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\input{preamble}
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\begin{document}
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\sloppy
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% ======================================================================
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% TITLE PAGE
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% ======================================================================
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\begin{titlepage}
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\thispagestyle{empty}
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\begin{tikzpicture}[remember picture,overlay]
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\fill[fnDark] (current page.north west) rectangle
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([yshift=-4.3cm]current page.north east);
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\fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle
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([yshift=-4.55cm]current page.north east);
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\node[anchor=north west,text=white,font=\Huge\bfseries]
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at ([xshift=2.2cm,yshift=-1.15cm]current page.north west)
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{FPGA\,--\,Neural~V2};
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\node[anchor=north west,text=fnLight,font=\large]
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at ([xshift=2.25cm,yshift=-2.15cm]current page.north west)
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{Neural Multiprocessor / Dataflow Machine};
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\node[anchor=north west,text=fnLight2,font=\normalsize]
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at ([xshift=2.25cm,yshift=-2.85cm]current page.north west)
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{N\_SLOTS-way concurrent INT8 accelerator -- Datasheet and reference manual};
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\node[anchor=north east,text=white,font=\ttfamily\small]
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at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east)
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{Rev.~\datasheetrev~~\textbullet~~\datasheetdate};
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\end{tikzpicture}
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\vspace*{5.0cm}
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% --- compact block diagram on the title page ---
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\begin{center}
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\begin{tikzpicture}[node distance=7mm and 10mm]
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\node[fnblockD,minimum width=26mm] (host) {HOST\\{\scriptsize graph loader}};
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\node[fnblockT,right=14mm of host,minimum width=30mm] (dm) {Dependency\\Manager};
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\node[fnblockT,right=14mm of dm,minimum width=28mm] (dir) {Neural\\Director};
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\node[fnblock,right=14mm of dir,minimum width=34mm] (slots) {N\_SLOTS $\times$ (Memory\\Manager $+$ Neural Proc.)};
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\node[fnblock,right=14mm of slots,minimum width=24mm] (ram) {PSRAM\\{\scriptsize 8\,MB, real V1 chain}};
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\draw[fnbus] (host) -- (dm);
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\draw[fnbus] (dm) -- (dir);
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\draw[fnbus] (dir) -- (slots);
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\draw[fnbus] (slots) -- node[fnlbl,above]{16-bit word} (ram);
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\node[below=1mm of slots,font=\scriptsize\itshape,text=fnGrey]
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{computation entirely on-chip, dependency graph resolved autonomously};
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\end{tikzpicture}
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\end{center}
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\vfill
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\begin{center}
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\begin{tikzpicture}
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\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{
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\footnotesize
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\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381C}
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(speed grade $-8$, CABGA381) --- identical device and board as V1.\\[2pt]
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\textbf{\color{fnDark}Recommended configuration:} INT8/INT32, \code{P\_IN}=8,
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\code{N\_SLOTS}=2 (real, measured net win --- see ch.~\ref{ch:impl2}), same real,
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unmodified V1 PSRAM backend, ISSI \code{IS66WVE4M16EBLL-70BLI}.\\[2pt]
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\textbf{\color{fnDark}Status:} RTL verified in real Verilator simulation and real
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synthesis + place\&route (Yosys + nextpnr-ecp5). Full benchmark campaign, two
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post-campaign memory optimizations, and a full alternative memory-subsystem
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redesign (the Neural Memory System, ch.~\ref{ch:nms}) complete and measured.
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Document describing the project as of \datasheetdate.
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};
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\end{tikzpicture}
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\end{center}
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\vspace{0.6cm}
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{\footnotesize\color{fnGrey}\raggedright
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Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\
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This datasheet documents V2 of the RTL code, documentation and benchmarks
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present in the repository \texttt{github.com/manvalan/FPGA-Neural}. V1 remains
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frozen and unmodified as the project's golden functional/performance reference;
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it is documented in a separate datasheet.\par}
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\end{titlepage}
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% ======================================================================
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% "FEATURES" PAGE (datasheet style)
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% ======================================================================
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\input{chapters/00-features}
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% ======================================================================
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% PINOUT SUMMARY (honesty note -- no real ball assignment for V2 yet)
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% ======================================================================
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\newpage
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\input{chapters/00b-pinout}
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% ======================================================================
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% TABLE OF CONTENTS
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% ======================================================================
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\newpage
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\pagenumbering{roman}
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{\color{fnDark}\tableofcontents}
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\newpage
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\pagenumbering{arabic}
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% ======================================================================
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% CHAPTERS
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% ======================================================================
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\include{chapters/01-overview}
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\include{chapters/02-architecture}
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\include{chapters/03-datapath}
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\include{chapters/04-parameters}
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\include{chapters/05-memory}
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\include{chapters/06-scheduling}
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\include{chapters/07-hostinterface}
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\include{chapters/08-toplevel}
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\include{chapters/09-implementation}
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\include{chapters/10-hardware}
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\include{chapters/11-registers}
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\include{chapters/12-roadmap}
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\include{chapters/13-nms}
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\appendix
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\include{chapters/A-modules}
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\end{document}
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