docs: bring datasheet/ into the main repo under hardware/v2/docs
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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\chapter[Graph network (Type \#2)]{Two-level configuration: graph network (Type \#2)}
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\label{ch:grafo}
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\section{Two network types}
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The engine exposes two \emph{network types} selectable by the host, with the same start
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command dispatching to the correct engine:
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\begin{itemize}
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\item \textbf{Type \#1 --- classic network (dense).} Layers with neurons per layer, fully
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connected between consecutive layers. It is the \code{layer\_sequencer} path
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(ch.~\ref{ch:seq}), started by \op{RUN\_NETWORK}. Connections are \emph{implicit by
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position}: nothing is enumerated, only the weights are defined, addressed as
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\code{w\_base + k*n\_inputs + j}.
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\item \textbf{Type \#2 --- arbitrary graph (sparse).} Starting from the input neuron ids,
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each neuron's connections up to the output are defined through a per-neuron \emph{sparse
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edge-list}. Connections are \emph{explicit by enumeration}: each connection is an edge
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\code{(src\_id, weight)}; if it is not in the list, it does not exist.
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\end{itemize}
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\begin{fnnote}[The difference in one line]
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Dense: you define the \emph{weights} by position in a matrix. Graph: you define each
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\emph{connection} as an edge \code{(src\_id, weight)} in a per-neuron list. The two
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descriptor tables share the same 11-byte format but different fields; the
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\code{net\_type} register tells the engine which interpretation to use.
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\end{fnnote}
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\section{Global activation buffer}
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Type \#2 introduces an \textbf{activation buffer} indexed by \emph{signal id}, one INT8
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byte per id, implemented in \textbf{on-chip \code{DP16KD} block RAM}
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(\code{rtl/act\_buffer.v}). Ids \code{0..N\_in-1} are the inputs; each neuron writes its
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own output into its own id. The source gather reads from here with \emph{single-cycle
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random access}: this is what makes the graph cheap, because it is the access that PSRAM
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(70~ns, sequential) could not accelerate.
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\begin{fnspec}[V1 sizing]
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\code{N\_TOTAL}=4096 signals, 16-bit id (room to 65\,536 without changing the format).
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Buffer = 4~KB, i.e. 2 \code{DP16KD} blocks out of 108. The real constraint becomes the
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PSRAM edge capacity ($\approx$2\,M edges at 4~B), not block RAM.
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\end{fnspec}
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\section{Feed-forward DAG and the \texttt{src\_id < out\_id} rule}
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The graph is a feed-forward DAG: every connection points to an \textbf{already-computed}
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id (\code{src\_id < out\_id}). Neurons are processed in ascending id order, so that when a
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neuron is computed all its sources are ready in the buffer. Cycles and recurrence are out
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of scope for V1. The rule is checked at two levels: by the host assembler (compile time)
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and by a runtime guard in \code{graph\_engine} (\code{STATUS.err}), in the same philosophy
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as the elaboration guard on \code{N\_INPUTS \% PARALLEL}.
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\section{Data formats}
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Both descriptors are 11~bytes/entry, MSB-first, at \code{table\_base}.
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\subsection{Type \#2 descriptor (graph)}
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\begin{tabularx}{\textwidth}{L{3.4cm} C{1.6cm} Y}
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\toprule
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\rowh \thd{Field} & \thd{Bytes} & \thd{Meaning} \\
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\midrule
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\code{conn\_ptr} & 3 & Byte address in PSRAM of the neuron's edge block. \\
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\rowa \code{n\_conn} & 2 & Real connections (pre-padding). \\
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\code{out\_id} & 2 & Id into which the neuron's output is written. \\
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\rowa \code{activation} & 1 & \code{ACT\_RELU} / \code{ACT\_NONE} (low 2 bits). \\
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\code{bias} & 1 & Neuron bias (INT8). \\
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\rowa \code{reserved} & 2 & 0. \\
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\midrule
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\rowh \thd{Total} & \thd{11} & entries in ascending \code{out\_id} order \\
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\bottomrule
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\end{tabularx}
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\subsection{Graph edge (4~bytes, aligned)}
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\begin{tabularx}{\textwidth}{L{3.4cm} C{1.6cm} Y}
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\toprule
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\rowh \thd{Field} & \thd{Bytes} & \thd{Meaning} \\
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\midrule
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\code{src\_id} & 2 & Source id (uint16 BE). \\
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\rowa \code{weight} & 1 & Weight (INT8). \\
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\code{reserved} & 1 & 0 (4-byte alignment). \\
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\bottomrule
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\end{tabularx}
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\begin{fnnote}[Padding to \texttt{PARALLEL}]
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An arbitrary \code{n\_conn} is not a multiple of \code{PARALLEL}: the neuron's edge-list
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is padded up to the multiple with \textbf{zero-weight} edges (waste
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$\le$\code{PARALLEL}$-1$ per neuron). This keeps the datapath and its guard intact.
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\end{fnnote}
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\section{\texttt{graph\_engine} --- graph engine}
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\code{rtl/graph\_engine.v} orchestrates Type \#2 \textbf{reusing \code{neuron\_parallel}
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unmodified}, as \code{neuron\_memory} does for the dense case. Key difference: between the
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two modes only the \emph{X addressing} changes. In Type \#1 the input is contiguous
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(\code{x\_base + i}); in Type \#2 it is a gather (\code{act\_buf[src\_id]}). The arithmetic
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core is untouched.
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=4mm,start chain=going below,
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every node/.style={on chain,fnblock,minimum width=52mm}]
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\node[fnblockA]{\code{COPY\_INPUTS}: PSRAM \code{x\_base} $\to$ \code{act\_buf[0..N\_in-1]}};
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\node{\code{READ\_DESC}: descriptor of neuron k};
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\node{\code{READ\_EDGES}: stream edges + gather \code{act\_buf[src\_id]}};
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\node{\code{START\_N} / \code{WAIT\_N}: group of \code{PARALLEL} $\to$ \code{neuron\_parallel}};
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\node[fnblockT]{\code{WRITE\_ACT}: y $\to$ \code{act\_buf[out\_id]}};
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\node{next neuron (id order)};
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\node[fnblockD]{\code{WRITE\_OUTPUTS}: last \code{n\_out} $\to$ PSRAM \code{out\_base}};
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\foreach \i [count=\j from 2] in {1,...,6}
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\draw[fnarrow] (chain-\i) -- (chain-\j);
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\end{tikzpicture}
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\end{center}
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The outputs are the \textbf{last \code{n\_out}} ids: in a DAG with the
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\code{src\_id < out\_id} ordering the output neurons (sinks, not reused as sources)
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naturally end up with the highest ids. At the end \code{graph\_engine} copies these
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\code{n\_out} bytes into a PSRAM region at \code{out\_base}, which the host reads back with
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\op{READ\_RAM}.
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\section{Type \#2 opcodes and registers}
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The type is selected with a new opcode; \op{RUN\_NETWORK} dispatches on the
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\code{net\_type} register (details in ch.~\ref{ch:spi}).
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\begin{tabularx}{\textwidth}{L{2.6cm} L{3.4cm} Y}
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\toprule
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\rowh \thd{Opcode / sel} & \thd{Name} & \thd{Function} \\
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\midrule
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\op{0x11} & SET\_NET\_TYPE & \code{type(1B)}: \code{0x01}=dense (\#1), \code{0x02}=graph (\#2). Default after \op{RESET}=dense. \\
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\rowa \code{SET\_BASE sel 9} & num\_neurons\_graph & Number of graph neurons (uint16). \\
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\code{SET\_BASE sel 10} & n\_out & Number of output ids (uint16). \\
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\bottomrule
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\end{tabularx}
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\begin{fnnote}[Zero regression on Type \#1]
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With \code{net\_type=dense} (the default value after \op{RESET}) the \#1 path is
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bit-identical to before: \op{RUN\_NETWORK} keeps its \code{num\_layers(1B)} payload and the
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framing of the existing opcodes does not change.
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\end{fnnote}
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\section{Occupancy (Type \#2 enabled)}
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Yosys synthesis of the full \code{spi\_neuron\_top} system with Type \#2 enabled
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(\code{PARALLEL}=2):
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\begin{tabularx}{\textwidth}{L{4.6cm} Y}
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\toprule
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\rowh \thd{Resource} & \thd{Use} \\
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\midrule
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\code{DP16KD} (block RAM) & 2 (activation buffer) \\
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\rowa \code{MULT18X18D} (DSP) & 4 (2 \code{neuron\_memory} + 2 \code{graph\_engine}) \\
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LUT4 & 2619 \\
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\rowa TRELLIS\_FF & 2467 \\
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\code{\$\_TBUF\_} (PSRAM bus) & 16 \\
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\bottomrule
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\end{tabularx}
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The device (108 \code{DP16KD}, 72 DSP, $\approx$44k LUT/FF) stays well below saturation:
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Type \#2 adds a complete mode at a contained resource cost. LUT4/TRELLIS\_FF grew from an
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earlier measurement (2367/2406) because of the PSRAM page mode added to the controller
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(ch.~\ref{ch:mem}, \S~5.5) --- under 6\% utilization, no practical impact.
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\section{Gather bandwidth (measured)}
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The per-edge gather cost was \textbf{isolated} by building two structurally-identical
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graphs with different edge counts and differencing the cycles: the subtraction cancels the
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fixed per-neuron overhead and leaves the edge cost alone.
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\begin{fnspec}[Per-edge cost]
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\textbf{37.53 cycles/edge} with PSRAM page mode enabled (ch.~\ref{ch:mem}, \S~5.5) ---
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\textbf{53.25 cycles/edge} without it (pre-page-mode baseline, consistent with theory:
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4~bytes/edge $\times$ $\approx$13 cycles/byte over async PSRAM $\approx$52). At 80~MHz:
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$\approx$2.13\,M edges/s ($\approx$8.5~MB/s, +42\% vs. baseline); at the real 16~MHz
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clock: $\approx$426\,k edges/s ($\approx$1.71~MB/s).
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\end{fnspec}
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Page-mode read (roadmap G7, ch.~\ref{ch:roadmap}) has been implemented and measured: the
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gather's sequential access benefits directly, cutting the per-edge cost by 29.5\%
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(53.25$\to$37.53 cycles/edge). Each edge still pays \code{int8\_memory\_access}'s
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byte-granular access (4 bytes/edge); page mode reduces the cost of each sequential byte,
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not the number of accesses.
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\section{\texttt{netasm} host assembler}
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Readable network configuration needs no dedicated FPGA logic: a pseudo-assembly is
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compiled \emph{on the host} (\code{tools/netasm/}) into the exact bytes of the tables and
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edges, then loaded with \op{WRITE\_RAM}. The assembler validates at compile time
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(\code{src\_id < out\_id}, \code{N\_TOTAL} bounds, padding to \code{PARALLEL}),
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complementing the runtime guard.
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\begin{lstlisting}[language=,caption={Pseudo-assembly example (graph)},basicstyle=\ttfamily\scriptsize]
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NET graph
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INPUTS 4 ; ids 0..3
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NEURON n4 relu bias=2
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CONN 0 w=5
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CONN 1 w=-3
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NEURON n5 none bias=0
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CONN n4 w=2 ; symbolic reference to n4's output
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CONN 2 w=7
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OUTPUT n5
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END
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\end{lstlisting}
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