docs: bring datasheet/ into the main repo under hardware/v2/docs
Was a separate, untracked directory (DataSheet/) outside the repo. Renamed to lowercase and moved in as hardware/v2/docs/datasheet/, with its own .gitignore for LaTeX build byproducts (compiled PDFs stay tracked, .aux/.log/.toc/etc do not). Now versioned and shares this repo's own remote instead of living untracked on disk. Content: IT+EN LaTeX chapter sources, reference manufacturer PDFs, and compiled datasheet PDFs including the 2026-09-07 SDRAM upgrade addendum (AS4C32M16SB-7BIN part/pinout/timing) in the v2-en chapters. Note: hardware/v2/docs/DatasheetLatex/ (and the v1 sibling) is a separate, already-tracked, differently-structured LaTeX document that predates this move -- left untouched, not merged, since its chapter set and content differ and merging was not requested. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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\thispagestyle{plain}
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\noindent
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\begin{tikzpicture}
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\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
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minimum width=\textwidth,anchor=west]
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{\large\bfseries FPGA-Neural --- General description and features};
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\end{tikzpicture}
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\vspace{6pt}
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\noindent
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{\small FPGA-Neural is a \textbf{parametric hardware accelerator for feed-forward
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neural networks} contained entirely within the FPGA. Computation (multiplication,
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accumulation, bias, activation, saturation) takes place entirely on-chip in INT8/INT32
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integer arithmetic; the host system only provides configuration, weights, input data
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and control through a simple SPI interface, without ever being part of the
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computational datapath. A single bitstream serves any topology up to the build
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maximum.}
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\vspace{8pt}
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\begin{multicols}{2}
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{\color{fnDark}\large\bfseries Features}\\[2pt]
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{\footnotesize
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\begin{itemize}[leftmargin=1.1em]
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\item \textbf{INT8 $\times$ INT8 $\to$ INT16 $\to$ INT32} datapath, 32-bit accumulation
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with sign extension.
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\item \textbf{Balanced binary adder tree} ($O(\log_2 \text{PARALLEL})$) instead of
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linear reduction.
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\item Configurable parallel MAC: \code{PARALLEL} simultaneous hardware MACs per neuron,
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mapped onto \code{MULT18X18D} DSPs.
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\item Fully \textbf{parametric} architecture: \code{N\_INPUTS}, \code{N\_NEURONS},
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\code{PARALLEL}, \code{DATA\_WIDTH}, \code{ACC\_WIDTH}, \code{N\_LAYERS}.
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\item \textbf{Runtime network width}: per-layer \code{n\_inputs\_real}/\code{n\_neurons\_real},
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a single bitstream for every topology up to the maximum.
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\item Configurable activations: \code{ACT\_RELU} (default) and \code{ACT\_NONE} (linear
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with bilateral saturation), with INT8 saturation.
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\item \textbf{Two network types}: classic multi-layer dense (\code{layer\_sequencer},
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ping-pong buffers) and \textbf{arbitrary sparse graph} (\code{graph\_engine} +
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activation buffer in \code{DP16KD} block RAM), selectable at runtime.
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\item \textbf{Dedicated memory} subsystem: byte$\leftrightarrow$word interface,
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asynchronous parallel PSRAM controller with \textbf{page mode} (70~ns random
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access, 20~ns page burst), 8~MB addressable (23~bit).
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\item \textbf{SPI Mode 0} MSB-first host interface, \code{SET\_NET\_TYPE}+dispatch, \code{STATUS.done}
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sticky/clear-on-read, runtime \code{READ\_CONFIG}.
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\item \textbf{Flash subsystem} for boot/persistence: FPGA-exclusive access to a
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\code{W25Q128JV} SPI NOR (16~MB) via a dedicated SPI master, a
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flash$\leftrightarrow$PSRAM copy engine, and a 16-slot catalog with CRC32,
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8 host opcodes.
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\item Verified in \textbf{simulation} (Icarus Verilog) and \textbf{real synthesis}
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(Yosys + nextpnr-ecp5 + ecppack).
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\end{itemize}}
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\columnbreak
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{\color{fnDark}\large\bfseries Applications}\\[2pt]
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{\footnotesize
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\begin{itemize}[leftmargin=1.1em]
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\item Deterministic low-latency inference as a peripheral of a
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Linux SoC, Raspberry-Pi-like board, ESP32, microcontrollers.
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\item Reusable hardware block integrable into heterogeneous projects
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(a platform, not a single network).
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\item Edge AI on compact dense INT8-quantized networks.
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\item Off-loading the neural workload from the host CPU to dedicated
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hardware with predictable throughput.
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\end{itemize}}
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\vspace{4pt}
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{\color{fnDark}\large\bfseries Target \& toolchain}\\[2pt]
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{\footnotesize
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\begin{itemize}[leftmargin=1.1em]
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\item FPGA: Lattice ECP5 \code{LFE5U-45F-8BG381C} ($-8$, CABGA381).
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\item Synthesis: Yosys; place\&route: nextpnr-ecp5; bitstream: Project~Trellis
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(\code{ecppack}).
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\item Simulation: Icarus Verilog (\code{-g2012}).
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\item PSRAM: ISSI \code{IS66WVE4M16EBLL-70BLI} (64\,Mb, 4M$\times$16).
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\end{itemize}}
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\end{multicols}
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\vspace{2pt}
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% --- key parameter table ---
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\noindent
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{\small\color{fnDark}\bfseries Key parameters (characterized baseline configuration)}
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\vspace{2pt}
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\noindent
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\begin{tabularx}{\textwidth}{L{3.2cm}L{3.6cm}Y}
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\toprule
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\rowh \thd{Quantity} & \thd{Value} & \thd{Notes} \\
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\midrule
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Data precision & INT8 (signed) & \code{DATA\_WIDTH}=8 \\
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\rowa Accumulator & INT32 (signed) & \code{ACC\_WIDTH}=32 \\
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Inputs / neurons & 256 / 4 & datapath benchmark baseline \\
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\rowa Simultaneous MACs & $2\ldots64$ & $=$\code{PARALLEL}$\times$\code{N\_NEURONS} \\
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Activations & ReLU, linear & \code{ACT\_RELU} / \code{ACT\_NONE} \\
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\rowa Fmax (P=2, datapath) & 87.88~MHz & isolated datapath benchmark \\
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Fmax (P=2, integrated system) & 67.91~MHz & full system incl. flash subsystem, real place\&route \\
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MAC throughput (P=16) & $\approx$3.34~G\,MAC/s & theoretical, datapath only \\
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\rowa Working memory & 8~MB PSRAM & 16-bit parallel bus, 70~ns / 20~ns page mode \\
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Address space & 23~bit (byte) & \code{ADDR\_WIDTH}=23 \\
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\bottomrule
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\end{tabularx}
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\vspace{8pt}
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\noindent
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{\small\color{fnDark}\bfseries System block diagram}
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\begin{center}
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\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize]
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\node[fnblockD,minimum width=26mm,minimum height=13mm] (host){HOST\\{\scriptsize configures / trains / controls}};
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\node[fnblockT,right=16mm of host,minimum width=52mm,minimum height=22mm] (eng){};
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\node[anchor=north,font=\footnotesize\bfseries,text=fnDark] at (eng.north){FPGA -- Neural Network Engine};
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\node[fnreg,fill=white] (spi) at ([yshift=-2mm]eng.center){\code{spi\_slave} + \code{spi\_engine}};
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\node[fnreg,fill=white,below=2.5mm of spi] (arb){\code{mem\_arbiter} + \code{layer\_sequencer}};
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\node[fnreg,fill=white,above=2.5mm of spi] (core){\code{neuron\_memory} $\to$ \code{neuron\_parallel} $\to$ \code{mac8}};
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\node[fnblock,right=16mm of eng,minimum width=24mm,minimum height=13mm] (ram){PSRAM 8\,MB\\{\scriptsize \code{psram\_controller}}};
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\draw[fnbus] (host) -- node[fnlbl,above]{SPI} (eng.west|-host);
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\draw[fnbus] (eng.east|-ram) -- node[fnlbl,above]{16-bit async} (ram);
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\end{tikzpicture}
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\end{center}
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\begin{center}\footnotesize\itshape\color{fnGrey}
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The neural datapath is entirely inside the FPGA; the host does not take part in the
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individual MAC operations.\end{center}
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