docs: consolidate all V2 datasheets into one current, complete document

The repository had accumulated multiple, contradictory "current state"
documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside
hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root
(docs/DatasheetLatex/), and a second, much older documentation track
(hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md,
MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/
N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board.
The LaTeX datasheet's own front matter (features/pinout cover pages) and
chapter 9 (benchmarks) were themselves still describing that obsolete
architecture, contradicting the real, current chapters 5/7/10 elsewhere
in the same document.

This commit:
- Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to
  hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting).
- Removes the old V1 IT/EN LaTeX copies and the stray root-level
  duplicate entirely (recoverable from git history, not from disk).
- Preserves the real component reference PDFs (ECP5 eval board, ISSI
  PSRAM, programming cables) under datasheet/references/.
- Removes 13 superseded hardware/v2/docs/*.md status documents after
  folding every real, unique fact they contained into the datasheet:
  SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed
  boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR),
  and the real FPGA<->SDRAM ball mapping cross-check.
- Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8
  (top-level module -- was documenting the wrong, non-physical top
  entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/
  N_SLOTS=4 production board, while keeping the real PSRAM-era chapters
  as clearly-labeled history rather than deleting correctly-measured
  work.
- Fixes a title-page tikzpicture that was clipped off the page edge
  (pre-existing, unrelated to this change) by scaling it to fit.

Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains
exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up
runbook, not a duplicate spec).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

chapters/00b-pinout.tex

@@ -0,0 +1,67 @@
+\thispagestyle{plain}
+\noindent
+\begin{tikzpicture}
+\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
+      minimum width=\textwidth,anchor=west]
+  {\large\bfseries Pinout summary --- real, board-verified};
+\end{tikzpicture}
+
+\vspace{6pt}
+\noindent
+{\footnotesize
+V2's top-level module, \code{fpga\_neural\_v2\_top.v}, has a complete,
+real ball assignment: every signal --- SDRAM bus, SPI host transport,
+clock/reset, \code{FPGA\_DATA\_READY}, JTAG, configuration mode straps,
+and the boot flash's dedicated MSPI pins --- carries a real CABGA381 ball
+site, sourced from the official Lattice pinout CSV (rev 3.0) and
+cross-checked against Project Trellis's own \code{iodb.json}. This
+supersedes an earlier V2 milestone in which the board-level top had been
+placed only \textbf{unconstrained}; a full, constrained \code{.lpf} now
+exists (\code{hardware/v2/constraints/v2\_board\_top.lpf}) and every
+Fmax number in this datasheet (\S\ref{sec:clock-closure-current}) is
+measured against it.
+}
+
+\vspace{6pt}
+\begin{fnnote}[What is real]
+Every ball in the summary table below is placed, P\&R-confirmed, and
+cross-checked against a real, exported KiCad schematic and BOM
+(\S\ref{sec:schematic-capture}--\ref{sec:bom}) --- not a simulation-only
+placeholder. No PSRAM signals exist anywhere in this revision: the
+single external memory is SDR SDRAM (\S\ref{sec:sdram-mem-addendum}).
+\end{fnnote}
+
+\begin{fnwarn}[What remains open]
+FPGA dynamic power/current draw has not been measured post-implementation
+(no ECP5 power estimator is available in this toolchain), so exact
+decoupling/regulator sizing uses datasheet-based engineering margin, not
+a computed budget. Hold-time closure is a genuine tool-chain limitation
+(no min-delay analysis path available) --- setup timing is fully
+verified. See ch.~\ref{ch:hw} for the complete, disclosed list.
+\end{fnwarn}
+
+\vspace{6pt}
+\noindent
+{\small\color{fnDark}\bfseries Ball summary (see ch.~\ref{ch:hw} for the
+complete, per-signal table)}
+\vspace{2pt}
+
+\noindent
+\begin{tabularx}{\textwidth}{L{3.4cm}L{2.4cm}Y}
+\toprule
+\rowh \thd{Interface} & \thd{Ball count} & \thd{Notes} \\
+\midrule
+SDRAM bus (A[0:12], BA[0:1], DQ[0:15], DQM[0:1], CKE/CS\#/RAS\#/CAS\#/WE\#) & 35 & Bank 6/7, real, P\&R-confirmed \\
+\rowa SPI host transport (\code{sclk}/\code{mosi}/\code{miso}/\code{cs\_n}) & 4 & Bank 6/7, plain GPIO \\
+\code{FPGA\_DATA\_READY}, \code{osc\_clk}, \code{ext\_rst\_n}, \code{sdram\_clk}, \code{pll\_locked} & 5 & Bank 6/7 \\
+\rowa JTAG (TCK/TMS/TDI/TDO) & 4 & Bank 40, to ESP32 \\
+Config control (PROGRAMN/INITN/DONE) + CFG[2:0] straps & 6 & Bank 8 \\
+\rowa Boot-flash dedicated MSPI (CSSPIN/MCLK/D0/D1) & 4 & Bank 8, dual-function \\
+\bottomrule
+\end{tabularx}
+
+\vspace{4pt}
+\noindent
+{\footnotesize\color{fnGrey}
+Complete per-signal ball tables and the real KiCad schematic/BOM: ch.~\ref{ch:hw}.
+Logical (not physical) register-level port list: ch.~\ref{ch:regs}.\par}