micheleandClaude Sonnet 5
6f7b6dd12c
Streaming (main feature this session): - New WebRadioConfig/WebRadioJson core types, ISecureStore-backed persistence - New webradio::WebRadioService (thread-safe live config) + GET/POST /api/streaming - web_radio_stream task now runtime-toggleable (no reboot), no hardcoded URL - Content-Type diagnostic: warns clearly when a URL is a webpage, not an audio stream Boot cleanup: - Removed boot-time auto FM/DAB tune, auto-beep, and the (now-concluded) Si4684 crystal IBIAS/CTUN empirical sweep from main.cpp — tuning/beep are on-demand via the existing REST API only Web UI: - Modernized styling (cards, gradients, toggle switches, light/dark theme) - New Stream tab wired to /api/streaming Fixes found via real idf.py build (not just clangd): - Restored wrongly-removed si4684/Si4684Tuner.hpp include in main.cpp - Fixed MP3Decode() argument types in web_radio_stream.cpp (unsigned char**/int*) Quality-gate fixes: - Host-test stub headers (esp_log.h, freertos/*) so TunerService.cpp's scanForStation logging/pacing compiles for station_service_test / integration_service_test instead of running stale binaries - Added WifiScanner and WebRadioService manual sections; filled in missing Doxygen docs on BluetoothService, i2s_sdata_probe, test_firmware, Bt1035At - Ignore clangd's .cache/ index directory Also includes prior uncommitted work carried in the tree: Wi-Fi/Bluetooth device scan REST API and UI (WifiScanner, BT scan), SigmaStudio TCP bridge, and the current ADAU1701 SigmaStudio DSP program export. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
566 lines
29 KiB
C
566 lines
29 KiB
C
/*
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* File: C:\Users\mikbi\Documents\Allegati\Desktop\DigiRadio\DigiRadioModificato\DigiRadio_IC_1_REG.h
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*
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* Created: Friday, August 7, 2026 3:19:11 AM
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* Description: DigiRadio:IC 1 control register definitions.
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*
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* This software is distributed in the hope that it will be useful,
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* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* This software may only be used to program products purchased from
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* Analog Devices for incorporation by you into audio products that
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* are intended for resale to audio product end users. This software
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* may not be distributed whole or in any part to third parties.
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*
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* Copyright ©2026 Analog Devices, Inc. All rights reserved.
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*/
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#ifndef __DIGIRADIO_IC_1_REG_H__
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#define __DIGIRADIO_IC_1_REG_H__
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/* InterfaceRegister0 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER0_IC_1_ADDR 0x800
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#define REG_INTERFACEREGISTER0_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER0_IC_1_VALUE 0x0
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/* InterfaceRegister1 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER1_IC_1_ADDR 0x801
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#define REG_INTERFACEREGISTER1_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER1_IC_1_VALUE 0x0
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/* InterfaceRegister2 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER2_IC_1_ADDR 0x802
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#define REG_INTERFACEREGISTER2_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER2_IC_1_VALUE 0x0
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/* InterfaceRegister3 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER3_IC_1_ADDR 0x803
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#define REG_INTERFACEREGISTER3_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER3_IC_1_VALUE 0x0
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/* InterfaceRegister4 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER4_IC_1_ADDR 0x804
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#define REG_INTERFACEREGISTER4_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER4_IC_1_VALUE 0x0
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/* InterfaceRegister5 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER5_IC_1_ADDR 0x805
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#define REG_INTERFACEREGISTER5_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER5_IC_1_VALUE 0x0
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/* InterfaceRegister6 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER6_IC_1_ADDR 0x806
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#define REG_INTERFACEREGISTER6_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER6_IC_1_VALUE 0x0
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/* InterfaceRegister7 - Registers (IC 1) */
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#define REG_INTERFACEREGISTER7_IC_1_ADDR 0x807
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#define REG_INTERFACEREGISTER7_IC_1_BYTE 4
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#define REG_INTERFACEREGISTER7_IC_1_VALUE 0x0
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/* GpioAllRegister - Registers (IC 1) */
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#define REG_GPIOALLREGISTER_IC_1_ADDR 0x808
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#define REG_GPIOALLREGISTER_IC_1_BYTE 2
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#define REG_GPIOALLREGISTER_IC_1_VALUE 0x0
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/* Adc0 - Registers (IC 1) */
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#define REG_ADC0_IC_1_ADDR 0x809
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#define REG_ADC0_IC_1_BYTE 1
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#define REG_ADC0_IC_1_VALUE 0x0
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/* Adc1 - Registers (IC 1) */
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#define REG_ADC1_IC_1_ADDR 0x80A
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#define REG_ADC1_IC_1_BYTE 1
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#define REG_ADC1_IC_1_VALUE 0x0
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/* Adc2 - Registers (IC 1) */
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#define REG_ADC2_IC_1_ADDR 0x80B
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#define REG_ADC2_IC_1_BYTE 1
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#define REG_ADC2_IC_1_VALUE 0x0
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/* Adc3 - Registers (IC 1) */
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#define REG_ADC3_IC_1_ADDR 0x80C
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#define REG_ADC3_IC_1_BYTE 1
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#define REG_ADC3_IC_1_VALUE 0x0
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/* CoreRegister - Registers (IC 1) */
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#define REG_COREREGISTER_IC_1_ADDR 0x81C
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#define REG_COREREGISTER_IC_1_BYTE 2
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#define REG_COREREGISTER_IC_1_VALUE 0x1C
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/* RAMRegister - Registers (IC 1) */
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#define REG_RAMREGISTER_IC_1_ADDR 0x81D
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#define REG_RAMREGISTER_IC_1_BYTE 1
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#define REG_RAMREGISTER_IC_1_VALUE 0xB
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/* SerialOutRegister1 - Registers (IC 1) */
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#define REG_SERIALOUTREGISTER1_IC_1_ADDR 0x81E
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#define REG_SERIALOUTREGISTER1_IC_1_BYTE 2
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#define REG_SERIALOUTREGISTER1_IC_1_VALUE 0x800
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/* SerialInputRegister - Registers (IC 1) */
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#define REG_SERIALINPUTREGISTER_IC_1_ADDR 0x81F
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#define REG_SERIALINPUTREGISTER_IC_1_BYTE 1
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#define REG_SERIALINPUTREGISTER_IC_1_VALUE 0x0
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/* MpCfg0 - Registers (IC 1) */
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#define REG_MPCFG0_IC_1_ADDR 0x820
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#define REG_MPCFG0_IC_1_BYTE 3
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#define REG_MPCFG0_IC_1_VALUE 0x440044
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/* MpCfg1 - Registers (IC 1) */
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#define REG_MPCFG1_IC_1_ADDR 0x821
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#define REG_MPCFG1_IC_1_BYTE 3
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#define REG_MPCFG1_IC_1_VALUE 0x440004
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/* AnalogPowerDownRegister - Registers (IC 1) */
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#define REG_ANALOGPOWERDOWNREGISTER_IC_1_ADDR 0x822
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#define REG_ANALOGPOWERDOWNREGISTER_IC_1_BYTE 2
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#define REG_ANALOGPOWERDOWNREGISTER_IC_1_VALUE 0x0
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/* TestRegister - Registers (IC 1) */
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#define REG_TESTREGISTER_IC_1_ADDR 0x823
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#define REG_TESTREGISTER_IC_1_BYTE 2
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#define REG_TESTREGISTER_IC_1_VALUE 0x0
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/* AnalogInterfaceRegister0 - Registers (IC 1) */
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#define REG_ANALOGINTERFACEREGISTER0_IC_1_ADDR 0x824
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#define REG_ANALOGINTERFACEREGISTER0_IC_1_BYTE 2
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#define REG_ANALOGINTERFACEREGISTER0_IC_1_VALUE 0x8000
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/* AnalogInterfaceRegister1 - Registers (IC 1) */
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#define REG_ANALOGINTERFACEREGISTER1_IC_1_ADDR 0x825
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#define REG_ANALOGINTERFACEREGISTER1_IC_1_BYTE 2
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#define REG_ANALOGINTERFACEREGISTER1_IC_1_VALUE 0x0
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/* AnalogInterfaceRegister2 - Registers (IC 1) */
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#define REG_ANALOGINTERFACEREGISTER2_IC_1_ADDR 0x826
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#define REG_ANALOGINTERFACEREGISTER2_IC_1_BYTE 2
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#define REG_ANALOGINTERFACEREGISTER2_IC_1_VALUE 0x0
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/* AnalogInterfaceRegister3 - Registers (IC 1) */
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#define REG_ANALOGINTERFACEREGISTER3_IC_1_ADDR 0x827
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#define REG_ANALOGINTERFACEREGISTER3_IC_1_BYTE 2
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#define REG_ANALOGINTERFACEREGISTER3_IC_1_VALUE 0x1
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/*
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*
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* Control register's field descriptions
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*
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*/
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/* InterfaceRegister0 (IC 1) */
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#define R0_INTERFACEREGISTER0_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R0_INTERFACEREGISTER0_IC_1_MASK 0xFFFFFFFF
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#define R0_INTERFACEREGISTER0_IC_1_SHIFT 0
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/* InterfaceRegister1 (IC 1) */
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#define R1_INTERFACEREGISTER1_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R1_INTERFACEREGISTER1_IC_1_MASK 0xFFFFFFFF
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#define R1_INTERFACEREGISTER1_IC_1_SHIFT 0
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/* InterfaceRegister2 (IC 1) */
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#define R2_INTERFACEREGISTER2_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R2_INTERFACEREGISTER2_IC_1_MASK 0xFFFFFFFF
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#define R2_INTERFACEREGISTER2_IC_1_SHIFT 0
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/* InterfaceRegister3 (IC 1) */
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#define R3_INTERFACEREGISTER3_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R3_INTERFACEREGISTER3_IC_1_MASK 0xFFFFFFFF
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#define R3_INTERFACEREGISTER3_IC_1_SHIFT 0
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/* InterfaceRegister4 (IC 1) */
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#define R4_INTERFACEREGISTER4_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R4_INTERFACEREGISTER4_IC_1_MASK 0xFFFFFFFF
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#define R4_INTERFACEREGISTER4_IC_1_SHIFT 0
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/* InterfaceRegister5 (IC 1) */
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#define R5_INTERFACEREGISTER5_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R5_INTERFACEREGISTER5_IC_1_MASK 0xFFFFFFFF
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#define R5_INTERFACEREGISTER5_IC_1_SHIFT 0
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/* InterfaceRegister6 (IC 1) */
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#define R6_INTERFACEREGISTER6_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R6_INTERFACEREGISTER6_IC_1_MASK 0xFFFFFFFF
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#define R6_INTERFACEREGISTER6_IC_1_SHIFT 0
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/* InterfaceRegister7 (IC 1) */
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#define R7_INTERFACEREGISTER7_IC_1 0x00000000 /* 00000000000000000000000000000000b [31:0] */
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#define R7_INTERFACEREGISTER7_IC_1_MASK 0xFFFFFFFF
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#define R7_INTERFACEREGISTER7_IC_1_SHIFT 0
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/* GpioAllRegister (IC 1) */
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#define R8_PIN0_IC_1 0x0 /* 0b [0] */
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#define R8_PIN1_IC_1 0x0 /* 0b [1] */
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#define R8_PIN2_IC_1 0x0 /* 0b [2] */
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#define R8_PIN3_IC_1 0x0 /* 0b [3] */
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#define R8_PIN4_IC_1 0x0 /* 0b [4] */
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#define R8_PIN5_IC_1 0x0 /* 0b [5] */
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#define R8_PIN6_IC_1 0x0 /* 0b [6] */
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#define R8_PIN7_IC_1 0x0 /* 0b [7] */
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#define R8_PIN8_IC_1 0x0 /* 0b [8] */
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#define R8_PIN9_IC_1 0x0 /* 0b [9] */
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#define R8_PIN10_IC_1 0x0 /* 0b [10] */
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#define R8_PIN11_IC_1 0x0 /* 0b [11] */
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#define R8_PIN0_IC_1_MASK 0x1
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#define R8_PIN0_IC_1_SHIFT 0
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#define R8_PIN1_IC_1_MASK 0x2
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#define R8_PIN1_IC_1_SHIFT 1
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#define R8_PIN2_IC_1_MASK 0x4
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#define R8_PIN2_IC_1_SHIFT 2
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#define R8_PIN3_IC_1_MASK 0x8
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#define R8_PIN3_IC_1_SHIFT 3
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#define R8_PIN4_IC_1_MASK 0x10
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#define R8_PIN4_IC_1_SHIFT 4
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#define R8_PIN5_IC_1_MASK 0x20
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#define R8_PIN5_IC_1_SHIFT 5
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#define R8_PIN6_IC_1_MASK 0x40
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#define R8_PIN6_IC_1_SHIFT 6
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#define R8_PIN7_IC_1_MASK 0x80
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#define R8_PIN7_IC_1_SHIFT 7
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#define R8_PIN8_IC_1_MASK 0x100
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#define R8_PIN8_IC_1_SHIFT 8
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#define R8_PIN9_IC_1_MASK 0x200
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#define R8_PIN9_IC_1_SHIFT 9
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#define R8_PIN10_IC_1_MASK 0x400
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#define R8_PIN10_IC_1_SHIFT 10
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#define R8_PIN11_IC_1_MASK 0x800
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#define R8_PIN11_IC_1_SHIFT 11
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/* Adc0 (IC 1) */
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#define R9_ADC0_IC_1 0x00 /* 00000000b [7:0] */
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#define R9_ADC0_IC_1_MASK 0xFF
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#define R9_ADC0_IC_1_SHIFT 0
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/* Adc1 (IC 1) */
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#define R10_ADC1_IC_1 0x00 /* 00000000b [7:0] */
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#define R10_ADC1_IC_1_MASK 0xFF
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#define R10_ADC1_IC_1_SHIFT 0
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/* Adc2 (IC 1) */
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#define R11_ADC2_IC_1 0x00 /* 00000000b [7:0] */
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#define R11_ADC2_IC_1_MASK 0xFF
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#define R11_ADC2_IC_1_SHIFT 0
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/* Adc3 (IC 1) */
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#define R12_ADC3_IC_1 0x00 /* 00000000b [7:0] */
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#define R12_ADC3_IC_1_MASK 0xFF
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#define R12_ADC3_IC_1_SHIFT 0
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/* CoreRegister (IC 1) */
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#define R13_PROGRAM_LENGTH_IC_1 0x0 /* 00b [1:0] */
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#define R13_REGISTER_ZERO_IC_1 0x1 /* 1b [2] */
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#define R13_MUTE_DAC_IC_1 0x1 /* 1b [3] */
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#define R13_MUTE_ADC_IC_1 0x1 /* 1b [4] */
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#define R13_SAFELOAD_IC_1 0x0 /* 0b [5] */
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#define R13_WRITESPI_INTERFACEREG_IC_1 0x0 /* 0b [6] */
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#define R13_WRITESPI_GPIO_IC_1 0x0 /* 0b [7] */
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#define R13_WRITESPI_ADC_IC_1 0x0 /* 0b [8] */
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#define R13_MUTE_SERIALIN_IC_1 0x0 /* 0b [9] */
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#define R13_GPIO_DEBOUNCE_IC_1 0x0 /* 00b [11:10] */
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#define R13_EXTMEM_SPEED_IC_1 0x0 /* 00b [13:12] */
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#define R13_PROGRAM_LENGTH_IC_1_MASK 0x3
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#define R13_PROGRAM_LENGTH_IC_1_SHIFT 0
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#define R13_REGISTER_ZERO_IC_1_MASK 0x4
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#define R13_REGISTER_ZERO_IC_1_SHIFT 2
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#define R13_MUTE_DAC_IC_1_MASK 0x8
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#define R13_MUTE_DAC_IC_1_SHIFT 3
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#define R13_MUTE_ADC_IC_1_MASK 0x10
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#define R13_MUTE_ADC_IC_1_SHIFT 4
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#define R13_SAFELOAD_IC_1_MASK 0x20
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#define R13_SAFELOAD_IC_1_SHIFT 5
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#define R13_WRITESPI_INTERFACEREG_IC_1_MASK 0x40
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#define R13_WRITESPI_INTERFACEREG_IC_1_SHIFT 6
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#define R13_WRITESPI_GPIO_IC_1_MASK 0x80
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#define R13_WRITESPI_GPIO_IC_1_SHIFT 7
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#define R13_WRITESPI_ADC_IC_1_MASK 0x100
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#define R13_WRITESPI_ADC_IC_1_SHIFT 8
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#define R13_MUTE_SERIALIN_IC_1_MASK 0x200
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#define R13_MUTE_SERIALIN_IC_1_SHIFT 9
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#define R13_GPIO_DEBOUNCE_IC_1_MASK 0xC00
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#define R13_GPIO_DEBOUNCE_IC_1_SHIFT 10
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#define R13_EXTMEM_SPEED_IC_1_MASK 0x3000
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#define R13_EXTMEM_SPEED_IC_1_SHIFT 12
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/* RAMRegister (IC 1) */
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#define R14_RAM_MODULO_IC_1 0xB /* 1011b [3:0] */
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#define R14_RAM_MODULO_IC_1_MASK 0xF
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#define R14_RAM_MODULO_IC_1_SHIFT 0
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/* SerialOutRegister1 (IC 1) */
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#define R15_WORDLENGTH_IC_1 0x0 /* 00b [1:0] */
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#define R15_MSB_POS_IC_1 0x0 /* 000b [4:2] */
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#define R15_TDM_IC_1 0x0 /* 0b [5] */
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#define R15_FRAMESYNC_TYPE_IC_1 0x0 /* 0b [6] */
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#define R15_LRCLK_FREQ_IC_1 0x0 /* 00b [8:7] */
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#define R15_BCLK_FREQ_IC_1 0x0 /* 00b [10:9] */
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#define R15_MASTER_SLAVE_IC_1 0x1 /* 1b [11] */
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#define R15_BCLK_POLARITY_IC_1 0x0 /* 0b [12] */
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#define R15_LRCLK_POLARITY_IC_1 0x0 /* 0b [13] */
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#define R15_WORDLENGTH_IC_1_MASK 0x3
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#define R15_WORDLENGTH_IC_1_SHIFT 0
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#define R15_MSB_POS_IC_1_MASK 0x1C
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#define R15_MSB_POS_IC_1_SHIFT 2
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#define R15_TDM_IC_1_MASK 0x20
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#define R15_TDM_IC_1_SHIFT 5
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#define R15_FRAMESYNC_TYPE_IC_1_MASK 0x40
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#define R15_FRAMESYNC_TYPE_IC_1_SHIFT 6
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#define R15_LRCLK_FREQ_IC_1_MASK 0x180
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#define R15_LRCLK_FREQ_IC_1_SHIFT 7
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#define R15_BCLK_FREQ_IC_1_MASK 0x600
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#define R15_BCLK_FREQ_IC_1_SHIFT 9
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#define R15_MASTER_SLAVE_IC_1_MASK 0x800
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#define R15_MASTER_SLAVE_IC_1_SHIFT 11
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#define R15_BCLK_POLARITY_IC_1_MASK 0x1000
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#define R15_BCLK_POLARITY_IC_1_SHIFT 12
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#define R15_LRCLK_POLARITY_IC_1_MASK 0x2000
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#define R15_LRCLK_POLARITY_IC_1_SHIFT 13
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/* SerialInputRegister (IC 1) */
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#define R16_INPUT_MODE_IC_1 0x0 /* 000b [2:0] */
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#define R16_BCLK_POLARITY_IC_1 0x0 /* 0b [3] */
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#define R16_LRCLK_POLARITY_IC_1 0x0 /* 0b [4] */
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#define R16_INPUT_MODE_IC_1_MASK 0x7
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#define R16_INPUT_MODE_IC_1_SHIFT 0
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#define R16_BCLK_POLARITY_IC_1_MASK 0x8
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#define R16_BCLK_POLARITY_IC_1_SHIFT 3
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#define R16_LRCLK_POLARITY_IC_1_MASK 0x10
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#define R16_LRCLK_POLARITY_IC_1_SHIFT 4
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/* MpCfg0 (IC 1) */
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#define R17_MFSELECT0_IC_1 0x4 /* 100b [2:0] */
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#define R17_MFINVERT0_IC_1 0x0 /* 0b [3] */
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#define R17_MFSELECT1_IC_1 0x4 /* 100b [6:4] */
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#define R17_MFINVERT1_IC_1 0x0 /* 0b [7] */
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#define R17_MFSELECT2_IC_1 0x0 /* 000b [10:8] */
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#define R17_MFINVERT2_IC_1 0x0 /* 0b [11] */
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#define R17_MFSELECT3_IC_1 0x0 /* 000b [14:12] */
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#define R17_MFINVERT3_IC_1 0x0 /* 0b [15] */
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#define R17_MFSELECT4_IC_1 0x4 /* 100b [18:16] */
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#define R17_MFINVERT4_IC_1 0x0 /* 0b [19] */
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#define R17_MFSELECT5_IC_1 0x4 /* 100b [22:20] */
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#define R17_MFINVERT5_IC_1 0x0 /* 0b [23] */
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#define R17_MFSELECT0_IC_1_MASK 0x7
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#define R17_MFSELECT0_IC_1_SHIFT 0
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#define R17_MFINVERT0_IC_1_MASK 0x8
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#define R17_MFINVERT0_IC_1_SHIFT 3
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#define R17_MFSELECT1_IC_1_MASK 0x70
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#define R17_MFSELECT1_IC_1_SHIFT 4
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#define R17_MFINVERT1_IC_1_MASK 0x80
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#define R17_MFINVERT1_IC_1_SHIFT 7
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#define R17_MFSELECT2_IC_1_MASK 0x700
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#define R17_MFSELECT2_IC_1_SHIFT 8
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#define R17_MFINVERT2_IC_1_MASK 0x800
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#define R17_MFINVERT2_IC_1_SHIFT 11
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#define R17_MFSELECT3_IC_1_MASK 0x7000
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#define R17_MFSELECT3_IC_1_SHIFT 12
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#define R17_MFINVERT3_IC_1_MASK 0x8000
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#define R17_MFINVERT3_IC_1_SHIFT 15
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#define R17_MFSELECT4_IC_1_MASK 0x70000
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#define R17_MFSELECT4_IC_1_SHIFT 16
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#define R17_MFINVERT4_IC_1_MASK 0x80000
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#define R17_MFINVERT4_IC_1_SHIFT 19
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#define R17_MFSELECT5_IC_1_MASK 0x700000
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#define R17_MFSELECT5_IC_1_SHIFT 20
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#define R17_MFINVERT5_IC_1_MASK 0x800000
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#define R17_MFINVERT5_IC_1_SHIFT 23
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/* MpCfg1 (IC 1) */
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#define R18_MFSELECT6_IC_1 0x4 /* 100b [2:0] */
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#define R18_MFINVERT6_IC_1 0x0 /* 0b [3] */
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#define R18_MFSELECT7_IC_1 0x0 /* 000b [6:4] */
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#define R18_MFINVERT7_IC_1 0x0 /* 0b [7] */
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#define R18_MFSELECT8_IC_1 0x0 /* 000b [10:8] */
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#define R18_MFINVERT8_IC_1 0x0 /* 0b [11] */
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#define R18_MFSELECT9_IC_1 0x0 /* 000b [14:12] */
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#define R18_MFINVERT9_IC_1 0x0 /* 0b [15] */
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#define R18_MFSELECT10_IC_1 0x4 /* 100b [18:16] */
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#define R18_MFINVERT10_IC_1 0x0 /* 0b [19] */
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#define R18_MFSELECT11_IC_1 0x4 /* 100b [22:20] */
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#define R18_MFINVERT11_IC_1 0x0 /* 0b [23] */
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#define R18_MFSELECT6_IC_1_MASK 0x7
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#define R18_MFSELECT6_IC_1_SHIFT 0
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#define R18_MFINVERT6_IC_1_MASK 0x8
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#define R18_MFINVERT6_IC_1_SHIFT 3
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#define R18_MFSELECT7_IC_1_MASK 0x70
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#define R18_MFSELECT7_IC_1_SHIFT 4
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#define R18_MFINVERT7_IC_1_MASK 0x80
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#define R18_MFINVERT7_IC_1_SHIFT 7
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#define R18_MFSELECT8_IC_1_MASK 0x700
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#define R18_MFSELECT8_IC_1_SHIFT 8
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#define R18_MFINVERT8_IC_1_MASK 0x800
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#define R18_MFINVERT8_IC_1_SHIFT 11
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#define R18_MFSELECT9_IC_1_MASK 0x7000
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#define R18_MFSELECT9_IC_1_SHIFT 12
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#define R18_MFINVERT9_IC_1_MASK 0x8000
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#define R18_MFINVERT9_IC_1_SHIFT 15
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#define R18_MFSELECT10_IC_1_MASK 0x70000
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#define R18_MFSELECT10_IC_1_SHIFT 16
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#define R18_MFINVERT10_IC_1_MASK 0x80000
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#define R18_MFINVERT10_IC_1_SHIFT 19
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#define R18_MFSELECT11_IC_1_MASK 0x700000
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#define R18_MFSELECT11_IC_1_SHIFT 20
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#define R18_MFINVERT11_IC_1_MASK 0x800000
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#define R18_MFINVERT11_IC_1_SHIFT 23
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/* AnalogPowerDownRegister (IC 1) */
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#define R19_DAC3_POWERDOWN_IC_1 0x0 /* 0b [0] */
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#define R19_DAC2_POWERDOWN_IC_1 0x0 /* 0b [1] */
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#define R19_DAC1_POWERDOWN_IC_1 0x0 /* 0b [2] */
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#define R19_DAC0_POWERDOWN_IC_1 0x0 /* 0b [3] */
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#define R19_DACS_RESET_IC_1 0x0 /* 0b [4] */
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#define R19_REF_CORE_POWERDOWN_IC_1 0x0 /* 0b [5] */
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#define R19_REF_BUF_POWERDOWN_IC_1 0x0 /* 0b [6] */
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#define R19_ADCS_POWERDOWN_IC_1 0x0 /* 0b [7] */
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#define R19_AUX_ADC_FILTER_IC_1 0x0 /* 000b [10:8] */
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#define R19_DAC3_POWERDOWN_IC_1_MASK 0x1
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#define R19_DAC3_POWERDOWN_IC_1_SHIFT 0
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#define R19_DAC2_POWERDOWN_IC_1_MASK 0x2
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#define R19_DAC2_POWERDOWN_IC_1_SHIFT 1
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#define R19_DAC1_POWERDOWN_IC_1_MASK 0x4
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#define R19_DAC1_POWERDOWN_IC_1_SHIFT 2
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#define R19_DAC0_POWERDOWN_IC_1_MASK 0x8
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#define R19_DAC0_POWERDOWN_IC_1_SHIFT 3
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#define R19_DACS_RESET_IC_1_MASK 0x10
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#define R19_DACS_RESET_IC_1_SHIFT 4
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#define R19_REF_CORE_POWERDOWN_IC_1_MASK 0x20
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#define R19_REF_CORE_POWERDOWN_IC_1_SHIFT 5
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#define R19_REF_BUF_POWERDOWN_IC_1_MASK 0x40
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#define R19_REF_BUF_POWERDOWN_IC_1_SHIFT 6
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#define R19_ADCS_POWERDOWN_IC_1_MASK 0x80
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#define R19_ADCS_POWERDOWN_IC_1_SHIFT 7
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#define R19_AUX_ADC_FILTER_IC_1_MASK 0x700
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#define R19_AUX_ADC_FILTER_IC_1_SHIFT 8
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/* TestRegister (IC 1) */
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#define R20_ADCCLOCKDELAY_IC_1 0x0 /* 000b [2:0] */
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#define R20_ADCSYNCFILTL_SDATAA_D_IC_1 0x0 /* 0b [3] */
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#define R20_ADCSYNCFILTR_SDATAA_D_IC_1 0x0 /* 0b [4] */
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#define R20_SPIKEFILT_SEROUT0_1_IC_1 0x0 /* 0b [5] */
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#define R20_UNUSED_IC_1 0x00 /* 0000000000b [15:6] */
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#define R20_ADCCLOCKDELAY_IC_1_MASK 0x7
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#define R20_ADCCLOCKDELAY_IC_1_SHIFT 0
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#define R20_ADCSYNCFILTL_SDATAA_D_IC_1_MASK 0x8
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#define R20_ADCSYNCFILTL_SDATAA_D_IC_1_SHIFT 3
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#define R20_ADCSYNCFILTR_SDATAA_D_IC_1_MASK 0x10
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#define R20_ADCSYNCFILTR_SDATAA_D_IC_1_SHIFT 4
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#define R20_SPIKEFILT_SEROUT0_1_IC_1_MASK 0x20
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#define R20_SPIKEFILT_SEROUT0_1_IC_1_SHIFT 5
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#define R20_UNUSED_IC_1_MASK 0xFFC0
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#define R20_UNUSED_IC_1_SHIFT 6
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/* AnalogInterfaceRegister0 (IC 1) */
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#define R21_CHOP_ENB_INT_AMP_IC_1 0x0 /* 0b [0] */
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#define R21_PD_INT_AMP_IC_1 0x0 /* 0b [1] */
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#define R21_ADC_NON_OVERLAP_ADJ_IC_1 0x0 /* 0b [2] */
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#define R21_ADC_I_SEL_IC_1 0x0 /* 00000b [7:3] */
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#define R21_ADC_CLK_ADJ_IC_1 0x0 /* 000b [10:8] */
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#define R21_LCHOP_PMOS_CTRL_IC_1 0x0 /* 00b [12:11] */
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#define R21_LCHOP_AMP_ENB_IC_1 0x0 /* 0b [13] */
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#define R21_LSCRAM_ENB_IC_1 0x0 /* 0b [14] */
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#define R21_AUX_ADC_EN_IC_1 0x1 /* 1b [15] */
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#define R21_CHOP_ENB_INT_AMP_IC_1_MASK 0x1
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#define R21_CHOP_ENB_INT_AMP_IC_1_SHIFT 0
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#define R21_PD_INT_AMP_IC_1_MASK 0x2
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#define R21_PD_INT_AMP_IC_1_SHIFT 1
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#define R21_ADC_NON_OVERLAP_ADJ_IC_1_MASK 0x4
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#define R21_ADC_NON_OVERLAP_ADJ_IC_1_SHIFT 2
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#define R21_ADC_I_SEL_IC_1_MASK 0xF8
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#define R21_ADC_I_SEL_IC_1_SHIFT 3
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#define R21_ADC_CLK_ADJ_IC_1_MASK 0x700
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#define R21_ADC_CLK_ADJ_IC_1_SHIFT 8
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#define R21_LCHOP_PMOS_CTRL_IC_1_MASK 0x1800
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#define R21_LCHOP_PMOS_CTRL_IC_1_SHIFT 11
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#define R21_LCHOP_AMP_ENB_IC_1_MASK 0x2000
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#define R21_LCHOP_AMP_ENB_IC_1_SHIFT 13
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#define R21_LSCRAM_ENB_IC_1_MASK 0x4000
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#define R21_LSCRAM_ENB_IC_1_SHIFT 14
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#define R21_AUX_ADC_EN_IC_1_MASK 0x8000
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#define R21_AUX_ADC_EN_IC_1_SHIFT 15
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/* AnalogInterfaceRegister1 (IC 1) */
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#define R22_RSWC_DAC_CTRL_IC_1 0x0 /* 00b [1:0] */
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#define R22_RCLK_SEL_PMOS_IC_1 0x0 /* 00b [3:2] */
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#define R22_RCLK_SEL_AMP_IC_1 0x0 /* 00b [5:4] */
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#define R22_RCHOP_PMOS_CTRL_IC_1 0x0 /* 00b [7:6] */
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#define R22_LCLK_SEL_PMOS_IC_1 0x0 /* 00b [9:8] */
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#define R22_LSWC_DAC_CTRL_IC_1 0x0 /* 00b [11:10] */
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#define R22_CLK_SEL_INT_AMP_IC_1 0x0 /* 00b [13:12] */
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#define R22_RSWC_DAC_CTRL_IC_1_MASK 0x3
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#define R22_RSWC_DAC_CTRL_IC_1_SHIFT 0
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#define R22_RCLK_SEL_PMOS_IC_1_MASK 0xC
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#define R22_RCLK_SEL_PMOS_IC_1_SHIFT 2
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#define R22_RCLK_SEL_AMP_IC_1_MASK 0x30
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#define R22_RCLK_SEL_AMP_IC_1_SHIFT 4
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#define R22_RCHOP_PMOS_CTRL_IC_1_MASK 0xC0
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#define R22_RCHOP_PMOS_CTRL_IC_1_SHIFT 6
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#define R22_LCLK_SEL_PMOS_IC_1_MASK 0x300
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#define R22_LCLK_SEL_PMOS_IC_1_SHIFT 8
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#define R22_LSWC_DAC_CTRL_IC_1_MASK 0xC00
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#define R22_LSWC_DAC_CTRL_IC_1_SHIFT 10
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#define R22_CLK_SEL_INT_AMP_IC_1_MASK 0x3000
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#define R22_CLK_SEL_INT_AMP_IC_1_SHIFT 12
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/* AnalogInterfaceRegister2 (IC 1) */
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#define R23_UNUSED_IC_1 0x0 /* 0b [0] */
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#define R23_ADC_DITHER_EN_IC_1 0x0 /* 0b [1] */
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#define R23_XTAL_ENB_IC_1 0x0 /* 0b [2] */
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#define R23_PLL_PD_IC_1 0x0 /* 0b [3] */
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#define R23_IBIAS_TO_PIN_IC_1 0x0 /* 0b [4] */
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#define R23_IBIAS_ADJ_IC_1 0x0 /* 0000b [8:5] */
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#define R23_VREF_TRIM_IC_1 0x0 /* 0000b [12:9] */
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#define R23_REF_I_SEL_IC_1 0x0 /* 0b [13] */
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#define R23_RSCRAM_ENB_IC_1 0x0 /* 0b [14] */
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#define R23_LCHOP_AMP_ENB_IC_1 0x0 /* 0b [15] */
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#define R23_UNUSED_IC_1_MASK 0x1
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#define R23_UNUSED_IC_1_SHIFT 0
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#define R23_ADC_DITHER_EN_IC_1_MASK 0x2
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#define R23_ADC_DITHER_EN_IC_1_SHIFT 1
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#define R23_XTAL_ENB_IC_1_MASK 0x4
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#define R23_XTAL_ENB_IC_1_SHIFT 2
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#define R23_PLL_PD_IC_1_MASK 0x8
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#define R23_PLL_PD_IC_1_SHIFT 3
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#define R23_IBIAS_TO_PIN_IC_1_MASK 0x10
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#define R23_IBIAS_TO_PIN_IC_1_SHIFT 4
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#define R23_IBIAS_ADJ_IC_1_MASK 0x1E0
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#define R23_IBIAS_ADJ_IC_1_SHIFT 5
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#define R23_VREF_TRIM_IC_1_MASK 0x1E00
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#define R23_VREF_TRIM_IC_1_SHIFT 9
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#define R23_REF_I_SEL_IC_1_MASK 0x2000
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#define R23_REF_I_SEL_IC_1_SHIFT 13
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#define R23_RSCRAM_ENB_IC_1_MASK 0x4000
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#define R23_RSCRAM_ENB_IC_1_SHIFT 14
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#define R23_LCHOP_AMP_ENB_IC_1_MASK 0x8000
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#define R23_LCHOP_AMP_ENB_IC_1_SHIFT 15
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/* AnalogInterfaceRegister3 (IC 1) */
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#define R24_DAC_OFFSET_IC_1 0x1 /* 01b [1:0] */
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#define R24_DAC_DITHER_ENABLE_IC_1 0x0 /* 0b [2] */
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#define R24_PCTRL_IC_1 0x0 /* 00b [4:3] */
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#define R24_DAC_PCLK_SEL_IC_1 0x0 /* 00b [6:5] */
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#define R24_DAC_I_SEL_IC_1 0x0 /* 0000b [10:7] */
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#define R24_DAC_CLK_SEL_IC_1 0x0 /* 00b [12:11] */
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#define R24_DAC_CHOP_ENB_IC_1 0x0 /* 0b [13] */
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#define R24_DAC_DRTZ_IC_1 0x0 /* 00b [15:14] */
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#define R24_DAC_OFFSET_IC_1_MASK 0x3
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#define R24_DAC_OFFSET_IC_1_SHIFT 0
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#define R24_DAC_DITHER_ENABLE_IC_1_MASK 0x4
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#define R24_DAC_DITHER_ENABLE_IC_1_SHIFT 2
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#define R24_PCTRL_IC_1_MASK 0x18
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#define R24_PCTRL_IC_1_SHIFT 3
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#define R24_DAC_PCLK_SEL_IC_1_MASK 0x60
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#define R24_DAC_PCLK_SEL_IC_1_SHIFT 5
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#define R24_DAC_I_SEL_IC_1_MASK 0x780
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#define R24_DAC_I_SEL_IC_1_SHIFT 7
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#define R24_DAC_CLK_SEL_IC_1_MASK 0x1800
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#define R24_DAC_CLK_SEL_IC_1_SHIFT 11
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#define R24_DAC_CHOP_ENB_IC_1_MASK 0x2000
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#define R24_DAC_CHOP_ENB_IC_1_SHIFT 13
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#define R24_DAC_DRTZ_IC_1_MASK 0xC000
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#define R24_DAC_DRTZ_IC_1_SHIFT 14
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#endif
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